Display device

Abstract

A display device includes: a substrate; a first light blocking layer disposed on the substrate and including a first scan line extending in a first direction; an active layer disposed on the first light blocking layer and including a semiconductor region of a first transistor; a gate layer disposed on the active layer and including a gate electrode of the first transistor; a second transistor receiving the first scan signal from the first scan line and supplying a data voltage to a gate electrode of the first transistor; a source metal layer disposed on the gate layer and including an anode connection electrode directly connected to the active layer and receiving the driving current flowing in the first transistor; a pixel electrode disposed on the source metal layer and directly connected to the anode connection electrode; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0137739, filed on October 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This manual relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices are being used, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices.

[0005] The image displayed on the display device can be a still image or a moving image, and the moving image can include various types, such as sports images, game images, and movies. The display device can include multiple pixels and multiple switching elements for driving the pixels. Summary of the Invention

[0006] This specification is intended to provide a display device in which the number of masks in the manufacturing process can be reduced and manufacturing costs can be lowered.

[0007] The purpose of this specification is not limited to the above-described purposes, and other technical purposes can be deduced from the following embodiments.

[0008] In one embodiment, the display device includes: a substrate; a first light-blocking layer on the substrate, the first light-blocking layer including a first scan line extending in a first direction; an active layer including a semiconductor region of a first transistor on the first light-blocking layer; a gate layer including a gate electrode of the first transistor on the active layer; a second transistor receiving a first scan signal from the first scan line and supplying a data voltage to the gate electrode of the first transistor; a source metal layer on the gate layer including an anode connection electrode directly connected to the active layer and receiving a drive current flowing in the first transistor; a pixel electrode on the source metal layer directly connected to the anode connection electrode; a light-emitting layer on the pixel electrode; and a common electrode on the light-emitting layer.

[0009] In one embodiment, the display device includes: a substrate; a first light-blocking layer on the substrate; a first scan line supplying a first scan signal, the first scan line being in the first light-blocking layer and extending in a first direction; a second scan line supplying a second scan signal, the second scan line being in the first light-blocking layer and extending in a first direction; an active layer including a semiconductor region of a first transistor, the active layer being on the first light-blocking layer; a gate layer including a gate electrode of the first transistor, the gate layer being on the active layer; a first light-emitting control line supplying a first light-emitting signal, the first light-emitting control line being in the gate layer and extending in a first direction; a second transistor receiving the first scan signal and supplying a data voltage to the gate electrode of the first transistor; a third transistor receiving the second scan signal and supplying a reference voltage to the gate electrode of the first transistor; and a fourth transistor receiving the first light-emitting signal and supplying a drive voltage to the drain electrode of the first transistor.

[0010] In one embodiment, the display device includes: a substrate; a first electrode and a first scan line of a first capacitor in the same layer on the substrate, the first electrode and the first scan line being spaced apart from each other; a first buffer layer covering the first electrode and the first scan line; an active layer on the first buffer layer, the active layer including a first semiconductor region of a driving transistor and a second semiconductor region of a light-emitting transistor; a second electrode of the first capacitor between the active layer and the first electrode of the first capacitor, the first buffer layer being between the first electrode and the second electrode of the first capacitor; a gate layer on the active layer, the gate layer including a gate electrode of a driving transistor and a gate electrode of a light-emitting transistor spaced apart from the gate electrode of the driving transistor; a first protective layer above the gate layer; a source metal layer on the first protective layer, the source metal layer including a connection electrode and an anode connection electrode spaced apart from the connection electrode, the connection electrode being connected to the gate electrode of the driving transistor and the first electrode of the first capacitor, and the anode connection electrode being directly connected to the active layer; a pixel electrode on the source metal layer, the pixel electrode being directly connected to the anode connection electrode; a light-emitting layer on the pixel electrode; and a common electrode on the light-emitting layer.

[0011] Details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0013] Figure 2 This is a plan view showing a display device according to one embodiment.

[0014] Figure 3This is a circuit diagram showing the circuitry of a display device according to one embodiment.

[0015] Figure 4 This is a cross-sectional view showing the circuitry of a display device according to one embodiment.

[0016] Figure 5 This is a layout diagram showing the pixels of a display device according to one embodiment.

[0017] Figure 6 This illustrates an embodiment. Figure 5 A view of some layers in the layout diagram.

[0018] Figure 7 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers.

[0019] Figure 8 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers.

[0020] Figure 9 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers.

[0021] Figure 10 It is based on one implementation method along Figures 5 to 8 A cross-sectional view of line I-I' in the diagram.

[0022] Figure 11 It is based on one implementation method along Figures 5 to 8 The cross-sectional view of line II-II' in the middle.

[0023] Figure 12 It is based on one implementation method along Figures 5 to 8 The cross-sectional view of line III-III' in the diagram.

[0024] Figure 13 It is based on one implementation method along Figures 5 to 8 A cross-sectional view of line IV-IV' in the diagram. Detailed Implementation

[0025] In the following description, embodiments will be described with reference to the accompanying drawings. In the specification, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled" to a second component, it means that the first component can be directly connected / coupled to the second component, or that a third component can be disposed between the first component and the second component.

[0026] The same reference numerals indicate the same parts. Additionally, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description of the technical content. The term "and / or" includes all one or more combinations that can be defined by associated configurations.

[0027] Terms such as "first" and "second" can be used to describe various components, but these components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the implementation, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular includes the plural.

[0028] Terms such as "below," "under," "above," and "on top" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated by the markings in the drawings.

[0029] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0030] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0031] Reference Figure 1 The display device 10 can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 can be applied to televisions, laptops, monitors, billboards, or display units in the Internet of Things (IoT). As another example, the display device 10 can be applied to wearable devices, such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays (HMDs).

[0032] The display device 10 may include a display panel 100, a controller 200, a gate driving unit 300 (e.g., circuit) that supplies gate signals to a plurality of pixels PX, a data driving unit 400 (e.g., circuit) that supplies data voltage to a plurality of pixels PX, and a power supply unit 500 (e.g., circuit) that supplies power to a plurality of pixels PX.

[0033] The display panel 100 may include a display area DA (see...) Figure 2 ) and non-display area NDA (see Figure 2 The display area DA may include multiple pixels PX. The non-display area NDA may surround the display area DA and includes a gate driving unit 300 and a data driving unit 400.

[0034] Multiple gate lines GL and multiple data lines DL can intersect each other in the display panel 100 and can be electrically connected to each of the pixels PX. For example, a pixel PX can receive a gate signal from the gate driving unit 300 via the gate line GL, a data signal from the data driving unit 400 via the data line DL, and a driving voltage EVDD and a low potential voltage EVSS from the power supply unit 500.

[0035] The gate line GL may include the scan line SCL and the light emission control line EML. The scan line SCL supplies the scan signal SC to the pixel PX, and the light emission control line EML supplies the light emission control signal EM to the pixel PX. The data line DL supplies the data voltage Vdata to the pixel PX, and the power line VL supplies the power voltage. Here, the power voltage may include, but is not limited to, the drive voltage EVDD, the low potential voltage EVSS, the initialization voltage Vint, the reference voltage Vref, and the bias voltage Vbias.

[0036] Display panel 100 may include a non-transmissive display panel or a transmissive display panel. A transmissive display panel can display images on a screen and can be applied to transparent display devices where the actual background is visible. For example, display panel 100 may be implemented as a flexible display panel comprising a plastic substrate.

[0037] A touch sensor can be mounted on the display panel 100. Touch input can be sensed using a separate touch sensor or via pixels (PX). The touch sensor can be an on-cell type or an add-on type touch sensor, and can be implemented as an in-cell type touch sensor mounted on the screen of the display panel 100 or embedded in the display panel 100.

[0038] The controller 200 can process image data RGB input from a host system (not shown) to a size and resolution suitable for the display panel 100, and supply the processed image data RGB to the data driving unit 400. Here, the host system can be one of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system. The controller 200 can generate a gate control signal GCS and a data control signal DCS based on a synchronization signal input from the host system. Here, the synchronization signal can include, but is not limited to, a clock signal CLK, a data enable signal DEN, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The gate control signal GCS can be supplied to the gate driving unit 300 to control the operating timing of the gate driving unit 300, and the data control signal DCS can be supplied to the data driving unit 400 to control the operating timing of the data driving unit 400. For example, the controller 200 can be configured in combination with a microprocessor, mobile processor, application processor, etc.

[0039] The controller 200 can drive the pixel PX at various refresh rates. The controller 200 can drive the pixel PX in a variable refresh rate (VRR) mode, or the pixel PX can be switched between a first refresh rate and a second refresh rate. For example, the controller 200 can drive the pixel PX at various refresh rates by simply changing the rate of the clock signal, generating a synchronization signal to generate horizontal or vertical blanking, or driving the gate drive unit 300 in a mask-like manner.

[0040] The gate control signal GCS can be converted into gate high voltage VGH and gate low voltage VGL voltage levels by a level shifter (not shown) and supplied to the gate drive unit 300. The level shifter can convert the high level voltage of the gate control signal GCS to gate high voltage VGH and the low level voltage of the gate control signal GCS to gate low voltage VGL. The gate control signal GCS may include a start pulse and a shift clock.

[0041] The gate driving unit 300 can supply gate signals to gate lines GL based on gate control signals GCS supplied from the controller 200. The gate driving unit 300 may include a scan driver 310 and a light emission control driver 320. The gate line GL may include a scan line SCL and a light emission control line EML. The scan driver 310 can supply a scan signal SC to the scan line SCL, and the light emission control driver 320 can supply a light emission control signal EM to the light emission control line EML. Each of the scan signal SC and the light emission control signal EM may include a pulse that oscillates between a gate high voltage VGH and a gate low voltage VGL. The scan signal SC can select a pixel PX on which data is written in a row, synchronized with the data voltage Vdata, and the light emission control signal EM can define the light emission time of the pixel PX. The gate driving unit 300 may be disposed on one or both sides of the display panel 100 in a gate-in-panel (GIP) manner. The gate driving unit 300 may use a shift register to shift the gate signals and sequentially supply the shifted gate signals to the gate lines GL.

[0042] The data driving unit 400 can convert image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and supply the converted data voltage Vdata to the data line DL. The number and arrangement of the data driving units 400 are not limited to... Figure 1 The number and arrangement positions are shown. For example, the data driving unit 400 may consist of multiple integrated circuits (ICs), and multiple data driving units may be individually configured on one side of the display panel 100.

[0043] The power supply unit 500 can use a DC-DC converter to generate the direct current (DC) power required to drive the display panel 100. For example, the DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 500 can receive a DC input voltage applied from the host system and generate DC voltages, such as gate high voltage VGH, gate low voltage VGL, drive voltage EVDD, low potential voltage EVSS, initialization voltage Vint, reference voltage Vref, and bias voltage Vbias. The gate high voltage VGH and gate low voltage VGL can be supplied to the level shifter and gate drive unit 300. The drive voltage EVDD, low potential voltage EVSS, initialization voltage Vint, and reference voltage Vref can be supplied to the pixel PX.

[0044] Figure 2 This is a plan view showing a display device according to one embodiment.

[0045] Reference Figure 2The display panel 100 may include a display area DA and a non-display area NDA. The flat surface shape of the display area DA may be rectangular. The display area DA may be a rectangular shape with rounded corners, but is not limited thereto. As another example, the flat surface shape of the display area DA may be a square, a circle, an ellipse, or other polygonal shapes.

[0046] In the following text, the first direction DR1 and the second direction DR2 are different directions that intersect each other, and are indicated by their perpendicular intersection in the plan view of the display device 10. The first direction DR1 may generally be the same as the extension direction of the short side of the display panel 100, and the second direction DR2 may be the same as the extension direction of the long side of the display panel 100. However, the directions described in the embodiments should be understood as indicating relative directions, and the embodiments are not limited to the described directions.

[0047] The display area DA may include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA may surround the display area DA. The non-display area NDA may include a first side disposed in the first direction DR1 of the display area DA, a second side disposed in the direction opposite to the first direction DR1, a third side disposed in the second direction DR2, and a fourth side disposed in the direction opposite to the second direction DR2. Here, in the non-display area NDA, the first side may be the right side, the second side may be the left side, the third side may be the top side, and the fourth side may be the bottom side.

[0048] Scan lines SCL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2. Scan lines SCL can sequentially supply scan signals SC to multiple pixels PX.

[0049] The emission control lines EML can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The emission control lines EML can sequentially supply the emission signal EM to multiple pixels PX.

[0050] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can supply data voltage to pixels PX. The data voltage determines the brightness of each pixel PX.

[0051] The power lines VL can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1. The power lines VL can supply power voltage to the pixel PX. Here, the power voltage may include, but is not limited to, the drive voltage EVDD, the low potential voltage EVSS, the initialization voltage Vint, the reference voltage Vref, and the bias voltage Vbias.

[0052] The gate driving unit 300 can be disposed on each of the first and second sides of the non-display area NDA. A low-potential line VSL can be disposed in the non-display area NDA to surround the gate driving unit 300 and the display area DA. For example, the low-potential line VSL can extend from the flexible film FPCB and pass through the sub-region SR and the curved region BR, and can be disposed on the first to fourth sides of the non-display area NDA to surround the gate driving unit 300 and the display area DA.

[0053] The display panel 100 may include a main region MR, a curved region BR, and a sub-region SR. The main region MR may include a display region DA and a non-display region NDA. The curved region BR may be disposed between the main region MR and the sub-region SR. The curved region BR may extend from the fourth side of the non-display region NDA in a direction opposite to the second direction DR2. The sub-region SR may extend from the curved region BR in a direction opposite to the second direction DR2.

[0054] The sub-region SR may include a first pad region PA1 and a second pad region PA2. The first pad region PA1 may be located in the center of the sub-region SR and connected to the data driving unit 400. The second pad region PA2 may be located at the end of the sub-region SR and connected to the flexible film FPCB.

[0055] The data driving unit 400 can be formed in the form of an integrated circuit (IC). For example, the data driving unit 400 can be provided in a chip-on-plastic (CIP) manner, wherein the data driving unit 400 is directly mounted on the display panel 100. As another example, the data driving unit 400 can be provided in a chip-on-glass or chip-on-film manner.

[0056] The display panel 100 may also include a crack sensing pattern CRP surrounding the low-potential line VSL. The crack sensing pattern CRP may be positioned on the first to fourth sides of the non-display area NDA to completely surround the display area DA. As another example, the crack sensing pattern CRP may not be positioned on a portion of the non-display area NDA.

[0057] Figure 3 This is a circuit diagram showing the circuitry of a display device according to one embodiment.

[0058] Reference Figure 3 Each of the multiple pixels PX can be connected to the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first light emission control line EML1, the second light emission control line EML2, the data line DL, the reference voltage line VRL, the drive voltage line VDL, the initialization voltage line VIL, and the low potential line VSL.

[0059] A pixel PX may include pixel circuitry and a light-emitting element ED. The pixel circuitry may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0060] The first transistor T1 is a driving transistor and may include a gate electrode, a drain electrode, and a source electrode. The first transistor T1 can control the drain-source current (Ids) (or driving current) based on the data voltage applied to the gate electrode. The driving current (Ids) flowing through the channel of the first transistor T1 is proportional to the square of the difference between the voltage (Vgs) between the gate and source electrodes of the first transistor T1 and the threshold voltage (Vth) (Ids = k × (Vgs - Vth)). 2 Here, k represents a scaling factor determined by the structure and physical characteristics of the first transistor T1, Vgs represents the gate-source voltage of the first transistor T1, and Vth represents the threshold voltage of the first transistor T1. The gate electrode of the first transistor T1 can be electrically connected to the first node N1, the drain electrode can be connected to the source electrode of the fourth transistor T4, and the source electrode can be electrically connected to the second node N2.

[0061] An OLED can receive a driving current (Ids) and emit light. The amount or brightness of the light emitted by the OLED can be proportional to the magnitude of the driving current (Ids). An OLED can be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the type of OLED is not limited to this.

[0062] The first electrode of the light-emitting element (ED) can be electrically connected to the third node N3. The first electrode of the ED can be connected via the third node N3 to the source electrode of the fifth transistor T5 and the drain electrode of the sixth transistor T6. Here, the first electrode of the ED can be an anode electrode or a pixel electrode. The second electrode of the ED can be electrically connected to the low-potential line VSL and can receive a low-potential voltage EVSS from the low-potential line VSL. Here, the second electrode of the ED can be a cathode electrode or a common electrode.

[0063] The second transistor T2 is a data transistor and can be turned on by a first scan signal on the first scan line SCL1 to electrically connect the data line DL to the first node N1, which is the gate electrode of the first transistor T1. The second transistor T2 can be turned on based on the first scan signal to supply a data voltage to the first node N1. In the second transistor T2, the gate electrode can be electrically connected to the first scan line SCL1, the drain electrode can be electrically connected to the data line DL, and the source electrode can be electrically connected to the first node N1.

[0064] The third transistor T3 is an initialization transistor and can be turned on by the second scan signal of the second scan line SCL2 to electrically connect the reference voltage line VRL to the first node N1, which is the gate electrode of the first transistor T1. The third transistor T3 can be turned on based on the second scan signal to supply the reference voltage Vref to the first node N1. In the third transistor T3, the gate electrode can be electrically connected to the second scan line SCL2, the drain electrode can be electrically connected to the reference voltage line VRL, and the source electrode can be electrically connected to the first node N1.

[0065] The fourth transistor T4 is a light-emitting transistor and can be turned on by a first light-emitting signal on the first light-emitting control line EML1 to electrically connect the driving voltage line VDL to the drain electrode of the first transistor T1. In the fourth transistor T4, the gate electrode can be electrically connected to the first light-emitting control line EML1, the drain electrode can be electrically connected to the driving voltage line VDL, and the source electrode can be electrically connected to the drain electrode of the first transistor T1.

[0066] The fifth transistor T5 is a light-emitting transistor and can be turned on by the second light-emitting signal of the second light-emitting control line EML2 to electrically connect the second node N2 to the third node N3. In the fifth transistor T5, the gate electrode can be electrically connected to the second light-emitting control line EML2, the drain electrode can be electrically connected to the second node N2, and the source electrode can be electrically connected to the third node N3.

[0067] The sixth transistor T6 is an initialization transistor and can be turned on by the third scan signal of the third scan line SCL3 to electrically connect the third node N3, which serves as the first electrode of the light-emitting element ED, to the initialization voltage line VIL. The sixth transistor T6 can be turned on based on the third scan signal to initialize the first electrode of the light-emitting element ED with the initialization voltage. In the sixth transistor T6, the gate electrode can be electrically connected to the third scan line SCL3, the drain electrode can be electrically connected to the third node N3, and the source electrode can be electrically connected to the initialization voltage line VIL.

[0068] The first to sixth transistors T1, T2, T3, T4, T5, and T6 may include an oxide-based active layer. The first to sixth transistors T1, T2, T3, T4, T5, and T6 may correspond to n-type transistors, and the current flowing into the drain electrode is output to the source electrode based on a high gate voltage VGH applied to the gate electrode. The oxide-based active layer can have a relatively small S-factor, increasing the constant current drive area in the low grayscale region and improving low grayscale performance.

[0069] As another example, at least one of the first to sixth transistors T1, T2, T3, T4, T5, and T6 may include an active layer formed of low-temperature polycrystalline silicon (LTPS). At least one of the first to sixth transistors T1, T2, T3, T4, T5, and T6 may correspond to a p-type transistor and output current flowing into the source electrode to the drain electrode based on a low gate voltage VGL applied to the gate electrode.

[0070] The first capacitor C1 can be electrically connected to a first node N1, which serves as the gate electrode of the first transistor T1, and a second node N2, which serves as the source electrode of the first transistor T1. For example, the first capacitor electrode of the first capacitor C1 can be electrically connected to the first node N1, and the second capacitor electrode of the first capacitor C1 can be electrically connected to the second node N2, thereby maintaining the potential difference between the gate electrode and the source electrode of the first transistor T1.

[0071] The second capacitor C2 can be electrically connected to the drive voltage line VDL and the second node N2, which serves as the source electrode of the first transistor T1. For example, the first capacitor electrode of the second capacitor C2 can be electrically connected to the drive voltage line VDL, and the second capacitor electrode of the second capacitor C2 can be electrically connected to the second node N2, thereby maintaining the potential difference between the drive voltage line VDC and the source electrode of the first transistor T1.

[0072] Figure 4 This is a cross-sectional view showing the circuitry of a display device according to one embodiment.

[0073] Reference Figure 4 The display panel 100 may include a substrate SUB, a first light blocking layer LS1, a first buffer layer BF1, a second light blocking layer LS2, a second buffer layer BF2, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first protective layer PLN1, a source metal layer SDL, a second protective layer PLN2, a light-emitting element ED, a pixel defining layer PDL, a packaging layer TFEL, a first insulating layer IL1, a bridge electrode BRE, a second insulating layer IL2, a first touch electrode TE1, a second touch electrode TE2, and a planarization layer OC.

[0074] The substrate SUB can be a base substrate or a base component. The substrate SUB can include at least one plastic material. For example, the substrate SUB can be a multi-substrate comprising multiple plastic materials such as polyimide, but the constituent materials of the substrate SUB are not limited to this.

[0075] A first light-blocking layer LS1 can be disposed on the substrate SUB. The first light-blocking layer LS1 may include a first capacitor electrode C1a of a first capacitor C1 and a first scan line SCL1. The first capacitor electrode C1a can be disposed below the first transistor T1 to block light incident on the first transistor T1. Therefore, the first capacitor electrode C1a overlaps with the first transistor T1 to block light. The first capacitor electrode C1a can generate capacitance by overlapping with a second capacitor electrode C1b on the thickness of the third-direction DR3 or the substrate SUB. The first scan line SCL1 can supply a first scan signal to... Figure 3 The second transistor T2 is shown. The first scan line SCL1 and the first capacitor electrode C1a are located on the same layer. In one embodiment, at least a portion of the first scan line SCL1 does not overlap with the second capacitor electrode C1b. The first light-blocking layer LS1 may be formed of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, but is not limited thereto.

[0076] A first buffer layer BF1 may be disposed on a first light-blocking layer LS1. For example, the first buffer layer BF1 covers the first scan line SCL1 and the first capacitor electrode C1a. The first buffer layer BF1 may include an inorganic membrane capable of preventing or at least reducing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic membranes stacked alternately.

[0077] A second light-blocking layer LS2 may be disposed on the first buffer layer BF1. The second light-blocking layer LS2 may include a second capacitor electrode C1b of the first capacitor C1. The second capacitor electrode C1b may be disposed below the first transistor T1 to block light incident on the first transistor T1. For example, the second light-blocking layer LS2 including the second capacitor electrode C1b is located between the first light-blocking layer LS1 and the first transistor T1. The second capacitor electrode C1b may generate capacitance by overlapping with the first capacitor electrode C1a. The second light-blocking layer LS2 may include, but is not limited to, the materials exemplified in the first light-blocking layer LS1.

[0078] The second buffer layer BF2 may be disposed on the second light-blocking layer LS2. Therefore, the second buffer layer BF2 covers the second light-blocking layer LS2, which includes the second capacitor electrode C1b. The second buffer layer BF2 may include an inorganic membrane capable of preventing or at least reducing the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic membranes stacked alternately.

[0079] An active layer ACTL may be disposed on the second buffer layer BF2. The active layer ACTL may include, but is not limited to, an oxide-based material. The active layer ACTL may include a semiconductor region ACT1 (e.g., a first semiconductor region), a drain electrode DE1, and a source electrode SE1 of a first transistor T1, and a semiconductor region ACT5 (e.g., a second semiconductor region), a drain electrode DE5, and a source electrode SE5 of a fifth transistor T5. The source electrode SE1 of the first transistor T1 and the drain electrode DE5 of the fifth transistor T5 may be integrally formed. Therefore, the source electrode SE1 of the first transistor T1 and the drain electrode DE5 of the fifth transistor T5 are integral with each other. In one embodiment, the drain electrode DE1 of the first transistor T1 is located on a first side of the semiconductor region ACT1, and the source electrode SE1 of the first transistor T1 is located on a second side of the semiconductor region ACT1. Similarly, the drain electrode DE5 of the fifth transistor T5 is located on a first side of the semiconductor region ACT5, and the source electrode SE5 of the fifth transistor T5 is located on a second side of the semiconductor region ACT5.

[0080] The gate insulating layer GI can be disposed on the active layer ACTL. The gate insulating layer GI can isolate the active layer ACTL from the gate layer GTL.

[0081] The gate layer GTL can be disposed on the gate insulating layer GI. The gate layer GTL may include the gate electrode GE1 of the first transistor T1 and the gate electrode GE5 of the fifth transistor T5. The gate electrode GE5 of the fifth transistor T5 can be... Figure 3 A portion of the second light-emitting control line EML2 shown.

[0082] An interlayer insulating layer (ILD) can be disposed on the gate layer (GTL). The ILD can insulate the gate layer (GTL) from the source metal layer (SDL).

[0083] The first protective layer PLN1 can be disposed on the interlayer insulating layer (ILD). The first protective layer PLN1 can planarize the top of the transistor and protect the transistor. The first protective layer PLN1 can include organic materials. For example, the first protective layer PLN1 can include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0084] A source metal layer (SDL) may be disposed on a first guard layer (PLN1). The source metal layer (SDL) may include a first connection electrode (CE1) and an anode connection electrode (ANE). The first connection electrode (CE1) may electrically connect the gate electrode (GE1) of the first transistor (T1) and the first capacitor electrode (C1a) of the first capacitor (C1). The first connection electrode (CE1) may be inserted into a contact hole passing through the first guard layer (PLN1) and the interlayer insulating layer (ILD) to contact the gate electrode (GE1) of the first transistor (T1). The first connection electrode (CE1) may also be inserted into a contact hole passing through the first guard layer (PLN1), the interlayer insulating layer (ILD), the gate insulating layer (GI), the second buffer layer (BF2), and the first buffer layer (BF1) to contact the first capacitor electrode (C1a).

[0085] The anode connection electrode ANE can electrically connect the source electrode SE5 of the fifth transistor T5 to the pixel electrode AE. The anode connection electrode ANE can be inserted into a contact hole passing through the first protective layer PLN1, the interlayer insulating layer ILD, and the gate insulating layer GI to contact the source electrode SE5 of the fifth transistor T5.

[0086] The second protective layer PLN2 may be disposed on the source metal layer SDL. The second protective layer PLN2 can planarize the upper part of the source metal layer SDL and protect the source metal layer SDL. The second protective layer PLN2 may include organic materials. For example, the second protective layer PLN2 may include the materials exemplified in the first protective layer PLN1, but is not limited thereto.

[0087] A pixel-defining layer (PDL) can be disposed on the second protective layer (PLN2). The PDL can define a light-emitting region (EA) or an opening region. The PDL can include, but is not limited to, materials containing black pigments, organic materials such as benzocyclobutene resin, polyimide resin, acrylic resin, and photosensitive polymers. When the PDL includes materials containing black pigments or black dyes, the PDL can be a black barrier. The PDL can include black pigments or black dyes to block external light and increase the brightness of the display device 10.

[0088] Optionally, spacers (not shown) may be provided on the pixel defining layer (PDL). The spacers may include, but are not limited to, the same material as the pixel defining layer (PDL).

[0089] The light-emitting element (ED) may include a pixel electrode AE, a light-emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a second protective layer PLN2. The pixel electrode AE ​​may overlap with one of a plurality of light-emitting regions EA defined by a pixel defining layer PDL. The pixel electrode AE ​​may receive drive current from the pixel circuitry of the pixel PX. Figure 3 The first electrode of the light-emitting element ED.

[0090] The light-emitting layer EL can be disposed on the pixel electrode AE. For example, the light-emitting layer EL can be an organic light-emitting layer formed of organic materials, but is not limited thereto. When the light-emitting layer EL corresponds to an organic light-emitting layer, when the pixel circuit of the pixel PX applies a predetermined voltage to the pixel electrode AE ​​and the common electrode CAT receives the common voltage or the cathode voltage, holes can move to the light-emitting layer EL through the hole transport layer, electrons can move to the light-emitting layer EL through the electron transport layer, and holes and electrons can combine in the light-emitting layer EL to emit light.

[0091] The common electrode CAT can be disposed on the light-emitting layer EL. For example, the common electrode CAT can be implemented as an electrode common to all pixels PX, rather than being distinguished by each pixel PX. The common electrode CAT can be a transparent electrode and can transmit light. The common electrode CAT can be electrically connected to the low-potential line VSL and can receive a low-potential voltage, a common voltage, or a cathode voltage. The common electrode CAT can be... Figure 3 The second electrode of the light-emitting element ED.

[0092] The encapsulation layer TFEL can be disposed on the light-emitting element ED. The encapsulation layer TFEL can be disposed on the common electrode CAT to cover multiple light-emitting elements ED. The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 sequentially stacked on the common electrode CAT.

[0093] The first encapsulation layer TFE1 may be disposed on the common electrode CAT. The first encapsulation layer TFE1 may include inorganic materials to prevent or at least reduce the penetration of oxygen or moisture into the light-emitting element ED. For example, the first encapsulation layer TFE1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0094] A second encapsulation layer TFE2 can be disposed on the first encapsulation layer TFE1 to planarize the upper ends of the multiple light-emitting elements (EDs). The second encapsulation layer TFE2 may include organic materials to protect the EDs from foreign matter such as dust. For example, the second encapsulation layer TFE2 may include organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The second encapsulation layer TFE2 can be formed by curing monomers or coating polymers.

[0095] A third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include inorganic materials to prevent oxygen or moisture from penetrating the light-emitting element ED. For example, the third encapsulation layer TFE3 may include the materials exemplified in the first encapsulation layer TFE1, but is not limited thereto.

[0096] The first insulating layer IL1 may be disposed on the encapsulation layer TFEL. The first insulating layer IL1 may have insulating and optical functions. The first insulating layer IL1 may include at least one inorganic film.

[0097] The bridge electrode BRE can be disposed on the first insulating layer IL1. The bridge electrode BRE can be disposed on a different layer from the first touch electrode TE1 and the second touch electrode TE2, so that the first touch electrodes TE1, which are spaced apart from each other by the second touch electrode TE2 inserted therebetween, are electrically connected.

[0098] The second insulating layer IL2 can be disposed on the bridge electrode BRE. The second insulating layer IL2 can insulate the bridge electrode BRE from the second touch electrode TE2. The second insulating layer IL2 may include at least one inorganic film.

[0099] The first touch electrode TE1 and the second touch electrode TE2 can be disposed on the second insulating layer IL2. The first touch electrode TE1 and the second touch electrode TE2 can be formed from a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and indium tin oxide (ITO), or from a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). A touch driving unit (not shown) can determine whether a touch input has occurred based on the change in capacitance between the first touch electrode TE1 and the second touch electrode TE2, and calculate the touch input coordinates.

[0100] A planarization layer OC can be disposed on the first touch electrode TE1 and the second touch electrode TE2. The planarization layer OC can planarize the upper parts of the first touch electrode TE1 and the second touch electrode TE2, and protect the first touch electrode TE1 and the second touch electrode TE2. The planarization layer OC may include an organic insulating material.

[0101] The display device 10 may include a source metal layer SDL between the transistor of the pixel circuit and the pixel electrode AE ​​of the light-emitting element ED, thereby reducing the number of masks in the manufacturing process and lowering manufacturing costs. The display device 10 can reduce the number of conductive layers, thereby optimizing the process and shortening the manufacturing cycle.

[0102] Figure 5 This is a layout diagram showing the pixels of a display device according to one embodiment. Figure 6 This illustrates an embodiment. Figure 5 The layout diagram shows some layer views and illustrates the stacked structure of the first light-blocking layer LS1 and the second light-blocking layer LS2. Figure 7 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers and illustrates the stacked structure of the active layer ACTL and the gate layer GTL. Figure 8 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers and also illustrates the source metal layer SDL. Figure 9 This illustrates an embodiment. Figure 5 The layout diagram shows views of other layers and illustrates the stacked structure of the first pixel electrode AE1, the second pixel electrode AE2, and the pixel definition layer PDL. Figure 10 It is based on one implementation method along Figures 5 to 8 The cross-sectional view of line I-I' in the middle, and Figure 11 It is based on one implementation method along Figures 5 to 8 The cross-sectional view of line II-II' in the middle. Figure 12 It is along Figures 5 to 8 The cross-sectional view of line III-III' in the middle, and Figure 13 It is based on one implementation method along Figures 5 to 8 A cross-sectional view of line IV-IV' in the diagram.

[0103] Reference Figures 5 to 13 Multiple pixels (PX) can be configured into multiple rows and multiple columns. Each pixel in a multiple pixel PX can be connected to the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first emission control line EML1, the second emission control line EML2, the data line DL, the reference voltage line VRL, the drive voltage line VDL, the initialization voltage line VIL, and the low potential line VSL.

[0104] The driving voltage line VDL may include a first driving voltage line VDL1 and a second driving voltage line VDL2. Figure 5 and Figure 8 In this configuration, the first driving voltage line VDL1 can extend from the source metal layer SDL along the second direction DR2. The first driving voltage line VDL1 can supply the driving voltage EVDD received from the power supply unit 500 to the pixel PX. Figure 10 In this configuration, the first driving voltage line VDL1 can be inserted into a contact hole passing through the first protective layer PLN1, the interlayer insulating layer ILD, the gate insulating layer GI, the second buffer layer BF2, and the first buffer layer BF1, and connected to the first capacitor electrode C2a of the second capacitor C2, which is part of the second driving voltage line VDL2. The first driving voltage line VDL1 can also be inserted into a contact hole passing through the first protective layer PLN1, the interlayer insulating layer ILD, and the gate insulating layer GI, and connected to the drain electrode DE4 of the fourth transistor T4.

[0105] The first driving voltage line VDL1, the first reference voltage line VRL1, and the first initialization voltage line VIL1 can be alternately arranged in multiple columns of pixel PX. For example, the first driving voltage line VDL1 can be arranged in some columns of pixel PX, the first reference voltage line VRL1 can be arranged in other columns of pixel PX, and the first initialization voltage line VIL1 can be arranged in other columns of pixel PX. Figure 10 The cross-sectional view discloses the configuration of the first driving voltage line VDL1 connected to the second driving voltage line VDL2. However, when the first reference voltage line VRL1 or the first initialization voltage line VIL1 is set in the corresponding position, the first reference voltage line VRL1 or the first initialization voltage line VIL1 may not be connected to the second driving voltage line VDL2.

[0106] exist Figure 5 and Figure 6 In this configuration, a second driving voltage line VDL2 can extend from the first light-blocking layer LS1 along the first direction DR1. The second driving voltage line VDL2 can be connected to the first driving voltage line VDL1 to receive and supply the driving voltage EVDD to the pixel PX. The second driving voltage line VDL2 may include the first capacitor electrode C2a of the second capacitor C2. Figure 10 In the second capacitor C2, the first capacitor electrode C2a can overlap with the second capacitor electrode C2b on the third-direction DR3 to generate capacitance. The second capacitor electrode C2b of the second capacitor C2 can be disposed in the second light-blocking layer LS2 and integrally formed with the second capacitor electrode C1b of the first capacitor C1.

[0107] The reference voltage line VRL may include a first reference voltage line VRL1 and a second reference voltage line VRL2. Figure 5 and Figure 8 In this configuration, the first reference voltage line VRL1 can extend from the source metal layer SDL in the second direction DR2. The first reference voltage line VRL1 can supply the reference voltage Vref received from the power supply unit 500 to the pixel PX.

[0108] exist Figure 5 and Figure 6 In this configuration, the second reference voltage line VRL2 can extend from the first light-blocking layer LS1 along the first direction DR1. The second reference voltage line VRL2 can be connected to the first reference voltage line VRL1 to receive and supply the reference voltage Vref to the pixel PX. The second reference voltage line VRL2 can be electrically connected to the drain electrode DE3 of the third transistor T3 via the fifth connection electrode CE5 disposed in the source metal layer SDL.

[0109] The initialization voltage line VIL can include a first initialization voltage line VIL1 and a second initialization voltage line VIL2. In Figure 5 and Figure 8 In this configuration, the first initialization voltage line VIL1 can extend from the source metal layer SDL in the second direction DR2. The initialization voltage line VIL can supply the initialization voltage Vint received from the power supply unit 500 to the pixel PX.

[0110] exist Figure 5 and Figure 6 In this configuration, the second initialization voltage line VIL2 can extend from the first photoblocking layer LS1 along the first direction DR1. The second initialization voltage line VIL2 can be connected to the first initialization voltage line VIL1 to receive the initialization voltage Vint and supply the initialization voltage Vint to the pixel PX. The second initialization voltage line VIL2 can be electrically connected to the source electrode SE6 of the sixth transistor T6 via the sixth connection electrode CE6 disposed in the source metal layer SDL.

[0111] The first transistor T1 may include a semiconductor region ACT1, a drain electrode DE1, a source electrode SE1, and a gate electrode GE1. The semiconductor region ACT1, drain electrode DE1, and source electrode SE1 of the first transistor T1 may be disposed in the active layer ACTL, and the gate electrode GE1 of the first transistor T1 may be disposed in the gate layer GTL. The gate electrode GE1 of the first transistor T1 may overlap with the semiconductor region ACT1 of the first transistor T1. For example, the semiconductor region ACT1 of the first transistor T1 may include oxide, and the drain electrode DE1 and source electrode SE1 of the first transistor T1 may be formed by N-type doping.

[0112] The gate electrode GE1 of the first transistor T1 can be part of the third capacitor electrode C1c of the first capacitor C1. The third capacitor electrode C1c of the first capacitor C1 can be electrically connected to the first capacitor electrode C1a of the first capacitor C1 of the first photoblocking layer LS1 through the first connection electrode CE1 of the source metal layer SDL. The first connection electrode CE1 can be electrically connected to the source electrode SE3 of the third transistor T3, the third capacitor electrode C1c of the first capacitor C1, the first capacitor electrode C1a of the first capacitor C1, and the source electrode SE2 of the second transistor T2.

[0113] The fourth capacitor electrode C1d of the first capacitor C1 can be disposed in the gate layer GTL, facing the third capacitor electrode C1c of the first capacitor C1. The third capacitor electrode C1c and the fourth capacitor electrode C1d of the first capacitor C1 can be formed on the same layer to generate capacitance. Figure 11In the first capacitor C1, the fourth capacitor electrode C1d can be electrically connected to the second capacitor electrode C1b of the first capacitor C1 via the second connection electrode CE2 of the source metal layer SDL. The second connection electrode CE2 can be electrically connected to the fourth capacitor electrode C1d of the first capacitor C1, the second capacitor electrode C1b of the first capacitor C1, and the source electrode SE1 of the first transistor T1.

[0114] The first capacitor electrode C1a and the second capacitor electrode C1b of the first capacitor C1 can overlap on the third direction DR3 to generate capacitance, and the third capacitor electrode C1c and the fourth capacitor electrode C1d can overlap on the first direction DR1 to generate capacitance. Therefore, the first capacitor C1 can be formed as a double layer to ensure capacitance and reduce coupling capacitance between pixel circuits.

[0115] The drain electrode DE1 of the first transistor T1 can be integrally formed with the source electrode SE4 of the fourth transistor T4. The source electrode SE1 of the first transistor T1 and the drain electrode DE5 of the fifth transistor T5 can also be integrally formed. Therefore, the source electrode SE1 of the first transistor T1 and the drain electrode DE5 of the fifth transistor T5 are integrally formed with each other. Figure 11 In the first transistor T1, the source electrode SE1 can be electrically connected to the second capacitor electrode C1b and the fourth capacitor electrode C1d of the first capacitor C1 through the second connection electrode CE2.

[0116] The second transistor T2 may include a semiconductor region ACT2, a drain electrode DE2, a source electrode SE2, and a gate electrode GE2. The semiconductor region ACT2, drain electrode DE2, and source electrode SE2 of the second transistor T2 may be disposed in the active layer ACTL, and the gate electrode GE2 of the second transistor T2 may be disposed in the gate layer GTL. The gate electrode GE2 of the second transistor T2 may overlap with the semiconductor region ACT2 of the second transistor T2. For example, the semiconductor region ACT2 of the second transistor T2 may include oxide, and the drain electrode DE2 and source electrode SE2 of the second transistor T2 may be formed by N-type doping.

[0117] exist Figure 12In this configuration, the gate electrode GE2 of the second transistor T2 can be electrically connected to the first scan line SCL1 of the first photoblocking layer LS1 via the third connection electrode CE3 disposed in the source metal layer SDL. The gate electrode GE2 of the second transistor T2 can receive the first scan signal from the first scan line SCL1. The drain electrode DE2 of the second transistor T2 can receive the data voltage from the data line DL. The data line DL can be disposed in the source metal layer SDL and can extend in the second direction DR2. The source electrode SE2 of the second transistor T2 can be electrically connected to the first capacitor electrode C1a of the first capacitor C1, the third capacitor electrode C1c of the first capacitor C1, and the source electrode SE3 of the third transistor T3 via the first connection electrode CE1.

[0118] The third transistor T3 may include a semiconductor region ACT3, a drain electrode DE3, a source electrode SE3, and a gate electrode GE3. The semiconductor region ACT3, drain electrode DE3, and source electrode SE3 of the third transistor T3 may be disposed in the active layer ACTL, and the gate electrode GE3 of the third transistor T3 may be disposed in the gate layer GTL. The gate electrode GE3 of the third transistor T3 may overlap with the semiconductor region ACT3 of the third transistor T3. For example, the semiconductor region ACT3 of the third transistor T3 may include oxide, and the drain electrode DE3 and source electrode SE3 of the third transistor T3 may be formed by N-type doping.

[0119] The gate electrode GE3 of the third transistor T3 can be electrically connected to the second scan line SCL2 of the first photoblocking layer LS1 via the fourth connection electrode CE4 disposed in the source metal layer SDL. The gate electrode GE3 of the third transistor T3 can receive the second scan signal from the second scan line SCL2. The drain electrode DE3 of the third transistor T3 can be electrically connected to the second reference voltage line VRL2 of the first photoblocking layer LS1 via the fifth connection electrode CE5 disposed in the source metal layer SDL. The drain electrode DE3 of the third transistor T3 can receive the reference voltage Vref from the second reference voltage line VRL2. The source electrode SE3 of the third transistor T3 can be electrically connected to the first capacitor electrode C1a of the first capacitor C1, the third capacitor electrode C1c of the first capacitor C1, and the source electrode SE2 of the third transistor T2 via the first connection electrode CE1.

[0120] The fourth transistor T4 may include a semiconductor region ACT4, a drain electrode DE4, a source electrode SE4, and a gate electrode GE4. The semiconductor region ACT4, drain electrode DE4, and source electrode SE4 of the fourth transistor T4 may be disposed in the active layer ACTL, and the gate electrode GE4 of the fourth transistor T4 may be disposed in the gate layer GTL. The gate electrode GE4 of the fourth transistor T4 may overlap with the semiconductor region ACT4 of the fourth transistor T4. For example, the semiconductor region ACT4 of the fourth transistor T4 may include oxide, and the drain electrode DE4 and source electrode SE4 of the fourth transistor T4 may be formed by N-type doping.

[0121] The gate electrode GE4 of the fourth transistor T4 can be part of the first light-emitting control line EML1. The first light-emitting control line EML1 can be disposed in the gate layer GTL and can extend in the first direction DR1. The gate electrode GE4 of the fourth transistor T4 can receive a first light-emitting signal from the first light-emitting control line EML1. The drain electrode DE4 of the fourth transistor T4 can receive a drive voltage EVDD from the first drive voltage line VDL1 disposed in the source metal layer SDL. The source electrode SE4 of the fourth transistor T4 and the drain electrode DE1 of the first transistor T1 can be integrally formed. Therefore, the source electrode SE4 of the fourth transistor T4 and the drain electrode DE1 of the first transistor T1 are integral with each other.

[0122] The fifth transistor T5 may include a semiconductor region ACT5, a drain electrode DE5, a source electrode SE5, and a gate electrode GE5. The semiconductor region ACT5, drain electrode DE5, and source electrode SE5 of the fifth transistor T5 may be disposed in the active layer ACTL, and the gate electrode GE5 of the fifth transistor T5 may be disposed in the gate layer GTL. The gate electrode GE5 of the fifth transistor T5 may overlap with the semiconductor region ACT5 of the fifth transistor T5. For example, the semiconductor region ACT5 of the fifth transistor T5 may include oxide, and the drain electrode DE5 and source electrode SE5 of the fifth transistor T5 may be formed by N-type doping.

[0123] The gate electrode GE5 of the fifth transistor T5 can be part of the second light-emitting control line EML2. The second light-emitting control line EML2 can be disposed in the gate layer GTL and can extend in the first direction DR1. The gate electrode GE5 of the fifth transistor T5 can receive a second light-emitting signal from the second light-emitting control line EML2. The drain electrode DE5 of the fifth transistor T5 can be integrally formed with the source electrode SE1 of the first transistor T1. The source electrode SE5 of the fifth transistor T5 and the drain electrode DE6 of the sixth transistor T6 can be integrally formed. Therefore, the source electrode SE5 of the fifth transistor T5 and the drain electrode DE6 of the sixth transistor T6 are integral with each other. Figure 13In the process, the source electrode SE5 of the fifth transistor T5 can be electrically connected to the anode connection electrode ANE of the source metal layer SDL. Figure 9 The first pixel electrode AE1 can be inserted into the first contact hole CNT1 through the second protective layer PLN2 to contact the anode connection electrode ANE. The light-emitting element ED including the first pixel electrode AE1 can emit light through the first light-emitting region EA1 defined by the pixel defining layer PDL.

[0124] exist Figure 9 In the middle, the second pixel electrode AE2 can be electrically connected to Figures 5 to 8 The pixel circuit shown is a pixel circuit disposed on the second direction DR2. The light-emitting element ED, including the second pixel electrode AE2, can emit light through the second light-emitting region EA2 defined by the pixel defining layer PDL.

[0125] The sixth transistor T6 may include a semiconductor region ACT6, a drain electrode DE6, a source electrode SE6, and a gate electrode GE6. The semiconductor region ACT6, drain electrode DE6, and source electrode SE6 of the sixth transistor T6 may be disposed in the active layer ACTL, and the gate electrode GE6 of the sixth transistor T6 may be disposed in the gate layer GTL. The gate electrode GE6 of the sixth transistor T6 may overlap with the semiconductor region ACT6 of the sixth transistor T6. For example, the semiconductor region ACT6 of the sixth transistor T6 may include oxide, and the drain electrode DE6 and source electrode SE6 of the sixth transistor T6 may be formed by N-type doping.

[0126] The gate electrode GE6 of the sixth transistor T6 can be part of the third scan line SCL3. The third scan line SCL3 can be disposed in the gate layer GTL and can extend in the first direction DR1. The gate electrode GE6 of the sixth transistor T6 can receive the third scan signal from the third scan line SCL3. The drain electrode DE6 of the sixth transistor T6 can be integrally formed with the source electrode SE5 of the fifth transistor T5. The source electrode SE6 of the sixth transistor T6 can be electrically connected to the second initialization voltage line VIL2 of the first photoblocking layer LS1 through the sixth connection electrode CE6 disposed in the source metal layer SDL. The source electrode SE6 of the sixth transistor T6 can receive the initialization voltage Vint from the second initialization voltage line VIL2.

[0127] The display device 10 according to various embodiments of this specification can be described as follows.

[0128] In one embodiment, the display device includes: a substrate; a first light-blocking layer on the substrate, the first light-blocking layer including a first scan line extending in a first direction; an active layer including a semiconductor region of a first transistor on the first light-blocking layer; a gate layer including a gate electrode of the first transistor on the active layer; a second transistor receiving a first scan signal from the first scan line and supplying a data voltage to the gate electrode of the first transistor; a source metal layer on the gate layer including an anode connection electrode directly connected to the active layer and receiving a drive current flowing in the first transistor; a pixel electrode on the source metal layer directly connected to the anode connection electrode; a light-emitting layer on the pixel electrode; and a common electrode on the light-emitting layer.

[0129] In one embodiment, the display device further includes: a data line supplying a data voltage, the data line being in a source metal layer and extending in a second direction intersecting the first direction.

[0130] In one embodiment, the display device further includes: a second scan line in a first light-blocking layer extending in a first direction; and a third transistor receiving a second scan signal from the second scan line and supplying a reference voltage to the gate electrode of the first transistor.

[0131] In one embodiment, the display device further includes: a first reference voltage line that supplies a reference voltage to a third transistor, the first reference voltage line being in a source metal layer and extending in a second direction intersecting the first direction; and a second reference voltage line electrically connected to the first reference voltage line, the second reference voltage line being in a first light-blocking layer and extending in the first direction.

[0132] In one embodiment, the display device further includes: a first light emission control line in a gate layer extending in a first direction; and a fourth transistor receiving a first light emission signal from the first light emission control line and supplying a driving voltage to the drain electrode of the first transistor.

[0133] In one embodiment, the display device further includes: a first driving voltage line supplying a driving voltage, the first driving voltage line being in a source metal layer and extending in a second direction intersecting the first direction; and a second driving voltage line electrically connected to the first driving voltage line, the second driving voltage line being in a first light-blocking layer and extending in the first direction.

[0134] In one embodiment, the display device further includes: a second light emission control line in a gate layer extending in a first direction; and a fifth transistor receiving a second light emission signal from the second light emission control line, the fifth transistor electrically connecting the source electrode of the first transistor to a pixel electrode.

[0135] In one embodiment, the display device further includes: a third scan line in the gate layer extending in a first direction; and a sixth transistor receiving a third scan signal from the third scan line and supplying an initialization voltage to a pixel electrode.

[0136] In one embodiment, the display device further includes: a first initialization voltage line that supplies an initialization voltage to a sixth transistor, the first initialization voltage line being in a source metal layer and extending in a second direction intersecting the first direction; and a second initialization voltage line electrically connected to the first initialization voltage line, the second initialization voltage line being in a first light-blocking layer and extending in the first direction.

[0137] In one embodiment, the display device further includes: a second light-blocking layer between the first light-blocking layer and the active layer; and a first capacitor connected to the gate electrode and the source electrode of the first transistor, the first capacitor including: a first capacitor electrode electrically connected to the gate electrode of the first transistor and in the first light-blocking layer; and a second capacitor electrode electrically connected to the source electrode of the first transistor and in the second light-blocking layer.

[0138] In one embodiment, the first capacitor electrode and the second capacitor electrode of the first capacitor overlap with the semiconductor region of the first transistor.

[0139] In one embodiment, the first capacitor further includes: a third capacitor electrode electrically connected to the first capacitor electrode, the third capacitor electrode being in the gate layer and including the gate electrode of the first transistor; and a fourth capacitor electrode electrically connected to the second capacitor electrode, the fourth capacitor electrode being in the gate layer and facing the third capacitor electrode.

[0140] In one embodiment, the display device further includes: a second capacitor connected to a drive voltage line supplying a drive voltage and a source electrode of a first transistor, the second capacitor comprising: a first capacitor electrode in a first light-blocking layer and electrically connected to the drive voltage line; and a second capacitor electrode in a second light-blocking layer and electrically connected to the source electrode of the first transistor.

[0141] In one embodiment, the second capacitor electrode of the first capacitor and the second capacitor electrode of the second capacitor are integral with each other.

[0142] In one embodiment, the display device further includes: a second light-emitting control line that supplies a second light-emitting signal, the second light-emitting control line being in a gate layer and extending in a first direction; a fifth transistor that receives the second light-emitting signal and is connected to the source electrode of a first transistor; a source metal layer on the gate layer, the source metal layer including an anode connection electrode that is directly connected to the source electrode of the fifth transistor; and a pixel electrode on the source metal layer that is directly connected to the anode connection electrode.

[0143] In one embodiment, the display device further includes: a third scan line that supplies a third scan signal, the third scan line being in a gate layer and extending in a first direction; and a sixth transistor that receives the third scan signal and supplies an initialization voltage to a pixel electrode.

[0144] In one embodiment, the display device further includes: a second light-blocking layer between the first light-blocking layer and the active layer; and a first capacitor connected to the gate electrode and the source electrode of the first transistor, the first capacitor including: a first capacitor electrode in the first light-blocking layer and electrically connected to the gate electrode of the first transistor; and a second capacitor electrode in the second light-blocking layer and electrically connected to the source electrode of the first transistor.

[0145] In one embodiment, the first capacitor further includes: a third capacitor electrode electrically connected to the first capacitor electrode, the third capacitor electrode being in the gate layer and including the gate electrode of the first transistor; and a fourth capacitor electrode electrically connected to the second capacitor electrode, the fourth capacitor electrode being in the gate layer and facing the third capacitor electrode.

[0146] In one embodiment, the display device further includes: a second capacitor connected to the source electrode of the first transistor and a drive voltage line supplying a drive voltage, the second capacitor including: a first capacitor electrode in a first light-blocking layer and electrically connected to the drive voltage line; and a second capacitor electrode in a second light-blocking layer and electrically connected to the source electrode of the first transistor.

[0147] In one embodiment, the display device includes: a substrate; a first electrode and a first scan line of a first capacitor in the same layer on the substrate, the first electrode and the first scan line being spaced apart from each other; a first buffer layer covering the first electrode and the first scan line; an active layer on the first buffer layer, the active layer including a first semiconductor region of a driving transistor and a second semiconductor region of a light-emitting transistor; a second electrode of the first capacitor between the active layer and the first electrode of the first capacitor, the first buffer layer being between the first electrode and the second electrode of the first capacitor; a gate layer on the active layer, the gate layer including a gate electrode of a driving transistor and a gate electrode of a light-emitting transistor spaced apart from the gate electrode of the driving transistor; a first protective layer above the gate layer; a source metal layer on the first protective layer, the source metal layer including a connection electrode and an anode connection electrode spaced apart from the connection electrode, the connection electrode being connected to the gate electrode of the driving transistor and the first electrode of the first capacitor, and the anode connection electrode being directly connected to the active layer; a pixel electrode on the source metal layer, the pixel electrode being directly connected to the anode connection electrode; a light-emitting layer on the pixel electrode; and a common electrode on the light-emitting layer.

[0148] In one embodiment, at least a portion of the first scan line does not overlap with the first and second electrodes of the first capacitor.

[0149] In one embodiment, the active layer further includes: a drain electrode of a driving transistor on a first side of the first semiconductor region; a source electrode of a driving transistor on a second side of the first semiconductor region; a drain electrode of a light-emitting transistor on the first side of the second semiconductor region; and a source electrode of a light-emitting transistor on a second side of the second semiconductor region, wherein the source electrode of the driving transistor and the drain electrode of the light-emitting transistor are integral with each other.

[0150] In one embodiment, the anode connection electrode is directly connected to the source electrode of the light-emitting transistor.

[0151] In one embodiment, the display device further includes: a data transistor having a gate electrode connected to a first scan line, the data transistor supplying a data voltage to the gate electrode of a driving transistor; and a data line in a source metal layer, the data line supplying a data voltage to the data transistor.

[0152] In one embodiment, the first electrode of the first capacitor is connected to the gate electrode of the driving transistor, and the second electrode of the first capacitor is connected to the source electrode of the driving transistor and the drain electrode of the light-emitting transistor.

[0153] In the display device according to the embodiments of this specification, by including a source metal layer between the transistor of the pixel circuit and the pixel electrode of the light-emitting element, the number of masks in the manufacturing process can be reduced and the manufacturing cost can be lowered.

[0154] In the display device according to the embodiments of this specification, the process can be optimized by reducing the number of conductive layers.

[0155] However, the effects that can be obtained from this specification are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art to which this specification pertains based on the following description.

[0156] Although one embodiment has been described above with reference to the accompanying drawings, those skilled in the art will understand that the above-described technical configuration of the invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive. Furthermore, the scope of the specification is described by the appended claims rather than the detailed description. Additionally, the meaning and scope of the claims, as well as all changes or modifications derived from equivalent concepts, should be interpreted as being included within the scope of the specification.

[0157] Description of reference numerals in the attached figures

[0158] 10: Display device 100: Display panel

[0159] 200: Controller; 300: Gate drive unit

[0160] 400: Data Driven Unit; 500: Power Supply Unit

[0161] LS1: First light-blocking layer

[0162] LS2: Second light-blocking layer

[0163] ACTL: Active Layer; GTL: Gate Layer

[0164] SDL: Source metal layer; ED: Light-emitting element.

Claims

1. A display device, comprising: substrate; A first light-blocking layer on the substrate, the first light-blocking layer including a first scan line extending in a first direction; An active layer, the active layer including a semiconductor region of a first transistor, the active layer being on the first light-blocking layer; A gate layer, the gate layer including the gate electrode of the first transistor, the gate layer being on the active layer; The second transistor receives the first scan signal from the first scan line and supplies data voltage to the gate electrode of the first transistor; A source metal layer on the gate layer, the source metal layer including an anode connection electrode, the anode connection electrode being directly connected to the active layer and receiving a drive current flowing in the first transistor; The pixel electrode is located on the source metal layer and is directly connected to the anode connection electrode. The light-emitting layer on the pixel electrode; as well as The common electrode on the light-emitting layer.

2. The display device according to claim 1, further comprising: A data line supplying the data voltage is located in the source metal layer and extends in a second direction intersecting the first direction.

3. The display device according to claim 1, further comprising: A second scan line in the first light-blocking layer, the second scan line extending in the first direction; as well as A third transistor receives a second scan signal from the second scan line and supplies a reference voltage to the gate electrode of the first transistor.

4. The display device according to claim 3, further comprising: A first reference voltage line supplies the reference voltage to the third transistor, the first reference voltage line being in the source metal layer and extending in a second direction intersecting the first direction; as well as A second reference voltage line is electrically connected to the first reference voltage line, and the second reference voltage line is in the first light-blocking layer and extends in the first direction.

5. The display device according to claim 3, further comprising: A first light emission control line in the gate layer, the first light emission control line extending in the first direction; as well as A fourth transistor receives a first light-emitting signal from the first light-emitting control line and supplies a driving voltage to the drain electrode of the first transistor.

6. The display device according to claim 5, further comprising: A first driving voltage line supplies the driving voltage, and the first driving voltage line is in the source metal layer and extends in a second direction intersecting the first direction; as well as A second driving voltage line is electrically connected to the first driving voltage line, and the second driving voltage line is in the first light-blocking layer and extends in the first direction.

7. The display device according to claim 5, further comprising: A second light emission control line in the gate layer, the second light emission control line extending in the first direction; as well as A fifth transistor receives a second light emission signal from the second light emission control line, and the fifth transistor electrically connects the source electrode of the first transistor to the pixel electrode.

8. The display device according to claim 7, further comprising: A third scan line in the gate layer, the third scan line extending in the first direction; as well as The sixth transistor receives the third scan signal from the third scan line and supplies an initialization voltage to the pixel electrode.

9. The display device according to claim 8, further comprising: A first initialization voltage line supplies the initialization voltage to the sixth transistor, and the first initialization voltage line extends in the source metal layer and in a second direction intersecting the first direction; as well as A second initialization voltage line is electrically connected to the first initialization voltage line, and the second initialization voltage line is in the first light-blocking layer and extends in the first direction.

10. The display device according to claim 1, further comprising: A second light-blocking layer is located between the first light-blocking layer and the active layer; as well as A first capacitor, connected to the gate electrode and the source electrode of the first transistor, the first capacitor comprising: The first capacitor electrode of the first capacitor is electrically connected to the gate electrode of the first transistor and is located in the first light-blocking layer; as well as The second capacitor electrode of the first capacitor is electrically connected to the source electrode of the first transistor and is located in the second light-blocking layer.

11. The display device according to claim 10, wherein, The first capacitor electrode and the second capacitor electrode of the first capacitor overlap with the semiconductor region of the first transistor.

12. The display device according to claim 10, wherein, The first capacitor further includes: A third capacitor electrode, electrically connected to the first capacitor electrode, is located in the gate layer and includes the gate electrode of the first transistor; and A fourth capacitor electrode, which is electrically connected to the second capacitor electrode, is located in the gate layer and faces the third capacitor electrode.

13. The display device according to claim 10, further comprising: A second capacitor is connected to the drive voltage line supplying the drive voltage and the source electrode of the first transistor. The second capacitor includes: The first capacitor electrode of the second capacitor is located in the first light-blocking layer and is electrically connected to the driving voltage line; and The second capacitor electrode of the second capacitor is located in the second light-blocking layer and is electrically connected to the source electrode of the first transistor.

14. The display device according to claim 13, wherein, The second capacitor electrode of the first capacitor and the second capacitor electrode of the second capacitor are integral with each other.

15. A display device, comprising: substrate; A first light-blocking layer on the substrate; A first scan line, the first scan line supplies a first scan signal, the first scan line is in the first light blocking layer and extends in a first direction; A second scan line supplies a second scan signal, and the second scan line is in the first light-blocking layer and extends in the first direction; An active layer, the active layer including a semiconductor region of a first transistor, the active layer being on the first light-blocking layer; A gate layer, the gate layer including the gate electrode of the first transistor, the gate layer being on the active layer; A first light-emitting control line supplies a first light-emitting signal, and the first light-emitting control line is in the gate layer and extends in the first direction; The second transistor receives the first scan signal and supplies a data voltage to the gate electrode of the first transistor; A third transistor receives the second scan signal and supplies a reference voltage to the gate electrode of the first transistor; as well as A fourth transistor receives the first light-emitting signal and supplies a driving voltage to the drain electrode of the first transistor.

16. The display device according to claim 15, further comprising: The second light emission control line supplies a second light emission signal and is located in the gate layer and extends in the first direction. A fifth transistor, which receives the second light-emitting signal, is connected to the source electrode of the first transistor; A source metal layer on the gate layer, the source metal layer including an anode connection electrode, the anode connection electrode being directly connected to the source electrode of the fifth transistor; as well as The pixel electrode is located on the source metal layer and is directly connected to the anode connection electrode.

17. The display device according to claim 16, further comprising: A third scan line, which supplies a third scan signal, is in the gate layer and extends in the first direction; as well as A sixth transistor receives the third scan signal and supplies an initialization voltage to the pixel electrode.

18. The display device according to claim 15, further comprising: A second light-blocking layer is located between the first light-blocking layer and the active layer; as well as A first capacitor, connected to the gate electrode and the source electrode of the first transistor, the first capacitor comprising: The first capacitor electrode of the first capacitor is located in the first light-blocking layer and is electrically connected to the gate electrode of the first transistor. as well as The second capacitor electrode of the first capacitor is located in the second light-blocking layer and is electrically connected to the source electrode of the first transistor.

19. The display device according to claim 18, wherein, The first capacitor further includes: A third capacitor electrode, electrically connected to the first capacitor electrode, is located in the gate layer and includes the gate electrode of the first transistor; and A fourth capacitor electrode, which is electrically connected to the second capacitor electrode, is located in the gate layer and faces the third capacitor electrode.

20. The display device according to claim 18, further comprising: A second capacitor is connected to the source electrode of the first transistor and the drive voltage line supplying the drive voltage. The second capacitor includes: The first capacitor electrode of the second capacitor is located in the first light-blocking layer and is electrically connected to the driving voltage line; and The second capacitor electrode of the second capacitor is located in the second light-blocking layer and is electrically connected to the source electrode of the first transistor.

21. A display device, comprising: substrate; The first electrode and the first scan line of the first capacitor are in the same layer on the substrate, and the first electrode and the first scan line are spaced apart from each other. A first buffer layer covering the first electrode and the first scan line; An active layer on the first buffer layer, the active layer comprising a first semiconductor region for driving transistors and a second semiconductor region for light-emitting transistors; The second electrode of the first capacitor is located between the active layer and the first electrode of the first capacitor, and the first buffer layer is located between the first electrode of the first capacitor and the second electrode of the first capacitor. A gate layer on the active layer, the gate layer including the gate electrode of the driving transistor and the gate electrode of the light-emitting transistor spaced apart from the gate electrode of the driving transistor; A first protective layer above the gate layer; A source metal layer on the first protective layer, wherein the source metal layer includes a connection electrode and an anode connection electrode spaced apart from the connection electrode, the connection electrode being connected to the gate electrode of the driving transistor and the first electrode of the first capacitor, and the anode connection electrode being directly connected to the active layer; The pixel electrode is located on the source metal layer and is directly connected to the anode connection electrode. The light-emitting layer on the pixel electrode; as well as The common electrode on the light-emitting layer.

22. The display device according to claim 21, wherein, At least a portion of the first scan line does not overlap with the first electrode and the second electrode of the first capacitor.

23. The display device according to claim 21, wherein, The active layer further includes: The drain electrode of the driving transistor on the first side of the first semiconductor region; The source electrode of the driving transistor on the second side of the first semiconductor region; The drain electrode of the light-emitting transistor on the first side of the second semiconductor region; The source electrode of the light-emitting transistor on the second side of the second semiconductor region, The source electrode of the driving transistor and the drain electrode of the light-emitting transistor are integral to each other.

24. The display device according to claim 23, wherein, The anode connection electrode is directly connected to the source electrode of the light-emitting transistor.

25. The display device according to claim 21, further comprising: A data transistor having a gate electrode connected to the first scan line, the data transistor supplying a data voltage to the gate electrode of the driving transistor; as well as A data line, located in the source metal layer, supplies the data voltage to the data transistor.

26. The display device according to claim 23, wherein, The first electrode of the first capacitor is connected to the gate electrode of the driving transistor, and the second electrode of the first capacitor is connected to the source electrode of the driving transistor and the drain electrode of the light-emitting transistor.

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