Touch display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a touch display panel and a display device. The touch display panel comprises a substrate, a driving substrate and a light-emitting substrate, the driving substrate is arranged on one side of the substrate and comprises a plurality of signal lines; the light-emitting substrate is arranged on the side, away from the underlayer substrate, of the driving substrate and comprises a cathode layer, the cathode layer comprises a plurality of electrode blocks arranged at intervals, and the electrode blocks are electrically connected to the signal lines and reused as touch electrodes. According to the touch display panel, the touch function is achieved through the cathodes, it is avoided that a touch layer set is arranged on the side, away from the substrate, of the packaging layer set, the number of film layers of the display panel is reduced, and therefore the patterning process is reduced, the cost is reduced, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular, to a touch display panel and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Display) display panel as a new type of light-emitting device has great application potential in the field of display and lighting. In the field of display, OLED has the advantages of self-luminous, fast response, wide viewing angle, high brightness, lightness and thinness, etc., and thus has attracted strong attention in the industry.

[0003] However, at present, in order to realize the touch function of the OLED display panel, a touch layer group needs to be set, resulting in more film layers and more patterning processes.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art and provide a touch display panel and a display device.

[0006] According to one aspect of the present disclosure, a touch display panel is provided, comprising: a substrate substrate; a driving substrate provided on one side of the substrate substrate, the driving substrate comprising a plurality of signal lines; a light-emitting substrate provided on the side of the driving substrate away from the substrate substrate, the light-emitting substrate comprising a cathode layer, the cathode layer comprising a plurality of electrode blocks arranged at intervals, the electrode blocks being electrically connected to the signal lines, and the electrode blocks being multiplexed as touch electrodes.

[0007] In an exemplary embodiment of the present disclosure, the light-emitting substrate comprises: an anode layer provided on the side of the driving substrate away from the substrate substrate, the anode layer comprising anodes arranged at intervals and adapter portions, the electrode blocks being electrically connected to the adapter portions, and the adapter portions being electrically connected to the signal lines; a pixel definition layer provided on the side of the anode layer away from the substrate substrate, the pixel definition layer being provided with pixel opening portions and adapter opening portions, the pixel opening portions being communicated to the anodes, and the adapter opening portions being communicated to the adapter portions; A light-emitting layer group is disposed on the side of the pixel definition layer opposite to the substrate, at least a portion of the light-emitting layer group is located within the pixel opening, and the cathode layer is disposed on the side of the light-emitting layer group opposite to the substrate.

[0008] In one exemplary embodiment of this disclosure, the anode layer further includes a first partition ring, the transition portion is spaced apart within the first partition ring, the outer ring sidewall of the first partition ring is provided with a first undercut structure, and the electrode block covers the top surface of the first partition ring away from the substrate and is disconnected at the position of the first undercut structure, so that two adjacent electrode blocks are spaced apart.

[0009] In one exemplary embodiment of this disclosure, the driving substrate includes: The second partition ring has a second undercut structure on its outer ring sidewall. The electrode block covers the top surface of the second partition ring away from the substrate and is broken at the position of the second undercut structure so that adjacent electrode blocks are spaced apart.

[0010] In one exemplary embodiment of this disclosure, the driving substrate includes: A connecting conductor layer, the connecting conductor layer including the second isolation ring.

[0011] In one exemplary embodiment of this disclosure, the driving substrate includes: Connecting conductor layers, including a first sub-segmentation ring; An inorganic layer is disposed on the side of the connecting conductor layer opposite to the substrate. The inorganic layer includes a second sub-segment ring that protrudes from the first sub-segment ring in a first direction to form a second undercut structure. The first direction is parallel to the substrate.

[0012] In one exemplary embodiment of this disclosure, the driving substrate includes: An active layer is disposed on one side of the substrate. A gate insulating layer is disposed on the side of the active layer opposite to the substrate. A gate layer is disposed on the side of the gate insulating layer opposite to the substrate, and the gate layer includes the signal line, gate, source and drain disposed at intervals.

[0013] In one exemplary embodiment of this disclosure, the driving substrate includes: An active layer is disposed on one side of the substrate. A gate insulating layer is disposed on the side of the active layer opposite to the substrate. A gate layer is disposed on the side of the gate insulating layer opposite to the substrate, and the gate layer includes a gate. An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate. A connecting conductor layer group is disposed on the side of the interlayer dielectric layer opposite to the substrate, and the connecting conductor layer group includes the signal lines, source and drain arranged at intervals.

[0014] In one exemplary embodiment of this disclosure, the active layer is made of metal oxide or low-temperature polycrystalline silicon.

[0015] According to another aspect of this disclosure, a display device is provided, comprising: a touch display panel as described in any one of the preceding claims.

[0016] The touch display panel disclosed herein achieves touch functionality through a cathode, avoiding the need to place the touch layer group on the side of the encapsulation layer group away from the substrate, reducing the number of film layers in the display panel, thereby reducing patterning processes, and thus reducing costs and improving production efficiency.

[0017] The touch display panel disclosed herein achieves touch functionality through a cathode, avoiding the need to place the touch layer group on the side of the encapsulation layer group away from the substrate, reducing the number of film layers in the display panel, thereby reducing patterning processes, and thus reducing costs and improving production efficiency.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 This is a schematic diagram of the structure of the cathode and signal lines in the touch display panel of this disclosure.

[0021] Figure 2 In accordance with Figure 1 A schematic diagram of the structure of the first example implementation of the AA section.

[0022] Figure 3 In accordance with Figure 1 A schematic diagram of the structure of the second example implementation of the AA section.

[0023] Figure 4 In accordance with Figure 1 The diagram shows the structure of the third example implementation of the AA section.

[0024] Figure 5 In accordance with Figure 1 The diagram shows the structure of the fourth example implementation of the AA section.

[0025] Figure 6 In accordance with Figure 1 The diagram shows the structure of the fifth example implementation of the AA section.

[0026] Figure 7 In accordance with Figure 1 The diagram shows the structure of the sixth example implementation of the AA section.

[0027] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Driving substrate; 21. Light-shielding layer; 211. Light-shielding portion; 22. Buffer layer; 221. First buffer film layer; 222. Second buffer film layer; 23. Active layer; 24. Gate insulating layer; 25. Gate layer; 251. Gate; 26. Interlayer dielectric layer; 261. First dielectric layer; 262. Second dielectric layer; 27. Connecting conductor layer group; 27a. Connecting conductor layer; 27a1. First sub-isolation ring; 271. First connecting conductor layer; 2711. Source; 2712. Drain; 272. First planarization layer; 273. Second connecting conductor layer; 274. Second planarization layer; 28. Signal line; 29. ​​Second isolation ring; 291. Second undercut structure; 210. Inorganic layer; 2101. Second sub-isolation ring; 3. Light-emitting substrate; 31. Anode layer; 311. Anode; 312. Transition section; 313. First partition ring; 3131. First undercut structure; 32. Pixel definition layer; 33. Light-emitting layer group; 331. Common layer; 34. Cathode layer; 341. Electrode block; X, the first direction. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0029] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0030] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0031] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0032] This disclosure provides an example embodiment of a touch display panel, with reference to... Figures 1-7 As shown, Figure 1 The black dots in the diagram represent the connection points between the electrode block 341 and the signal line 28. The touch display panel may include a substrate 1, a driving substrate 2, and a light-emitting substrate 3. The driving substrate 2 is disposed on one side of the substrate 1 and may include multiple signal lines 28. The light-emitting substrate 3 is disposed on the side of the driving substrate 2 away from the substrate 1 and may include a cathode layer 34. The cathode layer 34 may include multiple spaced electrode blocks 341. The electrode blocks 341 are electrically connected to the signal lines 28 and are reused as touch electrodes.

[0033] The touch display panel disclosed herein achieves touch functionality through a cathode, avoiding the need to set the touch layer group on the side of the encapsulation layer group away from the substrate 1, reducing the number of film layers in the display panel, thereby reducing the patterning process, and thus reducing costs and improving production efficiency.

[0034] Reference Figures 2-7As shown, the display panel may include a substrate 1, a driving substrate 2, a light-emitting substrate 3, and an encapsulation layer assembly (not shown in the figure). The driving substrate 2 can drive the light-emitting substrate 3 to emit light. The driving substrate 2 is disposed on one side of the substrate 1, and the light-emitting substrate 3 is disposed on the side of the driving substrate 2 opposite to the substrate 1. An encapsulation layer assembly is disposed on the side of the light-emitting substrate 3 opposite to the substrate 1.

[0035] The display panel can be an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light-Emitting Diodes) display panel, a Micro-LED (Micro-light emitting diode) display panel, etc.; the display panel has a display side and a non-display side, which are arranged opposite to each other. The display side can display the image, and the side that displays the image is the display surface.

[0036] In this example embodiment, taking an OLED display panel as an example, the driving substrate 2 may include pixel circuits for multiple sub-pixels. Each sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit is used to drive the light-emitting element to emit light. The pixel circuit may include multiple thin-film transistors and capacitors.

[0037] Specifically, the material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layers may be made of any of the materials mentioned above. Of course, the substrate 1 may also be a single layer, and may be any of the materials mentioned above.

[0038] Reference Figures 2-7 As shown, a light-shielding layer 21 can be disposed on one side of the substrate 1. The light-shielding layer 21 may include a plurality of spaced-apart light-shielding portions 211. Light incident from the substrate 1 onto the active layer 23 causes the active layer 23 to generate photogenerated carriers, which in turn has a significant impact on the characteristics of the thin-film transistor, ultimately affecting the display quality of the display device. The light-shielding layer 21 can block the light incident from the substrate 1, thereby preventing the influence on the characteristics of the thin-film transistor and avoiding the impact on the display quality of the display device. Depending on the type of thin-film transistor, the light-shielding layer 21 may be omitted.

[0039] A buffer layer 22 can be formed on the side of the light-shielding layer 21 facing away from the substrate 1. The buffer layer 22 serves to block moisture and impurity ions in the substrate 1 (especially organic materials) and to increase hydrogen ions for the subsequently formed active layer 23. The buffer layer 22 is made of an insulating material to insulate the light-shielding layer 21 from the active layer 23. The buffer layer 22 may include silicon nitride, silicon oxide, or silicon oxynitride. Specifically, the buffer layer 22 may include a first buffer film layer 221 and a second buffer film layer 222. The first buffer film layer 221 is located on the side of the light-shielding layer 21 facing away from the substrate 1, and the second buffer film layer 222 is located on the side of the first buffer film layer 221 facing away from the substrate 1. The first buffer film layer 221 may be made of silicon nitride, and the second buffer film layer 222 may be made of silicon oxide. Depending on the type of substrate 1 or the process conditions, the buffer layer 22 may be omitted.

[0040] An active layer 23 is disposed on the side of the buffer layer 22 facing away from the substrate 1. The active layer 23 can be made of, but is not limited to, metal oxide semiconductor materials. The metal oxide semiconductor materials can include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxides (RE-OS), wherein the rare earth element-doped metal oxides can include lanthanide-doped metal oxides (Ln-OS). The crystal state of the active layer 23 can be amorphous, partially crystalline, or polycrystalline. For example, the active layer 23 can be made of low-temperature polycrystalline silicon. The active layer 23 can include a channel portion and conductive portions disposed at both ends of the channel portion. One of the two conductive portions is a source connection portion, and the other is a drain connection portion.

[0041] Reference Figures 2-7 As shown, a gate insulating layer 24 is disposed on the side of the active layer 23 facing away from the substrate 1. The gate insulating layer 24 may include silicon compounds, metal oxides, or the like. For example, the gate insulating layer 24 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used individually or in combination. The gate insulating layer 24 may be a single-layer film or a multilayer film, and the multilayer film is formed as a stacked structure of different materials.

[0042] A gate layer 25 is disposed on the side of the gate insulating layer 24 facing away from the substrate 1. The gate layer 25 may include a gate 251 and gate lines (not shown in the figure). The gate layer 25 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate layer 25 may be a single-layer film or a multilayer film.

[0043] Optionally, refer to Figure 2 and Figure 3 As shown, the gate layer 25 may further include a signal line 28, a source 2711, and a drain 2712. The gate 251, signal line 28, source 2711, and drain 2712 are all spaced apart and not connected. The source 2711 can be connected to the source 2711 connection portion of the active layer 23 through a via on the gate insulating layer 24. The drain 2712 can be connected to the drain 2712 connection portion of the active layer 23 through a via on the gate insulating layer 24. The drain 2712 can also be connected to the light-shielding portion 211 through vias on the gate insulating layer 24 and the buffer layer 22, so that the light-shielding portion 211 can serve as the bottom gate of the thin-film transistor, which can be a driving transistor for a pixel circuit.

[0044] Reference Figures 2-7 As shown, an interlayer dielectric layer 26 is disposed on the side of the gate layer 25 away from the substrate 1. For example, the interlayer dielectric layer 26 may include a first dielectric layer 261 and a second dielectric layer 262. The first dielectric layer 261 is disposed on the side of the gate layer 25 away from the substrate 1, and the second dielectric layer 262 is disposed on the side of the first dielectric layer 261 away from the substrate 1. The material of the first dielectric layer 261 may be silicon nitride, and the material of the second dielectric layer 262 may be silicon oxide.

[0045] Reference Figure 2 and Figure 3 As shown, vias are provided on the interlayer dielectric layer 26, and the vias are connected to the signal line 28 and the drain 2712 respectively. A first planarization layer 272 is provided on the side of the interlayer dielectric layer 26 facing away from the substrate 1.

[0046] Reference Figures 4-7 As shown, vias are provided on the interlayer dielectric layer 26 and the gate insulating layer 24, and the vias connect to the source connection portion or the drain connection portion. A first connection conductor layer 271 is provided on the side of the interlayer dielectric layer 26 facing away from the substrate 1. The first connection conductor layer 271 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first connection conductor layer 271 may be a single-layer film or a multilayer film. For example, the first connection conductor layer 271 may be a Ti / Al / Ti three-layer stacked structure, or a Mo / Al / Mo, Mo / AlGe / Mo, etc. three-layer stacked structure.

[0047] Reference Figures 4-6As shown, the first interconnect conductor layer 271 may include signal lines 28, a source 2711, a drain 2712, and data lines (not shown in the figure); thus enabling the driving substrate 2 to include multiple signal lines 28. The source 2711 is connected to the source connection portion through vias on the interlayer dielectric layer 26 and the gate insulating layer 24, and the drain 2712 is connected to the drain connection portion through vias on the interlayer dielectric layer 26 and the gate insulating layer 24.

[0048] Please continue to refer to Figures 4-6 As shown, a first planarization layer 272 is provided on the side of the first connecting conductor layer 271 facing away from the substrate 1. A via is provided on the first planarization layer 272, and the via is connected to the drain electrode 2712. The first planarization layer 272 is made of an organic material.

[0049] Of course, in some other exemplary embodiments of this disclosure, reference is made to Figure 7 As shown, a connecting conductor layer group 27 is provided on the side of the interlayer dielectric layer 26 facing away from the substrate 1. Specifically, a second connecting conductor layer 273 can also be provided on the side of the first planarization layer 272 facing away from the substrate 1. The second connecting conductor layer 273 is connected to the source 2711 or drain 2712 through vias on the first planarization layer 272. For example, the second connecting conductor layer 273 may include a second drain, which is connected to the drain through vias on the first planarization layer 272. In this case, the second connecting conductor layer 273 is a connecting conductor layer 27a, that is, the second connecting conductor layer 273 may include multiple signal lines 28, so that the driving substrate 2 may include multiple signal lines 28. Alternatively, a second planarization layer 274 can be provided on the side of the second connecting conductor layer 273 facing away from the substrate 1. The material of the second planarization layer 274 is an organic material. The connecting conductor layer group 27 may include a first connecting conductor layer 271, a first planarization layer 272, a second connecting conductor layer 273, and a second planarization layer 274, etc.

[0050] Alternatively, a third connection conductor layer can be provided on the side of the second planarization layer 274 facing away from the substrate 1. The third connection conductor layer is connected to the second connection conductor layer 273 through vias on the second planarization layer 274. For example, the third connection conductor layer may include a third drain, which is connected to the second drain through vias on the second planarization layer 274. The third planarization layer, made of an organic material, is provided on the side of the third connection conductor layer facing away from the substrate 1. In this case, the third connection conductor layer 27a is a connection conductor layer 27a, meaning it may include multiple signal lines 28, allowing the driving substrate 2 to include multiple signal lines 28.

[0051] In other example embodiments of this disclosure, the gate layer 25 may also be a connection conductor layer 27a, that is, the gate layer 25 may include a gate 251, a signal line 28, a source 2711, a drain 2712, and a data line. In this case, the first connection conductor layer 271 may not be provided.

[0052] The active layer 23, gate 251, source 2711 and drain 2712 form a thin film transistor.

[0053] It should be noted that the thin-film transistor described in this specification is a top-gate thin-film transistor. In other exemplary embodiments of this disclosure, the thin-film transistor may also be a bottom-gate or dual-gate type, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 2711" and "drain 2712" are sometimes interchanged. Therefore, in this specification, the "source 2711" and "drain 2712" can be interchanged.

[0054] Reference Figures 2-6 As shown, a light-emitting substrate 3 is disposed on the side of the first planarization layer 272 facing away from the substrate 1. The light-emitting substrate 3 may include an anode layer 31, a pixel definition layer 32, a light-emitting layer group 33, and a cathode layer 34. (Refer to...) Figure 7 As shown, a light-emitting substrate 3 is disposed on the side of the second planarization layer 274 away from the substrate 1.

[0055] Specifically, an anode layer 31 is provided on the side of the first planarization layer 272 away from the substrate 1. The anode layer 31 may include a plurality of anodes 311 arranged in an array. The anodes 311 are connected to the driving substrate 2. Specifically, the anodes 311 are connected to the drain 2712 of the thin film transistor through vias on the first planarization layer 272.

[0056] A pixel definition layer 32 is disposed on the side of the anode layer 31 facing away from the substrate 1, and a pixel opening is disposed on the pixel definition layer 32. A light-emitting layer group 33 is disposed on the side of the pixel definition layer 32 facing away from the substrate 1, and at least a portion of the light-emitting layer group 33 is located within the pixel opening. For example, a portion of the light-emitting layer group 33 may be located within the pixel opening. The light-emitting layer group 33 may include a common layer 331 and a light-emitting layer (not shown separately in the figure). The light-emitting layer is only disposed within the pixel opening, and the common layer 331 is disposed as a whole layer, that is, the common layer 331 is not only disposed within the pixel opening, but also disposed on the side of the pixel definition layer 32 facing away from the substrate 1. In this case, a via needs to be disposed on the common layer 331. The via on the common layer 331 can be formed by laser drilling. The diameter of the via is greater than or equal to 4 micrometers and less than or equal to 8 micrometers, so that the electrode block 341 can be electrically connected to the signal line 28 through the via. Alternatively, the entire light-emitting layer group 33 may be located within the pixel opening. The light-emitting layer group 33 is directly contacted and electrically connected to the anode 311, and the anode 311 provides an electrical signal to the light-emitting layer group 33. A cathode is disposed on the side of the light-emitting layer group 33 facing away from the substrate 1. The light-emitting layer group 33, anode 311 and cathode layer 34 in a pixel opening form the light-emitting element of a sub-pixel, and the display panel may include multiple sub-pixels.

[0057] The light-emitting layer group 33 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer stacked sequentially. The hole injection layer is in contact with the anode 311, and the electron injection layer is in contact with the cathode layer 34. The common layer 331 may include the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer. Of course, in other exemplary embodiments of this disclosure, the light-emitting layer group may only include a hole transport layer, a light-emitting layer, and an electron transport layer. The light-emitting layer group may also have other structures, and its specific structure can be set as needed.

[0058] Reference Figure 1 As shown, the cathode layer 34 may include a plurality of spaced-apart electrode blocks 341, which may be arranged in an array. The electrode blocks 341 are electrically connected to signal lines 28, through which electrical signals are transmitted to the electrode blocks 341. Each electrode block 341 is electrically connected to at least one signal line 28; for example, one electrode block 341 may be electrically connected to one signal line 28, or one electrode block 341 may be electrically connected to two, three, or more signal lines 28.

[0059] Electrode block 341 can be reused as a touch electrode; that is, when implementing the display function, electrode block 341 is used as a cathode, and signal line 28 can be used as a cathode line, transmitting a common (COM) signal to electrode block 341 through signal line 28; when implementing the touch function, electrode block 341 is used as a touch electrode, and signal line 28 can be used as a touch trace, transmitting touch signals to electrode block 341 through signal line 28. This configuration, achieving touch function through the cathode, avoids placing the touch layer group on the side of the encapsulation layer group away from the substrate 1, reduces the number of film layers in the display panel, thereby reducing patterning processes, and ultimately lowering costs and improving production efficiency.

[0060] Since electrode block 341 can be reused as a touch electrode, it needs to be arranged in blocks. The side length of electrode block 341 is greater than or equal to 3.8 mm and less than or equal to 4.5 mm. For example, the side length of electrode block 341 can be 3.9 mm, 4 mm, 4.1 mm, 4.2 mm, 4.3 mm, 4.4 mm, etc. The side length of a pixel (a pixel includes three sub-pixels) is greater than or equal to 50 micrometers and less than or equal to 75 micrometers. For example, the side length of a pixel can be 52 micrometers, 55 micrometers, 57 micrometers, 60 micrometers, 63 micrometers, 65 micrometers, 68 micrometers, 70 micrometers, 72 micrometers, etc. The number of pixels that one electrode block 341 can cover is greater than or equal to 50×50 and less than or equal to 90×90, that is, one electrode block 341 can be arranged opposite to 50×50 and less than or equal to 90×90 anodes 311.

[0061] When electrode block 341 is used as a touch electrode, it forms a self-capacitive touch structure. A uniform electric field can be applied to electrode block 341. When a finger touches the display panel, a new capacitive coupling path is formed between the finger and electrode block 341 due to the charge on the human body. This path is connected in parallel with the original capacitor system, increasing the total capacitance. The touch controller periodically scans electrode block 341 to detect changes in capacitance. Near the touch point, the capacitance increases significantly due to the introduction of the finger; outside the touch point, the capacitance remains unchanged. By measuring the change in capacitance, the touch controller can calculate the finger's position coordinates. The self-capacitive touch structure sequentially detects the horizontal and vertical electrode arrays, determines the horizontal and vertical coordinates based on the capacitance changes before and after the touch, and then combines them into planar touch coordinates.

[0062] The edge of the electrode block 341 can be set as a sawtooth shape, and the size of two adjacent sawtooths can be the same or different; the edges of two adjacent electrode blocks 341 are basically parallel.

[0063] In some exemplary embodiments of this disclosure, reference is made to Figures 2-4As shown, the anode layer 31 may include a transition portion 312, which is spaced apart from the anode 311, meaning there is a gap between the transition portion 312 and the anode 311, and they are not connected. The electrode block 341 is electrically connected to the transition portion 312. Specifically, a transition opening is provided on the pixel definition layer 32, and the transition opening connects to the transition portion 312. That is, the transition portion 312 is not covered by the pixel definition layer 32, and the electrode block 341 can cover the transition portion 312, thereby achieving the connection between the electrode block 341 and the electrical transition portion 312. The transition portion 312 is electrically connected to the signal line 28. Specifically, vias are provided on the first planarization layer 272 and the interlayer dielectric layer 26, and the vias connect to the signal line 28. The transition portion 312 is connected to the signal line 28 through these vias. The size of the adapter 312 can be greater than or equal to 16 micrometers and less than or equal to 32 micrometers. For example, the size of the adapter 312 can be 18 micrometers, 20 micrometers, 22 micrometers, 25 micrometers, 27 micrometers, 30 micrometers, etc.

[0064] In some exemplary embodiments of this disclosure, the cathode material layer can be patterned to form a plurality of spaced electrode blocks 341. For example, the cathode material layer can be laser-cut to form a plurality of spaced electrode blocks 341, or a plurality of spaced electrode blocks 341 can be formed by photolithography, dry etching or other processes.

[0065] In some exemplary embodiments of this disclosure, multiple spaced electrode blocks 341 can be formed without patterning the cathode material layer, thereby reducing one patterning process, further reducing costs and improving production efficiency, as described below.

[0066] In some exemplary embodiments of this disclosure, reference is made to Figure 3 and Figure 4 As shown, the anode layer 31 may also include a first partition ring 313, and a transition portion 312 is spaced within the first partition ring 313, that is, there is a gap between the first partition ring 313 and the transition portion 312, and they are not connected; the transition portion 312 is located within the first partition ring 313.

[0067] Under normal circumstances, the first isolation ring 313 is not electrically connected, that is, the first isolation ring 313 does not conduct electrical signals.

[0068] The outer ring sidewall of the first partition ring 313 is provided with a first undercut structure 3131, that is, the first partition ring 313 is provided with a first undercut structure 3131 away from the outer ring sidewall of the transition part 312. Specifically, the first undercut structure 3131 includes a first film layer and a second film layer. The first film layer is provided on the side of the driving substrate 2 away from the substrate 1, and the second film layer is provided on the side of the first film layer away from the substrate 1. The second film layer protrudes from the first film layer in the first direction X, thereby forming the first undercut structure 3131. The electrode block 341 covers the top surface of the first partition ring 313 away from the substrate 1 and is interrupted at the position of the first undercut structure 3131, so that two adjacent electrode blocks 341 are spaced apart. The first partition ring 313 is used to divide the cathode material layer to form multiple electrode blocks 341. The orthographic projection of the outer ring surface of the first partition ring 313 on the substrate coincides with the edge line of the orthographic projection of the electrode block 341 on the substrate.

[0069] The second film layer protrudes from the first film layer in the first direction X by a size greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers. For example, the size of the second film layer protruding from the first film layer in the first direction X can be 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, etc.

[0070] If the second film layer protrudes too small from the first film layer in the first direction X, it will not function as a barrier electrode block 341. If the second film layer protrudes too large from the first film layer in the first direction X, it is difficult to achieve in the fabrication process, and the second film layer is prone to collapse at the position of the first undercut structure 3131, thus also failing to function as a barrier electrode block 341. Within the above-mentioned numerical range, it is easy to achieve in the fabrication process, the second film layer is not prone to collapse at the position of the first undercut structure 3131, and it can function as a barrier electrode block 341.

[0071] It should be noted that the first direction X is parallel to the substrate 1. Specifically, the first direction X is parallel to one side of the substrate 1 where the driving substrate 2 is disposed. The first direction X can be multiple directions parallel to the substrate 1.

[0072] In this case, the anode layer 31 can be a two-layer stacked structure, for example, the anode layer 31 can be MoNb / Cu; the anode layer 31 can also be a three-layer stacked structure, for example, the anode layer 31 can be ITO / Ag / ITO, WOx / Ag / ITO (WOx is closer to the substrate), etc. When the anode 311 material layer is patterned to form the anode 311, the transition portion 312, and the first isolation ring 313, the exposed outer ring sidewall of the first isolation ring 313 is selectively etched, so that the intermediate film layer or the film layer closer to the substrate 1 is etched, thereby forming the first undercut structure 3131. The inner ring sidewall of the anode 311, the transition portion 312, and the first isolation ring 313 can be covered by the pixel definition layer 32, and will not be selectively etched, thus not forming an undercut structure.

[0073] In other example embodiments of this disclosure, reference is made to Figures 5-7 As shown, the driving substrate 2 may include a second partition ring 29. The outer ring sidewall of the second partition ring 29 is provided with a second undercut structure 291. Specifically, the second undercut structure 291 may include a third film layer and a fourth film layer. The third film layer is disposed on one side of the substrate 1, and the fourth film layer is disposed on the side of the third film layer facing away from the substrate 1. The fourth film layer protrudes from the third film layer in the first direction X, thereby forming the second undercut structure 291. Electrode blocks 341 cover the top surface of the second partition ring 29 facing away from the substrate 1 and are interrupted at the position of the second undercut structure 291, so that adjacent electrode blocks 341 are spaced apart. The second partition ring 29 is used to partition the cathode material layer to form multiple electrode blocks 341. The orthographic projection of the outer ring surface of the second partition ring 29 onto the substrate coincides with the edge line of the orthographic projection of the electrode block 341 onto the substrate.

[0074] Under normal circumstances, the second isolation ring 29 is not electrically connected, that is, the second isolation ring 29 does not conduct electrical signals.

[0075] The fourth film layer protrudes from the third film layer in the first direction X by a size greater than or equal to 0.5 micrometers and less than or equal to 2 micrometers. For example, the size of the fourth film layer protruding from the third film layer in the first direction X can be 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, etc.

[0076] If the fourth film layer protrudes too little from the third film layer in the first direction X, it will not function as the barrier electrode block 341. If the fourth film layer protrudes too much from the third film layer in the first direction X, it is difficult to achieve in the fabrication process, and the fourth film layer is prone to collapse at the position of the second undercut structure 291, thus also failing to function as the barrier electrode block 341. Within the above-mentioned numerical range, it is easy to achieve in the fabrication process, the fourth film layer is not prone to collapse at the position of the second undercut structure 291, and it can function as the barrier electrode block 341.

[0077] Alternatively, the connecting conductor layer 27a may include a second isolation ring 29. The first connecting conductor layer 271 may be the connecting conductor layer 27a, the second connecting conductor layer 273 may also be the connecting conductor layer 27a, and the third connecting conductor layer 27a may also be the connecting conductor layer 27a.

[0078] Specifically, refer to Figure 5 As shown, when only the first connecting conductor layer 271 is provided, the first connecting conductor layer 271 may include a source electrode 2711, a drain electrode 2712, and a second isolation ring 29 spaced apart, that is, there is no connection between the source electrode 2711, the drain electrode 2712, and the second isolation ring 29. When the first connecting conductor layer 271 and the second connecting conductor layer 273 are provided, the second connecting conductor layer 273 may include a second isolation ring 29 spaced apart and a second drain electrode. When the first connecting conductor layer 271, the second connecting conductor layer 273, and the third connecting conductor layer are provided, the third connecting conductor layer may include a second isolation ring 29 spaced apart and a third drain electrode.

[0079] In this case, the connecting conductor layer 27a can be a two-layer stacked structure, for example, the connecting conductor layer 27a can be MoNb / Cu; the connecting conductor layer 27a can also be a three-layer stacked structure, for example, the connecting conductor layer 27a can be Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Mo / NbAl / Mo, etc. When the first connecting conductor material layer is patterned to form the source 2711, drain 2712, and second isolation ring 29, the exposed outer ring sidewall of the second isolation ring 29 is selectively etched, so that the intermediate film layer or the film layer closer to the substrate 1 is etched, thereby forming the second undercut structure 291. The source 2711, drain 2712, and inner ring sidewall of the second isolation ring 29 can be covered by the first planarization layer 272, and will not be selectively etched, thus preventing the formation of an undercut structure.

[0080] Alternatively, the connecting conductor layer 27a may include a first sub-isolation ring 27a1; the first connecting conductor layer 271 may be the connecting conductor layer 27a, the second connecting conductor layer 273 may also be the connecting conductor layer 27a, and the third connecting conductor layer 27a may also be the connecting conductor layer 27a.

[0081] Specifically, refer to Figure 6 As shown, when only the first connecting conductor layer 271 is provided, the first connecting conductor layer 271 may include a source electrode 2711, a drain electrode 2712, and a first sub-isolation ring 27a1 arranged at intervals, that is, there is no connection between the source electrode 2711, the drain electrode 2712, and the first sub-isolation ring 27a1. (Refer to...) Figure 7As shown, when a first connecting conductor layer 271 and a second connecting conductor layer 273 are provided, the second connecting conductor layer 273 may include a first sub-isolation ring 27a1 and a second drain electrode arranged at intervals. When a first connecting conductor layer 271, a second connecting conductor layer 273, and a third connecting conductor layer are provided, the third connecting conductor layer may include a first sub-isolation ring 27a1 and a third drain electrode arranged at intervals.

[0082] Reference Figure 6 and Figure 7 As shown, the inorganic layer 210 is disposed on the side of the connecting conductor layer 27a away from the substrate 1. The inorganic layer 210 may include a second sub-partition ring 2101, which protrudes from the first sub-partition ring 27a1 in the first direction X to form a second undercut structure 291. The thickness of the inorganic layer 210 is greater than or equal to 0.3 micrometers and less than or equal to 3 micrometers. For example, the thickness of the inorganic layer 210 may be 0.5 micrometers, 0.8 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, 2.5 micrometers, 2.8 micrometers, etc.

[0083] Specifically, the inorganic layer 210 can be disposed on the side of the first connecting conductor layer 271 facing away from the substrate 1, so that the inorganic layer 210 and the first connecting conductor layer 271 are in direct contact to form the second undercut structure 291. (Refer to...) Figure 6 As shown, the inorganic layer 210 can be disposed on the side of the first planarization layer 272 away from the substrate 1. In this case, the first planarization layer 272 may include a plurality of first planarization portions. The first planarization portions are disposed in the second partition ring 29, that is, the first planarization layer 272 is removed at the position of the second partition ring 29, so that the inorganic layer 210 directly contacts the first sub-partition ring 27a1 of the first connecting conductor layer 271 to form the second undercut structure 291.

[0084] Reference Figure 7 As shown, the inorganic layer 210 can be disposed on the side of the second planarization layer 274 away from the substrate 1. In this case, the second planarization layer 274 can include a plurality of second planar portions. The second planar portions are disposed in the second partition ring 29, that is, the second planarization layer 274 is removed at the position of the second partition ring 29, so that the inorganic layer 210 directly contacts the first sub-partition ring 27a1 of the second connecting conductor layer 273 to form the second undercut structure 291.

[0085] Reference Figures 5-7 As shown, when the connecting conductor layer 27a includes the second isolation ring 29, the adapter can be omitted, that is, the electrode block 341 is directly connected to the signal line 28.

[0086] The display panel may also include an encapsulation layer group. An encapsulation layer group is disposed on the side of the second electrode away from the substrate 1. The encapsulation layer group is used to encapsulate the display panel, preventing external moisture, impurities, etc., from entering the display panel and affecting its display effect. The encapsulation layer group can be multi-layered, and may include organic and inorganic encapsulation layers. Specifically, the encapsulation layer group may include a first inorganic encapsulation layer, an organic encapsulation layer disposed on the side of the first inorganic encapsulation layer away from the substrate 1, and a second inorganic encapsulation layer disposed on the side of the organic encapsulation layer away from the substrate 1. The materials of the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer will not be described in detail here. Of course, the encapsulation layer group may also include more or fewer layers.

[0087] Based on the same inventive concept, this disclosure provides a display device that may include any of the above-described touch display panels. The specific structure of the touch display panel has been described in detail above, and therefore will not be repeated here.

[0088] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0089] It should be noted that, in addition to the touch display panel, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0090] Compared with the prior art, the beneficial effects of the display device provided by the example embodiments of the present invention are the same as the beneficial effects of the touch display panel provided by the example embodiments described above, and will not be repeated here.

[0091] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments, and the features discussed in the various embodiments are interchangeable where possible. In the above description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0092] The terms “about” or “approximately” as used in this specification generally mean within 20%, preferably within 10%, and even more preferably within 5% of a given value or range. The quantities given here are approximate, meaning that unless otherwise specified, the meanings of “about,” “approximately,” “roughly,” or “approximately” are implied.

[0093] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A touch display panel, characterized in that, include: Substrate; A driving substrate is disposed on one side of the substrate, and the driving substrate includes multiple signal lines; A light-emitting substrate is disposed on the side of the driving substrate opposite to the substrate. The light-emitting substrate includes a cathode layer, and the cathode layer includes a plurality of spaced electrode blocks. The electrode blocks are electrically connected to the signal lines and are multiplexed as touch electrodes.

2. The touch display panel according to claim 1, characterized in that, The light-emitting substrate includes: An anode layer is disposed on the side of the driving substrate opposite to the substrate. The anode layer includes anodes and a transition portion disposed at intervals. The electrode block is electrically connected to the transition portion, and the transition portion is electrically connected to the signal line. A pixel definition layer is disposed on the side of the anode layer opposite to the substrate. The pixel definition layer is provided with a pixel opening and a transition opening. The pixel opening is connected to the anode, and the transition opening is connected to the transition opening. A light-emitting layer group is disposed on the side of the pixel definition layer opposite to the substrate, at least a portion of the light-emitting layer group is located within the pixel opening, and the cathode layer is disposed on the side of the light-emitting layer group opposite to the substrate.

3. The touch display panel according to claim 2, characterized in that, The anode layer further includes a first partition ring, the transition portion is spaced within the first partition ring, the outer ring sidewall of the first partition ring is provided with a first undercut structure, the electrode block covers the top surface of the first partition ring away from the substrate and is disconnected at the position of the first undercut structure, so that two adjacent electrode blocks are spaced apart.

4. The touch display panel according to claim 1, characterized in that, The driving substrate includes: The second partition ring has a second undercut structure on its outer ring sidewall. The electrode block covers the top surface of the second partition ring away from the substrate and is broken at the position of the second undercut structure so that adjacent electrode blocks are spaced apart.

5. The touch display panel according to claim 4, characterized in that, The driving substrate includes: A connecting conductor layer, the connecting conductor layer including the second isolation ring.

6. The touch display panel according to claim 4, characterized in that, The driving substrate includes: Connecting conductor layers, including a first sub-segmentation ring; An inorganic layer is disposed on the side of the connecting conductor layer opposite to the substrate. The inorganic layer includes a second sub-segment ring that protrudes from the first sub-segment ring in a first direction to form a second undercut structure. The first direction is parallel to the substrate.

7. The touch display panel according to claim 1, characterized in that, The driving substrate includes: An active layer is disposed on one side of the substrate. A gate insulating layer is disposed on the side of the active layer opposite to the substrate. A gate layer is disposed on the side of the gate insulating layer opposite to the substrate, and the gate layer includes the signal line, gate, source and drain disposed at intervals.

8. The touch display panel according to claim 1, characterized in that, The driving substrate includes: An active layer is disposed on one side of the substrate. A gate insulating layer is disposed on the side of the active layer opposite to the substrate. A gate layer is disposed on the side of the gate insulating layer opposite to the substrate, and the gate layer includes a gate. An interlayer dielectric layer is disposed on the side of the gate layer opposite to the substrate. A connecting conductor layer group is disposed on the side of the interlayer dielectric layer opposite to the substrate, and the connecting conductor layer group includes the signal lines, source and drain arranged at intervals.

9. The touch display panel according to claim 7 or 8, characterized in that, The active layer is made of metal oxide or low-temperature polycrystalline silicon.

10. A display device, characterized in that, include: The touch display panel according to any one of claims 1 to 9.

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