Device package

Abstract

A device package includes a first tier, a second tier stacked on the first tier, and a tier via singly penetrating the first and second tiers. The first level includes a first device and a first interconnect line structure electrically coupled to the first device, the first interconnect line structure including a first metal layer and the first metal layer including a first connection branch. The second level includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure including a second metal layer and the second metal layer including a second connection branch. A hierarchical via is electrically coupled to the first and second connection branches.

Description

Technical Field

[0001] This application relates to a device package, and more particularly to a device package including hierarchical through-holes for electrically connecting stacked layers. Background Technology

[0002] Three-dimensional (3D) device packages typically consist of multiple stacked layers. Upper layers in a 3D device package can be connected to lower layers using various configurations, including through-silicon vias (TSVs) and / or hybrid bonding. The manufacturing of 3D device packages aims to be more efficient and cost-effective, while providing more devices in a smaller package. Therefore, continuous efforts are being made to develop new mechanisms to create device packages with better reliability and performance. Summary of the Invention

[0003] According to one embodiment of this application, a device package includes a first layer, a second layer stacked on the first layer, and a single hierarchical via penetrating both the first and second layers. The first layer includes a first device and a first interconnect structure electrically coupled to the first device. The first interconnect structure includes a first metal layer and a first connection branch. The second layer includes a second device and a second interconnect structure electrically coupled to the second device. The second interconnect structure includes a second metal layer and a second connection branch. The hierarchical via is electrically coupled to the first and second connection branches.

[0004] According to another embodiment of this application, a device package includes a first bonding pair, N second bonding pairs stacked on the first bonding pair, and a hierarchical via. The first bonding pair includes a bottom layer and a first layer stacked on the bottom layer. The bottom layer includes a bottom device and a front redistribution layer (RDL) electrically coupled to the bottom device. The first layer includes a first device and a first connection branch electrically coupled to the first device. Each of the N second bonding pairs includes a second layer and a third layer stacked on the second layer. The second layer includes a second device and a second connection branch electrically coupled to the second device, and the third layer includes a third device and a third connection branch electrically coupled to the third device. The hierarchical vias unilaterally penetrate the N second bonding pairs and the first layer of the first bonding pair, and the hierarchical vias are electrically coupled to the front RDL and the first, second, and third connection branches, where N ≥ 1.

[0005] Based on the above, the device package of this application includes hierarchical vias passing through multiple layers overlying the bottom layer. Because the thickness of each layer above the bottom layer is reduced, the hierarchical vias passing through these layers with reduced thickness can be shortened, thereby reducing the resistance of the hierarchical vias. Furthermore, because the overall thickness of the device package is reduced, the aspect ratio of each hierarchical via can be reduced, and a closer spacing and higher interconnect density between adjacent hierarchical vias can be achieved. In addition, the hierarchical vias can pass only through the dielectric material in each layer overlying the bottom layer, thus obtaining a more uniform profile for each hierarchical via. Attached Figure Description

[0006] To further understand this application, the accompanying drawings are included and incorporated in, and constitute a part of, this specification. The drawings illustrate exemplary embodiments of the present application and, together with the specification, serve to explain the principles of the present application.

[0007] Figures 1 to 3 A schematic cross-sectional view of a device package according to various embodiments of this application is shown.

[0008] Figure 4A , 4B Figures 4D to 4E, 4G, 4I to 4J and 4L show schematic cross-sectional views of a method for forming an apparatus package according to some embodiments of this application.

[0009] Figure 4C , 4F 4H and 4K respectively illustrate some embodiments according to this application. Figure 4B , 4E Schematic and exemplary unfolded diagrams of 4G and 4J.

[0010] Figures 5A to 5H A schematic cross-sectional view of a method for forming an apparatus package according to some embodiments of this application is shown.

[0011] Figures 6A to 6H A schematic cross-sectional view of a method for forming an apparatus package according to some embodiments of this application is shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for achieving various features of the provided inventive objectives. Specific examples of components and arrangements are described below to simplify this disclosure. The specific examples described above are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, component symbols and / or letters may be repeated in various examples in this disclosure. The repetition above is for simplicity and clarity and does not in itself limit the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document uses spatially related terms such as "below" and "above" to describe the relationship between one component or feature and another, as shown in the figure. In addition to the orientations depicted in the figure, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptions used herein can be interpreted accordingly.

[0014] As used herein, terms such as “first” and “second” describe various components, parts, regions, layers, and / or portions, which should not be limited by these terms. These terms may be used only to distinguish one component, part, region, layer, or portion from another. Terms such as “first” and “second” as used herein do not imply order or ranking unless the context clearly indicates otherwise.

[0015] Three-dimensional integrated circuits (3DICs) have been developed in which at least two IC layers (e.g., wafers or dies) can be stacked. To enable the integration of various devices within each stacked layer, electrical connections providing conductors between vertical layers are provided. Typically, through-substrate vias (TSVs) are fabricated to provide vias filled with conductive material, which traverse the layer to connect to conductors in other TSVs and bonding layers. In some comparative embodiments, each layer of a 3DIC includes a substrate, active devices formed in / on the substrate, and oxide trenches formed in the substrate. The TSVs of the 3DIC traverse the oxide trenches without contacting the substrate to reduce leakage risk, and the TSVs also traverse the interconnect dielectric layers of each layer to adjacent layers. However, because each layer must contain a substrate, this 3DIC configuration cannot achieve thinner thicknesses. Furthermore, this configuration of 3DIC lacks dummy patterns in the oxide trenches, leading to inhomogeneities after planarization processes (such as chemical mechanical polishing, CMP) are performed on the TSV, oxide trenches, and substrate.

[0016] Therefore, in some embodiments of this application, a device package and a method for forming a device package are provided, wherein a substrate and oxide trenches overlying a plurality of layers in a bottom layer can be removed, thereby reducing the overall thickness of the device package. By omitting the oxide trenches, manufacturing steps and costs are reduced, and problems caused by filling trenches in the substrate to form oxide trenches are eliminated. The device package may include one or more vias passing through a plurality of layers overlying a bottom layer. Because the thickness of each layer above the bottom layer is reduced, the vias passing through these layers with reduced thicknesses are shortened, thereby reducing the resistance of the vias. Furthermore, because the overall thickness of the device package is reduced, the aspect ratio of the individual vias can be reduced, and closer spacing and higher interconnect density between adjacent vias can be achieved. Additionally, the vias may pass only through the dielectric material overlying each layer in the bottom layer, thus obtaining a more uniform profile for the individual vias.

[0017] Figures 1 to 3 A schematic cross-sectional view of a device package according to various embodiments of this application is shown. Reference Figure 1 A device package 10 is provided, comprising multiple stacked levels. It should be noted that... Figure 1The device package 10 shown has a four-level structure for illustrative purposes only. According to some embodiments, the device package may include two, three, or more levels. For example, the device package 10 includes a bottom level 100, a first level 200 stacked on and bonded to the bottom level 100, a second level 300 stacked on and bonded to the first level 200, and a third level 400 stacked on and bonded to the second level 300. The bottom level 100 includes a bottom substrate 102, one or more bottom devices 104 formed in / on the bottom substrate 102, a bottom interconnect structure 106 formed over the bottom substrate 102 and covering the bottom devices 104, and one or more first devices CAP1 formed in the bottom interconnect structure 106. The first devices CAP1 can be electrically coupled to the bottom devices 104 via the bottom interconnect structure 106. In some embodiments, bottom device 104 may be referred to as a logic device including transistors formed on a semiconductor substrate (e.g., bottom substrate 102). First device CAP1 may be referred to as a passive device, such as a capacitor or inductor formed above bottom substrate 102. In some embodiments, first device CAP1 is formed within bottom interconnect structure 106 and does not directly contact bottom substrate 102. In some embodiments, bottom layer 100 may include logic devices, passive devices (e.g., capacitors, inductors), logic devices accompanying passive devices, and / or the like. In some embodiments, bottom layer 104 may include logic device 104 without additionally formed passive devices (e.g., first device CAP1). In some embodiments, bottom layer 100 may include a front redistribution layer FRDL1 in bottom interconnect structure 106 and electrically coupled to bottom device 104 and first device CAP1.

[0018] The first layer 200 of the device package 10 may include a first interconnect structure 206 and one or more second devices CAP2 formed in the first interconnect structure 206. The first layer 200 includes a front side 200F bonded to a front side 100F of the bottom layer 100 and a back side 200B bonded to a front side 300F of the second layer 300. A front-to-front bonding interface FF1 is formed between the bottom layer 100 and the first layer 200, and a front-to-back bonding interface FB1 is formed between the second layer 300 and the first layer 200. That is, the bottom layer 100 and the first layer 200 are bonded in a front-to-front configuration, while the second layer 300 and the first layer 200 are bonded in a front-to-back configuration. For example, in a front-to-back configuration, the metal layer M3 in the second layer 300 is close to the front-to-back bonding interface FB1, while the metal layer M3 in the first layer 200 is far from the front-to-back bonding interface FB1. In some embodiments, the metal layer M3 may be referred to as the topmost metal layer in each interconnect structure and close to the front side of each layer.

[0019] The second layer 300 and the third layer 400 are similar to the first layer 200. For example, the second layer 300 includes a second interconnect structure 306 and one or more third devices CAP3 formed in the second interconnect structure 306. The third layer 400 may include a third interconnect structure 406 and one or more fourth devices CAP4 formed in the third interconnect structure 406. The back side 300B of the second layer 300 is engaged with the front side 400F of the third layer 400 to form a front-to-back engagement interface FB2 between them. For example, the second layer 300 and the third layer 400 are engaged in a front-to-back configuration. In some embodiments, the first layer 200, the second layer 300, and the third layer 400 contain only passive devices (e.g., capacitors, inductors, or the like) and do not contain active devices. The first layer 200, the second layer 300, and the third layer 400 may each contain multiple devices (e.g., any type of device formed within a back-end-of-line (BEOL) process) without requiring a substrate. In some embodiments, the first layer 200, the second layer 300, and the third layer 400 do not contain front-end-of-line (FEOL) devices that require a substrate.

[0020] Continue to refer to Figure 1The first layer 200, the second layer 300, and the third layer 400 may each include one or more connection branches (e.g., R1-R3 and DR1-DR3) in a metal layer (e.g., M3) of a corresponding interconnect structure. The device package 10 may include one or more through dielectric vias (TDVs) (e.g., 510 and 510D) that pass through the connection branches (e.g., R1-R3 and DR1-DR3) in each of the first layer 200, the second layer 300, and the third layer 400 and land on the front redistribution layer FRDL1 of the bottom layer 100. In some embodiments, the TDV (510 and / or 510D) extends continuously and singly through at least two stacked layers. The TDV (510 and 510D) may be referred to as a layer via.

[0021] In some embodiments, each TDV (510 or 510D) tapers in a direction from the third level 400 toward the bottom level 100. In some embodiments, TDV 510 is laterally and electrically contacted with connection branch R3 of the third level 400, connection branch R2 of the second level 300, and connection branch R1 of the first level 200. The third level 400, the second level 300, and the first level 200 can be electrically coupled to the bottom level 100 via TDV 510. That is, TDV 510 provides vertical electrical connections between stacked levels above the bottom level 100. In some embodiments, TDV 510D is laterally contacted with an additional connection branch DR3 in the third level 400, an additional connection branch DR2 in the second level 300, and an additional connection branch DR1 in the first level 200. TDV 510D can be considered as an additional TDV. In some embodiments, the additional TDV 510D is electrically isolated from the device (e.g., CAP2, CAP3, and CAP4) and can be used as a dummy pattern to improve the uniformity of etching or chemical mechanical polishing during TDV 510 formation. In some embodiments, the additional TDV 510D can be used for electrical / signal wiring in the device package 10, and the TDV 510D can provide direct electrical / signal wiring between the bottom layer 100 and the corresponding under-bump metallization pad 540.

[0022] Continue to refer to Figure 1The device package 10 may include a back-side redistribution layer BRDL1 formed on the back side 400B of the third layer 400 and connected to the TDV 510 (and 510D, if desired). The device package 10 may include a passivation structure 530 formed on the back side 400B of the third layer 400 and embedding the back-side redistribution layer BRDL1 therein. The device package 10 may include one or more under-bump metallization (UBM) pads 540 formed on the back-side redistribution layer BRDL1 and covered by the passivation structure 530. At least a portion of the UBM pads 540 are exposed by the passivation structure 530 for further electrical connection. The UBM pads 540 may be electrically coupled to the TDV 510 via the back-side redistribution layer BRDL1. The back-side redistribution layer BRDL1 and the UBM pads 540 may be collectively considered as conductive structures formed on the third layer 400.

[0023] Still referencing Figure 1 The bottom layer 100 can be significantly thicker than any of the upper layers (e.g., 200, 300, and 400), either individually or in combination. For example, the thickness 100H of the bottom layer 100 is approximately 760 micrometers, while the thicknesses 200H of the first layer 200, 300H of the second layer 300, and 400H of the third layer 400 can be approximately 6 micrometers. The upper layers in this embodiment (e.g., the first layer 200, the second layer 300, and the third layer 400) can be approximately 45.5% thinner than in a comparative embodiment with upper layers having a substrate. It should be noted that details of the device package 10 may be incorporated. Figures 4A to 4H Let me explain further.

[0024] refer to Figure 2 and Figure 1Except for the configuration of the second layer 300, the device package 20 is similar to the device package 10. For example, the back side 300B of the second layer 300 is bonded to the back side 200B of the first layer 200, and the front side 300F of the second layer 300 is bonded to the front side 400F of the third layer 400. Therefore, a back-to-back bonding interface BB1 ​​is formed between the second layer 300 and the first layer 200, and a front-to-front bonding interface FF2 is formed between the second layer 300 and the third layer 400. The second layer 300 and the first layer 200 are bonded in a back-to-back configuration, and the second layer 300 and the third layer 400 are bonded in a front-to-front configuration. In the back-to-back configuration, the metal layer M3 in the second layer 300 and the metal layer M3 in the first layer 200 can both be located away from the back-to-back bonding interface BB1. In a front-to-front configuration, the metal layer M3 in the third layer 400 and the metal layer M3 in the second layer 300 may both be close to the front-to-front bonding interface FF2. For example, the bonding interface (e.g., BB1 and FF2) involves dielectric-to-dielectric (e.g., oxide-to-oxide) bonding. The bottom layer 100 and the first layer 200 may be collectively considered as a first bonding pair P1, and the second layer 300 and the third layer 400 may be collectively considered as a second bonding pair P2 bonded to the first bonding pair P1. Details of the device package 20 can be combined... Figures 5A to 5H Let me explain further.

[0025] refer to Figure 3 and Figure 2 Device package 30 is similar to device package 20 except that it also includes a third bonding pair P3 stacked to and bonded to the second bonding pair P2. For example, the third bonding pair P3 includes a fourth layer 500 bonded to a third layer 400 and a fifth layer 600 bonded to the fourth layer 500. A back-to-back bonding interface BB2 can be formed by bonding the back side 500B of the fourth layer 500 to the back side 400B of the third layer 400. A front-to-front bonding interface FF3 can be formed by bonding the front side 600F of the fifth layer 600 to the front side 500F of the fourth layer 500. The fifth layer 600 and the fourth layer 500 are bonded in a front-to-front configuration. For example, the bonding interfaces (BB2 and FF3) involve dielectric-to-dielectric (e.g., oxide-to-oxide) bonding. The fourth level 500 and the fifth level 600 are similar to the second level 300 and the third level 400, respectively. For example, the fourth level 500 includes a fourth interconnect structure 506 and one or more fifth devices CAP5 formed therein. The fifth level 600 includes a fifth interconnect structure 606 and one or more sixth devices CAP6 formed therein.

[0026] Device package 30 may include one or more TDVs (e.g., 510 and 510D), and each TDV (510 or 510D) may extend through the fifth layer 600, the fourth layer 500, the third layer 400, the second layer 300, and the first layer 200, and land on the bottom layer 100. Device package 30 may include a backside redistribution layer BRDL1 formed on the backside 600B of the fifth layer 600 and connected to the TDVs 510 (and 510D, if desired). Passivation structure 530 of device package 30 may be formed on the backside 600B of the fifth layer 600 and embed the backside redistribution layer BRDL1 therein. In some embodiments, device package 30 includes a UBM pad 540 formed on the backside redistribution layer BRDL1 and partially exposed by the passivation structure 530. Details of device package 30 may be combined Figures 6A to 6H Let me explain further.

[0027] According to some embodiments of this application, Figure 4A , 4B 4D to 4E, 4G, 4I to 4J and 4L show schematic cross-sectional views of a method for forming a device package and Figure 4C , 4F 4H and 4K respectively show Figure 4B , 4E Schematic and exemplary unfolded diagrams of 4G and 4J. In manufacturing... Figure 1 The device shown in the diagram can be referenced when packaged in 10. Figure 4A to 4L . refer to Figures 4A to 4C This provides a bottom level of 100 and a first level of 200'. For example... Figure 4A As shown, the bottom layer 100 includes a bottom substrate 102 and one or more bottom devices 104 formed in / on the front side 102F of the bottom substrate 102. In some embodiments, the bottom substrate 102 may include a silicon substrate, a gallium arsenide substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, or other suitable materials. Figure 4A An example of a transistor (e.g., a complementary metal-oxide-semiconductor transistor or the like) is shown as the bottom device 104, but in other embodiments, the bottom device 104 may be or include other types of active and / or passive devices. For example, the bottom device 104 is formed by a FEOL process and may be referred to as a FEOL device.

[0028] The bottom layer 100 includes a bottom interconnect structure 106 formed over the front side 102F of the bottom substrate 102 and covering the bottom device 104. For example, the bottom interconnect structure 106 includes a dielectric structure ID1 and a metallization structure MS1 formed within the dielectric structure ID1. The dielectric structure ID1 may include an interlayer dielectric (ILD) layer and an inter-metal dielectric (IMD) layer. The metallization structure MS1 may include multiple metal layers (e.g., M0, M1, M2, and M3) electrically coupled through multiple metal vias. In some embodiments, the metal layer M0 and the metal vias connected to the metal layer M0 are made of tungsten (W), while the metal layers (e.g., M1, M2, and M3) overlying the metal layer M0 and the metal vias connected to the metal layers (e.g., M1, M2, and M3) are made of copper (Cu), aluminum (Al), or the like. It should be noted that the configuration of the bottom interconnect structure 106 shown in this document is merely an example and this application does not limit the number of metal layers, ILD layers and IMD layers.

[0029] Continue to refer to Figure 4A One or more first devices CAP1 may be formed in the bottom interconnect structure 106. For example, the first device CAP1 is formed in the dielectric structure ID1 and coupled to the metal layers (M0 and M1). In some embodiments, the first device CAP1 is a capacitor, with metal layer M0 serving as the bottom electrode of the capacitor and metal layer M1 serving as the top electrode of the capacitor. However, depending on product requirements, the first device CAP1 may be any type of device formed within a metal layer that does not require a back-end process (BEOL) for the bottom substrate 102. The first device CAP1 may be formed by a BEOL process and may be referred to as a BEOL device. In some embodiments, the first device CAP1 may be electrically coupled to the bottom device 104 via a metallization structure MS1. In some embodiments, the bottom layer 100 may include the bottom device 104 without the need to additionally form the first device CAP1 in the bottom layer 100. That is, the bottom layer 100 may include the bottom device 104 without the first device CAP1.

[0030] The bottom layer 100 includes a front redistribution layer FRDL1 formed above and electrically coupled to the metallized structure MS1. The front redistribution layer FRDL1 may be formed within the dielectric structure DL1. In some embodiments, the dielectric structure DL1 includes an etch stop layer ESL1 overlying the dielectric structure ID1 and separating the underlying dielectric structure ID1 from the upper dielectric layer. Vias of the front redistribution layer FRDL1 may penetrate the etch stop layer ESL1 and fall on top of the metallized structure MS1 (e.g., M3). In some embodiments, the dielectric structure DL1 includes a front-side bonding dielectric layer FD1 on top of the dielectric structure DL1 to facilitate subsequent bonding processes.

[0031] Continue to refer to Figures 4B to 4C The first layer 200' includes a first substrate 202 and a first interconnect structure 206 formed above the front side 202F of the first substrate 202. The first interconnect structure 206 may be similar to the bottom interconnect structure 106. For example, the first interconnect structure 206 includes a dielectric structure ID2 and a metallization structure MS2 formed in the dielectric structure ID2. The dielectric structure ID2 may include ILD layers (e.g., ILD1 and ILD2) and IMD layers (e.g., IMD0, IMD1, IMD2, and IMD3), such as... Figure 4C An exemplary unfolded diagram is shown. For example, the ILD layer ILD1 is located between the IMD layer IMD0 and the first substrate 202. In some embodiments, the ILD layer ILD1 is a deviceless layer. In some embodiments, during the subsequent removal process of the first substrate 202 (see... Figure 4E The ILD layer ILD1 is used as a stop layer. In some embodiments, the dielectric structure ID2 includes a front-side bonded dielectric layer FD2 on top of the dielectric structure ID2 to facilitate subsequent bonding processes. The front-side bonded dielectric layer FD2 may be thinner than the dielectric structure ID2. For example, the thickness BH1 of the front-side bonded dielectric layer FD2 is approximately 0.5 micrometers, while the overall thickness DH1 of the dielectric structure ID2 is approximately 5 micrometers. In some embodiments, the front-side bonded dielectric layers FD1 and FD2 may be or include oxides, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and / or any suitable one or more bonding dielectric materials.

[0032] Continue to refer to Figures 4B to 4CThe metallized structure MS2 of the first layer 200' may include multiple metal layers (e.g., M0, M1, M2, and M3) electrically coupled through metal vias (e.g., V0, V1, and V2). In some embodiments, metal layer M0 is made of tungsten, while the overlying metal layers (e.g., M1, M2, and M3) are made of aluminum, alloys thereof, or the like. In some embodiments, metal layer M0 is embedded in IMD layer IMD0, metal layer M1 and metal via V1 are embedded in IMD layer IMD1, metal layer M2 and metal via V2 are embedded in IMD layer IMD2, metal layer M3 is embedded in IMD layer IMD3, and a front bonding dielectric layer FD2 is overlying IMD layer IMD3. It should be noted that the configuration of the first interconnect structure 206 shown herein is merely an example, and this application does not limit the number of metal layers, ILD layers, and IMD layers.

[0033] In some embodiments, the top of the metallized structure MS2 (e.g., metal layer M3) includes one or more connecting branches (e.g., R1 and DR1). The connecting branches (e.g., R1 and DR1) may be made of aluminum, its alloys, or other suitable one or more metallic materials. In some embodiments, the material of the connecting branches may facilitate subsequent dry etching processes and generate fewer byproducts during the etching process. In some embodiments, the material of the connecting branches differs from the material of the hierarchical perforations to be formed in subsequent steps. Figure 4B A schematic top view of the connecting branches (such as R1 and DR1) in the metal layer M3, framed by the dashed square below, is shown. Figure 4B The upper part. For example, each connecting branch (e.g., R1 or DR1) includes a metal segment RM1 surrounding the hollow region RH1. The metal segment RM1 may include a ring RM11 and an extension RM12 connecting the ring RM11 to other parts of the metal layer M3, wherein the ring RM11 defines the hollow region RH1. At this stage, the hollow region RH1 is filled with one or more dielectric materials of the dielectric structure ID2. The metal segment RM1 may have a square (or rectangular) top view shape (similar to...) Figure 4B The upper left image), circular top view shape (similar to...) Figure 4B (The top right view) or any suitable top view shape, depending on circuit and product requirements. In some embodiments, the metal segment RM1 of the connecting branch R1 is electrically connected to other metal layers (e.g., M2, M1, and / or M0). In some embodiments, the metal segment RM1 of the additional connecting branch DR1 is electrically isolated from other metal layers and may be referred to as an additional metal segment. The connecting branch DR1 may also be considered as an additional connecting branch. For example, the metal segment RM1 of the additional connecting branch DR1 can be used to pattern the etching profile of the additional hierarchical via 510D in subsequent processes and improve the profile uniformity between the hierarchical via 510 and the additional hierarchical via 510D.

[0034] Continue to refer to Figures 4B to 4C One or more second devices CAP2 are formed in the first interconnect structure 206. For example, the second device CAP2 is embedded in the ILD layer ILD2 of the dielectric structure ID2 and is physically and electrically coupled to the metal layers (M0 and M1). In some embodiments, the ILD layer ILD2 is thicker than other IMD and ILD layers (e.g., ILD1, IMD0, IMD1, IMD2, and IMD3) due to space requirements for forming the second device CAP2. In some embodiments, the thickness of the ILD layer ILD2 is in the range of about 1 to 3 micrometers. In some embodiments, the second device CAP2 is a capacitor, with metal layer M0 serving as the bottom electrode of the capacitor and metal layer M1 serving as the top electrode of the capacitor. In some embodiments, the second device CAP2 is a capacitor and may include a plurality of first conductive films and second conductive films. The first conductive films are electrically coupled to the top electrode (e.g., metal layer M1) and extend toward the bottom electrode (e.g., metal layer M0). The second conductive films are electrically coupled to the bottom electrode and extend toward the top electrode. The first conductive films and the second conductive films are alternately arranged. However, depending on product requirements, the second device CAP2 can be any type of BEOL device (e.g., an inductor or similar). The metal section RM1 of the connecting branch R1 can be electrically coupled to the second device CAP2, while the additional metal section RM1 of the connecting branch DR1 is electrically isolated from the second device CAP2.

[0035] refer to Figure 4D and Figures 4A to 4C The first layer 200' is bonded to the bottom layer 100. For example, the front bonding dielectric layer FD2 of the first layer 200' is bonded to the front bonding dielectric layer FD1 of the bottom layer 100 by fusion bonding (e.g., oxide-to-oxide bonding or the like). A bonding interface FF1 is then formed between the bottom layer 100 and the first layer 200'. The front side 102F of the bottom substrate 102 faces the front side 202F of the first substrate 202 and may be referred to as a front-to-front interface depending on the position of the bonding interface FF1 in the bonding structure. In some embodiments where the bottom layer 100 and the first layer 200' are provided in wafer form, a wafer-to-wafer bonding process is performed to bond the first layer 200' to the bottom layer 100. In some embodiments where the bottom layer 100 is provided in wafer form and the first layer 200' is provided in die form, a die-to-wafer bonding process is performed to bond the first layer 200' to the bottom layer 100.

[0036] refer to Figures 4E to 4F and Figure 4DThe first substrate 202 of the first layer 200' can be removed by, for example, chemical mechanical polishing (CMP), dry etching, wet etching, a combination thereof, or any suitable removal process, thereby forming the first layer 200 bonded to the bottom layer 100. In some embodiments, the first substrate 202 is completely removed, exposing the dielectric structure ID2 (e.g., ILD layer ILD1) after the removal of the first substrate 202, and the metal layer M0 connected to the second device CAP2 remains embedded in the dielectric structure ID2. In some embodiments, the first substrate 202 of the first layer 200' can be removed by wet etching, and the dielectric structure ID2 is exposed when the wet etching stops. The removal process by wet etching is more cost-effective than the removal process using chemical mechanical polishing. In some embodiments, after the removal of the first substrate 202, a back-side bonding dielectric layer BD2 is formed on the exposed dielectric structure ID2 (e.g., ILD layer ILD1) for further bonding processes. The back-side bonding dielectric layer BD2 can be or includes oxide, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and / or any suitable one or more bonding dielectric materials. For example... Figure 4F As shown in the exemplary unfolded diagram, after the first substrate 202 is removed, the ILD layer ILD1 lies between the IMD layer IMD0 and the back-side bonding dielectric layer BD2. The back-side bonding dielectric layer BD2 can be directly connected to the ILD layer ILD1 of the dielectric structure ID2. In some embodiments, the back-side bonding dielectric layer BD2 (or Figure 4G The vertical distance L1 between the outermost surface of the bonding interface FB1 described herein and the surface of the metal layer M0 that intersects with the ILD layer ILD1 is less than 2 micrometers. The thinner height is achieved by completely removing the first substrate 202.

[0037] refer to Figure 4G to 4H and Figures 4E to 4F The second layer 300 is bonded to the first layer 200. The second layer 300 is similar to the first layer 200, so for simplicity, the details of the second layer 300 will not be repeated here. For example, the second layer 300 includes a second interconnect structure 306, and the second interconnect structure 306 includes a dielectric structure ID3 and a metallization structure MS3 formed in the dielectric structure ID3. In some embodiments, the dielectric structure ID3 includes a front-side bonded dielectric layer FD3 on top of the dielectric structure ID3 and bonded to the back-side bonded dielectric layer BD2 of the first layer 200. The metallization structure MS3 may include multiple metal layers (e.g., M0, M1, M2, and M3) electrically coupled through metal vias. It should be noted that the configuration of the second interconnect structure 306 shown herein is merely an example, and this application does not limit the number of metal layers, ILD layers, and IMD layers.

[0038] In some embodiments, the metallized structure MS3 of the second layer 300 includes one or more connecting branches (e.g., R2 and DR2) formed in the metal layer M3. Except that the hollow region RH2 of connecting branch R2 / DR2 is larger than the hollow region RH1 of connecting branch R1 / DR1, connecting branches R2 and DR2 are respectively connected to… Figure 4B The connection branches R1 and DR1 are similar. Details will be provided in conjunction with... Figure 4I The following description is provided. In some embodiments, the connection branch R2 of the metallized structure MS3 of the second layer 300 is directly above the connection branch R1 of the first layer 200. For example, the hollow region RH2 of the second layer 300 is substantially and perpendicularly aligned with the hollow region RH1 of the first layer 200. An additional connection branch DR2 of the metallized structure MS3 of the second layer 300 may be directly above the additional connection branch DR1 of the first layer 200. For example, the hollow region RH2 of the second layer 300 is substantially and perpendicularly aligned with the hollow region RH1 of the first layer 200. The second layer 300 includes one or more third devices CAP3 formed in the second interconnect structure 306. For example, the third device CAP3 is embedded in the dielectric structure ID3 and physically and electrically coupled to the metal layers (M0 and M1). The third device CAP3 of the second layer 300 may be... Figure 4B The second device CAP2 of the first level 200 described herein is similar. The metal segment RM2 of the connecting branch R2 can be electrically coupled to the third device CAP3, while the additional metal segment RM2 of the additional connecting branch DR2 is electrically isolated from the third device CAP3.

[0039] Continue to refer to Figure 4G to 4H In some embodiments, a similar approach is provided. Figure 4B The initial second layer (not shown) of the first layer 200' is then bonded to the back-side bonding dielectric layer BD2 of the first layer 200, and then the front-side bonding dielectric layer FD3 of the initial second layer is bonded to it. Subsequently, it can be bonded to the back-side bonding dielectric layer BD2 of the first layer 200. Figure 4E The removal process of the first substrate 202 described herein is similar to that used to remove the initial second-level substrate, thereby forming the second level 300. A back-side bonding dielectric layer BD3 of the second level 300 is optionally formed on the exposed dielectric structure ID3 for further bonding processes (if desired). In some embodiments, reference is made to... Figure 4H The exemplary unfolded diagram shown illustrates a bonding interface FB1 formed between a first layer 200 and a second layer 300. The front side of the second layer 300 faces the back side of the first layer 200, and the bonding interface FB1 can be referred to as a front-to-back interface depending on its position in the bonding structure.

[0040] refer to Figure 4I and Figure 4G to 4HThe third layer 400 is bonded to the second layer 300. The third layer 400 is similar to the first layer 200, therefore, for simplicity, the details of the third layer 400 will not be repeated here. For example, the third layer 400 includes a third interconnect structure 406, and the third interconnect structure 406 includes a dielectric structure ID4 and a metallization structure MS4 formed in the dielectric structure ID4. In some embodiments, the dielectric structure ID4 includes a front-side bonded dielectric layer FD4 on top of the dielectric structure ID4 and bonded to the back-side bonded dielectric layer BD3 of the second layer 300. The metallization structure MS4 may include multiple metal layers (e.g., M0, M1, M2, and M3) electrically coupled through metal vias. It should be noted that the configuration of the third interconnect structure 406 shown herein is merely an example, and this application does not limit the number of metal layers, ILD layers, and IMD layers.

[0041] In some embodiments, the metallization structure MS4 of the third layer 400 includes one or more connection branches (e.g., R3 and DR3) formed in the metal layer M3. The connection branches R3 and DR3 are respectively connected to… Figure 4B The connecting branches R1 and DR1 are similar. In some embodiments, the connecting branch R3 of the third level 400 is directly above the connecting branch R2 of the second level 300 and the connecting branch R1 of the first level 200. For example, the hollow region RH3 of the connecting branch R3 of the third level 400 is substantially and perpendicularly aligned with the hollow region RH2 of the connecting branch R2 of the second level 300 and the hollow region RH1 of the connecting branch R1 of the first level 200. The additional connecting branch DR3 of the third level 400 is directly above the additional connecting branch DR2 of the second level 300 and the additional connecting branch DR1 of the first level 200. For example, the hollow region RH3 of the third level 400 is substantially and perpendicularly aligned with the hollow region RH2 of the second level 300 and the hollow region RH1 of the first level 200.

[0042] exist Figure 4I In Figure 4I A schematic top view of the connecting branches (R1-R3 and DR1-DR3) enclosed by dashed squares on the left is shown. Figure 4I The difference between connecting branches R1-R3 (or DR1-DR3) is that the width (or diameter) HD3 of the hollow area RH3 in the third level 400 is greater than the width (or diameter) HD2 of the hollow area RH2 in the second level 300, and the width (or diameter) HD2 of the hollow area RH2 in the second level 300 is greater than the width (or diameter) HD1 of the hollow area RH1 in the first level 200.

[0043] Still referencing Figure 4IThe third layer 400 includes one or more fourth devices CAP4 formed in the third interconnect structure 406. For example, the fourth device CAP4 is embedded in the dielectric structure ID4 and physically and electrically coupled to the metal layers (M0 and M1). The fourth device CAP4 of the third layer 400 can be connected to… Figure 4B The second device CAP2 of the first level 200 described herein is similar. The metal segment RM3 of the connecting branch R3 is electrically coupled to the fourth device CAP4, while the additional metal segment RM3 of the additional connecting branch DR3 is electrically isolated from the fourth device CAP4.

[0044] Continue to refer to Figure 4I In some embodiments, a method similar to that in Figure 4B The first layer 200' described herein has an initial third layer (not shown), and then the front-side bonding dielectric layer FD4 of the initial third layer is bonded to the back-side bonding dielectric layer BD3 of the second layer 300. Subsequently, it can be bonded to the first layer 200' with the second layer 300. Figure 4E The removal process of the first substrate 202 described herein is similar to that used to remove the initial third-level substrate, thereby forming the third level 400. A back-side bonding dielectric layer (not shown) of the third level 400 may be formed on the exposed dielectric structure ID4 for further bonding processes. Alternatively, the back-side bonding dielectric layer may be omitted. For example, a bonding interface FB2 is formed between the second level 300 and the third level 400. The front side of the third level 400 faces the back side of the second level 300, and the bonding interface FB2 may be referred to as the front-to-back interface based on its position in the bonding structure.

[0045] refer to Figure 4J to 4K and Figure 4IOne or more TDVs (e.g., 510 and 510D) are formed to pass through the third layer 400, the second layer 300, and the first layer 200, and land on the front redistribution layer FRDL1 of the bottom layer 100. For example, the TDVs (510 and 510D) are formed by the following steps: removing dielectric material in the upper portions of the third layer 400, the second layer 300, the first layer 200, and the bottom layer 100 to form a via 510H; and forming one or more conductive materials in the via 510H to form the TDVs (510 and 510D). The via 510H can be formed by a suitable etching process (e.g., dry etching), and the one or more conductive materials can be formed by a plating process or a suitable deposition process. In some embodiments, the materials of each TDV (510 or 510D) include copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or other suitable one or more metallic materials having better filling capacity and / or lower cost than tungsten (W). In some embodiments, references... Figure 4K The exemplary unfolded diagram shown illustrates that each TDV (510 or 510D) includes a barrier pad 512 and a metal filler layer 514 covering the barrier pad 512. For example, the barrier pad 512 is made of tantalum nitride and the metal filler layer 514 is made of copper.

[0046] In some embodiments, during the step of forming the perforation 510H, at least partially (or entirely) the dielectric material in the hollow regions RH3 of the connecting branches (R3 and DR3), RH2 of the connecting branches (R2 and DR2), and RH1 of the connecting branches (R1 and DR1) is removed. The TDVs (510 and 510D) may be in lateral contact with the metal segments of the corresponding connecting branches in each layer overlaid on the bottom layer 100. For example, the TDV 510 is in lateral and electrical contact with the metal segment RM3 of the connecting branch R3 in the third layer 400, the metal segment RM2 of the connecting branch R2 in the second layer 300, and the metal segment RM1 of the connecting branch R1 in the first layer 200. TDV 510D may laterally contact the metal segment RM3 of the additional connection branch DR3 in the third layer 400, the metal segment RM2 of the additional connection branch DR2 in the second layer 300, and the metal segment RM1 of the additional connection branch DR1 in the first layer 200. TDV 510D can be considered as an additional TDV and can be used as a dummy pattern to improve the uniformity of etching or chemical mechanical polishing during TDV 510 formation. In some embodiments, the additional TDV 510D may be used for electrical / signal wiring in a device package, and TDV 510D may provide direct electrical / signal wiring between the bottom layer 100 and the corresponding under-bump metallized pad.

[0047] Continue to refer to Figure 4J to 4K Each TDV (510 or 510D) can taper in the direction from the third layer 400 toward the bottom layer 100. For example, the top width (or diameter) D1 of each TDV (510 or 510D) is greater than the bottom width (or diameter) D2 of each TDV (510 or 510D). The change in the critical dimension (CD) of each TDV (510 or 510D) can be obtained by the following formula: [(D1-D2) / D1]*100%. For example, the CD change of each TDV (510 or 510D) is approximately 48.5%. Compared with the above embodiment where the layers have a substrate, the CD change of each TDV in this embodiment is reduced due to the lower TDV etching height.

[0048] Continue to refer to Figure 4K The exemplary unfolded diagram shown is as follows. Figure 4K The explanation is based on the entirety of the second layer 300 and a portion of the third layer 400. The TDV (510 or 510D) tapers from top to bottom in the third layer 400. For example, the width (or diameter) D11 of the TDV (510 or 510D) is greater than the width (or diameter) D12 of the TDV (510 or 510D), and the width (or diameter) D12 is greater than the width (or diameter) D13 of the TDV (510 or 510D), where the width (or diameter) D12 is measured on a virtual plane coplanar with the top surface MT3 of the metal layer M3 in the third layer 400, and the width (or diameter) D13 is measured on a virtual plane coplanar with the bottom surface MB3 of the metal layer M3 in the third layer 400. In some embodiments, the first tapered profile in the third layer 400, laterally surrounded by a dielectric material (e.g., IMD2), differs from the second profile in the third layer 400, laterally surrounded by the connecting branch (R3 or DR3). In the third layer 400, the TDV (510 or 510D) extending through the dielectric material (e.g., IMD2) may have a different slope than the TDV (510 or 510D) extending through the metal segment RM3 of the connecting branch (R3 or DR3). In some embodiments, during the formation of the TDV (510 and / or 510D), the metal segment of the connecting branch may be partially etched away to create sloping sidewalls of the TDV in the corresponding connecting branch. For example, in the third layer 400, the first sidewall SW1, laterally covered by the IMD layer IMD2, has a larger slope than the second sidewall SW2, laterally covered by the metal segment RM3.

[0049] Still referencing Figure 4KIn the exemplary unfolded diagram shown, the width (or diameter) D13 of TDV (510 or 510D) is greater than the width (or diameter) D13' of TDV (510 or 510D), wherein the width (or diameter) D13' is measured on a virtual plane coplanar with the bottom of IMD layer IMD2 in the second layer 300. The width (or diameter) D13' is greater than the width (or diameter) D14 of TDV (510 or 510D), and the width (or diameter) D14 is greater than the width (or diameter) D15 of TDV (510 or 510D), wherein the width (or diameter) D14 is measured on a virtual plane coplanar with the top surface MT3 of metal layer M3 in the second layer 300, and the width (or diameter) D15 is measured on a virtual plane coplanar with the bottom surface MB3 of metal layer M3 in the second layer 300. In some embodiments, the third tapered profile laterally surrounded by dielectric material (e.g., FB4, BB3, ILD1, IMD0, ILD2, IMD1, and IMD2) differs from the fourth profile laterally surrounded by connecting branches (R2 or DR2) in the second layer 300. The TDV (510 or 510D) extending through the dielectric material (e.g., FB4, BB3, ILD1, IMD0, ILD2, IMD1, and IMD2) may have a different slope than the TDV (510 or 510D) extending through the metal segment RM2 of the connecting branch (R2 or DR2). For example, the third sidewall SW3 laterally covered by dielectric material (e.g., FB4, BB3, ILD1, IMD0, ILD2, IMD1, and IMD2) has a larger slope than the fourth sidewall SW4 laterally covered by the metal segment RM2 in the second layer 300.

[0050] The different tapered profiles of the TDV (510 or 510D) are formed by the dimensional shrinkage caused by the aspect ratio of the section height between the widths (D13 and D13') and by the dimensional shrinkage caused by the contact of the etchant with the connecting branches (R1-R3 or DR1-DR3) during the formation of the 510H via. For example, the third sidewall SW3 defines a third tapered profile laterally surrounded by dielectric material (e.g., FD4, BD3, ILD1, IMD0, ILD2, IMD1, and IMD2), and this portion of the TDV (510 or 510D) has a third tapered profile and an aspect ratio defined as depth divided by width. The second sidewall SW2 defines a second tapered profile laterally surrounded by connecting branches (R3 or DR3), and the third sidewall SW3 may have a steeper slope than the second sidewall SW2. Similarly, the fourth sidewall SW4 defines a fourth tapered profile laterally surrounded by the connecting branches (R2 or DR2), and the third sidewall SW3 may have a steeper slope than the fourth sidewall SW4. In some embodiments, the diameter design of the hollow region in the connecting branches and the selection of suitable materials for the connecting branches and the dielectric layer can be used to limit the etching profile of the via 510H of the TDV. Different tapered profiles (e.g., sidewalls SW2 / SW4 compared to sidewall SW3) can limit the profile of the TDV during high-depth and long-duration etching processes.

[0051] refer to Figure 4L and Figure 4J to 4KA back-side redistribution layer BRDL1 is formed on the third layer 400 and connected to TDV 510 (and 510D, if desired). For example, the back-side redistribution layer BRDL1 is electrically and physically contacted with TDV 510. Devices (e.g., CAP1-CAP4) in the upper layers (e.g., 200, 300, and 400) are electrically coupled to the back-side redistribution layer BRDL1 via TDV 510, and the bottom device 104 is electrically coupled to the back-side redistribution layer BRDL1 via TDV 510 (or TDV 510D, if desired) and the front-side redistribution layer FRDL1. In some embodiments, additional TDV 510Ds are physically connected to additional patterns (not specifically marked) on the back-side redistribution layer BRDL1. In some embodiments, additional TDV 510Ds may be used for signal / power cabling of the bottom device 104. In some embodiments, the bottom device 104 may be electrically coupled to a passive device (e.g., CAP1-CAP4 alone or in combination) via a front redistribution layer FRDL1, TDV 510, and a rear redistribution layer BRDL1. In some embodiments, the passive device (e.g., CAP1-CAP4) may be used for power conditioning / conversion or signal filtering on the bottom device 104. A passivation structure 530 may be formed on the third layer 400 and the rear redistribution layer BRDL1 may be embedded therein. For example, the passivation structure 530 may include one or more sublayers (e.g., 531, 532, 533, 534, and 535) and the rear redistribution layer BRDL1 may be embedded in the sublayer 531. In some embodiments, one or more UBM pads 540 may be formed on the rear redistribution layer BRDL1 and covered by the passivation structure 530. For example, the UBM pads 540 may be laterally covered by the sublayers (e.g., 532, 533, 534, and 535). UBM pad 540 can be electrically coupled to TDV 510 via the backside rewiring layer BRDL1. For example... Figure 4L As shown, device package 10 can be obtained.

[0052] Continue to refer to Figure 4LIn some embodiments, bottom layer 100 may simultaneously include a first device CAP1 and bottom device 104. Bottom layer 100 may be dynamic-random-access-memory (DRAM), while bottom device 104 may be control circuitry (e.g., peripheral circuitry) signaled to the first device CAP1. In some embodiments, bottom layer 100 may be a processor chip, such as a central processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), neural processing unit (NPU), or the like. Bottom device 104 may be a logic transistor in the processor chip, while the first device CAP1 may be a passive device integrated into the processor chip. In some other embodiments, bottom layer 100 may include bottom device 104 without forming the first device CAP1. In some other embodiments, bottom layer 100 may include the first device CAP1 without forming the bottom device 104. In this embodiment, the bottom layer 100 can be a passive device that has a similar function to the passive devices in the upper layers (e.g., layers 200 / 300 / 400).

[0053] Figures 5A to 5H A schematic cross-sectional view is shown of a method for forming an apparatus package according to some embodiments of this application. In manufacturing... Figure 2 The device shown in package 20 can be referenced. Figures 5A to 5H . refer to Figure 5A and Figures 4A to 4D Each layer (100) and a first layer (200') are provided, and then the two are joined together. The details of these processes are... Figures 4A to 4D The process described herein is similar. A bonding interface FF1 is formed between the first layer 200' and the bottom layer 100. For example, the first layer 200' and the bottom layer 100 are bonded in a front-to-front configuration, and the bonding interface FF1 is referred to as a front-to-front bonding interface.

[0054] refer to Figure 5B , Figure 5A and Figure 4E After bonding the first layer 200' to the bottom layer 100, the first substrate 202 of the first layer 200' is removed to form the first layer 200. The removal process can be similar to... Figure 4E The process described herein. Figure 5B The structure shown is considered as the first pair of structures P1.

[0055] refer to Figures 5C to 5D The second layer (300') and the third layer (400') are provided respectively, and then the two are joined together. Figure 5C As shown in the stage, the second layer 300' includes a second substrate 302, a second interconnect structure 306 formed on the second substrate 302, and a third device CAP3 formed in the second interconnect structure 306. Similarly, the third layer 400' includes a third substrate 402, a third interconnect structure 406 formed on the third substrate 402, and a fourth device CAP4 formed in the third interconnect structure 406. A bonding interface FF2 is formed between the second layer 300' and the third layer 400'. For example, the front side 300F of the second layer 300' faces the front side 400F of the third layer 400', and is referred to as a front-to-front interface according to the position of the bonding interface FF2 in the bonding structure. Next, the second substrate 302 of the second layer 300' is removed to form the second layer 300. The removal process can be similar to... Figure 4E The substrate removal process described herein. Figure 5D The structure shown is considered as the second pair of structures P2.

[0056] refer to Figures 5E to 5F , Figure 5D and Figure 5B The second pair of structures P2 is bonded to the first pair of structures P1. For example, the back side 300B of the second layer 300 is bonded to the back side 200B of the first layer 200 by, for example, fusion bonding or the like, to form a bonding interface BB1. Depending on its position in the bonding structure, the bonding interface BB1 ​​can be referred to as a back-to-back interface. Next, the third substrate 402 of the third layer 400' can be removed to form the third layer 400, as... Figure 5F As shown. The removal of the third substrate 402 can be similar to... Figure 4E The substrate removal process described herein.

[0057] refer to Figure 5G , Figure 5F and Figure 4G TDV (510 and 510D) are formed in Figure 5F The joint structure shown is illustrated. Details of the TDVs (510 and 510D) can be found in the reference. Figure 4J to 4KThe TDVs (510 and 510D) described herein. For example, TDV 510 passes through connection branch R3 in the third level 400, connection branch R2 in the second level 300, and connection branch R1 in the first level 200, and lands on the front redistribution layer FRDL1 in the bottom level 100. The dimensions of one or more connection branches (e.g., R1-R3 and DR1-DR3) in each of the first level 200, second level 300, and third level 400 can be adjusted according to the height of the corresponding TDV (510 or 510D). The TDVs (510 and 510D) can make lateral and electrical contact with the devices (CAP2, CAP3, and CAP4) through the connection branches (e.g., R1-R3) in the first level 200 to the third level 400. The TDVs (510 and 510D) and Figure 4G The corresponding components described in the document are similar, so their details will not be repeated here.

[0058] refer to Figure 5H , Figure 5G and Figure 4L A back-side redistribution layer BRDL1 is formed on the back side 400B of the third layer 400 and connected to the TDV 510 (and 510D, if desired). A passivation structure 530 may be formed on the back side 400B of the third layer 400 and embed the back-side redistribution layer BRDL1 therein. In some embodiments, a UBM pad 540 is formed on the back-side redistribution layer BRDL1 and partially exposed by the passivation structure 530. The UBM pad 540 can be electrically coupled to the TDV 510 through the back-side redistribution layer BRDL1. The back-side redistribution layer BRDL1, the passivation structure 530, and the UBM pad 540 are connected to the TDV 510. Figure 4L The corresponding components described are similar, so they will not be repeated here. Figure 5H As shown, device package 20 can be obtained.

[0059] Figures 6A to 6H A schematic cross-sectional view is shown of a method for forming an apparatus package according to some embodiments of this application. In manufacturing... Figure 3 The device shown in the diagram can be referenced when packaged in 30. Figures 6A to 6H . refer to Figure 6A and Figure 5B The bottom layer 100 and the first layer 200 are joined together and a front-to-front joint interface FF1 is formed between them. Figure 6A The structure shown is considered the first pair of structures P1. A detailed description of the first pair of structures P1 can be found in [reference needed]. Figure 5B The foregoing embodiments are described in the above description.

[0060] refer to Figure 6B and Figure 5DThe second layer 300 and the third layer 400' are joined together to form a second pair of structures P2, wherein a front-to-front joining interface FF2 is formed between the second layer 300 and the third layer 400'. A detailed description of the second pair of structures P2 can be found in [reference needed]. Figure 5D The foregoing embodiments are described in the above description.

[0061] refer to Figure 6C and Figure 6B The fourth layer 500 and the fifth layer 600' are joined together to form a third pair of structures P3. The third pair of structures P3 may be similar to the second pair of structures P2. For example, the fourth layer 500 includes a fourth interconnect structure 506 and a fifth device CAP5 formed therein. The fifth layer 600' includes a fifth substrate 602, a fifth interconnect structure 606 formed on the fifth substrate 602, and a sixth device CAP6 formed in the fifth interconnect structure 606. A bonding interface FF3 is formed between the fourth layer 500 and the fifth layer 600'. For example, the front side 500F of the fourth layer 500 faces the front side 600F of the fifth layer 600', and is referred to as a front-to-front interface according to the position of the bonding interface FF3 in the third pair of structures P3.

[0062] refer to Figures 6D to 6E and Figures 6A to 6B The second pair of structures P2 is bonded to the first pair of structures P1. The back side 300B of the second layer 300 can be bonded to the back side 200B of the first layer 200 to form a back-to-back bonding interface BB1. Next, the third substrate 402 of the third layer 400' can be removed to form the third layer 400, as... Figure 6E As shown. The removal of the third substrate 402 can be similar to... Figure 4E The substrate removal process described herein.

[0063] refer to Figures 6F to 6G and Figure 6E and Figure 6C The third pair of structures P3 is bonded to the second pair of structures P2. The back side 500B of the fourth layer 500 can be bonded to the back side 400B of the third layer 400 by, for example, fusion bonding or the like, to form a back-to-back bonding interface BB2. Next, the fifth substrate 602 of the fifth layer 600' can be removed to form the fifth layer 600, as... Figure 6G As shown. The removal of the fifth substrate 602 can be similar to... Figure 4E The substrate removal process described herein.

[0064] refer to Figure 6H , Figure 6G and Figure 4G TDV (510 and 510D) are formed in Figure 6GThe joint structure shown is illustrated. Details of the TDVs (510 and 510D) can be found in the reference. Figure 4J to 4K and Figure 5G-5H The TDVs (510 and 510D) described herein. In the illustrated embodiment, TDV 510 passes through connection branch R5 in the fifth level 600, connection branch R4 in the fourth level 500, connection branch R3 in the third level 400, connection branch R2 in the second level 300, and connection branch R1 in the first level 200, and lands on the front redistribution layer FRDL1 in the bottom level 100. Connection branch R5 in the fifth level 600 and connection branch R4 in the fourth level 500 are similar to connection branch R3 in the third level 400 and connection branch R2 in the second level 300, respectively, and therefore details will not be repeated here. TDV 510 may pass through the connection branches (e.g., R1-R5) in the first level 200 to the fifth level 600 and make lateral and electrical contact with the device (CAP2-CAP6). TDV 510 can be electrically coupled to the bottom device 104 and the first device CAP1 in the bottom layer 100 via the front redistribution layer FRDL1. Therefore, TDV 510 can provide electrical interconnection between the bottom layer 100 and the fifth layer 600 in a vertical stack.

[0065] In some embodiments, TDV 510D can also be used for the electrical connection of the bottom device 104 and the devices (CAP1, CAP2, CAP3, CAP4, CAP5, and CAP6). In some other embodiments, TDV 510D can be used for additional TDV patterns. In this embodiment, additional TDV 510D can be used to improve the uniformity of TDV 510 during the manufacturing process.

[0066] Continue to refer to Figure 6H and Figure 4L A backside redistribution layer BRDL1 is formed on the backside 600B of the fifth layer 600 and connected to the TDV 510 (and 510D, if desired). A passivation structure 530 may be formed on the backside 600B of the fifth layer 600 and embed the backside redistribution layer BRDL1 therein. In some embodiments, a UBM pad 540 is formed on the backside redistribution layer BRDL1 and partially exposed by the passivation structure 530. The UBM pad 540 can be electrically coupled to the TDV 510 through the backside redistribution layer BRDL1. The backside redistribution layer BRDL1, the passivation structure 530, and the UBM pad 540 are connected to the TDV 510. Figure 4L The corresponding components described are similar, so they will not be repeated here. Figure 6H As shown, device package 30 can be obtained.

[0067] In one example aspect, a device package is provided. The device package includes a first layer, a second layer stacked on the first layer, and a single hierarchical via penetrating both the first and second layers. The first layer includes a first device and a first interconnect structure electrically coupled to the first device, the first interconnect structure including a first metal layer and the first metal layer including a first connection branch. The second layer includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure including a second metal layer and the second metal layer including a second connection branch. The hierarchical via is electrically connected to the first and second connection branches.

[0068] In another exemplary aspect, a device package is provided. The device package includes a first bonding pair, N second bonding pairs stacked on the first bonding pair, and a hierarchical via. The first bonding pair includes a bottom layer and a first layer stacked on the bottom layer. The bottom layer includes a bottom device and a front-side RDL electrically coupled to the bottom device. The first layer includes a first device and a first connection branch electrically coupled to the first device. Each of the N second bonding pairs includes a second layer and a third layer stacked on the second layer. The second layer includes a second device and a second connection branch electrically coupled to the second device, and the third layer includes a third device and a third connection branch electrically coupled to the third device. The hierarchical vias extend singly through the N second bonding pairs and the first layer of the first bonding pair, and the hierarchical vias are electrically coupled to the front-side RDL and the first, second, and third connection branches, where N ≥ 1.

[0069] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this application. In view of the foregoing, this application is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A device package, characterized in that, include: The first layer includes a first device and a first interconnect structure electrically coupled to the first device, the first interconnect structure including a first metal layer, and the first metal layer including a first connection branch; The second layer, stacked on the first layer, includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure including a second metal layer, and the second metal layer including a second connection branch; as well as The perforation is a single, continuous perforation that penetrates both the first and second layers and is electrically coupled to the first and second connection branches.

2. The device package according to claim 1, characterized in that, in: The first layer includes a first side bonding layer that is bonded to the second layer, and The first interconnect structure of the first layer further includes a first interlayer dielectric layer that is located away from the first metal layer and directly connected to the first side bonding layer.

3. The device package according to claim 2, characterized in that, in: The second layer includes a first side bonding layer bonded to the first layer, and The first bonding interface is located between the first side bonding layer of the first level and the first side bonding layer of the second level.

4. The device package according to claim 3, characterized in that, in: The first interlayer dielectric layer includes a first side surface remote from the first bonding interface, and The vertical distance between the first side surface and the first bonding interface is less than 2 micrometers.

5. The device package according to claim 3, characterized in that, in: The first side bonding layer of the second level is close to the second metal layer of the second level, and The second layer and the first layer are joined in a front-to-back configuration.

6. The device package according to claim 3, characterized in that, in: The first side bonding layer of the second level is far from the second metal layer of the second level, and The second layer and the first layer are joined in a back-to-back configuration.

7. The device package according to claim 1, characterized in that, The first device and the second device are capacitors or inductors.

8. The device package according to claim 1, characterized in that, The first device and the second device are downstream process devices.

9. The device package according to claim 1, characterized in that, in: The first connecting branch includes a first metal segment and a first hollow region surrounded by the first metal segment. The second connecting branch includes a second metal segment and a second hollow region surrounded by the second metal segment, and The first metal segment and the second metal segment are electrically coupled to the layered via.

10. The device package according to claim 9, characterized in that, in: The first hollow region includes a first width. The second hollow region includes a second width, and The first width is smaller than the second width.

11. The device package according to claim 9, characterized in that, in: The hierarchical perforation includes a first sidewall that intersects with the second metal segment and a second sidewall that extends between the first metal segment and the second metal segment. The slope of the second sidewall is greater than the slope of the first sidewall.

12. The device package according to claim 1, characterized in that, Also includes: The bottom layer, below the first layer, includes a bottom device, a bottom interconnect structure electrically coupled to the bottom device, and a front redistribution layer electrically coupled to the layer vias.

13. The device package according to claim 12, characterized in that, The layered perforations thereunder fall directly on the front redistribution layer of the bottom layer.

14. The device package according to claim 12, characterized in that, The bottom device in the bottom layer is a logic device.

15. The device package according to claim 12, characterized in that, in: The bottom layer also includes a second side bonding layer near the front redistribution layer. The first layer also includes a second side bonding layer adjacent to the first metal layer. The second bonding interface is between the second side bonding layer of the bottom layer and the second side bonding layer of the first layer, and The first level and the bottom level are joined in a front-to-front configuration.

16. The device package according to claim 1, characterized in that, Also includes: A passivated structure is applied over the second layer; as well as A conductive structure, comprising, in the passivation structure: Re-lay out the circuit layer and electrically couple it to the vias at that level; as well as The conductive pads are electrically coupled to the redistributed circuit layer and exposed by the passivation structure.

17. The device package according to claim 1, characterized in that, Also includes: Additional layer perforations extend through the first layer and the second layer, wherein one of the first layer and the second layer further includes additional connecting branches connected to the additional layer perforations.

18. The device package according to claim 17, characterized in that, The additional connection branch is electrically isolated from one of the first and second devices of the first and second layers, respectively.

19. A device package, characterized in that, include: The first bonding pair includes a bottom layer and a first layer stacked on the bottom layer, the bottom layer including a bottom device and a front redistribution layer electrically coupled to the bottom device, and the first layer including a first device and a first connection branch electrically coupled to the first device. N second bonding pairs are stacked on the first bonding pair. The N second bonding pairs include a second level and a third level stacked on the second level. The second level includes a second device and a second connection branch electrically coupled to the second device. The third level includes a third device and a third connection branch electrically coupled to the third device. as well as A hierarchical via, uniquely penetrating the first layer of the N second bonding pairs and the first bonding pair, and electrically coupled to the front redistribution layer, the first connection branch, the second connection branch, and the third connection branch. Where N≧1.

20. The device package according to claim 19, characterized in that, in: The bottom layer and the first layer are joined in a front-to-front configuration. The second and third levels are joined in the front-to-front configuration, and The first layer and the layers of the N second bonding pairs are bonded to the first layer in a back-to-back configuration.

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