Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate (100) and a gate drive circuit disposed on the substrate (100). The gate drive circuit comprises a plurality of cascaded shift register circuits. The shift register circuit comprises an input circuit (10), a first control circuit (11), a second control circuit (12), a third control circuit (13) and an output circuit (15). The orthographic projection of the first control circuit (11) on the substrate (100) is located between the orthographic projection of the input circuit (10) and the orthographic projection of the output circuit (15) on the substrate (100) in the first direction (X). The orthographic projection of the third control circuit (13) on the substrate (100) is located between the first control circuit (11) and the orthographic projection of the output circuit (15) on the substrate (100) in the first direction (X). The orthographic projection of the second control circuit (12) on the substrate (100) is located between the orthographic projection of the first control circuit (11) and the orthographic projection of the third control circuit (13) on the substrate (100) in the first direction (X).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

[0006] In one aspect, the embodiment provides a display substrate, comprising: a substrate and a gate drive circuit disposed on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, each of the shift register circuits comprising: an input circuit, a first control circuit, a second control circuit, a third control circuit and an output circuit. The input circuit is connected with a first node, an input terminal and a first clock terminal, and is configured to transmit an input signal provided by the input terminal to the first node under the control of the first clock terminal. The output circuit is connected with a second node. The first control circuit is connected with the first node, the second node, a third node, a first voltage terminal and a second clock terminal, and is configured to control a voltage of the second node under the control of the first node, the third node and the second clock terminal. The second control circuit is connected with the first node, the third node and the first voltage terminal, and is configured to control a voltage of the third node under the control of the first node. The third control circuit is connected with the first node, the second node, a third clock terminal and the first voltage terminal, and is configured to transmit a first voltage signal provided by the first voltage terminal to the first node under the control of the second node and the third clock terminal. Wherein, a projection of the first control circuit on the substrate in a first direction is located between a projection of the input circuit on the substrate and a projection of the output circuit on the substrate; a projection of the third control circuit on the substrate in the first direction is located between a projection of the first control circuit on the substrate and a projection of the output circuit on the substrate; and a projection of the second control circuit on the substrate in the first direction is located between a projection of the first control circuit on the substrate and a projection of the third control circuit on the substrate.

[0007] In some example embodiments, active layers of the plurality of transistors connected with the first voltage terminal in the first control circuit, the second control circuit and the third control circuit are integrated structures.

[0008] In some example embodiments, the first control circuit comprises a plurality of transistors arranged along a second direction; the third control circuit comprises a plurality of transistors arranged along the second direction; and the second direction intersects the first direction.

[0009] In some example embodiments, the first control circuit includes a second transistor, a third transistor and a tenth transistor. A gate of the second transistor is connected with the first node, a first pole of the second transistor is connected with a second pole of the tenth transistor, and a second pole of the second transistor is connected with the second node. A gate of the third transistor is connected with the third node, a first pole of the third transistor is connected with the third clock terminal, and a second pole of the third transistor is connected with the second node. A gate of the tenth transistor is connected with the second clock terminal, and a first pole of the tenth transistor is connected with the first voltage terminal. The tenth transistor, the second transistor and the third transistor are arranged along the second direction.

[0010] In some example embodiments, an active layer of the second transistor, an active layer of the third transistor and an active layer of the tenth transistor are an integral structure; the active layer of the second transistor is located between the active layer of the third transistor and the active layer of the tenth transistor in the second direction. The active layer of the tenth transistor extends along the first direction, and the active layer of the second transistor and the active layer of the third transistor both extend along the second direction. The gate of the tenth transistor extends along the second direction, and the gate of the second transistor and the gate of the third transistor both extend along the first direction.

[0011] In some example embodiments, the second control circuit includes a seventh transistor; a gate of the seventh transistor is connected with the first node, a first pole of the seventh transistor is connected with the first voltage terminal, and a second pole of the seventh transistor is connected with the third node. The seventh transistor, the second transistor and the third transistor are located on the same side of the tenth transistor in the second direction, and the seventh transistor is adjacent to the second transistor in the first direction. An active layer of the seventh transistor is an integral structure with the active layer of the tenth transistor; the active layer of the seventh transistor extends along the second direction. The gate of the seventh transistor is an integral structure with the gate of the second transistor, and the gate of the seventh transistor extends at least along the first direction.

[0012] In some example embodiments, the third control circuit includes a sixth transistor and a ninth transistor. A gate of the sixth transistor is connected with the second node, a first pole of the sixth transistor is connected with the first voltage terminal, and a second pole of the sixth transistor is connected with a first pole of the ninth transistor. A gate of the ninth transistor is connected with the third clock terminal, and a second pole of the ninth transistor is connected with the first node. The sixth transistor and the ninth transistor are arranged in alignment along the second direction, and the sixth transistor and the ninth transistor are adjacent to the seventh transistor in the first direction.

[0013] In some example embodiments, the active layer of the sixth transistor, the active layer of the ninth transistor and the active layer of the tenth transistor are a unitary structure; the active layer of the sixth transistor is between the active layer of the tenth transistor and the active layer of the ninth transistor in the second direction; the active layer of the sixth transistor and the active layer of the ninth transistor both extend along the second direction. The gate of the sixth transistor and the gate of the ninth transistor both extend along the first direction and are arranged in sequence along the second direction.

[0014] In some example embodiments, the shift register circuit further comprises a fourth control circuit and a fifth control circuit. The fourth control circuit is connected with the first node, the output circuit and a second voltage terminal. The fourth control circuit is located on one side of the input circuit in the second direction. The fifth control circuit is connected with the third node and the third clock terminal and is configured to control the voltage of the third node by using the third clock terminal. The fifth control circuit is between the fourth control circuit and the input circuit in the projection of the substrate in the second direction; the fifth control circuit is adjacent to the third transistor in the projection of the substrate in the first direction.

[0015] In some example embodiments, the output circuit comprises a fourth transistor, a fifth transistor, a second capacitor and a third capacitor. The gate of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first voltage terminal, and the second pole of the fourth transistor is connected with an output terminal. The gate of the fifth transistor is connected with the fourth control circuit, the first pole of the fifth transistor is connected with the third clock terminal, and the second pole of the fifth transistor is connected with the output terminal. The first plate of the second capacitor is connected with the second node, and the second plate of the second capacitor is connected with the first voltage terminal; the first plate of the third capacitor is connected with the gate of the fifth transistor, and the second plate of the third capacitor is connected with the output terminal. The fourth transistor and the fifth transistor are arranged in alignment along the second direction, the second capacitor and the third capacitor are located on the same side of the fourth transistor and the fifth transistor in the first direction, and the second capacitor and the third capacitor are arranged in alignment along the second direction. The active layer of the fourth transistor and the active layer of the fifth transistor are a unitary structure. The gate of the fourth transistor, the first plate of the second capacitor and the gate of the sixth transistor are a unitary structure. The gate of the fifth transistor and the first plate of the third capacitor are a unitary structure.

[0016] In some example embodiments, the display substrate further comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line. The first clock terminal of the 4n-3th stage shift register circuit is connected with the first clock signal line, the second clock terminal of the 4n-3th stage shift register circuit is connected with the second clock signal line, and the third clock terminal of the 4n-3th stage shift register circuit is connected with the third clock signal line; the first clock terminal of the 4n-2th stage shift register circuit is connected with the second clock signal line, the second clock terminal of the 4n-2th stage shift register circuit is connected with the third clock signal line, and the third clock terminal of the 4n-2th stage shift register circuit is connected with the fourth clock signal line; the first clock terminal of the 4n-1th stage shift register circuit is connected with the third clock signal line, the second clock terminal of the 4n-1th stage shift register circuit is connected with the fourth clock signal line, and the third clock terminal of the 4n-1th stage shift register circuit is connected with the first clock signal line; the first clock terminal of the 4nth stage shift register circuit is connected with the fourth clock signal line, the second clock terminal of the 4nth stage shift register circuit is connected with the first clock signal line, and the third clock terminal of the 4nth stage shift register circuit is connected with the second clock signal line; n is an integer greater than 0.

[0017] In some example embodiments, the output terminal of the 2i-1th stage shift register circuit is connected with the input terminal of the 2i+1th stage shift register circuit, and the output terminal of the 2ith stage shift register circuit is connected with the input terminal of the 2i+2th stage shift register circuit, i being an integer greater than 0.

[0018] In some example embodiments, the input terminal of the 2i+1th stage shift register circuit is connected with the output terminal of the 2i-1th stage shift register circuit through an input electrode, a stage connection signal line and an output electrode connected in sequence; the input electrode and the output electrode both extend along the first direction, and the stage connection signal line extends at least along a second direction; the second direction intersects the first direction; and the stage connection signal line is located on the side of the input electrode and the output electrode away from the substrate.

[0019] In some example embodiments, in the direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged on the substrate; the stage connection signal line, the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are located in the fourth conductive layer; the input electrode is located in the third conductive layer; and the output electrode is located in the second conductive layer.

[0020] In some example embodiments, the first control circuit of the shift register circuit comprises a tenth transistor, a gate of the tenth transistor being connected with the second clock end. The gate of the tenth transistor is connected with a clock signal line through a second clock connecting electrode; a connection via between the gate of the tenth transistor and the second clock connecting electrode is located between the third clock signal line and the fourth clock signal line in the orthographic projection of the substrate.

[0021] In some example embodiments, the third clock end of the n-th shift register circuit and the second clock end of the n+1-th shift register circuit are connected with the same clock signal line through different vias.

[0022] In another aspect, the embodiments provide a display device comprising the display substrate as described above.

[0023] In another aspect, the embodiments provide a method for manufacturing the display substrate as described above, the method comprising: providing a substrate; and forming a gate driving circuit on the substrate. The gate driving circuit comprises a plurality of cascaded shift register circuits, each of the shift register circuits comprising: an input circuit, a first control circuit, a second control circuit, a third control circuit, and an output circuit; the input circuit being connected with a first node, an input end, and a first clock end, and being configured to transmit an input signal provided by the input end to the first node under the control of the first clock end; the output circuit being connected with a second node; the first control circuit being connected with the first node, the second node, a third node, a first voltage end, and a second clock end, and being configured to control a voltage of the second node under the control of the first node, the third node, and the second clock end; the second control circuit being connected with the first node, the third node, and the first voltage end, and being configured to control a voltage of the third node under the control of the first node; and the third control circuit being connected with the first node, the second node, a third clock end, and the first voltage end, and being configured to transmit a first voltage signal provided by the first voltage end to the first node under the control of the second node and the third clock end. The first control circuit is located between the input circuit and the output circuit in the orthographic projection of the substrate in a first direction; the third control circuit is located between the first control circuit and the output circuit in the orthographic projection of the substrate in the first direction; and the second control circuit is located between the first control circuit and the third control circuit in the orthographic projection of the substrate in the first direction.

[0024] In another aspect, the embodiment provides a display substrate, comprising: a substrate and a gate drive circuit disposed on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, each of the shift register circuits comprising: an input circuit, a control circuit and an output circuit. The input circuit is connected with a first node, an input terminal and a first clock terminal, and is configured to transmit an input signal provided by the input terminal to the first node under the control of the first clock terminal; the control circuit is connected with the first node, a second node, a fourth node, a second clock terminal, a third clock terminal and a first voltage terminal, and is configured to control voltages of the second node and the fourth node; the output circuit is connected with the second node, the fourth node, the third clock terminal, the first voltage terminal and an output terminal, and is configured to control the output terminal to provide an output signal under the control of the second node and the fourth node. In the control circuit, active layers of a plurality of transistors connected with the first voltage terminal are in an integrated structure, the integrated structure has a common connection terminal and a plurality of branches extending from the common connection terminal, and the common connection terminal is configured to be connected with the first voltage terminal.

[0025] In some example embodiments, the integrated structure has a first branch, a second branch and a third branch; the first branch, the second branch and the third branch are arranged along the first direction; the first branch extends from the common connection terminal in a stepped manner along a second direction; the second branch extends from the common connection terminal along the first direction and the second direction in sequence; the third branch extends along the second direction; and the second direction intersects the first direction.

[0026] Other aspects can become apparent from a review of the drawings and detailed description.

[0027] SUMMARY

[0028] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0029] FIG. 1 is a structural schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0030] FIG. 2 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0031] FIG. 3 is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure;

[0032] FIG. 4 is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0033] FIG. 5 is a top view of a shift register circuit in FIG. 4;

[0034] FIG. 6 is a schematic view of a partial cross section along the QQ' direction in FIG. 4;

[0035] FIG. 7 is a schematic view of the display substrate after forming a semiconductor layer in FIG. 4;

[0036] FIG. 8 is a schematic view of the display substrate after forming a first conductive layer in FIG. 4;

[0037] FIG. 9 is a schematic view of the first conductive layer in FIG. 8;

[0038] FIG. 10 is a schematic view of the display substrate after forming a second conductive layer in FIG. 4;

[0039] FIG. 11 is a schematic view of the second conductive layer in FIG. 10;

[0040] FIG. 12 is a schematic view of the display substrate after forming a third insulating layer in FIG. 4;

[0041] FIG. 13 is a schematic view of the display substrate after forming a third conductive layer in FIG. 4;

[0042] FIG. 14 is a schematic view of the third conductive layer in FIG. 13;

[0043] FIG. 15 is a schematic view of the display substrate after forming a fourth insulating layer in FIG. 4;

[0044] FIG. 16 is a schematic view of a fourth conductive layer in FIG. 4;

[0045] FIG. 17 is a partial equivalent circuit diagram of a gate drive circuit according to at least one embodiment of the present disclosure;

[0046] FIG. 18 is another partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0047] FIG. 19 is a schematic view of the display substrate after forming a third conductive layer in FIG. 18;

[0048] FIG. 20 is a schematic view of the display substrate after forming a fourth insulating layer in FIG. 18;

[0049] FIG. 21 is a schematic view of a display device according to at least one embodiment of the present disclosure.

[0050] Detailed Description

[0051] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and contents can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other without conflict.

[0052] In the drawings, the size, the thickness, or the region of one or more of constituent elements shown in the drawings can sometimes be exaggerated for clarity. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of one or more of the components in the drawings do not reflect actual proportions of the components. Furthermore, the present disclosure is not limited to the shapes, the values, and the like illustrated in the drawings.

[0053] The ordinal numbers, such as "first", "second", and "third", are used for the purpose of avoiding ambiguity, and do not necessarily limit the number or order of the constituent elements. "A plurality of" in the present disclosure means two or more.

[0054] In the present specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside", and the like used to describe the positional relationship of the constituent elements with reference to the drawings are used for the purpose of facilitating the description of the present specification and simplifying the description, and do not indicate or imply that a specific orientation is required for the device or element being referred to, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed depending on the situation.

[0055] In the present specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or connection; it can be direct connection, or indirect connection through an intermediate, or communication between two elements inside. Among them, "connection" includes "electrical connection". "Electrical connection" includes the case where the constituent elements are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like. The meaning of the above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0056] In the present specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In the present specification, the channel region refers to a region where current flows mainly.

[0057] In this specification, the first electrode can be a drain electrode, the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In addition, the gate electrode can also be referred to as a control electrode. In the case of using a transistor whose polarity is reversed or in the case where the current direction is changed in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged from each other. Thus, the "source electrode" and the "drain electrode" can be interchanged with each other in this specification.

[0058] In this specification, "parallel" indicates a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus also includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" indicates a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus also includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0059] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformations due to a tolerance, such as a draft angle, a curved edge, and a deformation.

[0060] In this specification, "approximately" and "substantially" mean that a limit is not strictly defined and a range of process and measurement errors is allowed. In this disclosure, "substantially the same" means that the values differ within a range of 10 %.

[0061] In this specification, A extending in the direction of B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends in the direction of B, and the length of the main portion extending in the direction of B is greater than the length of the sub-portion extending in another direction. In this specification, "A extending in the direction of B" means "the main portion of A extending in the direction of B".

[0062] In this specification, "A and B are in the same layer structure" or "A and B are provided in the same layer" means that A and B are formed at the same time by one patterning process. The "same layer" does not always mean that the thickness or the height of the layer is the same in a cross-sectional view. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. "The orthogonal projection of A contains the orthogonal projection of B" means that the orthogonal projection of B falls within the range of the orthogonal projection of A or the orthogonal projection of A covers the orthogonal projection of B.

[0063] In some implementations, as the number of transistors and capacitors of the gate driving circuit increases, the arrangement space occupied by the gate driving circuit increases, which is not conducive to narrow the frame. Moreover, the increase of the wiring will increase the arrangement difficulty, and there is a case that the node overlapping capacitor distribution is not conducive to the stable output signal.

[0064] The embodiment provides a display substrate, comprising a substrate and a gate drive circuit arranged on the substrate. The gate drive circuit comprises a plurality of cascaded shift register circuits. The shift register circuit comprises an input circuit, a first control circuit, a second control circuit, a third control circuit and an output circuit. The input circuit is connected with a first node, an input end and a first clock end, and is configured to transmit an input signal provided by the input end to the first node under the control of the first clock end. The output circuit is connected with a second node. The first control circuit is connected with the first node, the second node, a third node, a first voltage end and a second clock end, and is configured to control a voltage of the second node under the control of the first node, the third node and the second clock end. The second control circuit is connected with the first node, the third node and the first voltage end, and is configured to control a voltage of the third node under the control of the first node. The third control circuit is connected with the first node, the second node, a third clock end and the first voltage end, and is configured to transmit a first voltage signal provided by the first voltage end to the first node under the control of the second node and the third clock end.

[0065] The first control circuit is located between the input circuit and the output circuit in the orthographic projection of the substrate in the first direction; the third control circuit is located between the first control circuit and the output circuit in the orthographic projection of the substrate in the first direction; and the second control circuit is located between the first control circuit and the third control circuit in the orthographic projection of the substrate in the first direction.

[0066] The display substrate provided by the embodiment can save the space occupied by the arrangement of the gate drive circuit by optimizing the spatial arrangement of the input circuit, the first control circuit, the second control circuit, the third control circuit and the output circuit, and is beneficial to stable signal output.

[0067] In some example embodiments, the active layers of the plurality of transistors connected with the first voltage end in the first control circuit, the second control circuit and the third control circuit can be integrated structures. The arrangement mode of the example can effectively utilize the arrangement space and reduce space waste.

[0068] In some example embodiments, the first control circuit can comprise a plurality of transistors, and the plurality of transistors can be arranged along a second direction. The third control circuit can comprise a plurality of transistors, and the plurality of transistors can be arranged along the second direction. The second direction intersects the first direction. For example, the first direction can be perpendicular to the second direction. In some examples, the plurality of transistors of the first control circuit can be arranged staggered along the second direction, and the plurality of transistors of the third control circuit can be arranged aligned along the second direction. The arrangement mode of the example can effectively utilize the arrangement space and reduce space waste.

[0069] In some example embodiments, the first control circuit can include a second transistor, a third transistor and a tenth transistor. A gate of the second transistor is connected with the first node, a first pole of the second transistor is connected with a second pole of the tenth transistor, and a second pole of the second transistor is connected with the second node. A gate of the third transistor is connected with the third node, a first pole of the third transistor is connected with the third clock terminal, and a second pole of the third transistor is connected with the second node. A gate of the tenth transistor is connected with the second clock terminal, and a first pole of the tenth transistor is connected with the first voltage terminal. The tenth transistor, the second transistor and the third transistor can be arranged along the second direction. For example, the tenth transistor, the second transistor and the third transistor can be arranged in a stepped manner along the second direction. The arrangement of the second transistor, the third transistor and the tenth transistor in the example can effectively utilize the arrangement space.

[0070] In some example embodiments, the second control circuit can include a seventh transistor. A gate of the seventh transistor is connected with the first node, a first pole of the seventh transistor is connected with the first voltage terminal, and a second pole of the seventh transistor is connected with the third node. The seventh transistor, the second transistor and the third transistor are located on the same side of the tenth transistor along the second direction, and the seventh transistor is adjacent to the second transistor along the first direction. The active layer of the seventh transistor and the active layer of the tenth transistor can be an integral structure. The gate of the seventh transistor and the gate of the second transistor are an integral structure. The arrangement of the seventh transistor in the example can effectively utilize the arrangement space and optimize the spatial layout.

[0071] In some example embodiments, the third control circuit can include a sixth transistor and a ninth transistor. A gate of the sixth transistor is connected with the second node, a first pole of the sixth transistor is connected with the first voltage terminal, and a second pole of the sixth transistor is connected with a first pole of the ninth transistor. A gate of the ninth transistor is connected with the third clock terminal, and a second pole of the ninth transistor is connected with the first node. The sixth transistor and the ninth transistor are arranged in alignment along the second direction, and the sixth transistor and the ninth transistor are adjacent to the seventh transistor along the first direction. The active layer of the sixth transistor, the active layer of the ninth transistor and the active layer of the tenth transistor can be an integral structure. The arrangement of the third control circuit in the example can be conducive to optimizing the wiring space along the first direction.

[0072] In some example embodiments, the shift register circuit can further include a fourth control circuit and a fifth control circuit. The fourth control circuit is connected with the first node, the output circuit and the second voltage terminal. The fourth control circuit is located on one side of the input circuit in the second direction. The fifth control circuit is connected with the third node and the third clock terminal, and is configured to control the voltage of the third node by using the third clock terminal. The fifth control circuit can be located between the fourth control circuit and the input circuit in the second direction in the orthographic projection of the substrate. The fifth control circuit can be adjacent to the third transistor in the first direction in the orthographic projection of the substrate. In some examples, the fifth control circuit can include a first capacitor. The first plate of the first capacitor is in an integral structure with the gate of the third transistor, and the second plate of the first capacitor is connected with the third clock terminal. The first capacitor in this example can ensure the size of the plate area of the first capacitor, and can also reduce the lateral wiring distance by reasonable layout.

[0073] In some example embodiments, the input circuit can include a first transistor. The gate of the first transistor is connected with the first clock terminal, the first electrode of the first transistor is connected with the input terminal, and the second electrode of the first transistor is connected with the first node. The active layer of the first transistor is in a U shape in the orthographic projection of the substrate, and the opening of the U shape faces away from the first capacitor.

[0074] In some example embodiments, the display substrate can further include a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line. The first clock terminal of the 4n-3 stage shift register circuit is connected with the first clock signal line, the second clock terminal is connected with the second clock signal line, and the third clock terminal is connected with the third clock signal line; the first clock terminal of the 4n-2 stage shift register circuit is connected with the second clock signal line, the second clock terminal is connected with the third clock signal line, and the third clock terminal is connected with the fourth clock signal line; the first clock terminal of the 4n-1 stage shift register circuit is connected with the third clock signal line, the second clock terminal is connected with the fourth clock signal line, and the third clock terminal is connected with the first clock signal line; the first clock terminal of the 4n stage shift register circuit is connected with the fourth clock signal line, the second clock terminal is connected with the first clock signal line, and the third clock terminal is connected with the second clock signal line; n is an integer greater than 0. This example takes four shift register circuits as one cycle, and can reduce the toggle number of clock signals, thereby reducing the clock power consumption.

[0075] In some example embodiments, the third clock terminal of the n-th stage shift register circuit and the second clock terminal of the n+1-th stage shift register circuit can be connected to the same clock signal line through different vias. In this example, the adjacent shift register circuits are connected to the same clock signal line through different vias, which can optimize the layout space and ensure that the arrangement of the clock signal access at different positions is the same, thereby ensuring the consistency of the signal load when accessed.

[0076] The scheme of the present embodiment is illustrated below by way of some examples.

[0077] In some examples, the display substrate can include a display area and a non-display area. For example, the non-display area can be located at the periphery of the display area. The non-display area can be a bezel area surrounding the display area. In other examples, the non-display area can be located between adjacent display areas.

[0078] In some examples, the display area can include a plurality of sub-pixels. One pixel unit in the display area can include three sub-pixels, which can be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which can include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. In other examples, one pixel unit can include four sub-pixels, which can include a red sub-pixel, a blue sub-pixel, and two green sub-pixels.

[0079] In some examples, a sub-pixel can include a pixel circuit and a light emitting element connected to the pixel circuit. The shape of the light emitting element can be rectangular, rhombic, pentagonal, or hexagonal. When one pixel unit includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner. When one pixel unit includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiment is not limited thereto.

[0080] In some examples, the display area can include at least a plurality of pixel circuits arranged in an array, a plurality of gate lines (e.g., including scan lines, reset signal lines, and light emitting control lines) extending in a first direction, and a plurality of data lines extending in a second direction. A plurality of rows of pixel circuits can be arranged in the second direction, and each row of pixel circuits can include a plurality of pixel circuits arranged in the first direction. The first direction and the second direction can be in the same plane, and the first direction and the second direction can intersect, e.g., the first direction can be perpendicular to the second direction.

[0081] In some examples, the pixel circuit can be configured to drive the connected light emitting element. For example, the pixel circuit can be configured to provide a driving current to drive the light emitting element to emit light. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit can be P-type transistors or can be N-type transistors, and the use of the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0082] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, and the light emitting element can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiment is not limited thereto.

[0083] In some examples, the non-display area can be provided with a timing controller, a data driving circuit, and a gate driving circuit. Wherein, the gate driving circuit can be respectively arranged at opposite sides of the display area, for example, the left side and the right side of the display area (such as the left and right side frames included in the peripheral area); the timing controller and the data driving circuit can be arranged at one side of the display area, for example, the lower side of the display area (such as the lower side frame included in the peripheral area). However, the present embodiment is not limited thereto. In some examples, the gate driving circuit can be located in the display area.

[0084] In some examples, the data driving circuit can provide a data signal to the sub-pixel of the display area through the data line. The timing controller can provide a driving signal to the data driving circuit and the gate driving circuit. The actions of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide the data driving circuit with the gray data that specifies the gray scale at which the sub-pixel should be displayed. The data driving circuit can provide the data signal corresponding to the potential of the gray data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuit through the data line.

[0085] In some examples, the display substrate can include a plurality of gate driving circuits, such as a gate driving circuit for outputting a scan signal, a gate driving circuit for outputting a light-emitting control signal, and the like. For example, the gate driving circuit for outputting a scan signal can provide a scan signal to the sub-pixel through a scan line and provide a reset signal to the sub-pixel through a reset signal line. The gate driving circuit for outputting a light-emitting control signal can provide a light-emitting control signal to the sub-pixel through a light-emitting control line. Each gate driving circuit can include a plurality of cascaded shift register circuits. The output end of each shift register circuit can be connected to a plurality of pixel circuits in a corresponding row of pixel circuits, respectively, and configured to provide a driving signal (such as a scan signal) to the row of pixel circuits.

[0086] FIG. 1 is a structural schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the shift register circuit of the present example can include an input circuit 10, a control circuit, and an output circuit 16. The control circuit can include a first control circuit 11, a second control circuit 12, a third control circuit 13, a fourth control circuit 14, and a fifth control circuit 15.

[0087] In some examples, the input circuit 11 is connected with the input terminal IN, the first clock terminal CLK1 and the first node N1, and is configured to transmit an input signal provided by the input terminal IN to the first node N1 under the control of the first clock terminal CLK1. The first control circuit 11 is connected with the first node N1, the second node N2, the third node N3, the second clock terminal CLK2, the third clock terminal CLK3 and the first voltage terminal VH, and is configured to control the voltage of the second node N2 under the control of the first node N1, the third node N3 and the second clock terminal CLK2. The second control circuit 12 is connected with the first node N1, the third node N3 and the first voltage terminal VH, and is configured to control the potential of the third node N3 under the control of the first node N1. The third control circuit 13 is connected with the first node N1, the second node N2, the first voltage terminal VH and the third clock terminal CLK3, and is configured to transmit a first voltage signal provided by the first voltage terminal VH to the first node N1 under the control of the second node N2 and the third clock terminal CLK3. The fourth control circuit 14 is connected with the first node N1, the fourth node N4 and the second voltage terminal VL, and is configured to turn on the first node N1 and the fourth node N4 under the control of the second voltage terminal VL. The fourth control circuit 14 can be configured to transmit a signal from the first node N1 to the fourth node N4 and stabilize the voltage of the fourth node N4. The fifth control circuit 15 is connected with the third node N3 and the third clock terminal CLK3, and is configured to control the voltage of the third node N3 by using the third clock terminal CLK3. The output circuit 16 is connected with the second node N2, the fourth node N4, the output terminal OUT, the first voltage terminal VH and the third clock terminal CLK3, and is configured to transmit a first voltage signal transmitted by the first voltage terminal VH to the output terminal OUT under the control of the second node N2, or transmit a signal provided by the third clock terminal CLK3 to the output terminal OUT under the control of the fourth node N4.

[0088] In some examples, the first voltage terminal VH can be connected with a first voltage line VGH and is configured to continuously provide a first voltage signal at a high level, and the second voltage terminal VL can be connected with a second voltage line VGL and is configured to continuously provide a second voltage signal at a low level. The first voltage signal is greater than the second voltage signal. However, the present embodiment is not limited in this regard.

[0089] The "high level" and "low level" mentioned herein are relative, and the voltage value of the "high level" and the voltage value of the "low level" are not limited.

[0090] The shift register circuit provided by the embodiment can avoid transmitting the first voltage signal provided by the first voltage terminal VH to the output terminal OUT in the process of transmitting the signal provided by the third clock terminal CLK3 to the output terminal OUT, and can avoid transmitting the signal provided by the third clock terminal CLK3 to the output terminal OUT in the process of transmitting the first voltage signal to the output terminal OUT, so that the accuracy of the output signal can be avoided. Moreover, by setting the third control circuit 13, the voltage of the first node N1 can be high when the voltage of the second node N2 is low, so that the third node N3 is in a floating state, and the voltage of the third node N3 is controlled by the signal provided by the third clock terminal CLK3. In this way, the second control circuit 12 can avoid transmitting the high-level first voltage signal to the third node N3, and the first control circuit 11 can avoid transmitting the high-level first voltage signal to the second node N2, so as to ensure that the voltage of the second node N2 remains in a low state, and to ensure that the output circuit 16 can stably output the first voltage signal. In addition, by setting the fourth control circuit 14, the fourth node N4 can avoid leakage through the input circuit 10, so that the voltage of the fourth node N4 is relatively stable, and the output circuit 16 has a relatively stable conduction state, and the voltage of the first node N1 is relatively controllable and stable, so as to avoid affecting the working performance of the input circuit 10 and the third control circuit 13 due to the large change of the voltage of the first node N1.

[0091] FIG. 2 is an equivalent circuit diagram of the shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2, the input circuit 10 includes a first transistor T1. The gate of the first transistor T1 is connected with the first clock terminal CLK1, the first electrode of the first transistor T1 is connected with the input terminal IN, and the second electrode of the first transistor T1 is connected with the first node N1.

[0092] In some examples, the first control circuit 11 includes a second transistor T2, a third transistor T3, and a tenth transistor T10. The gate of the second transistor T2 is connected with the first node N1, the first electrode of the second transistor T2 is connected with the second electrode of the tenth transistor T10, and the second electrode of the second transistor T2 is connected with the second node N2. The gate of the third transistor T3 is connected with the third node N3, the first electrode of the third transistor T3 is connected with the third clock terminal CLK3, and the second electrode of the third transistor T3 is connected with the second node N2. The gate of the tenth transistor T10 is connected with the second clock terminal CLK2, and the first electrode of the tenth transistor T10 is connected with the first voltage terminal VH.

[0093] In some examples, the second control circuit 12 includes a seventh transistor T7. The gate of the seventh transistor T7 is connected with the first node N1, the first electrode of the seventh transistor T7 is connected with the first voltage terminal VH, and the second electrode of the seventh transistor T7 is connected with the third node N3.

[0094] In some examples, the third control circuit 13 includes a sixth transistor T6 and a ninth transistor T9. The gate of the sixth transistor T6 is connected with the second node N2, the first electrode of the sixth transistor T6 is connected with the first voltage terminal VH, and the second electrode of the sixth transistor T6 is connected with the first electrode of the ninth transistor T9. The gate of the ninth transistor T9 is connected with the third clock terminal CLK3, and the second electrode of the ninth transistor T9 is connected with the first node N1.

[0095] In some examples, the fourth control circuit 14 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected with the second voltage terminal VL, the first electrode of the eighth transistor T8 is connected with the first node N1, and the second electrode of the eighth transistor T8 is connected with the fourth node N4.

[0096] In some examples, the fifth control circuit 15 includes a first capacitor C1. The first plate of the first capacitor C1 is connected with the third node N3, and the second plate of the first capacitor C1 is connected with the third clock terminal CLK3.

[0097] In some examples, the output circuit 16 includes a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a third capacitor C3. The gate of the fourth transistor T4 is connected with the second node N2, the first electrode of the fourth transistor T4 is connected with the first voltage terminal VH, and the second electrode of the fourth transistor T4 is connected with the output terminal OUT. The gate of the fifth transistor T5 is connected with the fourth node N4, the first electrode of the fifth transistor T5 is connected with the third clock terminal CLK3, and the second electrode of the fifth transistor T5 is connected with the output terminal OUT. The first plate of the second capacitor C2 is connected with the second node N2, and the second plate of the second capacitor C2 is connected with the first voltage terminal VH. The first plate of the third capacitor C3 is connected with the fourth node N4, and the second plate of the third capacitor C3 is connected with the output terminal OUT. In this example, the fourth transistor T4 and the fifth transistor T5 are output transistors.

[0098] In this example, the first node N1 is the connection point of the first transistor T1, the second transistor T2, the seventh transistor T7, the ninth transistor T9 and the eighth transistor T8, the second node N2 is the connection point of the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the second capacitor C2, the third node N3 is the connection point of the third transistor T3, the seventh transistor T7 and the first capacitor C1, and the fourth node N4 is the connection point of the fifth transistor T5, the eighth transistor T8 and the third capacitor C3.

[0099] In the present example, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not represent actual components, but rather junctions of relevant electrical connections in the circuit diagram. In other words, these nodes are equivalent to junctions of relevant electrical connections in the circuit diagram.

[0100] An exemplary structure of the first control circuit 11, the second control circuit 12, the third control circuit 13, the fourth control circuit 14, the fifth control circuit 15, the input circuit 10 and the output circuit 16 is shown in FIG. 2. A person skilled in the art can understand that the implementation of the first control circuit, the second control circuit, the third control circuit, the fourth control circuit, the fifth control circuit, the input circuit and the output circuit is not limited to this, as long as the functions thereof can be realized.

[0101] FIG. 3 is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 3, the gate drive circuit can include a plurality of shift register circuits (such as a first stage shift register circuit GOA(1) to a fourth stage shift register circuit GOA(4)). Among them, the 2i-1 stage shift register circuit and the 2i+1 stage shift register circuit are connected in series, the 2i stage shift register circuit and the 2i+2 stage shift register circuit are connected in series, and i is an integer greater than 0. The output terminal of the 2i-1 stage shift register circuit is connected with the input terminal of the 2i+1 stage shift register circuit, and the output terminal of the 2i stage shift register circuit is connected with the input terminal of the 2i+2 stage shift register circuit. Except for the last even stage shift register circuit, the output signal of each even stage shift register circuit can be used as the input signal of the next even stage shift register circuit; except for the last odd stage shift register circuit, the output signal of each odd stage shift register circuit can be used as the input signal of the next odd stage shift register circuit. In the present example, the even stage shift register circuit and the odd stage shift register circuit are connected in series separately.

[0102] In some examples, as shown in FIG. 3, the input terminal IN of the first stage shift register circuit GOA(1) is connected with the start signal line STV, and the input terminal IN of the second stage shift register circuit GOA(2) is connected with the start signal line STV. Among them, the input terminal IN of the first stage shift register circuit GOA(1) and the input terminal IN of the second stage shift register circuit GOA(2) can be configured to receive the same start signal. In other examples, the input terminal IN of the first stage shift register circuit GOA(1) and the input terminal IN of the second stage shift register circuit GOA(2) can be connected with different start signal lines, such as configured to receive different start signals. The present embodiment is not limited in this regard.

[0103] In some examples, the output terminal OUT of the first-stage shift register circuit GOA(1) is connected with the input terminal of the third-stage shift register circuit GOA(3), and the output terminal OUT of the second-stage shift register circuit GOA(2) is connected with the input terminal of the fourth-stage shift register circuit GOA(4). The output terminal OUT of the third-stage shift register circuit GOA(3) can be connected with the input terminal of the fifth-stage shift register circuit, and the output terminal OUT of the fourth-stage shift register circuit GOA(4) can be connected with the input terminal of the sixth-stage shift register circuit.

[0104] In some examples, as shown in FIG. 3, the first voltage terminal VH of each stage of shift register circuit can be connected with the first voltage line VGH, and the second voltage terminal VL of each stage of shift register circuit can be connected with the second voltage line VGL.

[0105] In some examples, the first clock terminal CLK1 of the 4n-3 stage shift register circuit (for example, the first-stage shift register circuit GOA(1)) is connected with the first clock signal line CL1, the second clock terminal CLK2 is connected with the second clock signal line CL2, and the third clock terminal CLK3 is connected with the third clock signal line CL3. The first clock terminal CLK1 of the 4n-2 stage shift register circuit (for example, the second-stage shift register circuit GOA(2)) is connected with the second clock signal line CL2, the second clock terminal CLK2 is connected with the third clock signal line CL3, and the third clock terminal CLK3 is connected with the fourth clock signal line CL4. The first clock terminal CLK1 of the 4n-1 stage shift register circuit (for example, the third-stage shift register circuit GOA(3)) is connected with the third clock signal line CL3, the second clock terminal CLK2 is connected with the fourth clock signal line CL4, and the third clock terminal CLK3 is connected with the first clock signal line CL1. The first clock terminal CLK1 of the 4n stage shift register circuit (for example, the fourth-stage shift register circuit GOA(4)) is connected with the fourth clock signal line CL4, the second clock terminal CLK2 is connected with the first clock signal line CL1, and the third clock terminal CLK3 is connected with the second clock signal line CL2. Wherein, n is an integer greater than 0.

[0106] In the present example, the gate drive circuit is connected with four clock signal lines (i.e., the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4), and every four stages of shift register circuit forms a cycle, so that the signals of the three clock terminals of the four stages of shift register circuit are provided by the four clock signal lines. By providing the four clock signal lines, the present example can reduce the toggle times of the clock signals, which is conducive to reducing the clock power consumption. The connection mode of the stages of shift register circuit and the connection mode of the four clock signal lines can be matched to meet the working timing of the shift register circuit.

[0107] FIG. 4 is a partial top view of a display substrate according to an embodiment of the present disclosure. FIG. 5 is a top view of a shift register circuit in FIG. 4. FIG. 6 is a partial cross-sectional view of FIG. 4 along the direction of QQ'. The top view of one shift register circuit (e.g., the 4n-3th shift register circuit, n is an integer greater than 0) of the display substrate in FIG. 4 and FIG. 5 is shown. The equivalent circuit of the shift register circuit in the present example can be as shown in FIG. 2. In the present example, the transistors in the shift register circuit are all P-type transistors, and a low-temperature polysilicon thin-film transistor is taken as an example for illustration. However, the present embodiment is not limited thereto.

[0108] In some examples, as shown in FIG. 4 and FIG. 5, the outer contour of a single shift register circuit can be substantially rectangular in the plane parallel to the display substrate. The arrangement area of the gate driving circuit can be divided into a first area S1, a second area S2 and a third area S3 arranged in sequence along the first direction X. The first area S1, the second area S2 and the third area S3 can be arranged in the direction close to the display area along the first direction X. The input circuit 10, the fifth control circuit 15 and the fourth control circuit 14 of the shift register circuit can be located in the first area S1 in the orthographic projection of the substrate; the first control circuit 11, the second control circuit 12 and the third control circuit 13 can be located in the second area S2 in the orthographic projection of the substrate; and the output circuit 16 can be located in the third area S3 in the orthographic projection of the substrate. In the first area S1, the fifth control circuit 15 can be located between the input circuit 10 and the fourth control circuit 14 in the orthographic projection of the substrate along the second direction Y. In the second area S2, the second control circuit 12 can be located between the first control circuit 11 and the third control circuit 13 in the orthographic projection of the substrate along the first direction X, and the orthographic projection of the second control circuit 12 in the substrate can be adjacent to the orthographic projection of the first control circuit 11 in the substrate along the second direction Y. The arrangement manner of the present example can make full use of the arrangement space of the gate driving circuit.

[0109] In some examples, as shown in FIG. 6, in a direction perpendicular to the display substrate, the display substrate can include: a base 100, a semiconductor layer (for example, the active layer 310 including the tenth transistor) disposed on the base 100 in sequence, a first conductive layer (for example, the gate 210 including the tenth transistor), a second conductive layer, a third conductive layer (for example, including the second clock connection electrode 422a), and a fourth conductive layer (for example, including the second clock signal line CL2 and the third clock signal line CL3). Among them, a first insulating layer 101 can be disposed between the semiconductor layer and the first conductive layer, a second insulating layer 102 can be disposed between the first conductive layer and the second conductive layer, a third insulating layer 103 can be disposed between the second conductive layer and the third conductive layer, and a fourth insulating layer 104 can be disposed between the third conductive layer and the fourth conductive layer. In some examples, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can each be an inorganic insulating layer, and the fourth insulating layer 104 can be an organic insulating layer. However, the present embodiment is not limited in this regard.

[0110] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development, etc. for organic materials. Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, coating can use any one or more of spraying, spin coating and inkjet printing, etching can use any one or more of dry etching and wet etching, and the present disclosure is not limited in this regard. "Thin film" refers to a thin film of a certain material made on a substrate by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0111] The preparation process of the display substrate of the present example can include the following steps.

[0112] (1), providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass, quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer can adopt polyimide (PI), polyethylene terephthalate (PET) or surface treated polymer soft film and the like, the materials of the first inorganic material layer and the second inorganic material layer can adopt silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0) and the like, for improving the water and oxygen resistance of the substrate.

[0113] (2), forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate. In some examples, the material of the semiconductor layer can adopt amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathienyl or polythiophene and the like.

[0114] Figure 7 is a schematic view of the display substrate after forming the semiconductor layer in Figure 4. In some examples, as shown in Figure 7, the semiconductor layer of the display substrate can at least include the active layer of the plurality of transistors of the shift register circuit, for example including the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 34 of the fourth transistor T4, the active layer 35 of the fifth transistor T5, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 38 of the eighth transistor T8, the active layer 39 of the ninth transistor T9 and the active layer 310 of the tenth transistor T10.

[0115] In some examples, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. The material of the semiconductor layer may, for example, include polysilicon or an oxide (e.g., indium gallium zinc oxide (IGZO)). The channel region of the transistor can be undoped with impurities and have semiconductor properties. The first region and the second region can be doped regions on both sides of the channel region and doped with impurities and thus have electrical conductivity. The impurities can vary depending on the type of the transistor. In some examples, the doped regions of the active layer can be interpreted as the source electrode or the drain electrode of the transistor. For example, the first region of the active layer can be interpreted as the first electrode of the transistor, and the second region of the active layer can be interpreted as the second electrode of the transistor. The portion of the active layer between the transistors can be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors. The present embodiments are not limited in this regard.

[0116] In some examples, as shown in FIGS. 5 and 7, the active layer 31 of the first transistor T1 and the active layer 38 of the eighth transistor T8 can be located in the first region S1; the active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 39 of the ninth transistor T9, and the active layer 310 of the tenth transistor T10 can be located in the second region S2; and the active layer 34 of the fourth transistor T4 and the active layer 35 of the fifth transistor T5 can be located in the third region S3.

[0117] In some examples, the active layer 31 of the first transistor T1 and the active layer 38 of the eighth transistor T8 can be arranged along the second direction Y. The orthogonal projection of the active layer 31 of the first transistor T1 on the substrate can be U-shaped. The orthogonal projection of the active layer 38 of the eighth transistor T8 on the substrate can be a strip extending along the second direction Y. The active layer 38 of the eighth transistor T8 can be located on a side of the U-shaped opening of the active layer 31 of the first transistor T1 facing away from the second direction Y.

[0118] In some examples, the active layer 34 of the fourth transistor T4 and the active layer 35 of the fifth transistor T5 can be arranged along the second direction Y. The active layer 34 of the fourth transistor T4 and the active layer 35 of the fifth transistor T5 can be an integral structure, and the orthogonal projection of the integral structure on the substrate can be rectangular.

[0119] In some examples, the active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 39 of the ninth transistor T9, and the active layer 310 of the tenth transistor T10 can be an integrated structure, and the integrated structure is located between the active layer 31 of the first transistor T1 and the active layer 34 of the fourth transistor T4 in the first direction X. The active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, and the active layer 39 of the ninth transistor T9 are located on the same side of the active layer 310 of the tenth transistor T10 in the second direction Y. The active layer 33 of the third transistor T3 is located on one side of the active layer 32 of the second transistor T2 in the first direction X, and the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 39 of the ninth transistor T9, and the active layer 310 of the tenth transistor T10 are located on the other side of the active layer 32 of the second transistor T2 in the first direction X.

[0120] In some examples, the active layer 33 of the third transistor T3 is adjacent to the active layer 38 of the eighth transistor T8 in the first direction X, and the active layer 32 of the second transistor T2 is adjacent to the active layer 31 of the first transistor T1 in the first direction X. The active layer 33 of the third transistor T3 can be located on the side of the active layer 32 of the second transistor T2 close to the active layer 38 of the eighth transistor T8. The active layer 310 of the tenth transistor T10 can be located on the side of the active layer 32 of the second transistor T2 away from the active layer 31 of the first transistor T1 in the first direction X. The active layer 36 of the sixth transistor T6 and the active layer 39 of the ninth transistor T9 are adjacent to the integrated structure of the active layer 34 of the fourth transistor T4 and the active layer 35 of the fifth transistor T5 in the first direction X. The active layer 37 of the seventh transistor T7 is located between the active layer 32 of the second transistor T2 and the active layer 36 of the sixth transistor T6 in the first direction X.

[0121] In some examples, the active layer 310 of the tenth transistor T10, the active layer 32 of the second transistor T2, and the active layer 33 of the third transistor T3 can be arranged along the second direction Y, for example, arranged in a stepped manner along the second direction Y. The active layer 32 of the second transistor T2 can be connected between the active layer 310 of the tenth transistor T10 and the active layer 33 of the third transistor T3. Among them, the second region of the active layer 33 of the third transistor T3 can simultaneously serve as the second region of the active layer 32 of the second transistor T2, and the first region of the active layer 32 of the second transistor T2 can simultaneously serve as the second region of the active layer 310 of the tenth transistor T10.

[0122] In some examples, the active layer 32 of the second transistor T2 and the active layer 33 of the third transistor T3 can extend at least along the second direction Y, and the active layer 310 of the tenth transistor T10 extends at least along the first direction X. The orthogonal projection of the active layer 33 of the third transistor T3 on the substrate can be substantially I-shaped. The orthogonal projection of the active layer 32 of the second transistor T2 on the substrate can be substantially L-shaped. The orthogonal projection of the active layer 310 of the tenth transistor T10 on the substrate can be substantially a strip extending along the first direction X.

[0123] In some examples, the active layer 310 of the tenth transistor T10 is connected with the active layer 37 of the seventh transistor T7 and the active layer 36 of the sixth transistor T6 simultaneously. The first region of the active layer 310 of the tenth transistor T10 can be the first region of the active layer 37 of the seventh transistor T7 and the first region of the active layer 36 of the sixth transistor T6 simultaneously. The common connection end of the active layer 310 of the tenth transistor T10, the active layer 37 of the seventh transistor T7 and the active layer 36 of the sixth transistor T6 can be configured as the first voltage connection end and connected with the first voltage line.

[0124] In some examples, the active layer 37 of the seventh transistor T7 can extend at least along the second direction Y. The orthogonal projection of the active layer 37 of the seventh transistor T7 on the substrate can be substantially L-shaped.

[0125] In some examples, the active layer 36 of the sixth transistor T6 is connected with the active layer 39 of the ninth transistor T9, for example, can be an integrated structure. The second region of the active layer 36 of the sixth transistor T6 can be the first region of the active layer 39 of the ninth transistor T9 simultaneously. The active layer 36 of the sixth transistor T6 and the active layer 39 of the ninth transistor T9 can both extend along the second direction Y. The orthogonal projection of the integrated structure of the active layer 36 of the sixth transistor T6 and the active layer 39 of the ninth transistor T9 on the substrate can be substantially I-shaped.

[0126] In some examples, the active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 39 of the ninth transistor T9, and the active layer 310 of the tenth transistor T10 can have a common connection end and three branches extending from the common connection end, i.e., a first branch, a second branch, and a third branch. The common connection end of the active layer 310 of the tenth transistor T10, the active layer 37 of the seventh transistor T7, and the active layer 36 of the sixth transistor T6 can be configured as a first voltage connection end and connected with a first voltage line. The first branch can extend from the common connection end in a second direction Y in a stepped manner, the second branch can extend from the common connection end in a first direction X and then in the second direction Y, and the third branch can extend in the second direction Y. The first branch is an integrated structure of the active layer 310 of the tenth transistor T10, the active layer 32 of the second transistor T2, and the active layer 33 of the third transistor T3; the second branch is the active layer 37 of the seventh transistor T7; and the third branch is an integrated structure of the active layer 36 of the sixth transistor T6 and the active layer 39 of the ninth transistor T9.

[0127] In the present example, the active layer 32 of the second transistor T2, the active layer 33 of the third transistor T3, the active layer 36 of the sixth transistor T6, the active layer 37 of the seventh transistor T7, the active layer 39 of the ninth transistor T9, and the active layer 310 of the tenth transistor T10 are integrated structures. By reasonably arranging the positions of the active layers of the plurality of transistors, the arrangement space can be effectively utilized, and the space waste of the display substrate can be reduced.

[0128] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate of the foregoing structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.

[0129] FIG. 8 is a schematic view of the display substrate after the first conductive layer is formed in FIG. 4. FIG. 9 is a schematic view of the first conductive layer in FIG. 8. In some examples, as shown in FIGS. 8 and 9, the first conductive layer of the display substrate can include the gates of the plurality of transistors of the shift register circuit (e.g., including the gate 21 of the first transistor T1, the gate 22 of the second transistor T2, the gate 23 of the third transistor T3, the gate 24 of the fourth transistor T4, the gate 25 of the fifth transistor T5, the gate 26 of the sixth transistor T6, the gate 27 of the seventh transistor T7, the gate 28 of the eighth transistor T8, the gate 29 of the ninth transistor T9, and the gate 210 of the tenth transistor T10) and the first plates of the plurality of capacitors of the shift register circuit (e.g., including the first plate 211 of the first capacitor C1, the first plate 212 of the second capacitor C2, and the first plate 213 of the third capacitor C3).

[0130] In some examples, the gate 21 of the first transistor T1 can extend along the first direction X. The orthogonal projection of the gate 21 of the first transistor T1 on the substrate can be a strip extending along the first direction X.

[0131] In some examples, the gate 22 of the second transistor T2 can extend along the first direction X. The gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 can be an integrated structure. The gate 27 of the seventh transistor T7 can extend at least along the first direction X. The orthogonal projection of the integrated structure of the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 on the substrate can be L-shaped. In the present example, the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 are integrated, and the extension direction of the integrated structure intersects at least the extension direction of the active layer 32 of the second transistor T2 and the active layer 37 of the seventh transistor T7, which can reduce the wiring space. Moreover, the integrated structure of the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 can be connected with the first connection electrode 401 located in the third conductive layer, thereby optimizing the spatial layout and saving the occupied space.

[0132] In some examples, the gate 23 of the third transistor T3 can extend along the first direction X, for example, be a strip extending along the first direction X. The gate 23 of the third transistor T3 and the first plate 211 of the first capacitor C1 can be an integrated structure. The first plate 211 of the first capacitor C1 can be located on the side of the active layer 33 of the third transistor T3 away from the active layer 37 of the seventh transistor T7 in the first direction X. The first plate 211 of the first capacitor C1 can be located between the active layer 31 of the first transistor T1 and the active layer 38 of the eighth transistor T8 in the second direction Y, and the orthogonal projection of the first plate 211 on the substrate does not overlap with the orthogonal projection of the active layer 31 of the first transistor T1 and the active layer 38 of the eighth transistor T8 on the substrate. The orthogonal projection of the first plate 211 of the first capacitor C1 on the substrate can be approximately L-shaped. Among them, the maximum length W1 of the first plate 211 of the first capacitor C1 along the first direction X can be greater than the minimum length L1 of the first plate 211 along the second direction Y. The first plate 211 of the first capacitor C1 can have a minimum length L1a and a maximum length L1b along the second direction Y. In the present example, the first capacitor C1 is arranged between the active layer 31 of the first transistor T1 and the active layer 38 of the eighth transistor T8, which can ensure that the first plate 211 of the first capacitor C1 has a larger area to achieve the requirement of pulling down the voltage of the third node, and the reasonable arrangement of the longitudinal wire can reduce the horizontal wiring distance.

[0133] In some examples, the gate 24 of the fourth transistor T4 can extend along the first direction X. The gate 24 of the fourth transistor T4, the gate 26 of the sixth transistor T6, and the first plate 212 of the second capacitor C2 can be an integral structure. The gate 26 of the sixth transistor T6 can extend along the first direction X. The first plate 212 of the second capacitor C2 is located on a side of the active layer 34 of the fourth transistor T4 away from the active layer 36 of the sixth transistor T6 in the first direction X. The first plate 212 of the second capacitor C2 can have a substantially rectangular footprint on the substrate.

[0134] In some examples, the gate 25 of the fifth transistor T5 can include a first gate strip 25-1, a second gate strip 25-2, and a third gate strip 25-3. The first gate strip 25-1, the second gate strip 25-2, and the third gate strip 25-3 can each extend along the first direction X and be arranged in sequence along the second direction Y. The first gate strip 25-1, the second gate strip 25-2, and the third gate strip 25-3 can be arranged in sequence along a direction away from the gate 24 of the fourth transistor T4 in the second direction Y. The third gate strip 25-3 can extend along the first direction X to a position adjacent to the active layer 28 of the eighth transistor T8, so as to be subsequently connected to the active layer 38 of the eighth transistor T8.

[0135] In some examples, the gate 25 of the fifth transistor T5 and the first plate 213 of the third capacitor C3 can be an integral structure. The first plate 213 of the third capacitor C3 can be located on a side of the active layer 35 of the fifth transistor T5 away from the active layer 39 of the ninth transistor T9 in the first direction X. The first plate 213 of the third capacitor C3 can have a substantially rectangular footprint on the substrate. The length L3 of the first plate 213 of the third capacitor C3 along the second direction Y can be greater than the length L2 of the first plate 212 of the second capacitor C2 along the second direction Y. The length W3 of the first plate 213 of the third capacitor C3 along the first direction X can be substantially the same as the length W2 of the first plate 212 of the second capacitor C2 along the first direction X. The length L2 of the first plate 212 of the second capacitor C2 along the second direction Y can be greater than the minimum length L1a of the first plate 211 of the first capacitor C1 along the second direction Y, and can be greater than or equal to the maximum length L1b of the first plate 211 of the first capacitor C1 along the second direction Y. The maximum length W1 of the first plate 211 of the first capacitor C1 along the first direction X can be greater than the length W2 of the second capacitor C2 along the first direction X.

[0136] In some examples, the gate 28 of the eighth transistor T8 can extend along the first direction X. The gate 29 of the ninth transistor T9 can extend along the first direction X. The gate 29 of the ninth transistor T9 and the gate 26 of the sixth transistor T6 can be arranged in alignment along the second direction Y. In the present example, the gate 26 of the sixth transistor T6 and the gate 29 of the ninth transistor T9 are parallel and arranged in sequence along the second direction Y, which can facilitate the space optimization of the lateral wiring of the shift register circuit.

[0137] In some examples, the gate 310 of the tenth transistor T10 can extend along the second direction Y, thereby facilitating the access of the gate of the tenth transistor T10 to the corresponding clock signal line through the laterally extending connection electrode.

[0138] In the present example, the gate of the tenth transistor T10 of the shift register circuit extends along the second direction Y, and the gates of the remaining transistors extend along the first direction X, which can reduce the wiring space and facilitate the optimization of the spatial layout of the overall circuit.

[0139] (4) Forming a second conductive layer. In some examples, on the substrate on which the foregoing structure is formed, a second insulating thin film and a second conductive thin film are sequentially deposited, the second conductive thin film is patterned through a patterning process, and a second insulating layer and a second conductive layer disposed on the second insulating layer are formed.

[0140] FIG. 10 is a schematic diagram of the display substrate after the second conductive layer is formed in FIG. 4. FIG. 11 is a schematic diagram of the second conductive layer in FIG. 10. In some examples, as shown in FIG. 10 and FIG. 11, the second conductive layer of the display substrate can include: the second plate of the plurality of capacitors of the shift register circuit (for example, including the second plate 221 of the first capacitor C1, the second plate 222 of the second capacitor C2, and the second plate 223 of the third capacitor C3), the capacitor connection electrode 511, and the output electrode (for example, the output electrode 501a).

[0141] In some examples, the second plate 221 of the first capacitor C1 and the capacitor connection electrode 511 can be an integral structure. For example, the part of the integral structure that overlaps with the first plate 211 of the first capacitor C1 in the orthographic projection of the substrate can serve as the second plate 221 of the first capacitor C1. The capacitor connection electrode 511 can be located on the side of the second plate 221 of the first capacitor C1 close to the gate 28 of the eighth transistor T8, and can not overlap with the first plate 211 of the first capacitor C1 in the orthographic projection of the substrate.

[0142] In some examples, the second plate 221 of the first capacitor C1 can be located within the projection of the first plate 211 of the first capacitor C1 on the substrate. The second plate 222 of the second capacitor C2 can be located within the projection of the first plate 212 of the second capacitor C2 on the substrate. The second plate 223 of the third capacitor C3 can be located within the projection of the first plate 213 of the third capacitor C3 on the substrate. For example, the second plate 222 of the second capacitor C2 and the second plate 223 of the third capacitor C3 can be substantially rectangular in the projection on the substrate.

[0143] In some examples, the second plate 223 of the third capacitor C3 can be an integral structure with the output electrode 501a. For example, the portion of the integral structure that overlaps the first plate 213 of the third capacitor C3 in the projection on the substrate can serve as the second plate 223 of the third capacitor C3. The output electrode 501a can be located on the side of the second plate 223 of the third capacitor C3 away from the second plate 222 of the second capacitor C2, and can not overlap the first plate 213 of the third capacitor C3 in the projection on the substrate. The output electrode 501a can extend at least along the first direction X, and be located on the side of the active layer 35 of the fifth transistor T5 away from the active layer 34 of the fourth transistor T4 in the second direction Y.

[0144] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate formed in the foregoing step, and the third insulating film is patterned by a patterning process to form a third insulating layer.

[0145] FIG. 12 is a schematic view of the display substrate after the third insulating layer is formed in FIG. 4. In some examples, as shown in FIG. 12, a plurality of vias are formed in the third insulating layer. For example, the plurality of vias can include a first via V1 to a twenty-seventh via V27. The third insulating layer, the second insulating layer, and the first insulating layer in the first via V1 to the fourteenth via V14 are removed to expose part of the surface of the semiconductor layer; the third insulating layer and the second insulating layer in the fifteenth via V15 to the twenty-third via V23 are removed to expose part of the surface of the first conductive layer; and the third insulating layer in the twenty-fourth via V24 to the twenty-seventh via V27 is removed to expose part of the surface of the second conductive layer.

[0146] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate formed in the foregoing step, and the third conductive film is patterned by a patterning process to form a third conductive layer disposed on the third insulating layer.

[0147] FIG. 13 is a schematic view of the display substrate after forming the third conductive layer in FIG. 4. FIG. 14 is a schematic view of the third conductive layer in FIG. 13. In some examples, as shown in FIGS. 13 and 14, the third conductive layer of the display substrate can include a plurality of connection electrodes (e.g., including the first connection electrode 401, the second connection electrode 402, the third connection electrode 403, the fourth connection electrode 404, the fifth connection electrode 405, the sixth connection electrode 406, the seventh connection electrode 407, the eighth connection electrode 408, the ninth connection electrode 409, and the tenth connection electrode 410), an initial connection line 411, a power supply connection line 412, an input electrode (e.g., the input electrode 502a), a first clock connection electrode (e.g., including the first clock connection electrode 421a), a second clock connection electrode (e.g., the second clock connection electrode 422a), and a third clock connection electrode (e.g., the third clock connection electrode 423a).

[0148] In some examples, as shown in FIG. 14, the first connection electrode 401 can have a first body 4010, a first connection end 4011, a second connection end 4012, and a third connection end 4013. The first body 4010 can extend along the second direction Y and is adjacent to the first transistor T1 and the first capacitor C1 in the first direction X. The first connection end 4011, the second connection end 4012, and the third connection end 4013 each extend along the first direction X and are sequentially arranged along the second direction Y. The first connection end 4011, the second connection end 4012, and the third connection end 4013 are located on the same side of the first body 4010 in the first direction X. The first body 4010, the first connection end 4011, the second connection end 4012, and the third connection end 4013 are an integral structure. For example, the first connection electrode 401 can have a substantially “mountain” shape in the orthographic projection of the substrate.

[0149] In some examples, the first connection end 4011 can be connected to the second region of the active layer 31 of the first transistor T1 through the first via V1, the second connection end 4012 can be connected to the gate 22 of the second transistor T2 through the sixteenth via V16, and the third connection end 4013 can be connected to the first region of the active layer 38 of the eighth transistor T8 through the third via V3.

[0150] In some examples, the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 are in an integrated structure, and the integrated structure of the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 can be connected with the second connection electrode 402 through the nineteenth via V19, and the second connection electrode 402 can be connected with the second region of the active layer 39 of the ninth transistor T9 through the ninth via V9. The first connection electrode 401, the integrated structure of the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7, and the second connection electrode 402 can be connected as a first node, realizing the electrical connection of the first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9.

[0151] In some examples, the input electrode 502a can be located on the same side of the first transistor T1 and the tenth transistor T10 in the second direction Y. The orthogonal projection of the input electrode 502a on the substrate can be a broken line shape extending along the first direction X. One end of the input electrode 502a can be connected with the first region of the active layer 31 of the first transistor T1 of the current stage shift register circuit through the second via V2, and the other end can be connected with the stage connection signal line located in the fourth conductive layer. In the present example, the input electrode 502a can serve as the input end of the current stage shift register circuit.

[0152] In some examples, the third connection electrode 403 can be located between the first connection electrode 401 and the second connection electrode 402. The orthogonal projection of the third connection electrode 403 on the substrate can be approximately L-shaped. The orthogonal projection of the third connection electrode 403 on the substrate can overlap with the integrated structure of the gate 22 of the second transistor T2 and the gate 27 of the seventh transistor T7 on the substrate. One end of the third connection electrode 403 can be connected with the second region of the active layer 32 of the second transistor T2 through the fifth via V5, and the other end can be connected with the gate 26 of the sixth transistor T6 through the twenty-first via V21. Since the second region of the active layer 32 of the second transistor T2 also serves as the second region of the active layer 33 of the third transistor T3, the gate 26 of the sixth transistor T6, the gate 24 of the fourth transistor T4 and the first plate 212 of the second capacitor C2 are in an integrated structure, therefore, the third connection electrode 403 can serve as a second node, realizing the electrical connection of the second transistor T2, the third transistor T3, the sixth transistor T6, the fourth transistor T4 and the second capacitor C2.

[0153] In some examples, the fourth connection electrode 404 can be located at one side of the third connection electrode 403 along the second direction Y. The orthogonal projection of the fourth connection electrode 404 on the substrate can be a strip extending along the first direction X. One end of the fourth connection electrode 404 can be connected with the gate 23 of the third transistor T3 through the seventeenth via V17, and the other end can be connected with the second region of the active layer 37 of the seventh transistor T7 through the seventh via V7. Since the gate 23 of the third transistor T3 and the first plate 211 of the first capacitor C1 are in an integrated structure, the fourth connection electrode 404 can serve as a third node to realize the electrical connection of the third transistor T3, the first capacitor C1 and the seventh transistor T7.

[0154] In some examples, the fifth connection electrode 405 can be located at one side of the first connection electrode 401 close to the eighth transistor T8 along the second direction Y. The orthogonal projection of the fifth connection electrode 405 on the substrate can be a strip extending along the first direction X. One end of the fifth connection electrode 405 can be connected with the second region of the active layer 38 of the eighth transistor T8 through the fourth via V4, and the other end can be connected with the third gate strip 25-3 of the gate 25 of the fifth transistor T5 through the twenty-third via V23. Since the gate 25 of the fifth transistor T5 and the first plate 213 of the third capacitor C3 are in an integrated structure, the fifth connection electrode 405 can serve as a fourth node to realize the electrical connection of the fifth transistor T5, the eighth transistor T8 and the third capacitor C3.

[0155] In some examples, the sixth connection electrode 406 can be located at one side of the fifth connection electrode 405 close to the eighth transistor T8 along the first direction X. The orthogonal projection of the sixth connection electrode 406 on the substrate can be a strip extending along the second direction Y. The sixth connection electrode 406 can be connected with the gate 28 of the eighth transistor T8 through the twenty-second via V22. The sixth connection electrode 406 can be connected with the second voltage line VGL formed subsequently.

[0156] In some examples, the seventh connection electrode 407 can be located at one side of the third connection electrode 403 along the first direction X. The orthogonal projection of the seventh connection electrode 407 on the substrate can be a polyline extending along the first direction X. The seventh connection electrode 407 can be connected with the integrated structure of the active layer 310 of the tenth transistor T10, the active layer 36 of the sixth transistor T6 and the active layer 37 of the seventh transistor T7 through the eighth via V8, and can be connected with the second plate 222 of the second capacitor C2 through two twenty-fifth vias V25 arranged side by side, and can be connected with the first region of the active layer 34 of the fourth transistor T4 through a plurality of (for example, seven) tenth vias V10 arranged side by side. The seventh connection electrode 407 can be connected with the first voltage line VGH formed subsequently.

[0157] In the present example, the "side-by-side arrangement" can mean sequentially arranged along the first direction X, and the "vertical arrangement" can mean sequentially arranged along the second direction Y.

[0158] In some examples, the eighth connection electrode 408 can be located on the side of the seventh connection electrode 407 close to the fifth transistor T5 in the second direction Y. The orthogonal projection of the eighth connection electrode 408 on the substrate can be substantially in the shape of a U. The opening of the U-shaped eighth connection electrode 408 can face the ninth transistor T9. The eighth connection electrode 408 can be connected to the second region of the active layer 34 of the fourth transistor T4 through a plurality of (for example, seven) eleventh vias V11 arranged side by side, to the second region of the active layer 35 of the fifth transistor T5 through a plurality of (for example, seven) thirteenth vias V13 arranged side by side, and to the second plate 223 of the third capacitor C3 through two twenty-sixth vias V26 arranged vertically. The eighth connection electrode 408 can be configured as an output terminal to provide a driving signal (for example, a scan signal) to the pixel circuit of the display area.

[0159] In some examples, the ninth connection electrode 409 can be located on the side of the second connection electrode 402 close to the third capacitor C3 in the first direction X. The orthogonal projection of the ninth connection electrode 409 on the substrate can be substantially in the shape of a U. The opening of the U-shaped ninth connection electrode 409 can face the eighth connection electrode 408. The ninth connection electrode 409 can be connected to the first region of the active layer 35 of the fifth transistor T5 through a plurality of (for example, seven) twelfth vias V12 arranged side by side and a plurality of (for example, seven) fourteenth vias V14 arranged side by side, and to the gate 29 of the ninth transistor T9 through a twentieth via V20. In the present example, the eighth connection electrode 408 and the ninth connection electrode 409 can be interleaved with each other, so that the connection electrodes are placed more reasonably, which is conducive to improving the space utilization.

[0160] In some examples, the tenth connection electrode 410 can be located on the side of the ninth connection electrode 409 away from the seventh connection electrode 407 in the second direction Y. The orthogonal projection of the tenth connection electrode 410 on the substrate can be substantially rectangular. The tenth connection electrode 410 can be connected to the output electrode 501a of the shift register circuit of the present stage through two twenty-seventh vias V27 arranged side by side.

[0161] In some examples, the initial connection line 411 can be located on the side of the eighth connection electrode 408 away from the ninth connection electrode 409 in the first direction X. The initial connection electrode 411 can be configured to be connected to the initial signal line INIT formed in the fourth conductive layer subsequently. The initial signal line INIT can be configured to provide an initial signal to the pixel circuit of the display area through the initial connection line 411.

[0162] In some examples, the first clock connection electrode 421a can be located between the input electrode 502a and the second connection end 4012 of the first connection electrode 401 in the second direction Y. The first clock connection electrode 421a can be a strip extending in the second direction Y in the orthographic projection of the substrate. The first clock connection electrode 421a can be connected to the gate 21 of the first transistor T1 through the fifteenth via V15. The first clock connection electrode 421a can be configured to be connected to a clock signal line (e.g., the first clock signal line CL1) formed subsequently.

[0163] In some examples, the second clock connection electrode 422a can be located on the side of the first clock connection electrode 421a away from the first connection electrode 401 in the first direction X. The second clock connection electrode 422a can be a strip extending in the first direction X in the orthographic projection of the substrate. The second clock connection electrode 422a can be connected to the gate 210 of the tenth transistor T10 through the eighteenth via V18. The second clock connection electrode 422a can be configured to be connected to a clock signal line (e.g., the second clock signal line CL2) formed subsequently.

[0164] In some examples, the third clock connection electrode 423a can be located on the side of the fourth connection electrode 404 away from the third connection electrode 403 in the second direction Y. The third clock connection electrode 423a can be a strip extending in the first direction X in the orthographic projection of the substrate. The third clock connection electrode 423a can be connected to the second plate 221 of the first capacitor C1 through the twenty-fourth via V24, and can be connected to the first region of the active layer 33 of the third transistor T3 through the sixth via V6. The third clock connection electrode 423a and the ninth connection electrode 409 can be an integral structure. The third clock connection electrode 423a can be configured to be connected to a clock signal line (e.g., the third clock signal line CL3) formed subsequently.

[0165] In some examples, the power connection line 412 of the third conductive layer can be located on the side of the third connection electrode 403 away from the fourth connection electrode 404 in the second direction Y. The power connection line 412 can be a polyline extending in the first direction X in the orthographic projection of the substrate. The power connection line 412 can be configured to be connected to the third voltage lines VSSa and VSSb formed subsequently and located in the fourth conductive layer. The third voltage lines VSSa and VSSb can be configured to provide a third voltage signal. The third voltage lines VSSa and VSSb can be connected through the power connection line 412 and configured to provide the third voltage signal to the cathodes of the light emitting elements in the display area.

[0166] (7), forming a fourth insulating layer. In some examples, on the substrate formed with the aforementioned pattern, a fourth insulating film is coated, and the fourth insulating film is patterned by a patterning process to form the fourth insulating layer.

[0167] FIG. 15 is a schematic diagram of the display substrate after the fourth insulating layer is formed in FIG. 4. In some examples, as shown in FIG. 15, a plurality of vias are formed in the fourth insulating layer. For example, the plurality of vias can include a thirty-first via (e.g., a thirty-first via V31a), a thirty-second via (e.g., a thirty-second via V32a), a thirty-third via (e.g., a thirty-third via V33a), a thirty-fourth via V34 to a fortieth via V40. The fourth insulating layer in the thirty-first via V31a to the fortieth via V40 can be removed to expose part of the surface of the third conductive layer.

[0168] (8), forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate formed with the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form the fourth conductive layer on the fourth insulating layer.

[0169] FIG. 16 is a schematic diagram of the fourth conductive layer in FIG. 4. In some examples, as shown in FIG. 4 and FIG. 16, the fourth conductive layer of the display substrate can include at least a first voltage line VGH, a second voltage line VGL, a third voltage line VSSa and VSSb, four clock signal lines (e.g., a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, and a fourth clock signal line CL4), a start signal line STV, an initial signal line INIT, and a plurality of stage connection signal lines (such as including stage connection signal lines 503a, 503b, and 503c).

[0170] In some examples, the first voltage line VGH, the second voltage line VGL, the third voltage line VSSa and VSSb, the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, the fourth clock signal line CL4, the start signal line STV, and the initial signal line INIT extend along the second direction Y. The four clock signal lines are located between the third voltage line VSSa and the stage connection signal line. The first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 are arranged in sequence along the first direction X. The second voltage line VGL is located on the side of the third voltage line VSSa away from the four clock signal lines along the first direction X. The third voltage line VSSb, the start signal line STV, the first voltage line VGH, and the initial signal line INIT are arranged in sequence along the first direction away from the stage connection signal line.

[0171] In some examples, the cascade signal line can be in a zigzag shape extending along the second direction Y. For example, one end of the cascade signal line 503a can be connected with the input electrode 502a of the current stage shift register circuit (e.g., the 4n-3th shift register circuit) through the thirty-fourth via hole V34, and the other end can be connected with the output electrode of the 4n-5th shift register circuit or the start signal line. One end of the cascade signal line 503c can be connected with the tenth connection electrode 410 through the thirty-ninth via hole V39, so as to be connected with the output electrode 501a of the current stage shift register circuit (e.g., the 4n-3th shift register circuit) through the tenth connection electrode 410, and the other end can be connected with the input electrode of the 4n-1th shift register circuit. One end of the cascade signal line 503b can be connected with the output electrode of the 4n-4th shift register circuit, and the other end can be connected with the input electrode of the 4n-2th shift register circuit.

[0172] In some examples, the third voltage line VSSa can be connected with the power supply connection line 412 through the thirty-fifth via hole V35, and the third voltage line VSSb can be connected with the power supply connection line 412 through the thirty-sixth via hole V36. The power supply connection line 412 can extend to the display area and be configured to provide the third voltage signal to the cathode of the light emitting element of the sub-pixel in the display area. The initial signal line INIT can be connected with the initial connection line 411 through the fortieth via hole V40. The present example transmits the third voltage signal through two third voltage lines VSSa and VSSb, which is conducive to reducing the transmission resistance, and the third voltage lines VSSa and VSSb have an overlap with the orthographic projection of the gate driving circuit on the substrate, which can be conducive to narrow frame design.

[0173] In some examples, the second voltage line VGL can be connected with the sixth connection electrode 406 through the thirty-eighth via hole V38, and can provide the second voltage signal to the gate 28 of the eighth transistor T8 through the sixth connection electrode 406. The first voltage line VGH can be connected with the seventh connection electrode 407 through the thirty-seventh via hole V37, and can provide the first voltage signal to the seventh transistor T7, the sixth transistor T6, the tenth transistor T10, the fourth transistor T4 and the second capacitor C2 through the seventh connection electrode 407.

[0174] In some examples, the first clock signal line CL1 can be connected with the first clock connection electrode 421a through the thirty-first via V31a, and can provide the first clock signal to the first transistor T1 of the current stage shift register circuit through the first clock connection electrode 421a. The second clock signal line CL2 can be connected with the second clock connection electrode 422a through the thirty-second via V32a, and can provide the second clock signal to the tenth transistor T10 of the current stage shift register circuit through the second clock connection electrode 422a. The third clock signal line CL3 can be connected with the third clock connection electrode 423a through the thirty-third via V33a, and can provide the third clock signal to the third transistor T3, the fifth transistor T5, the ninth transistor T9 and the first capacitor C1 of the current stage shift register circuit through the third clock connection electrode 423a.

[0175] In the present example, the first voltage line, the second voltage line and the four clock signal lines are arranged on the fourth conductive layer, i.e., on the side of the gate driving circuit away from the substrate. By reasonably arranging the longitudinal wires, the arrangement space can be optimized, the arrangement difficulty can be reduced, and the capacitance caused by node overlap and the instability of the output signal can be improved.

[0176] In some examples, after the fourth conductive layer is formed, the fifth insulating layer, the anode layer, the pixel definition layer, the organic light-emitting layer, the cathode layer and the encapsulation layer pattern can be sequentially formed in the display area. In some examples, on the substrate on which the display area with the aforementioned pattern is formed, an anode thin film is deposited, and the anode thin film is patterned by a patterning process to form an anode pattern on the fifth insulating layer. Then, a pixel definition thin film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by a mask, exposure and development process. The pixel definition layer is formed in each sub-pixel of the display area, and the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode. Subsequently, the organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected with the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned by a patterning process to form a cathode pattern, and the cathode is connected with the organic light-emitting layer and the second power supply line, respectively. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer can include a laminated structure of inorganic material / organic material / inorganic material. In some possible implementations, the cathode can be connected with the power supply connection line in various ways, such as laser drilling.

[0177] In some examples, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer and the third insulating layer can adopt any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The fourth insulating layer and the fifth insulating layer can adopt an organic material such as polyimide, acrylic or polyethylene terephthalate. However, the present embodiment is not limited thereto.

[0178] The structure shown in the present example and the preparation process thereof are merely exemplary descriptions. In some examples, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs. The preparation process of the exemplary embodiment can be realized by using the currently mature preparation equipment, can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost and high yield.

[0179] The embodiment can save the space occupied by the shift register circuit by optimizing the layout of the shift register circuit, which is conducive to realizing the narrow-frame display substrate, and can stabilize the signal output.

[0180] FIG. 17 is a partial equivalent circuit diagram of a gate drive circuit according to at least one embodiment of the present disclosure. FIG. 17 shows equivalent circuit diagrams of four shift register circuits (for example, a 4n-3 stage, a 4n-2 stage, a 4n-1 stage and a 4n stage shift register circuit, n is an integer greater than 0).

[0181] In some examples, as shown in FIG. 17, the 4n-3 stage shift register circuit is connected with the first clock signal line CL1, the second clock signal line CL2 and the third clock signal line CL3. Among them, the gate of the first transistor T1 of the 4n-3 stage shift register circuit is connected with the first clock signal line CL1, the gate of the tenth transistor T10 is connected with the second clock signal line CL2, the second plate of the third capacitor C3, the first pole of the third transistor T3, the first pole of the fifth transistor T5 and the gate of the ninth transistor T9 are connected with the third clock signal line CL3.

[0182] In some examples, the 4n-2th-stage shift register circuit is connected with the second clock signal line CL2, the third clock signal line CL3 and the fourth clock signal line CL4. The gate of the first transistor T1 of the 4n-2th-stage shift register circuit is connected with the second clock signal line CL2, the gate of the tenth transistor T10 is connected with the third clock signal line CL3, and the second plate of the third capacitor C3, the first pole of the third transistor T3, the first pole of the fifth transistor T5 and the gate of the ninth transistor T9 are connected with the fourth clock signal line CL4.

[0183] In some examples, the 4n-1th-stage shift register circuit is connected with the third clock signal line CL3, the fourth clock signal line CL4 and the first clock signal line CL1. The gate of the first transistor T1 of the 4n-1th-stage shift register circuit is connected with the third clock signal line CL3, the gate of the tenth transistor T10 is connected with the fourth clock signal line CL4, and the second plate of the third capacitor C3, the first pole of the third transistor T3, the first pole of the fifth transistor T5 and the gate of the ninth transistor T9 are connected with the first clock signal line CL1.

[0184] In some examples, the 4nth-stage shift register circuit is connected with the fourth clock signal line CL4, the first clock signal line CL1 and the second clock signal line CL2. The gate of the first transistor T1 of the 4nth-stage shift register circuit is connected with the fourth clock signal line CL4, the gate of the tenth transistor T10 is connected with the first clock signal line CL1, and the second plate of the third capacitor C3, the first pole of the third transistor T3, the first pole of the fifth transistor T5 and the gate of the ninth transistor T9 are connected with the second clock signal line CL2.

[0185] In some examples, the output end OUT(4n-3) of the 4n-3th-stage shift register circuit is connected with the input end IN(4n-1) of the 4n-1th-stage shift register circuit, and the output end OUT(4n-2) of the 4n-2th-stage shift register circuit is connected with the input end IN(4n) of the 4nth-stage shift register circuit. The output end OUT(4n-1) of the 4n-1th-stage shift register circuit can be connected with the input end of the 4n+1th-stage shift register circuit, and the output end OUT(4n) of the 4nth-stage shift register circuit can be connected with the input end of the 4n+2th-stage shift register circuit.

[0186] The description of each stage of the shift register circuit can refer to the description of the embodiment shown in FIG. 2, which will not be repeated here.

[0187] FIG. 18 is another partial top view of a display substrate according to at least one embodiment of the present disclosure. In FIG. 18, top views of four shift register circuits (4n-3, 4n-2, 4n-1, and 4n shift register circuits) of the display substrate are shown. The equivalent circuit diagram of the shift register circuits of the present example can be as shown in FIG. 17. FIG. 19 is a schematic view of the display substrate after formation of a third conductive layer in FIG. 18. FIG. 20 is a schematic view of the display substrate after formation of a fourth insulating layer in FIG. 18.

[0188] In some examples, as shown in FIGS. 18-20, the input terminal of the 4n-3 shift register circuit GOA(4n-3) is connected to the input electrode 502a, and the output terminal is connected to the output electrode 501a; the input terminal of the 4n-2 shift register circuit GOA(4n-2) is connected to the input electrode 502b, and the output terminal is connected to the output electrode 501b; the input terminal of the 4n-1 shift register circuit GOA(4n-1) is connected to the input electrode 502c, and the output terminal is connected to the output electrode 501c; and the input terminal of the 4n shift register circuit GOA(4n) is connected to the input electrode 502d, and the output terminal is connected to the output electrode 501d.

[0189] In some examples, the output electrodes 501a, 501b, 501c, and 501d are located in the second conductive layer and extend along the first direction X. The input electrodes 502a, 502b, 502c, and 502d are located in the third conductive layer and extend along the first direction X. The input electrodes 502a, 502b, 502c, and 502d can have substantially the same shape in orthographic projection on the substrate; and the output electrodes 501a, 501b, 501c, and 501d can have substantially the same shape in orthographic projection on the substrate.

[0190] In some examples, the cascade signal line 503a is connected to the input electrode 502a. The cascade signal line 503b is connected to the input electrode 502b. The cascade signal line 503c is connected to the output electrode 501a and the input electrode 502c, electrically connecting the output terminal of the 4n-3 shift register circuit GOA(4n-3) and the input terminal of the 4n-1 shift register circuit GOA(4n-1). The cascade signal line 503d is connected to the output electrode 501b and the input electrode 502d, electrically connecting the output terminal of the 4n-2 shift register circuit GOA(4n-2) and the input terminal of the 4n shift register circuit GOA(4n). The cascade signal line 503e is connected to the output electrode 501c. The cascade signal line 503f is connected to the output electrode 501d. The cascade signal lines 503a, 503b, 503c, 503d, 503e, and 503f can have substantially the same shape in orthographic projection on the substrate.

[0191] The example adopts the input electrode and the output electrode extending along the first direction X to be connected with the cascade signal line extending along the second direction Y, realizes the electrical connection between the cascade shift register circuits, and can save the space occupied by the longitudinal wire.

[0192] In some examples, the first clock connection electrode 421b of the 4n-2th shift register circuit can have a generally dumbbell shape extending along the first direction X in the orthographic projection on the substrate, the second clock connection electrode 422b can have a generally rectangular shape in the orthographic projection on the substrate, and the third clock connection electrode 423b can have a generally strip shape extending along the first direction X in the orthographic projection on the substrate. The first clock connection electrode 421c of the 4n-1th shift register circuit can have a strip shape extending along the first direction X in the orthographic projection on the substrate, the second clock connection electrode 422c can have a generally rectangular shape in the orthographic projection on the substrate, and the third clock connection electrode 423c can have a generally strip shape extending along the first direction X in the orthographic projection on the substrate. The first clock connection electrode 421d of the 4nth shift register circuit can have a strip shape extending along the first direction X in the orthographic projection on the substrate, the second clock connection electrode 422d can have a generally strip shape extending along the first direction X in the orthographic projection on the substrate, and the third clock connection electrode 423c can have a generally strip shape extending along the first direction X in the orthographic projection on the substrate.

[0193] In some examples, the third clock end of the current shift register circuit and the second clock end of the next shift register circuit are connected with the same clock signal line through different vias. For example, the third clock connection electrode 423a of the 4n-3th shift register circuit can be connected with the third clock signal line CL3 through the thirty-third via V33a, and the second clock connection electrode 422b of the 4n-2th shift register circuit can be connected with the third clock signal line CL3 through the thirty-second via V32b. The third clock connection electrode 423b of the 4n-2th shift register circuit can be connected with the fourth clock signal line CL4 through the thirty-third via V33b, and the second clock connection electrode 422c of the 4n-1th shift register circuit can be connected with the fourth clock signal line CL4 through the thirty-second via V32c. The third clock connection electrode 423c of the 4n-1th shift register circuit can be connected with the first clock signal line CL1 through the thirty-third via V33c, and the second clock connection electrode 422d of the 4nth shift register circuit can be connected with the first clock signal line CL1 through the thirty-second via V32d.

[0194] In the example, the input electrodes (e.g., the input electrodes 502a, 502b, 502c, and 502d) extend along the first direction X and are located between the adjacent two-stage shift register circuits along the second direction Y, and the two-stage shift register circuits are connected to the same clock signal line through different via holes, so that the arrangement space can be simplified. Moreover, when the gate of the tenth transistor T10 is connected to the clock signal through the second clock connection electrode, the second clock connection electrodes of the two groups of shift register circuits connected to the same clock signal at the straight side and the corner positions have the same layout, so that the loading of the gate of the tenth transistor T10 is consistent when the gate is connected to the clock signal.

[0195] In some examples, the gate of the tenth transistor T10 of the shift register circuit can be connected to the second clock connection electrode through a connection via hole (e.g., the eighteenth via hole shown in FIG. 10) formed in the third insulating layer. For example, the gate 210 of the tenth transistor T10 of the 4n-3 stage shift register circuit can be connected to the second clock connection electrode 422a, the gate 210 of the tenth transistor T10 of the 4n-2 stage shift register circuit can be connected to the second clock connection electrode 422b, the gate 210 of the tenth transistor T10 of the 4n-1 stage shift register circuit can be connected to the second clock connection electrode 422c, and the gate 210 of the tenth transistor T10 of the 4n-1 stage shift register circuit can be connected to the second clock connection electrode 422d.

[0196] In some examples, the connection via hole between the gate of the tenth transistor T10 of the shift register circuit and the second clock connection electrode can be located between the projections of the third clock signal line CL3 and the fourth clock signal line CL4 on the substrate. For example, the projection of the gate of the tenth transistor T10 of the shift register circuit on the substrate can be located between the projections of the third clock signal line CL3 and the fourth clock signal line CL4 on the substrate. In this way, the gate of the tenth transistor can be directly connected to the third clock signal line or the fourth clock signal line through the second clock connection electrode located in the third conductive layer, avoiding the setting of redundant connection traces, so that the arrangement space can be optimized. Moreover, the connection via hole between the second clock connection electrode and the third clock signal line or the fourth clock signal line does not overlap with the connection via hole between the gate of the tenth transistor T10 and the second clock connection electrode, so that a large difference in the via hole can be avoided.

[0197] The remaining description of the display substrate of the example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0198] The embodiment also provides a display substrate, comprising: a substrate and a gate drive circuit arranged on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, each of the shift register circuits comprising: an input circuit, a control circuit and an output circuit. The input circuit is connected with a first node, an input terminal and a first clock terminal, and is configured to transmit an input signal provided by the input terminal to the first node under control of the first clock terminal. The control circuit is connected with the first node, a second node, a fourth node, a second clock terminal, a third clock terminal and a first voltage terminal, and is configured to control voltages of the second node and the fourth node. The output circuit is connected with the second node, the fourth node, the third clock terminal, the first voltage terminal and an output terminal, and is configured to control the output terminal to provide an output signal under control of the second node and the fourth node. In the control circuit, active layers of a plurality of transistors connected with the first voltage terminal are in an integrated structure, the integrated structure has a common connection terminal and a plurality of branches extending from the common connection terminal, and the common connection terminal is configured to be connected with the first voltage terminal.

[0199] In some example embodiments, the integrated structure of the active layers of the plurality of transistors connected with the first voltage terminal in the control circuit has a first branch, a second branch and a third branch; the first branch, the second branch and the third branch are arranged along the first direction. The first branch extends from the common connection terminal in a second direction in a stepped manner; the second branch extends from the common connection terminal along the first direction and the second direction in sequence; the third branch extends along the second direction; and the second direction intersects the first direction.

[0200] In some example embodiments, the control circuit includes: a first control circuit, a second control circuit, and a third control circuit. The first control circuit includes: a second transistor, a third transistor, and a tenth transistor; a gate of the second transistor is connected with the first node, a first electrode of the second transistor is connected with a second electrode of the tenth transistor, and a second electrode of the second transistor is connected with the second node; a gate of the third transistor is connected with the third node, a first electrode of the third transistor is connected with the third clock terminal, and a second electrode of the third transistor is connected with the second node; a gate of the tenth transistor is connected with the second clock terminal, and a first electrode of the tenth transistor is connected with the first voltage terminal. The second control circuit includes: a seventh transistor; a gate of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with the first voltage terminal, and a second electrode of the seventh transistor is connected with the third node. The third control circuit includes: a sixth transistor and a ninth transistor; a gate of the sixth transistor is connected with the second node, a first electrode of the sixth transistor is connected with the first voltage terminal, and a second electrode of the sixth transistor is connected with a first electrode of the ninth transistor; a gate of the ninth transistor is connected with the third clock terminal, and a second electrode of the ninth transistor is connected with the first node. The first branch is an integrated structure of active layers of the second transistor, the third transistor, and the tenth transistor; the second branch is an active layer of the seventh transistor; and the third branch is an integrated structure of active layers of the sixth transistor and the ninth transistor.

[0201] The display substrate of the present example can refer to the description of the foregoing embodiments, and thus will not be described again.

[0202] The embodiment also provides a preparation method of a display substrate, used for preparing the display substrate as described above, and the preparation method comprises the following steps: providing a substrate; and forming a gate drive circuit on the substrate. The gate drive circuit comprises a plurality of cascaded shift register circuits, and each shift register circuit comprises an input circuit, a first control circuit, a second control circuit, a third control circuit and an output circuit. The input circuit is connected with a first node, an input end and a first clock end, and is configured to transmit an input signal provided by the input end to the first node under the control of the first clock end. The output circuit is connected with a second node. The first control circuit is connected with the first node, the second node, a third node, a first voltage end and a second clock end, and is configured to control the voltage of the second node under the control of the first node, the third node and the second clock end. The second control circuit is connected with the first node, the third node and the first voltage end, and is configured to control the voltage of the third node under the control of the first node. The third control circuit is connected with the first node, the second node, a third clock end and the first voltage end, and is configured to transmit a first voltage signal provided by the first voltage end to the first node under the control of the second node and the third clock end. The first control circuit is located between the input circuit and the output circuit in the projection of the substrate in the first direction; the third control circuit is located between the first control circuit and the output circuit in the projection of the substrate in the first direction; and the second control circuit is located between the first control circuit and the third control circuit in the projection of the substrate in the first direction.

[0203] The preparation method of the display substrate of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0204] FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 21, the display device 91 according to the present embodiment comprises a display substrate 910. The display substrate 910 is the display substrate provided in the foregoing embodiments. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be an OLED display device, a watch, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. However, the present embodiment is not limited thereto.

[0205] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an example", "some examples" or the like means that the particular feature, structure, material or characteristic following the term is included in at least one embodiment or example of the application. The illustrative appearances of the above terms in various places in the specification are not necessarily referred to the same embodiment or example. Also, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, in non-contradictory relation to each other, those skilled in the art can combine and combine the features described in the specification of different embodiments or examples and the features of different embodiments or examples.

[0206] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be interpreted as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: A substrate and a gate drive circuit disposed on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, the shift register circuit comprising: an input circuit, a first control circuit, a second control circuit, a third control circuit and an output circuit; The input circuit is connected with a first node, an input terminal and a first clock terminal, and is configured to transmit an input signal provided by the input terminal to the first node under the control of the first clock terminal; The output circuit is connected with a second node; The first control circuit is connected with the first node, the second node, a third node, a first voltage terminal and a second clock terminal, and is configured to control the voltage of the second node under the control of the first node, the third node and the second clock terminal; The second control circuit is connected with the first node, the third node and the first voltage terminal, and is configured to control the voltage of the third node under the control of the first node; The third control circuit is connected with the first node, the second node, a third clock terminal and the first voltage terminal, and is configured to transmit a first voltage signal provided by the first voltage terminal to the first node under the control of the second node and the third clock terminal; The first control circuit is located between the input circuit and the output circuit in the projection of the substrate in the first direction; the third control circuit is located between the first control circuit and the output circuit in the projection of the substrate in the first direction; and the second control circuit is located between the first control circuit and the third control circuit in the projection of the substrate in the first direction. 2.The display substrate of claim 1, wherein, The active layers of the plurality of transistors connected with the first voltage terminal in the first control circuit, the second control circuit and the third control circuit are integrated structures. 3.The display substrate of claim 1, wherein, The first control circuit comprises a plurality of transistors arranged along a second direction; the third control circuit comprises a plurality of transistors arranged along the second direction; and the second direction intersects the first direction. 4.The display substrate of claim 3, wherein, The first control circuit comprises a second transistor, a third transistor and a tenth transistor; the gate of the second transistor is connected with the first node, the first electrode of the second transistor is connected with the second electrode of the tenth transistor, and the second electrode of the second transistor is connected with the second node; the gate of the third transistor is connected with the third node, the first electrode of the third transistor is connected with the third clock terminal, and the second electrode of the third transistor is connected with the second node; the gate of the tenth transistor is connected with the second clock terminal, and the first electrode of the tenth transistor is connected with the first voltage terminal; and the tenth transistor, the second transistor and the third transistor are arranged along the second direction. 5.The display substrate of claim 4, wherein, The active layer of the second transistor, the active layer of the third transistor and the active layer of the tenth transistor are integrated structures; the active layer of the second transistor is located between the active layer of the third transistor and the active layer of the tenth transistor in the second direction; The active layer of the tenth transistor extends in the first direction, and the active layer of the second transistor and the active layer of the third transistor both extend in the second direction; The gate of the tenth transistor extends in the second direction, and the gate of the second transistor and the gate of the third transistor both extend in the first direction. 6.The display substrate of claim 4, wherein, The second control circuit comprises a seventh transistor; the gate of the seventh transistor is connected with the first node, the first pole of the seventh transistor is connected with the first voltage terminal, and the second pole of the seventh transistor is connected with the third node; The seventh transistor, the second transistor and the third transistor are located on the same side of the tenth transistor in the second direction, and the seventh transistor is adjacent to the second transistor in the first direction; The active layer of the seventh transistor and the active layer of the tenth transistor are integrated structures; the active layer of the seventh transistor extends in the second direction; The gate of the seventh transistor and the gate of the second transistor are integrated structures, and the gate of the seventh transistor extends at least in the first direction. 7.The display substrate of claim 6, wherein, The third control circuit comprises a sixth transistor and a ninth transistor; the gate of the sixth transistor is connected with the second node, the first pole of the sixth transistor is connected with the first voltage terminal, and the second pole of the sixth transistor is connected with the first pole of the ninth transistor; the gate of the ninth transistor is connected with the third clock terminal, and the second pole of the ninth transistor is connected with the first node; The sixth transistor and the ninth transistor are arranged in alignment in the second direction, and the sixth transistor and the ninth transistor are adjacent to the seventh transistor in the first direction. 8.The display substrate of claim 7, wherein, The active layer of the sixth transistor, the active layer of the ninth transistor and the active layer of the tenth transistor are integrated structures; the active layer of the sixth transistor is located between the active layer of the tenth transistor and the active layer of the ninth transistor in the second direction; and the active layer of the sixth transistor and the active layer of the ninth transistor both extend in the second direction; The gate of the sixth transistor and the gate of the ninth transistor both extend in the first direction and are arranged in sequence in the second direction. 9.The display substrate of claim 7, wherein, The shift register circuit further comprises: A fourth control circuit connected with the first node, the output circuit and a second voltage terminal; the fourth control circuit is located on one side of the input circuit in the second direction; A fifth control circuit connected with the third node and the third clock terminal and configured to control the voltage of the third node by using the third clock terminal. The fifth control circuit is located between the fourth control circuit and the input circuit in the projection of the substrate in the second direction; and the fifth control circuit is adjacent to the third transistor in the projection of the substrate in the first direction. 10.The display substrate of claim 9, wherein, The output circuit comprises a fourth transistor, a fifth transistor, a second capacitor and a third capacitor. The gate of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first voltage terminal, and the second pole of the fourth transistor is connected with an output terminal. The gate of the fifth transistor is connected with the fourth control circuit, the first pole of the fifth transistor is connected with the third clock terminal, and the second pole of the fifth transistor is connected with the output terminal. The first pole plate of the second capacitor is connected with the second node, and the second pole plate of the second capacitor is connected with the first voltage terminal; the gate of the fifth transistor is connected with the first pole plate of the third capacitor, and the second pole plate of the third capacitor is connected with the output terminal. The fourth transistor and the fifth transistor are arranged in alignment along the second direction, the second capacitor and the third capacitor are located on the same side of the fourth transistor and the fifth transistor in the first direction, and the second capacitor and the third capacitor are arranged in alignment along the second direction. The active layer of the fourth transistor and the active layer of the fifth transistor are an integral structure; the gate of the fourth transistor, the first pole plate of the second capacitor and the gate of the sixth transistor are an integral structure; and the gate of the fifth transistor and the first pole plate of the third capacitor are an integral structure. 11.The display substrate of any one of claims 1 to 10, further comprising: A first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; The first clock terminal of the 4n-3 stage shift register circuit is connected with the first clock signal line, the second clock terminal of the 4n-3 stage shift register circuit is connected with the second clock signal line, and the third clock terminal of the 4n-3 stage shift register circuit is connected with the third clock signal line; The first clock terminal of the 4n-2 stage shift register circuit is connected with the second clock signal line, the second clock terminal of the 4n-2 stage shift register circuit is connected with the third clock signal line, and the third clock terminal of the 4n-2 stage shift register circuit is connected with the fourth clock signal line; The first clock terminal of the 4n-1 stage shift register circuit is connected with the third clock signal line, the second clock terminal of the 4n-1 stage shift register circuit is connected with the fourth clock signal line, and the third clock terminal of the 4n-1 stage shift register circuit is connected with the first clock signal line; The first clock terminal of the 4n stage shift register circuit is connected with the fourth clock signal line, the second clock terminal of the 4n stage shift register circuit is connected with the first clock signal line, and the third clock terminal of the 4n stage shift register circuit is connected with the second clock signal line; n is an integer greater than 0. 12.The display substrate of claim 11, wherein, An output terminal of a 2i-1th stage shift register circuit is connected with an input terminal of a 2i+1th stage shift register circuit, and an output terminal of a 2i stage shift register circuit is connected with an input terminal of a 2i+2th stage shift register circuit, where i is an integer greater than 0. 13.The display substrate of claim 12, wherein, The input terminal of the 2i+1th stage shift register circuit is connected with the output terminal of the 2i-1th stage shift register circuit through an input electrode, a stage connection signal line and an output electrode connected in sequence; the input electrode and the output electrode both extend along the first direction, and the stage connection signal line extends at least along a second direction; the second direction intersects the first direction; The stage connection signal line is located on a side of the input electrode and the output electrode away from the substrate. 14.The display substrate of claim 13, wherein, In a direction perpendicular to the display substrate, the display substrate at least comprises: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer disposed on the substrate; the stage connection signal line, the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are located in the fourth conductive layer; the input electrode is located in the third conductive layer; and the output electrode is located in the second conductive layer. 15.The display substrate of claim 11, wherein, The first control circuit of the shift register circuit comprises: a tenth transistor, a gate of the tenth transistor is connected with a second clock terminal; the gate of the tenth transistor is connected with a clock signal line through a second clock connection electrode; The connection via between the gate of the tenth transistor and the second clock connection electrode is located between the projection of the third clock signal line and the projection of the fourth clock signal line on the substrate. 16.The display substrate of claim 11, wherein, The third clock terminal of an nth stage shift register circuit is connected with the second clock terminal of an n+1th stage shift register circuit through different vias and the same clock signal line.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A manufacturing method of a display substrate, for manufacturing the display substrate according to any one of claims 1 to 16, the manufacturing method comprising: providing a substrate; forming a gate drive circuit on the substrate; The gate drive circuit comprises a plurality of cascaded shift register circuits, and each shift register circuit comprises an input circuit, a first control circuit, a second control circuit, a third control circuit and an output circuit. The first control circuit is located between the input circuit and the output circuit in the first direction on the projection of the substrate; the third control circuit is located between the first control circuit and the output circuit in the first direction on the projection of the substrate; and the second control circuit is located between the first control circuit and the third control circuit in the first direction on the projection of the substrate.

19. A display substrate, comprising: A substrate and a gate drive circuit arranged on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, and each shift register circuit comprising an input circuit, a control circuit and an output circuit. The input circuit is connected with a first node, an input terminal and a first clock terminal, and is configured to transmit an input signal provided by the input terminal to the first node under the control of the first clock terminal. The control circuit is connected with the first node, a second node, a fourth node, a second clock terminal, a third clock terminal and a first voltage terminal, and is configured to control the voltages of the second node and the fourth node. The output circuit is connected with the second node, the fourth node, the third clock terminal, the first voltage terminal and an output terminal, and is configured to control the output terminal to provide an output signal under the control of the second node and the fourth node. The active layers of a plurality of transistors connected with the first voltage terminal in the control circuit are in an integrated structure, and the integrated structure has a common connection terminal and a plurality of branches extending from the common connection terminal, and the common connection terminal is configured to be connected with the first voltage terminal. 20.The display substrate of claim 19, wherein, The integrated structure has a first branch, a second branch and a third branch; and the first branch, the second branch and the third branch are arranged along a first direction. The first branch extends in a second direction from the common connection end in a stepped manner; the second branch extends from the common connection end in a first direction and then in a second direction; the third branch extends in the second direction; and the second direction intersects the first direction.

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