Voltage-delay converter

Abstract

The present disclosure describes a voltage-delay converter comprising: a first reset transistor (402P) having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal (CLKRST), and a second terminal coupled to a top plate of a first integrating capacitor (404P); and a second reset transistor (402M) having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal (CLKRST), and a second terminal coupled to a top plate of a second integrating capacitor (404M). A first input transistor (412P) and a second input transistor (412M) receive a first input voltage (INP) and a second input voltage (INM), and are coupled between the top plates of the first integrating capacitor and the second integrating capacitor and a first current source (410), respectively. A discharge current source (406) is coupled to the base plates of the first and second integrating capacitors. A pulse generator (330) has first and second inputs coupled to the top plates of the first and second integrating capacitors, respectively.

Description

Background Technology

[0001] This specification relates to data conversion circuit systems, and more specifically, to delay-domain analog-to-digital converters.

[0002] Advances in wireless communication technology in recent years have led to widespread deployments and new applications for such communications. Wireless communication is now common in short-range communications (e.g., "personal area networks"), wireless public area networks (e.g., home or office "WiFi" networks), and long-range communications (e.g., cellular networks). Performance requirements across these network types range from low-data-rate and latency-tolerant applications to high-data-rate, real-time applications at gigahertz frequencies.

[0003] In any of these wireless communication applications, the conversion of analog signal levels to digital data and vice versa is a critical function performed at every network node or device. The performance requirements for high data rate communication devices, particularly mobile and battery-powered devices (e.g., user equipment capable of “5G” cellular communication), are reflected in the performance requirements of the data conversion circuitry systems within those devices. In these applications (especially for mobile devices), data converters may need to provide high-performance (e.g., low error rate) conversion at high data rates, wide input bandwidths, but with low power consumption. Power constraints on data converters are particularly stringent in Multiple-Input Multiple-Output (MIMO) network devices, which typically include integrated transceivers with up to eight or sixteen transmitters and receivers (e.g., 8T8R, 16T16R).

[0004] ADCs operating in the "delay domain" have been proposed for high-performance applications. An exemplary delay-domain ADC includes a voltage-to-delay (V2D) converter that translates an input voltage level into a delay between two pulses. A time-to-digital converter (TDC) encodes the delay interval output from the V2D converter into a digital output word.

[0005] Figure 1AA prior art dynamic differential amplifier 100 is shown, which receives differential input voltages at input terminals INP and INM and presents differential output voltages at output terminals INTP and INTM. In one branch of the dynamic amplifier 100, an integrating capacitor 106P has a top plate coupled to the output terminal INTP and a bottom plate at a common potential (e.g., circuit ground). An N-channel metal-oxide-semiconductor (NMOS) transistor 104P has a drain coupled to the top plate of the integrating capacitor 106P and a gate that receives a clock signal CLK_V2V. The source of the NMOS transistor 104P is coupled to the drain of the NMOS input transistor 102P at node VP and also to the drain of a p-channel MOS (PMOS) transistor 105P. The PMOS transistor 105P has a connection to a power supply voltage V. dd The source of the NMOS input transistor 102P is coupled to the gate of the input terminal INP and the source of the PMOS input transistor 105M is coupled to the tail node T. Similarly, the second branch of the dynamic amplifier 100 is constructed, wherein the integrating capacitor 106M has a top plate coupled to the output terminal INTM and a bottom plate at circuit ground. The NMOS transistor 104M has a drain coupled to the top plate of the integrating capacitor 106M, a gate for receiving the clock signal CLK_V2V, and a source coupled to the drain of the NMOS input transistor 102M and the drain of the PMOS transistor 105M at node VM. The PMOS transistor 105M has a source coupled to the power supply voltage V. dd The source of the NMOS input transistor 102M is coupled to the gate of the input terminal INM and the source of the NMOS input transistor 102M is coupled to the tail node T.

[0006] The tail node T is coupled to the drain of NMOS transistor 109. NMOS transistor 109 has a gate for receiving the signal CLK_BIAS and a source coupled to the drain of NMOS transistor 110. NMOS transistor 110 has a drain coupled to the source of NMOS transistor 109, a gate for receiving the signal NBIAS_V2V, and a source at circuit ground.

[0007] The dynamic amplifier 100 initially precharges the integrating capacitors 106P and 106M to a selected voltage (e.g., the supply voltage V). dd The differential input voltage at the input terminals INP and INM differentially turns on the input transistors 102P and 102M, thereby discharging the integrating capacitors 102P and 102M toward ground at a relative rate corresponding to the input differential voltage, so as to generate a differential voltage at the output terminals INTP and INTM. Summary of the Invention

[0008] In one example, a voltage-delay converter includes: a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal for receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor; and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal for receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. A first input transistor and a second input transistor have gates coupled to receive a first input voltage and a second input voltage, first terminals coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively, and second terminals coupled to a first current source. A discharge current source is coupled to the base plates of the first integrating capacitor and the second integrating capacitor. A pulse generator has a first input and a second input coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively.

[0009] In another example, an analog-to-digital conversion method includes: charging a first plate of each of a first integrating capacitor and a second integrating capacitor to a first voltage; applying a differential voltage across the gate terminals of a first transistor and a second transistor coupled between the first plates of the first integrating capacitor and the second integrating capacitor, respectively; discharging a second plate of each of the first integrating capacitor and the second integrating capacitor; generating a first pulse and a second pulse having a relative delay corresponding to the voltage at the first plates of the first integrating capacitor and the second integrating capacitor; and generating a digital output word corresponding to the relative delay of the first pulse and the second pulse.

[0010] In another example, an analog-to-digital converter includes a voltage-delay converter and a delay-to-digital converter. The voltage-delay converter includes: a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor; and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. A first input transistor and a second input transistor have gates coupled to receive a first input voltage and a second input voltage, first terminals coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively, and second terminals coupled to a first current source. A discharge current source is coupled to the base plates of the first integrating capacitor and the second integrating capacitor. A pulse generator has a first input and a second input coupled to the top plates of the first integrating capacitor and the second integrating capacitor, respectively. The delay-to-digital converter has a first input and a second input coupled to the first output and the second output of the pulse generator, respectively, and has a digital output, configured to generate a digital output word corresponding to a relative delay between pulses at the first output and the second output of the pulse generator.

[0011] Exemplary technical advantages achieved by one or more of these examples include providing a delay-domain analog-to-digital converter with improved noise performance, reduced sensitivity to input transistor mismatch, and improved current source margin to maintain transistor saturation. Improved linearity in the conversion can be provided by calibrating the gain characteristics of the current discharge stage to eliminate nonlinearity in the input stage, thereby providing good linearity for variations in process, voltage, and temperature.

[0012] Those skilled in the art will understand the other technical advantages achieved through the disclosed examples after referring to the following instructions and diagrams. Attached Figure Description

[0013] Figure 1A It is an electrical diagram in schematic form of a prior art dynamic amplifier.

[0014] Figure 1B It is shown Figure 1A Timing diagram of the operation of the dynamic amplifier.

[0015] Figure 1C yes Figure 1A The gain versus input voltage curve of an example of a dynamic amplifier.

[0016] Figure 2 This is a box-shaped electrical diagram of an exemplary analog-to-digital converter (ADC).

[0017] Figure 3This is a box-format electrical diagram of an exemplary voltage-delay (V2D) converter.

[0018] Figure 4A yes Figure 3 An electrical diagram in schematic form of an exemplary dynamic amplifier, constant current discharge circuit, and pulse generator for a V2D converter.

[0019] Figure 4B It is shown Figure 4A Timing diagrams for the operation of examples of dynamic amplifiers and constant current discharge circuits.

[0020] Figure 4C yes Figure 4A The gain versus input voltage curve of an example of a constant current discharge circuit.

[0021] Figure 4D yes Figure 4A The gain linearity versus input voltage curve of an example of a V2D converter.

[0022] Figure 5 This is an electrical diagram in schematic form of another exemplary constant current discharge circuit.

[0023] Figure 6 It is used for Figure 3 An electrical diagram in schematic form is provided for an exemplary calibration logic of a V2D converter.

[0024] Figure 7 This is an electrical diagram in schematic form of another exemplary constant current discharge circuit.

[0025] Figure 8 It is used for Figure 3 An electrical diagram in schematic form of a portion of an exemplary pulse generator for a V2D converter.

[0026] Figure 9 This is a flowchart illustrating an exemplary method for converting an input voltage into a delay domain signal.

[0027] Use the same reference numerals or other reference indicators in the drawings to show the same or similar features (functionally and / or structurally). Detailed Implementation

[0028] Figure 2 The high-level architecture of an exemplary delay-domain analog-to-digital converter (ADC) 200 is shown. The ADC 200 includes a voltage-to-delay (V2D) converter 210 and a time-to-digital converter (TDC) 220.

[0029] The V2D converter 210 has the function of receiving input voltage V in The input. Input voltage V inThe voltage can be single-ended or differential, and the ADC 200 generates a digital output word D from the single-ended or differential voltage. out For example, the input voltage V in This can be a sample acquired from a received communication signal via a sample-and-hold circuit operating at a selected sampling rate. In this example, the V2D converter 210 generates a sample corresponding to the input voltage V. in The amplitude of the delayed domain signal ΔT is given. For example, the delayed domain signal ΔT can be transmitted by the V2D converter 210 with a value corresponding to the input voltage V. in The output is in the form of one or more conductor pairs of pulses whose amplitude corresponds to the relative delay ΔT.

[0030] TDC 220 has inputs that receive a delay domain signal ΔT from V2D converter 210 on one or more conductor pairs. TDC 220 includes components arranged to generate a digital output word D at the output. out Analog circuit systems, digital logic, or combinations thereof. For example, the TDC 220 may have series or parallel outputs, thereby adapting to the input voltage V. in Each converted sample presents an m-bit digital output word D out Digital output word D out It can be output synchronously with the associated system clock for communication to downstream processing circuitry systems (not shown) suitable for a specific application.

[0031] Examples of TDC converter architectures applicable to the TDC 220 used in this example are described in U.S. Patent Nos. 10,673,453, 10,778,243, 11,316,525, 11,387,840, and 11,316,526; U.S. Patent Application Publication Nos. 2022 / 0247420, 2022 / 0247421, and 2022 / 0224349; and pending U.S. Patent Application No. 18 / 174,187, filed February 24, 2023, each of which is jointly assigned with this application and each is incorporated herein by reference in its entirety.

[0032] The linearity of the ADC's output amplitude as a function of the input amplitude is a crucial factor in the accuracy and performance of the ADC converter. The variation in the input voltage step width associated with each output codeword value is called differential nonlinearity (DNL) error. Excessive DNL error can lead to the loss of output codeword values ​​across the ADC's full-scale range. Integral nonlinearity (INL) error represents the deviation of the ADC transfer function from a straight line across the full-scale range.

[0033] The use of a dynamic differential amplifier in the V2D converter stage is attractive when implementing a delay-domain ADC because dynamic amplifier operation helps generate delayed pulses from the differential input voltage. Additionally, the gain from the dynamic amplifier effectively relaxes the noise specifications of the delay-domain ADC. However, for example... Figure 1A Existing technologies such as Dynamic Amplifier 100 and other dynamic amplifiers exhibit significant nonlinearity.

[0034] On this point, Figure 1B Show Figure 1A An exemplary operating cycle of a prior art dynamic amplifier 100. This operating cycle includes a reset phase in which integrating capacitors 106P and 106M are precharged to a selected voltage, such as close to the supply voltage V. dd During this reset phase, transistors 105P, 105M, and 108 are turned on by having their gate signals CLK_BIAS low, and transistors 104P, 104M, and 109 are turned off by having their gate signals CLK_BIAS and CLK_V2V low. As a result, nodes VP, VM, and T are at or near the supply voltage V. dd Furthermore, the top plates of capacitors 106pF and 106M are charged to the power supply voltage V. dd At or near the location. This reset phase causes the output nodes INTP and INTM to be charged to the supply voltage V. dd Level at or near the location, such as Figure 1B As shown in the image.

[0035] After the pre-charging of integrating capacitors 106P and 106M during the reset phase, the differential voltage at input terminals INP and INM is sensed during the amplification phase of the operating cycle. This amplification phase is initiated by a low-to-high transition of the signal CLK_BIAS, thereby turning on NMOS transistor 109 and turning off PMOS transistors 105P, 105M, and 108. Transistors 104P and 104M are turned on during the amplification phase, thereby allowing the differential gate voltage applied at inputs INP and INM during this amplification phase to determine the relative rate at which integrating capacitors 106P and 106M are discharged through input transistors 102P and 102M, respectively. NMOS transistor 110 acts as a current source, thereby controlling the sum of the discharge currents according to the gate voltage NBIAS_V2V. Figure 1B In this example, the negative differential voltage (e.g., the voltage at input INP is differentially lower than the voltage at input INM) causes the integrating capacitor 106M to discharge faster relative to the integrating capacitor 106P through the input transistor 102M. While the integrating capacitors 106P and 106M discharge during this amplification phase, the voltage at the output node INTP remains differentially higher than the voltage at the output node INTM.

[0036] During the hold phase following the amplification phase, transistors 104P and 104M are turned off by the high-to-low transition of the signal CLK_V2V. Therefore, output nodes INTP and INTM are isolated from their corresponding input transistors 102P and 102M, thereby preventing the discharge of integrating capacitors 106P and 106M. At the end of the amplification phase, the differential output voltage across output nodes INTP and INTM is thus maintained at a certain interval, allowing downstream circuitry to respond, for example, by generating a pair of pulses with a relative delay corresponding to the differential voltage at output nodes INTP and INTM. The dynamic amplifier 100 can then be reset for the next operating cycle.

[0037] The first-order expression for the gain G of the dynamic amplifier 100 can be expressed as:

[0038] (1)

[0039] Where g m It is the transconductance of the input transistor, T int is the discharge time constant of the integrating capacitor, and C is the capacitance of the integrating capacitor. As is evident from equation (1), the gain G is related to the input voltage V. in This is irrelevant, and therefore, good linearity is possible as long as the transistors in the dynamic amplifier 100 are in saturation. Furthermore, the linearity in the operation of the dynamic amplifier is often affected by the drain-to-source voltage (Vd) of the transistors used to maintain device saturation. ds The limitations of tolerances, especially in the low supply voltages (e.g., nominal V of 1.0 V) common in modern high-performance integrated circuits. dd )Down.

[0040] For example, such as Figure 1A As shown, the dynamic amplifier 100 includes four MOS transistors (e.g., transistors 104P, 102P, 109, and 110), with the source / drain paths connected in series at the supply voltage V. dd Between and the circuit ground. If the power supply voltage V dd Approximately 1.0 V, therefore a very small drain-to-source voltage (V) can be used. ds Tolerances are provided to keep all these devices in saturation, especially at a specified differential input voltage V. in Within the full range. Additionally... Figure 1B The diagram shows that when the integrating capacitors 106P and 106M discharge during amplification, the common-mode voltage at the output terminals INTP and INTM drops, which often causes one or more of the transistors in the series-coupled path to go out of saturation.

[0041] Therefore, the dynamic amplifier 100 can exhibit nonlinearity in its gain as a function of the input differential voltage. For example, the gain of the dynamic amplifier 100 has been observed to exhibit quadratic characteristics over the input voltage range, where the square term (e.g., V in the gain equation)... in 2 The item has a negative coefficient. Figure 1C An exemplary normalized graph showing this gain characteristic of the dynamic amplifier 100 is provided, in which the gain decreases as the differential input voltage increases, exhibiting a “compressed” nonlinearity.

[0042] Figure 3 An exemplary V2D converter 210 in ADC 200 is shown. In this example, V2D converter 210 includes a dynamic amplifier input stage 310, a constant current discharge stage 320, a pulse generator 330, and calibration logic 340.

[0043] In this example, the dynamic amplifier input stage 310 is a differential dynamic amplifier, where the differential input terminals INP and INM receive the differential input voltage V. in The dynamic amplifier input stage 310 operates at an input voltage V. in A voltage-to-voltage (V2V) conversion is performed to generate corresponding differential voltages at intermediate output nodes INTP and INTM. A constant current discharge stage 320 is coupled to the intermediate output nodes INTP and INTM, as is the input to pulse generator 330. Pulse generator 330 generates logic level pulses at output terminals OUTP and OUTM based on the voltages at intermediate output nodes INTP and INTM, respectively. The relative delay of the logic level pulses from pulse generator 330 at output terminals OUTP and OUTM reflects the differential input voltage V at the input of dynamic amplifier input stage 310. in This enables voltage-delay (V2D) conversion to a delay domain signal ΔT.

[0044] In this example of the V2D converter 210, the calibration logic 340 has inputs coupled to output terminals OUTP and OUTM, and one or more output CALs coupled to a constant current discharge stage 320. Optionally, the calibration logic 340 may also have inputs coupled to input terminals INP and INM. The calibration logic 340 includes analog or digital logic arranged to generate a calibration word at its output CAL in response to a comparison of a pulse at output terminals OUTP and OUTM with a known input value (e.g., as transmitted from input terminals INP and INM).

[0045] Figure 4AThe diagram illustrates the construction of an exemplary dynamic amplifier input stage 310, an exemplary constant current discharge stage 320, and an exemplary pulse generator 330 implemented in a V2D converter 210. The V2D converter 210 also includes a clock circuitry 440 and is under the timing control of said clock circuitry. The dynamic amplifier input stage 310 includes NMOS transistors 408P, 408M, 409, 410, 412P, and 412M. The constant current discharge stage 320 includes PMOS transistors 402M, 402P, and 402B, NMOS transistors 405 and 406, integrating capacitors 404P and 404M, boost capacitors 420P and 420M, and a boost driver 425. The pulse generator 330 includes inverters 432P, 432M, 434P, 434M, 436P, and 436M.

[0046] The NMOS transistor 408P in the input stage 310 of the dynamic amplifier has a drain coupled to the intermediate output node INTP and a gate that receives the clock signal CLK_V2V from the clock circuit system 440. The source of NMOS transistor 408P is coupled to the drain of NMOS input transistor 412P, which has a gate coupled to the input terminal INP and a source coupled to the drain of NMOS transistor 409 at node T. Similarly, NMOS transistor 408M has a drain coupled to the intermediate output node INTM and a gate that receives the clock signal CLK_V2V from the clock circuit system 440. The source of NMOS transistor 408M is coupled to the drain of NMOS input transistor 412M, which has a gate coupled to the input terminal IMN and a source coupled to the drain of NMOS transistor 409 at node T. NMOS transistor 409 has a gate that receives a clock signal CLK_BIAS from clock circuitry 440, and a source coupled to the drain of NMOS transistor 410. NMOS transistor 410 has a source coupled to a common potential (e.g., circuit ground) and a gate that receives a reference voltage NBIAS_V2V. The reference voltage NBIAS_V2V may be a regulated voltage, for example, generated by a voltage regulator circuitry. The voltage NBIAS_V2V controls the total current conducted by the two input transistor branches (e.g., the sum of the currents conducted by input transistors 412P and 412M) so that NMOS transistor 410 functions as a current source.

[0047] The integrating capacitor 404P in the constant current discharge stage 320 has a top plate coupled to the intermediate output node INTP. The integrating capacitor 404M has a top plate coupled to the intermediate output node INTM. The PMOS reset transistor 402P has a drain coupled to the intermediate output node INTP and a drain coupled to the supply voltage V. ddThe source of the PMOS reset transistor 402M is coupled to the drain of the intermediate output node INTM and the power supply voltage V. dd The integrating capacitors 404P and 404M each have a base plate coupled to the drain of NMOS transistor 405 at node BP. NMOS transistor 405 has a gate that receives the clock signal CLK_V2D from clock circuit system 440, and a source coupled to the drain of NMOS transistor 406. NMOS transistor 406 has a source coupled to circuit ground and a gate that receives the reference voltage NBIAS_V2D. Voltage NBIAS_V2D may be a regulated voltage generated by a voltage regulator circuit system included in V2D converter 210 or elsewhere in the same integrated circuit. PMOS reset transistor 402B has a drain coupled to node BP at the base plate of integrating capacitors 404P and 404M, and a source coupled to the power supply voltage V. dd The source of the PMOS reset transistors 402B, 402P, and 402M. Each of them has a gate that receives the reset clock signal CLK_RST from the clock circuit system 440.

[0048] Boost capacitor 420P has a top plate coupled to intermediate output node INTP, and boost capacitor 420M has a top plate coupled to intermediate output node INTM. The bottom plates of boost capacitors 420P and 420M are coupled to the output of boost driver 425, which has an input that receives a boost clock signal CLK_BOOST from clock circuit system 440. Figure 4A The boost capacitors 420P and 420M are shown as single examples. However, each of the boost capacitors 420P and 420M can be implemented as multiple capacitors connected in parallel, as described below.

[0049] The clock circuitry 440 may be located within the ADC 200 or elsewhere in the same integrated circuit having the ADC 200. The clock circuitry 440 includes appropriate clock generator circuitry for generating clock signals CLK_V2V, CLK_RST, CLK_BOOST, CLK_V2D, and CLK_BOOST at appropriate times during the conversion cycle. In this example, the clock circuitry 440 generates these clock signals in response to a sampling clock ADC_CLK operating at the desired conversion rate.

[0050] In this example, pulse generator 330 includes a pair of inverter chains. In one inverter chain, inverter 432P has an input coupled to an intermediate output node INTP, with inverters 434P and 436P coupled in series at the output of inverter 432P. The output of inverter 436P is coupled to the output terminal OUTP. Similarly, inverter 432M has an input coupled to an intermediate output node INTM. Inverters 434M and 436M are coupled in series at the output of inverter 432M. Inverter 436M has an output that drives the output terminal OUTM.

[0051] Figure 4B Show Figure 4A Exemplary operation of the V2D converter 210. In this example, each conversion cycle can be considered to include a reset phase, a V2V phase, and a V2D phase. In the reset phase, the power supply voltage V is directed towards the reset transistors 402P and 402M respectively. dd The integrating capacitors 404P and 404M and the boost capacitors 420P and 420M are charged. During the V2V phase, in response to the differential voltage at the input terminals INP and INM, the dynamic amplifier input stage 310 generates a differential voltage at the intermediate output nodes INTP and INTM. During the V2D phase, the constant current discharge stage 320 forwards the differential voltage at the intermediate output nodes INTP and INTM to the pulse generator 330, and the pulse generator 330 generates pulses at the output terminals OUTP and OUTM with a relative delay corresponding to the differential voltage at the input terminals INTP and INTM.

[0052] Figure 4B The transition cycle shown begins at time t0, where clock circuitry 440 drives each of the clock signals CLK_RST, CLK_V2V, and CLK_V2D to a low logic level, thereby enabling the reset phase. During this reset phase, reset transistors 402P, 402M, and 402B are turned on by the low level of clock signal CLK_RST, and transistors 408P and 408M in the dynamic amplifier input stage 310 and transistor 405 in the constant current discharge stage 320 are turned off. In the turn-on stage, reset transistors 402P, 402M, and 402B direct the integrating capacitors 404P and 404M and the boost capacitors 420P and 420M toward the supply voltage V. dd (For example, in this instance, charging is performed at approximately 1.0 V.) This pre-charge voltage is presented as follows: Figure 4B The intermediate output nodes INTP and INTM are shown in the image.

[0053] After the integrating capacitors 404P and 404M and the boost capacitors 420P and 420M are charged during the reset phase, the clock circuit system 440...Figure 4B The time t1 shown drives the clock signal CLK_RST to a high logic level. The high logic level of the clock signal CLK_RST turns off reset transistors 402P, 402M, and 402B, and turns on transistors 408P and 408M in the dynamic amplifier input stage 310. At this time, the clock signal CLK_V2D remains low, thus keeping transistor 405 off in the constant current discharge stage 320. In this V2V stage, the differential voltage at input terminals INP and INM (e.g., obtainable by a sample-and-hold circuit) generates a differential voltage at intermediate output nodes INTP and INTM. Figure 4B In the example, compared to the input transistor 412P, a negative differential input voltage (the voltage at input terminal INTP is lower than the voltage at input terminal INTM) makes it more difficult to turn on the input transistor 412M. As a result, the intermediate output node INTM discharges faster in the V2V stage than the intermediate output node INTP, such as... Figure 4B As shown in the diagram. The total discharge current through the input transistors 412P and 412M is controlled by transistor 410, which serves as a current source in the input stage 310 of the dynamic amplifier.

[0054] As from Figure 4B It is evident that during the V2V phase, both intermediate output nodes INTP and INTM discharge through the input stage 310 of the dynamic amplifier. Therefore, during the V2V phase, the common-mode voltage V of intermediate output nodes INTP and INTM... CM_INT (For example, the midpoint voltage) also decreases. According to this example, during the V2V phase, the clock circuit system 440 ramps up the signal CLK_BOOST from a low level. The voltage ramp of the CLK_BOOST signal causes the boost driver 425 to drive the base plates of the boost capacitors 420P and 420M, thereby slowing down the discharge rate of the intermediate output nodes INTP and INTM during the V2V phase. As a result, the common-mode voltage V at the intermediate output nodes INTP and INTM decreases. CM_INT This is maintained at a high level, thus helping to keep the transistors in the input stage 310 of the dynamic amplifier saturated. At the end of the approximately V2V phase, the signal CLK_BOOST reaches a selected voltage (e.g., approximately 250 mV) and is maintained at this voltage by the clock circuitry system 440.

[0055] exist Figure 4BIn this example, the clock circuit system 440 initiates the V2D phase of the transition cycle at time t2 by driving the clock signal CLK_V2D high and the clock signal CLK_V2V low. The low logic level of the clock signal CLK_V2V turns off transistors 408P and 408M in the dynamic amplifier input stage 310, which decouples the input transistors 412P and 412M from the intermediate output nodes INTP and INTM, respectively. During the V2D phase, the high logic level of the clock signal CLK_V2D turns on transistor 405 in the constant current discharge stage 320. In response, the base plates of the integrating capacitors 404P and 404M at node BP discharge toward circuit ground through transistors 405 and 406. The total discharge current is controlled by transistor 406, which acts as a current source. In this example, the constant current discharge of the base plates of the integrating capacitors 404P and 404M helps to isolate the margin of the current source transistor 406 from the voltage at the top plate of the integrating capacitors. This effect has been observed to significantly reduce noise effects in constant current discharge stages. This effect also reduces flicker noise exhibited by dynamic amplifiers, where the integrating capacitor discharges from the top plate, as in... Figure 1A In the example.

[0056] During the V2V phase of this conversion cycle, the voltages at the intermediate output nodes INTP and INTM continue to decrease, such as Figure 4B As shown in the diagram. In this example, the intermediate output node INTM drops to the input threshold of the inverter 432M in pulse generator 330 at approximately time t3 during the V2D phase. In response to the intermediate output node INTM dropping to this level, the chain of inverters 432M, 434M, and 436M in pulse generator 330 produces a low-to-high transition at the output terminal INTM. This will be shown at a later time. Figure 4B At time t4, the intermediate output node INTP drops to the input threshold of the inverter 432P in pulse generator 330. This produces a low-to-high transition at the output terminal INTP, as generated by the inverters 432P, 434P, and 436P of pulse generator 330. The relative delay ΔT between the low-to-high transitions of output terminals OUTP and OUTPM indicates the magnitude of the differential input voltage applied to input terminals INP and INM. For example, a larger input differential voltage produces a longer relative delay at output terminals OUTP and OUTM. The polarity of the differential voltage at input terminals INP and INM determines which pulse at output terminals OUTP and OUTM leads the other.

[0057] The clock circuit system 440 drives the clock signals CLK_V2D and CLK_RST low to a low level. Figure 4BThe V2D phase of the conversion cycle ends at approximately time t5. As the intermediate output nodes INTP and INTM are pre-charged again to the supply voltage V... dd This causes the pulse generator 330 to drive both output terminals OUTP and OUTM to a high logic level during this reset phase of the next conversion cycle.

[0058] As mentioned above Figure 1C The description, for example Figure 1A The dynamic amplifier shown exhibits compression nonlinearity in its gain characteristics, where the amplifier gain decreases with increasing differential input voltage, largely according to a quadratic characteristic. Figure 4A In the example of the V2D converter 210, the dynamic amplifier input stage 310 can exhibit similar nonlinear characteristics. However, in this example, as... Figure 4A The constant current discharge stage 320 shown in the figure exhibits an "expanded" nonlinearity in its gain characteristics, which is also largely based on the quadratic characteristics. Figure 4C An example of the secondary expansion gain characteristics for a constant current discharge stage 320 is shown. (See example from...) Figure 4C It is evident that the gain increases with increasing differential input voltage. The combination of the dynamic amplifier input stage 310 and the constant current discharge stage 320 provides two opposing nonlinear characteristics that can be effectively canceled out. Therefore, the resulting V2D converter 210 exhibits excellent gain linearity over its full-scale input voltage range.

[0059] In a general sense, as a differential input voltage V in Gain of the input stage of the dynamic amplifier with a function of 310 v2v The expression follows a quadratic relation:

[0060] (2)

[0061] Among them G v2v It is the nominal gain of the input stage 310, and A1 and A2 are positive coefficients. In one instance, coefficient A1 is several orders of magnitude smaller than coefficient A2. The negative sign of the squared term in this equation (2) indicates compression nonlinearity, where Gain v2v With the differential input value V in Increases and decreases. Gain of constant current discharge stage 320. v2d Relative to differential input voltage V in Similar expressions follow a quadratic relation:

[0062] (3)

[0063] Among them G v2dIt is the nominal gain of the constant current discharge stage 320, and B1 and B2 are positive coefficients. In one instance, coefficient B1 is several orders of magnitude smaller than coefficient B2. The positive sign of the squared term in this equation (3) indicates the expansion nonlinearity, where Gain v2d With the differential input value V in Increase and increase. Based on this example, a constant current discharge stage 320 is implemented such that the value of its square term coefficient B2 in equation (3) is close to the value of the square term coefficient A2 in equation (2).

[0064] The analysis of the delay at one of the intermediate output nodes INTP and INTM (e.g., INTP for which we will discuss below) during the V2D phase of the transformation loop provides the following expression for the coefficient B2 of the squared term in equation (3):

[0065] (4)

[0066] in:

[0067] (5)

[0068] Where C 404 and C 420 These are the capacitances of the integrating capacitor 404P and the boost capacitor 420P (or the integrating capacitor 404P and the boost capacitor 420P), respectively. In this equation (5), I is the regulated current conducted by the current source transistor 406, and R is the source resistance of the transistor 406 (e.g., the on-resistance R). on V th It is the input threshold voltage of the first inverters 432P and 432M in the pulse generator 330, and V CM_INT This refers to the common-mode output voltage at intermediate output nodes INTP and INTM. Therefore, the voltage can be controlled by adjusting the capacitance ratio of integrating capacitors 404P and 404M and boost capacitors 420P and 420M, by controlling the resistance R of current source transistor 406, by controlling the threshold voltage at inverters 432P and 432M, or by controlling the common-mode voltage at intermediate output nodes INTP and INTM. Figure 4A The extended nonlinear gain characteristics of the constant current discharge stage 320 control equation (3).

[0069] Figure 5 The common-mode voltage V is shown, arranged to control the intermediate output nodes INTP and INTM. CM_INT An example of a constant current discharge stage 520. More specifically, the constant current discharge stage 520 controls the common-mode voltage V by controlling the amount of boost capacitor enabled in the V2D phase of the conversion cycle. CM_INTThe constant current discharge stage 520 includes reset transistors 402M, 402P, and 402B, integrating transistors 404P and 404M, and NMOS transistors 405 and 406, as shown in... Figure 4A In the example.

[0070] like Figure 5 As shown, the constant current discharge stage 520 includes multiple boost capacitors 520 coupled to each of the intermediate output nodes INTP and INTM. In this example, three boost capacitors 520PA, 520PB, and 520PC each have a top plate coupled to the intermediate output node INTP. Similarly, three boost capacitors 520MA, 520MB, and 520MC each have a top plate coupled to the intermediate output node INTM. Boost driver 525A has outputs coupled to the bottom plates of boost capacitors 520PA and 520MA. Boost driver 525B has outputs coupled to the bottom plates of boost capacitors 520PB and 520MB. Boost driver 525C has outputs coupled to the bottom plates of boost capacitors 520PC and 520MC. The capacitances of boost capacitors 520PA, 520PB, 520PC and boost capacitors 520MA, 520MB, and 520MC may be binary-weighted, equivalent-weighted, or have some other weighting relationship. In this example, Figure 5 The example shows three boost capacitors, 520PA, 520PB, and 520PC, and three boost capacitors, 520MA, 520MB, and 520MC. In other examples, more or fewer boost capacitors may be provided, depending on the adjustment of the common-mode voltage V. CM_INT The desired resolution.

[0071] In this example, boost drivers 525A, 525B, and 525C each have inputs driven by the outputs of the decoder and timing logic 530. The decoder and timing logic 530 have inputs that receive the calibration word CAL and inputs from the clock circuit system 440 (…). Figure 4A It receives the clock input of the clock signal CLK_BOOST.

[0072] During operation, the clock signal CLK_BOOST is activated at the appropriate time within the transition cycle (e.g., starting in the V2V level and entering the V2D level, such as...). Figure 4BAs shown in the diagram, the decoder and timing logic 530 drive one or more of the boost drivers 525A, 525B, and 525C. The value of the calibration word CAL received by the decoder and timing logic 530 determines which boost drivers 525A, 525B, and 525C are selected to be driven by the decoder and timing logic 530. Driving more boost capacitors at the intermediate output nodes INTP and INTM (e.g., driving more of the boost drivers 525A, 525B, and 525C, or driving those associated with more boost capacitors) enhances the effect of the boost capacitors and thus reduces the common-mode voltage V. CM_INT The discharge. Fewer boost capacitors at the intermediate output nodes INTP and INTM will allow the common-mode voltage V to be discharged. CM_INT Discharges more quickly.

[0073] Figure 6 An example of calibration logic 340 is shown. Calibration logic 340 includes duty cycle measurement circuitry 602, analog-to-digital converter (ADC) 604, and linearity correction circuitry 606. Duty cycle measurement circuitry 602 has inputs coupled to output terminals OUTP and OUTM, and corresponding outputs DCP and DCM coupled to the inputs of ADC 604. Duty cycle measurement circuitry 602 includes analog and digital circuitry arranged to measure the duty cycle of pulses at output terminals OUTP and OUTM, as pulse generator 330 generates those pulses in response to samples of differential input voltages at input terminals INP and IMN, as described above. In this example, the outputs DCP and DCM from duty cycle measurement circuitry 602 transmit analog levels indicating the measured duty cycle. ADC 604 includes multiple channels to convert each of the analog levels into a digital value at its input. Figure 6 As shown, the ADC 604 can optionally include additional channels to convert the differential input voltage V0. in The current sample (e.g., an input sample corresponding to the pulse received by calibration logic 340 at output terminals OUTP, OUTM) is converted into a digital value. The digital value obtained by ADC 604 is forwarded to the input of linear correction circuit 606.

[0074] Linear correction circuit 606 includes digital logic configured or programmed to analyze V2D converter 210 as a function of differential input voltage V. in The varying linearity is controlled, and the appropriate value of the calibration word CAL is provided to the decoder and timing logic 530. The decoder and timing logic 530 then selectively drive the boost drivers 525A, 525B, and 525C to adjust the boost surge at the intermediate output nodes INTP and INTM, and thus control the common-mode voltage at these nodes to compensate for detected nonlinearities. For Figure 6An example where the differential input voltage V in Forwarded (directly or indirectly) to calibration logic 340, the operation of linear correction circuit 606 can be periodically executed during normal operation of V2D converter 210. Alternatively or additionally, calibration logic 340 can be enabled to execute calibration routines during power-on reset routines or otherwise. Furthermore, in an alternative where calibration logic 340 is enabled during a separate calibration routine, linear correction circuit 606 can analyze the nonlinearity of V2D converter 210 based on a preset sequence of differential input voltages within the input range. In this case, the input voltage V... in It is not necessary to apply it to ADC 604.

[0075] The common-mode voltage V is adjusted by controlling the boost capacitor. CM_INT In this example, improved linearity of the V2D converter 210 can be obtained. In one embodiment evaluated by means of simulation, the second-order gain characteristics of the dynamic amplifier input stage 310 are evaluated as follows:

[0076] (6a)

[0077] As is evident from equation (6a), this gain characteristic is dominated by negative square terms and is therefore compressed. Figure 4D Curve 450 in the figure shows one side of this compression gain characteristic (e.g., for the input voltage V). in (positive value). Similarly, according to Figure 5 and Figure 6 Example calibration of common-mode voltage V CM_INT Subsequently, the second-order gain characteristics of the constant current discharge stage 320 example were evaluated as follows:

[0078] (6b)

[0079] Curve 452 shows the input voltage V in This extended gain characteristic is within the positive range. Therefore, due to the close correspondence in the coefficient values ​​of the squared terms with opposite signs in equations (6a) and (6b), the extended gain characteristic of the constant current discharge stage 320 closely compensates for the compressed gain characteristic of the dynamic amplifier input stage 310. The combination of the two stages in the V2D converter 210 according to this example provides good gain linearity of the input voltage, such as Figure 4DAs illustrated by curve 455, the nonlinearity of the dynamic amplifier input stage 310, as shown by curve 450, is 50.2 dBc. On the other hand, the nonlinearity of the constant current discharge stage 320, as shown by curve 452, is approximately 51 dBc, but in the opposite direction. In this example, the combined nonlinearity of the two stages in the V2D converter 210, as shown by curve 455, is approximately 72 dBc, thus providing an improvement of approximately 20 dBc with proper calibration.

[0080] As described above, according to Figure 5 The V2D converter 210 in this example controls the common-mode voltage V by controlling the boost capacitors applied at the intermediate output nodes INTP and INTM. CM_INT This control can calibrate the nonlinear compensation applied by the constant current discharge stage 320 to improve the linearity of the V2D stage 210. As described above, other parameters can be calibrated to control the coefficients of the square term of the quadratic gain characteristic of equation (3) for the constant current discharge stage 320. Figure 7 A constant current discharge stage 730 is shown as an example of such calibration according to an alternative parameter. This alternative parameter is the source resistance R associated with the current source transistor 406.

[0081] Figure 7 The example of the constant current discharge stage 230 shown includes a set of switches 710 associated with a set of resistors 715. At circuit ground, each switch 710 and its associated resistor 715 are coupled in series between the drain and source of the current source transistor 406. Figure 7 A network of three series-connected switches 710 and resistors 715 coupled in parallel is shown. However, more or fewer switch and resistor networks can be implemented. Resistors 715 can have different resistances, such as binary weighted, or they can have the same resistance value.

[0082] The decoder and timing logic 730 has an input that receives the calibration word CAL and a clock input that receives the clock signal CLK_BOOST, as previously described. The decoder and timing logic 730 has outputs coupled to the inputs of a boost driver 725, which has outputs coupled to the baseboard of boost capacitors 420pF and 420mF. Additionally, the decoder and timing logic 730 also has outputs coupled to the control inputs of each switch 710.

[0083] In operation, the decoder and timing logic 730 receive a calibration word CAL, for example, from calibration logic 340. In response to the value of the calibration word CAL, the decoder and timing logic 730 issue control signals to each switch 710. These control signals operate the corresponding switch in the switches 710 to connect its associated resistor 715 in parallel with the source / drain path of the current source transistor 406, or to disconnect the associated resistor from the parallel connection of the source / drain path. The total source resistance R of the current source implemented by transistor 406 is the on-resistance R of transistor 406 itself, connected in parallel with one or more of the resistors 715 associated with the closed switch 710. on Determined. As described above with respect to equations (3) to (5), this can be achieved by using... Figure 7 The example is adjusting the source resistor R to control the gain of the constant current discharge stage 320 with respect to the quadratic coefficient B2 in the quadratic expression of the input voltage.

[0084] In this example, such as Figure 7 As shown, the decoder and timing logic 730 can be used to drive the boost driver 725 in response to the clock signal CLK_BOOST. In this example, only a single instance of boost capacitors 420P and 420M needs to be implemented, through calibration of the source resistor R by switch 710 and resistor 715. The driving of the baseboard of boost capacitors 420P and 420M by boost driver 725 reduces the common-mode voltage V. CM_INT The discharge helps keep the circuit transistors in a saturated state.

[0085] Figure 8 An example of a portion 330P of a pulse generator 330 coupled between an input at an intermediate output node INTP and an output at an output terminal OUTP is shown. In this example, the pulse generator 330 also includes a portion 330M with a similar configuration having an input at an intermediate output node INTM and an output at an output terminal OUTM.

[0086] like Figure 8 As shown, pulse generator section 330P includes inverters 432P, 434P, and 436P. Inverter 432P includes a PMOS transistor 840 and an NMOS transistor 842. Inverter 434P includes a PMOS transistor 850 and an NMOS transistor 852. Inverter 436P includes a PMOS transistor 860 and an NMOS transistor 862. In this example, pulse generator section 330P includes a set of switches 820 associated with a set of capacitors 825. At node B, each switch 820 and its associated capacitor 825 are coupled in series between the intermediate output node INTP and the output of inverter 434P. Figure 8A network of three series-connected switches 820 and capacitors 825 coupled in parallel is shown. However, fewer or more switch and capacitor networks can be implemented. The capacitors 825 may have different capacitances, such as binary weighted, or they may have the same capacitance. Each switch 820 has a control input coupled to a corresponding output of the decoder and timing logic 830 so that it can be controlled independently.

[0087] The PMOS transistor 840 in inverter 432P is coupled to the supply voltage V. dd The source of the inverter 434P is coupled to the drain of the NMOS transistor 842 at the output node A, and the gate of the NMOS transistor 842 is coupled to the gate of the NMOS transistor 842 at the intermediate output node INTP. The drain of the NMOS transistor 842 is located at circuit ground. The PMOS transistor 850 in the inverter 434P is coupled to the power supply voltage V. dd The source of the NMOS transistor 852 is coupled to the drain of the NMOS transistor 852 at output node B. The source of the NMOS transistor 852 is at circuit ground. The gate of the NMOS transistor 852 is coupled to the output of the inverter 432P at node A, and the gate of the PMOS transistor 850 receives the clock signal CLK_PULSE_RESET from the clock circuit system 440. The PMOS transistor 860 in the inverter 436P has a connection to the power supply voltage V. dd The source of the NMOS transistor 862 is coupled to the drain of the NMOS transistor 862 at the output terminal OUTP, and the gate of the NMOS transistor 862 is coupled to the gate of the NMOS transistor 862 at the output node B from the inverter 434P. The drain of the NMOS transistor 862 is located at circuit ground.

[0088] During operation, the pulse generator section 330P is reset by driving the clock signal CLK_PULSE_RESET to a low logic level via the clock circuit system 440, for example, during the V2V phase of the conversion cycle of the V2D converter 210. Figure 4B The low level of the clock signal CLK_PULSE_RESET turns on the PMOS transistor 850 of inverter 434P and forces the output node B to the power supply voltage V. dd The inverter 436P then drives the output terminal OUTP to a low logic level. During the reset phase of the conversion cycle ( Figure 4B The intermediate output node INTP is pre-charged to the supply voltage V. dd This causes output node A to be pulled to ground by NMOS transistor 842.

[0089] When intermediate output nodes INTP and INTM discharge during the conversion cycle, the nodes that first discharge to the input threshold voltage of inverters 432P and 432M (depending on the specific case) will cause the inverter to change state. However, the transition at the inverter's output can be coupled back to its corresponding input. For example, refer to... Figure 8 The low-to-high transition at output node A of the pulse generator section 330P and inverter 432P can be coupled back to the inverter input at the intermediate output node INTP as a positive noise pulse. This noise, attributed to the coupling at pulse generator 330, has been observed to degrade the linearity of the V2D converter 210.

[0090] supply Figure 8 In this example, the "recoil" capacitor 825 is used to eliminate the noise caused by the switching of inverter 432P. The decoder and timing logic 830 closes one or more of the switches 820, which in turn couples one or more of the corresponding capacitors 825 between the intermediate output node INTP and the output node B of inverter 434P. Because inverter 434P makes a transition opposite to that made by inverter 432P, a high-to-low transition occurs at output node B in response to a low-to-high transition at output node A. By coupling one or more capacitors 825 between the intermediate output node INTP and output node B, this high-to-low transition at output node B is coupled back to the intermediate output node INTP, thus providing a noise pulse of opposite polarity to that caused by the transition of inverter 432P. Therefore, this example improves the linearity of the V2D converter 210.

[0091] The capacitive coupling of the recoil capacitor 825 can be calibrated, for example, by generating a corresponding calibration word CAL2 for the decoder and timing logic 830 via calibration logic 340. Figure 8 As shown in the diagram. This calibration can be performed periodically during normal operation of the V2D converter 210 or alternatively (or additionally) during calibration routines (e.g., during power-on reset).

[0092] Figure 9 An exemplary method for converting an input voltage into a delay domain signal is shown, which may be performed by an ADC 200 including a T2D converter 210. The following description of this exemplary method refers to the above description relative to... Figure 4A And specific components of the ADC 200 and T2D converter 210 described below.

[0093] Figure 9 An exemplary method shows the input voltage V in A conversion of a sample, for example, can be performed by an ADC 200 in a manner that includes relative to... Figure 4BThe aforementioned operations are performed within a conversion loop. For example, for additional samples at a selected sampling or data rate corresponding to the incoming communication bitstream or data stream. Figure 9 The operation of the exemplary method can continue by repeating this exemplary method in the loop.

[0094] Figure 9 The conversion cycle operation begins at process block 900, where the top plates of integrating capacitors 404P and 404M are charged to, for example, the supply voltage V. dd Location or vicinity. (Reference) Figure 4A and 4B Process block 900 is executed by reset transistors 402P, 402M, and 402B, which are turned on by the clock signal CLK_RST from clock circuit system 440. During this process block 900, the top plates of integrating capacitors 404P and 404M, as well as boost capacitors 420P and 420M, are directed towards the power supply voltage V via reset transistors 402P, 402M, and 402B. dd Charge.

[0095] In process block 902, a differential input voltage V is applied at input terminals INP and INM. in The clock circuit system 440 also turns off reset transistors 402P, 402M, and 402B, and turns on transistors 408P and 408M. This allows input transistors 412P and 412M to operate according to the differential input voltage V at input terminals INP and INM. in The top plates of integrating capacitors 404P and 404M are discharged differentially toward circuit ground. The differential voltage at intermediate output nodes INTP and INTM is presented as the result. Process block 902 corresponds to... Figure 4B The V2V phase of the transition cycle.

[0096] In process block 904, the constant current discharge stage 320 of the V2D converter 210 discharges the base plate of the integrating capacitors 404P and 404M toward circuit ground via transistor 405 and current source transistor 406. In this example, process block 904 is initiated by the clock signal CLK_V2D from the clock circuit system 440 of the turn-on transistor 405, thus initiating the above relative to... Figure 4B The V2D phase of the described conversion cycle. In process block 904, the total discharge current from the base plates of integrating capacitors 404P and 404M is controlled by current source transistor 406 in response to an regulated voltage NBIAS_V2D applied to its gate. By controlling the conduction of current source transistor 406 by the regulated voltage NBIAS_V2D, this total discharge current can be maintained as a function of the differential input voltage V. in The changes are largely constant.

[0097] During the operation of process block 904 in the V2D stage, a drive signal CLK_BOOST can also be applied to the input of boost driver 425 to control the common-mode voltage V at intermediate output nodes INTP and INTM. CM_INT As described above. The signal CLK_BOOST can be initiated by clock circuitry 440 during the V2V phase (e.g., during process block 902), as described above relative to... Figure 4B As described.

[0098] In process block 904, the constant current discharge from the base plates of integrating capacitors 404P and 404M continues to discharge the voltages at intermediate output nodes INTP and INTM toward circuit ground, while maintaining the differential voltage across these nodes. When the voltages at intermediate output nodes INTP and INTM discharge to the input threshold voltages of inverters 432P and 432M, respectively, process block 906 is executed by generating a corresponding pair of pulses (e.g., a low-to-high logic level transition) at output terminals OUTP and OUTM via pulse generator 330. The relative delay ΔT between the leading edges of the pulses at output terminals OUTP and OUTM corresponds to the polarity and magnitude of the differential input voltage applied at input terminals INTP and INTM.

[0099] In process block 908, TDC converter 220 outputs D out The process generates digital output words corresponding to the relative delay ΔT of the pulses generated at the output terminals OUTP and OUTM as described in process block 906. The manner in which the delay in these pulses is converted into digital output words depends on the specific construction and arrangement of the TDC converter 220. Examples of architectures that can be used in the TDC converter 220 are described in the U.S. Patent and Publication incorporated above.

[0100] As described above, the constant current discharge stage 320 can be calibrated for operation in process block 904 based on a gain characteristic that has nonlinear behavior that is opposite to and thus compensates for the nonlinearity of the gain characteristic of the dynamic amplifier input stage 310. In the example described above, this calibration involves adjusting the common-mode voltage V that includes intermediate output nodes INTP and INTM. CM_INT Parameters such as the source resistance R of the constant current discharge current source. Adjusting one or more of these parameters adjusts the square term coefficient in the secondary gain characteristic of the constant current discharge stage 320 to match the characteristics of the dynamic amplifier input stage 310, but with the opposite sign. This calibration can be performed at manufacturing, during power-on, or in other reset routines, or periodically during normal operation of the ADC 200. In any case, this calibration of the gain of the constant current discharge stage 320... Figure 9 The exemplary method begins at process block 910.

[0101] In process block 910, pulses at output terminals OUTP and OUTM are applied to the input of calibration logic 340. In this example, process block 910 includes measurement circuit 602 measuring the duty cycle of the pulses at output terminals OUTP and OUTM to generate analog values ​​at their outputs DCP and DCM. ADC 604 converts these analog levels into digital values ​​and forwards those digital values ​​to linearity correction circuit 606. Furthermore, in process block 910, linearity correction circuit 606 responds to input values ​​(e.g., the differential input voltage V forwarded to ADC 604). in The calibration word CAL is generated from the digitized duty cycle value (or from the stored reference value of the programmed calibration routine).

[0102] As pointed out above, it is possible to Figure 9 The calibration is performed using one or more various parameters shown in process frames 912A, 912B, and 912C. (This is in contrast to the previous text.) Figure 5 In the process block 912A corresponding to the described example, the calibration word CAL is used to select one or more boost capacitors 520PA, 520PB, and 520C, and one or more boost capacitors 520MA, 520MB, and 520MC to be driven by the corresponding boost drivers 525A, 525B, and 525C, and thus adjust the common-mode voltage V. CM_INT In contrast to the above... Figure 7 In the process block 912B corresponding to the described example, the calibration word CAL is used to close one or more of the switches 710 to include one or more of the corresponding resistors 715 into the effective source resistance R of the current source transistor 406 in the constant current discharge stage 720.

[0103] Additionally, process block 912C may be executed, for example, in response to the same or different calibration word CAL2 generated in process block 910. Executing process block 912C closes one or more of the switches 820, with one or more corresponding capacitors 825 serving as "recoil" capacitors at pulse generator 330, as described above. Figure 8 As described in the examples.

[0104] After performing one or more of the calibration process blocks 912A, 912B, and 912C, the operation of the V2D converter 210 may continue, for example, from the operation of the constant current discharge stage 320 in process block 904.

[0105] One or more exemplary technical advantages can be achieved based on the described examples. Using a boost capacitor at the constant current discharge stage helps maintain the input stage transistors in saturation and control the output common-mode voltage. Improved noise performance, reduced sensitivity to input transistor mismatch, and improved current source margin can be achieved. Calibration of the constant current discharge block improves the linearity of the T2D stage by providing gain characteristics that eliminate nonlinearity in the input stage and providing good linearity in variations in process, voltage, and temperature.

[0106] One or more examples described in this specification are implemented in delay-domain analog-to-digital converters because such implementations are considered particularly advantageous in the stated context. However, it is also considered that aspects of these examples can be advantageously applied to other applications operating in the delay domain. Therefore, it should be understood that the following description is provided by way of example only and is not intended to limit the true scope of the claimed invention.

[0107] As used herein, the terms “terminal,” “node,” “interconnect,” and “pin” are used interchangeably. Unless otherwise stated, these terms are generally used to refer to interconnects or their terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0108] Unless otherwise stated, “about,” “approximately,” or “generally” preceding a value means + / - 10% of the stated value. Modifications are possible in the described instances, and other instances are possible within the scope of the claims.

[0109] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. The configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0110] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party. While in some exemplary embodiments certain elements are included in an integrated circuit and others are outside the integrated circuit, in other exemplary embodiments additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as outside the integrated circuit may be included in the integrated circuit, and / or some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0111] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the illustrated resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. Components shown as switches may be implemented as a single transistor controlled by a gate voltage, a parallel-coupled complementary transistor controlled by a complementary gate voltage, or a through-gate controlled by other means and circuits suitable for the relevant manufacturing techniques.

[0112] The use of the phrase “grounding” in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding and / or any other form of grounding connection applicable to or suited to the teachings of this specification.

[0113] In the described examples, modifications are possible, and other examples are possible within the scope of the claims.

Claims

1. A voltage-delay converter circuit, comprising: A first reset transistor has a first terminal coupled to a power supply terminal and a gate terminal coupled to receive a reset signal. A first integrating capacitor having a first terminal coupled to the second terminal of the first reset transistor and having a second terminal; The second reset transistor has a first terminal coupled to the power supply terminal and a gate terminal coupled to receive the reset signal. The second integrating capacitor has a first terminal coupled to the second terminal of the second reset transistor and has a second terminal; A first current source having a first terminal coupled to a common potential; The first input transistor has a first terminal coupled to a second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage. The second input transistor has a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive the second input voltage. A discharge current source having a first terminal coupled to a second terminal of each of the first integrating capacitor and the second integrating capacitor, and a second terminal coupled to the common potential; as well as A pulse generator having a first input coupled to the first terminal of the first integrating capacitor, a second input coupled to the first terminal of the second integrating capacitor, and a first output and a second output.

2. The converter circuit according to claim 1, further comprising: A first boost capacitor has a first terminal coupled to the first terminal of the first integrating capacitor, and a second terminal; The second boost capacitor has a first terminal coupled to the first terminal of the second integrating capacitor, and has a second terminal; as well as A boost driver having an output coupled to the second terminal of each of the first boost capacitor and the second boost capacitor.

3. The converter circuit of claim 2, wherein the boost driver has an input coupled to receive a boost clock signal; Furthermore, the converter circuit further includes: A clock circuit system used to generate the boost clock signal.

4. The converter circuit of claim 2, wherein the first boost capacitor is one of a first plurality of boost capacitors, each of the first plurality of boost capacitors having a first terminal coupled to the first terminal of the first integrating capacitor and having a second terminal; The second boost capacitor is one of a second plurality of boost capacitors, each of the second plurality of boost capacitors having a first terminal coupled to the first terminal of the second integrating capacitor, and having a second terminal; The boost driver is one of a plurality of boost drivers, each of the plurality of boost drivers having an output coupled to a second terminal of one of the first plurality of boost capacitors and one of the second plurality of boost capacitors; Furthermore, the converter circuit further includes: The decoder and timing logic have multiple outputs, each coupled to an input of one of the plurality of boost drivers, a clock input coupled to receive a boost clock signal, and a digital input coupled to receive a calibration signal.

5. The converter circuit according to claim 4, further comprising: The calibration logic has one or more outputs coupled to the digital inputs of the decoder and timing logic, and the calibration logic is configured to generate the calibration signal in response to pulses at the first and second outputs of the pulse generator.

6. The converter circuit according to claim 1, further comprising: Multiple resistors; Multiple switches, each switch being coupled in series with one of the multiple resistors across the first and second terminals of the discharge current source, each switch having a control terminal; as well as The decoder and timing logic have multiple outputs, each coupled to a control terminal of one of the plurality of switches, and digital inputs coupled to receive calibration signals.

7. The converter circuit according to claim 1, wherein the pulse generator comprises: The first series of inverters has an input coupled to the first terminal of the first integrating capacitor; Furthermore, the converter circuit further includes: The first multiple recoil capacitors; A plurality of first switches, each having a control terminal, are coupled in series with one of the first plurality of recoil capacitors between a first terminal of the first integrating capacitor and the output of one of the first series of inverters of the pulse generator; and each switch has a control terminal. The decoder and timing logic have multiple outputs, each coupled to a control terminal of one of the first plurality of switches, and digital inputs coupled to receive calibration signals.

8. The converter circuit according to claim 1, wherein the pulse generator further comprises: The second series of inverters has an input coupled to the first terminal of the second integrating capacitor; Furthermore, the converter circuit further includes: The second set of multiple recoil capacitors; as well as The second plurality of switches, each having a control terminal, are coupled in series with one of the second plurality of recoil capacitors between the first terminal of the second integrating capacitor and the output of one of the second series of inverters of the pulse generator. The decoder and timing logic have multiple outputs, each output being coupled to a control terminal of one of the second plurality of switches.

9. The converter circuit according to claim 1, further comprising: A first clock transistor has a first terminal coupled to the first terminal of the first integrating capacitor, a second terminal coupled to the first terminal of the first input transistor, and a gate terminal coupled to receive a first clock signal. The second clock transistor has a first terminal coupled to the first terminal of the second integrating capacitor, a second terminal coupled to the first terminal of the second input transistor, and a gate terminal coupled to receive the first clock signal. A third clock transistor has a first terminal and a second terminal coupled in series with the first current source between the first terminal of the first input transistor and the second input transistor and the common potential, and has a gate terminal coupled to receive a second clock signal. A clock circuit system for generating the first clock signal, the second clock signal, and the reset signal.

10. The converter circuit according to claim 9, further comprising: A fourth clock transistor has a first terminal coupled to the second terminals of the first integrating capacitor and the second integrating capacitor, a second terminal coupled to the discharge current source, and a gate terminal coupled to receive a third clock signal. The clock circuit system is also used to generate the third clock signal.

11. A method comprising: Charge the first plate of each of the first and second integrating capacitors to a first voltage. A differential voltage is applied across a first input and a second input, the first input being coupled to the gate terminal of a first transistor coupled between the first plate of the first integrating capacitor and a reference potential, and the second input being coupled to the gate terminal of a second transistor coupled between the first plate of the second integrating capacitor and the reference potential. Discharge the second plate of each of the first and second integrating capacitors toward the reference potential; as well as Then, a first pulse and a second pulse with relative delays corresponding to the voltages at the first plates of the first and second integrating capacitors are generated; as well as A digital output word is generated corresponding to the relative delay of the first pulse and the second pulse.

12. The method of claim 11, further comprising: During the discharge, a boost voltage is applied to the second plate of each of the first boost capacitor and the second boost capacitor, each having a first plate that is respectively coupled to the first plate of the first integrating capacitor and the second integrating capacitor.

13. The method of claim 12, wherein the first boost capacitor is one of a first plurality of boost capacitors, each of the first plurality of boost capacitors having a first plate coupled to the first plate of the first integrating capacitor; The second boost capacitor is one of a second plurality of boost capacitors, each of the second plurality of boost capacitors having a first plate coupled to the first plate of the second integrating capacitor; And wherein the application of the boost voltage is to apply the boost voltage to one or more selected boost capacitors of each of the first plurality of boost capacitors and the second plurality of boost capacitors; The method further includes: A calibration signal is generated in response to the relative delay between the first pulse and the second pulse; as well as In response to the calibration signal, one or more boost capacitors are selected from each of the first plurality of boost capacitors and the second plurality of boost capacitors.

14. The method of claim 11, further comprising during the discharge: A calibration signal is generated in response to the relative delay between the first pulse and the second pulse; In response to the calibration signal, one or more of each of the first plurality of recoil capacitors and the second plurality of recoil capacitors are selected; Couple one of the first plurality of recoil capacitors to the first plate of the first integrating capacitor; as well as The selected one of the second plurality of recoil capacitors is coupled to the first plate of the second integrating capacitor.

15. The method of claim 11, wherein the discharge comprises discharging the second plate of the first integrating capacitor and the second integrating capacitor through a discharge current source; The method further includes: A calibration signal is generated in response to the relative delay between the first pulse and the second pulse; as well as In response to the calibration signal, one or more resistors are selected for coupling across the first and second terminals of the discharge current source.

16. An analog-to-digital converter, comprising: Voltage-delay converter, comprising: A first reset transistor has a first terminal coupled to a power supply terminal and a gate terminal coupled to receive a reset signal. A first integrating capacitor having a first terminal coupled to the second terminal of the first reset transistor and having a second terminal; The second reset transistor has a first terminal coupled to the power supply terminal and a gate terminal coupled to receive the reset signal. The second integrating capacitor has a first terminal coupled to the second terminal of the second reset transistor and has a second terminal; A first current source having a first terminal coupled to a common potential; The first input transistor has a first terminal coupled to a second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage. The second input transistor has a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive the second input voltage. A discharge current source having a first terminal coupled to a second terminal of each of the first integrating capacitor and the second integrating capacitor, and a second terminal coupled to the common potential; and A pulse generator having a first input coupled to a first terminal of a first integrating capacitor, a second input coupled to a first terminal of a second integrating capacitor, and a first output and a second output; and A delay-to-digital converter having a first input and a second input respectively coupled to a first output and a second output of the pulse generator and having a digital output, the delay-to-digital converter being configured to generate a digital output word corresponding to a relative delay between pulses at the first output and the second output of the pulse generator.

17. The analog-to-digital converter of claim 16, wherein the voltage-delay converter further comprises: The first plurality of boost capacitors, each having a first terminal coupled to the first terminal of the first integrating capacitor, and having a second terminal; The second plurality of boost capacitors each have a first terminal coupled to the first terminal of the second integrating capacitor and have a second terminal; A plurality of boost drivers, each having an output coupled to a second terminal of one of the first plurality of boost capacitors and one of the second plurality of boost capacitors; as well as The decoder and timing logic have multiple outputs, each coupled to an input of one of the plurality of boost drivers, a clock input coupled to receive a boost clock signal, and a digital input coupled to receive a calibration signal.

18. The analog-to-digital converter of claim 16, wherein the voltage-delay converter further comprises: A first boost capacitor has a first terminal coupled to the first terminal of the first integrating capacitor, and a second terminal; The second boost capacitor has a first terminal coupled to the first terminal of the second integrating capacitor, and has a second terminal; as well as A boost driver having an output coupled to the second terminal of each of the first boost capacitor and the second boost capacitor.

19. The analog-to-digital converter of claim 18, wherein the voltage-delay converter further comprises: Multiple resistors; Multiple switches, each switch being coupled in series with one of the multiple resistors across the first and second terminals of the discharge current source, each switch having a control terminal; as well as The decoder and timing logic have multiple outputs, each coupled to a control terminal of one of the plurality of switches, and digital inputs coupled to receive calibration signals.

20. The analog-to-digital converter of claim 16, wherein the pulse generator comprises: The first series of inverters has an input coupled to the first terminal of the first integrating capacitor; as well as The second series of inverters has an input coupled to the first terminal of the second integrating capacitor; And the voltage-delay converter further includes: The first multiple recoil capacitors; A plurality of first switches, each having a control terminal, are coupled in series with one of the first plurality of recoil capacitors between a first terminal of the first integrating capacitor and the output of one of the first series of inverters of the pulse generator; and each switch has a control terminal. The second set of multiple recoil capacitors; and The second plurality of switches, each having a control terminal, are coupled in series with one of the second plurality of recoil capacitors between the first terminal of the second integrating capacitor and the output of one of the second series of inverters of the pulse generator. The decoder and timing logic have multiple outputs, each coupled to a control terminal of one of the first plurality of switches and the second plurality of switches, and digital inputs coupled to receive calibration signals.

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