Photoelectric detection device and electronic equipment

Abstract

According to the invention, the image quality performance is improved. The photodetection device includes: a semiconductor layer having a first surface portion and a second surface portion on opposite sides to each other in one direction; a photoelectric conversion region provided in the semiconductor layer adjacent to the isolation region in plan view, the photoelectric conversion region having a rectangular planar shape; a photoelectric conversion unit provided in the photoelectric conversion region; and a transfer transistor that is provided in the photoelectric conversion region and transfers the signal charge obtained by photoelectric conversion by the photoelectric conversion unit to a charge holding unit. The charge holding portion is provided in the isolation region so as to span a center line that is orthogonal to an outer peripheral edge portion connecting both corner portions of the photoelectric conversion region in a plan view and passes through a center portion of the photoelectric conversion region.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to photoelectric detection devices and electronic devices, and in particular, to effective technologies applicable to photoelectric detection devices comprising a transfer transistor that transfers signal charge from a photoelectric conversion unit to a charge holding unit, and to electronic devices having such photoelectric detection devices. Background Technology

[0002] Photoelectric detection devices, such as solid-state imaging devices or rangefinders, include a photoelectric conversion unit, a transfer transistor, and a charge retention unit in each pixel. Patent Document 1 discloses a technique in which the photoelectric conversion unit and the transfer transistor are disposed in the photoelectric conversion region, and the charge retention unit is disposed in an isolation region surrounding the photoelectric conversion region. Existing technical documents Patent documents

[0003] Patent Document 1: WO 2021 / 193915 Summary of the Invention The problem the invention aims to solve

[0004] In recent years, the market demand for high-resolution image sensors has been growing, and pixel miniaturization is constantly being pursued to improve resolution. With pixel miniaturization, the distance between the transmission transistor and the charge holding unit has become too close, exacerbating concerns about white spot problems. Therefore, as in Patent Document 1, a common arrangement is to place the transmission transistor and the charge holding unit diagonally from the center of the photoelectric conversion region in a planar view to ensure the appropriate distance between them.

[0005] However, this oblique arrangement results in a longer distance from the center of the photoelectric conversion region to the charge holding region, which affects the signal charge transmission characteristics in terms of ensuring the transmission electric field and barrier control, and ultimately leads to a decrease in the image quality performance of the image sensor.

[0006] Therefore, the purpose of this technology is to provide a technique that can improve image quality performance. Solution to the problem

[0007] (1) One aspect of the photoelectric detection device of this technology includes: A semiconductor layer comprising a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed adjacent to an isolation region in the semiconductor layer in a planar view, and the planar shape of the photoelectric conversion region is formed as square; A photoelectric conversion unit, disposed in the photoelectric conversion region; and A transmission transistor is disposed in the photoelectric conversion region and transmits the signal charge generated by the photoelectric conversion unit to the charge holding unit. In addition, the charge holding portion is disposed in the isolation region in such a way that it crosses a center line that is orthogonal to the outer periphery of the two corners of the photoelectric conversion region in the plan view and passes through the center of the photoelectric conversion region.

[0008] (2) Another aspect of the photoelectric detection device of this technology includes: A semiconductor layer comprising a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion unit is disposed adjacent to an isolation region in the semiconductor layer in a planar view, and the photoelectric conversion unit includes two photoelectric conversion regions whose planar shape is formed into a square. A photoelectric conversion unit is disposed in each of the two photoelectric conversion regions; and A transmission transistor is disposed on the first face side of the semiconductor layer in each of the two photoelectric conversion regions, and the transmission transistor transmits the signal charge generated by the photoelectric conversion by the photoelectric conversion unit to the charge holding unit. In addition, the charge holding portion is disposed in the isolation region in such a way that it crosses a center line that is orthogonal to the outer periphery of the two corners of the photoelectric conversion region in the plan view and passes through the center of the photoelectric conversion region. (3) Another aspect of the photoelectric detection device of this technology includes: A semiconductor layer comprising a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed adjacent to an isolation region in the semiconductor layer in a planar view, and the planar shape of the photoelectric conversion region is formed as square; A photoelectric conversion unit, disposed in the photoelectric conversion region; and Multiple transmission transistors are disposed in the photoelectric conversion region and transmit the signal charge generated by the photoelectric conversion unit to the charge holding unit. Furthermore, the charge holding portion is disposed adjacent to the corner of the photoelectric conversion region in the isolation region in the plan view, and The gate electrodes of each of the plurality of transmission transistors are arranged along a direction intersecting a diagonal line extending inward from the corner of the charge holding portion side of the photoelectric conversion region.

[0009] (4) Another aspect of the electronic device of the present technology includes: The photoelectric detection device; An optical lens that forms an image of the image light from the subject on the imaging surface of the photoelectric detection device; and The signal processing circuit processes the signal output from the photoelectric detection device. Attached Figure Description

[0010] Figure 1 This is a chip layout diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. Figure 3 This is an equivalent circuit diagram illustrating a construction example of a pixel and pixel circuit according to a first embodiment of the present technology. Figure 4 It is shown schematically. Figure 1 A plan view illustrating an example of the construction of pixel blocks contained in a pixel array section. Figure 5 It is shown schematically. Figure 4 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 6A It is a schematic diagram showing along Figure 5 The longitudinal section diagram of the longitudinal section structure is taken from line a5-a5. Figure 6B It is a schematic diagram showing along Figure 5 The longitudinal section diagram of the longitudinal section structure is taken from line b5-b5. Figure 7A It is a schematic plan view showing the center line and diagonal of the photoelectric conversion region. Figure 7B It is a schematic plan view showing the center line of the photoelectric conversion region and the charge transport path. Figure 8 This is a schematic plan view of a pixel of a variation 1-1 according to the first embodiment of the present technology. Figure 9A This is a schematic plan view of a pixel of a variation 1-2 of the first embodiment of the present technology. Figure 9B It is a schematic diagram showing along Figure 9A The longitudinal section diagram of the longitudinal section structure is taken from line a9-a9. Figure 10 This is a plan view schematically showing one pixel of variations 1-3 of the first embodiment of the present technology. Figure 11 This is a plan view schematically showing one pixel of variations 1-4 of the first embodiment of the present technology. Figure 12 This is a plan view schematically showing a pixel of a variation of the first embodiment of the present technology, 1-5. Figure 13 This is a schematic plan view of a pixel block comprising four pixels, according to variations 1-6 of the first embodiment of the present technology. Figure 14A This is a schematic plan view of a pixel block according to variations 1-7 of the first embodiment of the present technology. Figure 14B It is a schematic diagram showing along Figure 14A The longitudinal section diagram of the longitudinal section structure is taken from line a14-a14. Figure 15A This is a plan view schematically showing a pixel of a variation of the first embodiment of the present technology, 1-8. Figure 15B It is a schematic diagram showing along Figure 15A The longitudinal section diagram of the longitudinal section structure is taken from line a15-a15. Figure 16A This is a plan view schematically showing a pixel of a variation of the first embodiment of the present technology, 1-9. Figure 16B It is a schematic diagram showing along Figure 16A The longitudinal section diagram of the longitudinal section structure is taken from line a16-a16. Figure 17A This is a schematic plan view of a pixel of a variation 1-10A according to the first embodiment of the present technology. Figure 17B This is a schematic plan view of a pixel of a variant 1-10B according to the first embodiment of the present technology. Figure 17C This is a schematic plan view illustrating a pixel block comprising four pixels, according to a variation 1-10C of the first embodiment of the present technology. Figure 17D This is a schematic plan view of a pixel block comprising four pixels, according to a variation 1-10D of the first embodiment of the present technology. Figure 18 This is a schematic longitudinal cross-sectional view of the longitudinal cross-sectional structure of a pixel according to a variation 1-11 of the first embodiment of the present technology. Figure 19A This is a plan view schematically illustrating an example of the construction of a pixel in a solid-state imaging device according to a second embodiment of the present technology. Figure 19B It is a schematic diagram showing along Figure 19A The longitudinal section diagram of the longitudinal section structure is taken from line a19-a19. Figure 20A This is an equivalent circuit diagram schematically illustrating an example of the construction of pixels and pixel circuits in a solid-state imaging device according to a third embodiment of the present technology. Figure 20B This is a plan view schematically illustrating an example of the construction of a pixel in a solid-state imaging device according to a third embodiment of the present technology. Figure 20C It is a schematic diagram showing along Figure 20B The longitudinal section diagram of the longitudinal section structure cut by line a20-a20. Figure 21A It is a schematic plan view showing the center line and diagonal of the photoelectric conversion region. Figure 21B It is a schematic plan view showing the center line of the photoelectric conversion region and the charge transport path. Figure 22 This is a schematic plan view of a pixel of a variation 3-1 according to the third embodiment of the present technology. Figure 23 This is a schematic plan view of a pixel of a variation 3-2 according to the third embodiment of the present technology. Figure 24 This is a schematic plan view of a pixel of a variation 3-3 according to the third embodiment of the present technology. Figure 25 This is a schematic plan view of a pixel of a variation 3-4 of the third embodiment of the present technology. Figure 26 This is a schematic plan view of a pixel of a variation 3-5 according to the third embodiment of the present technology. Figure 27 This is a schematic plan view of a pixel of a variation 3-6 according to the third embodiment of the present technology. Figure 28 This is a schematic plan view of a pixel of a variation 3-7 according to the third embodiment of the present technology. Figure 29 This is a schematic plan view of a pixel of a variation 3-8 of the third embodiment of the present technology. Figure 30 This is a schematic plan view of a pixel of a variation 3-9 of the third embodiment of the present technology. Figure 31A This is a schematic plan view of a pixel block containing four pixels, according to a variation 3-10 of the third embodiment of the present technology. Figure 31B It is shown schematically. Figure 31A A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 32 This is an exploded view schematically illustrating a construction example of a solid-state imaging device according to a fourth embodiment of the present technology. Figure 33 This is an equivalent circuit diagram illustrating an example of the construction of a pixel and pixel circuit according to a fourth embodiment of the present technology. Figure 34 This is an equivalent circuit diagram schematically illustrating an example of the construction of pixels and pixel circuits in a solid-state imaging device according to a fifth embodiment of the present technology. Figure 35 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to a fifth embodiment of the present technology. Figure 36 It is shown schematically. Figure 35 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 37 It is a schematic diagram showing along Figure 37 The longitudinal section diagram of the longitudinal section structure cut by line a36-a36. Figure 38 This is a timing diagram illustrating a first operational example of the pixel circuit and the transmission transistor. Figure 39 This is a timing diagram illustrating a second operational example of the pixel circuit and the transmission transistor. Figure 40A It is a schematic diagram showing along Figure 36 The longitudinal section diagram of the longitudinal section structure taken from the center line. Figure 40B It is a schematic plan view showing the diagonal of the photoelectric conversion region. Figure 41 This is a plan view schematically illustrating an example of the structure of pixels included in the pixel array section of a solid-state imaging device according to a sixth embodiment of the present technology. Figure 42 It is a schematic diagram showing along Figure 41 The longitudinal section diagram of the longitudinal section structure cut by line a41-a41. Figure 43 This is a plan view schematically illustrating an example of the structure of pixels included in the pixel array section of a solid-state imaging device according to a seventh embodiment of the present technology. Figure 44 It is a schematic diagram showing along Figure 43 The longitudinal section diagram of the longitudinal section structure is taken from line a43-a43. Figure 45 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the eighth embodiment of the present technology. Figure 46 It is shown schematically.Figure 45 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 47 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to a ninth embodiment of the present technology. Figure 48 It is shown schematically. Figure 47 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 49 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to a tenth embodiment of the present technology. Figure 50 It is shown schematically. Figure 49 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 51 It is shown Figure 50 A plan view showing the arrangement direction of the gate electrodes in the photoelectric conversion region. Figure 52 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the eleventh embodiment of the present technology. Figure 53 It is shown schematically. Figure 52 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 54 This is a plan view schematically illustrating an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the twelfth embodiment of the present technology. Figure 55 It is shown schematically. Figure 54 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 56 This is a diagram illustrating a schematic configuration of an electronic device according to the thirteenth embodiment of the present technology. Detailed Implementation

[0011] The implementation of this technology will now be described in detail with reference to the accompanying drawings.

[0012] Note that in the accompanying drawings referenced in the following description, identical or similar parts are indicated by identical or similar reference numerals. It should be noted that the drawings are schematic diagrams, and the relationships between thickness and planar dimensions, the thickness ratios between layers, etc., differ from actual conditions. Therefore, specific thicknesses and dimensions should be determined in conjunction with the following description.

[0013] Furthermore, needless to say, the dimensional relationships and proportions differ between the various figures. Also, the effects described in this specification are merely illustrative and not restrictive, and may produce other effects.

[0014] Furthermore, the following embodiments describe examples of apparatus and methods for implementing the technical concept of this technology, and are not intended to limit the configuration to those described below. That is, various modifications can be made to the technical concept of this technology within the scope of the claims.

[0015] Furthermore, the definitions of directions such as up and down in the following description are for descriptive convenience only and are not intended to limit the technical ideas of this technology. For example, it goes without saying that when an object is rotated 90° and then observed, up and down are converted to left and right; when an object is rotated 180° and then observed, up and down are reversed.

[0016] Furthermore, in the following embodiments, among the three directions orthogonal to each other in space, the first and second directions orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, while the third direction orthogonal to the first and second directions is defined as the Z direction. Additionally, in the following embodiments, the thickness direction of the semiconductor layer 21, described later, will be described as the Z direction. Furthermore, in the following embodiments, the Z direction will be described as "a direction" of this technology.

[0017] In addition, in the following embodiments, the thickness of the semiconductor layer 21 is the separation distance between the first face S1 and the second face S2 located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 is the direction representing the thickness of the semiconductor layer 21.

[0018] Additionally, in the following embodiments, a plan view refers to the view of the semiconductor layer 21 from the Z direction (one direction). A cross-sectional view refers to the view of the cross-section from a direction orthogonal to the cross-section taken along the Z direction (one direction).

[0019] [First Implementation Method] In the first embodiment, an example of the application of this technology as a photoelectric detection device to a solid-state imaging device will be described, wherein the solid-state imaging device is a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor. Furthermore, in the first embodiment, a transmission transistor having a vertical structure will be described as an example of a transmission transistor.

[0020] Overall Structure of Solid State Camera First, the overall structure of the solid-state imaging device 1A will be described. Figure 1 This is a chip layout diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device according to a first embodiment of the present technology. Figure 3 This is an equivalent circuit diagram illustrating a construction example of a pixel and pixel circuit according to a first embodiment of the present technology. Figure 4 It is shown schematically. Figure 1 A plan view illustrating an example of the construction of pixel blocks contained in a pixel array section. Figure 5 It is shown schematically. Figure 4 A planar diagram illustrating the construction example of pixels contained within a pixel block. Figure 6A It is a schematic diagram showing along Figure 5 The longitudinal section diagram of the longitudinal section structure is taken from line a5-a5. Figure 6B It is a schematic diagram showing along Figure 5 The longitudinal section diagram of the longitudinal section structure is taken from line b5-b5.

[0021] Please note that, for easier understanding of the view, in Figures 4-6B The diagrams of the multi-layer wiring system described later are omitted. Furthermore, Figure 1 This is a planar view of semiconductor chip 2 observed from the light incident surface, and Figure 4 and Figure 5 This is a plan view of the semiconductor chip 2 viewed from the opposite side of the light incident surface (the first surface S1 side of the semiconductor layer 21).

[0022] like Figure 1 As shown, the solid-state imaging device 1A according to the first embodiment of this technology mainly includes a semiconductor chip 2 having a square two-dimensional planar shape in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. Figure 56 As shown, the solid-state imaging device 1A (301) captures image light (incident light 306) from the subject through the optical lens 302, converts the amount of light of the incident light 306 that is focused on the imaging surface into an electrical signal in units of pixels, and outputs it as a pixel signal.

[0023] like Figure 1As shown, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a rectangular pixel array portion 2A disposed in its central portion and a peripheral portion 2B disposed around the pixel array portion 2A in a two-dimensional plane containing mutually orthogonal X and Y directions. During the manufacturing process, a semiconductor wafer containing the semiconductor layer 21 described later is cut into small pieces as chip formation regions to form the semiconductor chip 2. Therefore, the structure of the solid-state imaging device 1A described below is substantially similar to the state before the semiconductor wafer is cut into small pieces. In other words, this technology is applicable both as a semiconductor chip and as a semiconductor wafer.

[0024] Pixel array section 2A is, for example, used to receive by Figure 56 The light-receiving surface of the optical lens (optical system) 302 shown is where the light rays are converged. Furthermore, in the pixel array section 2A, a plurality of pixels 3 (sensor pixels) are arranged in a matrix on a two-dimensional plane encompassing the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the X and Y directions, which are orthogonal to each other, in the two-dimensional plane.

[0025] like Figure 1 As shown, a plurality of pads 14 are arranged in the peripheral portion 2B. Each of the plurality of pads 14 is arranged, for example, along one of the four sides of the two-dimensional plane of the semiconductor chip 2. Each of the plurality of pads 14 serves as an input / output terminal for electrically connecting the semiconductor chip 2 to an external device.

[0026] <Logic Circuits> Semiconductor chip 2 includes Figure 2 The logic circuit 13 shown is as follows. Figure 2 As shown, logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc. Logic circuit 13 may include, for example, a complementary metal-oxide-semiconductor (CMOS) circuit, which includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel MOSFET as field-effect transistors.

[0027] Figure 2The vertical driving circuit 4 shown includes, for example, a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving lines 10, supplies pulses for driving the pixels 3 to the selected pixel driving lines 10, and drives the pixels 3 row by row. That is, the vertical driving circuit 4 selectively scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3, representing the signal charges generated by the photoelectric conversion section of each pixel 3 according to the amount of light received, to the corresponding column signal processing circuit 5 via the corresponding vertical signal lines 11.

[0028] The column signal processing circuit 5 is configured for each column of pixels 3, and performs signal processing such as noise removal on the signal output from a row of pixels 3 for each column of pixels. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) for removing pixel-specific fixed-pattern noise and analog-to-digital (AD) conversion.

[0029] Figure 2 The horizontal drive circuit 6 shown includes, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scan pulses to the column signal processing circuit 5 to sequentially select the column signal processing circuit 5 and cause the column signal processing circuit 5 to output the pixel signal obtained after signal processing to the horizontal signal line 12.

[0030] Figure 2 The output circuit 7 shown processes the pixel signals sequentially supplied from the column signal processing circuit 5 via the horizontal signal line 12 and outputs the processed pixel signals. Signal processing methods include, for example, buffering, black level adjustment, inter-column difference correction, and various types of digital signal processing.

[0031] Figure 2 The control circuit 8 shown generates clock and control signals as operating references for the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6.

[0032] <pixel blocks> Semiconductor chip 2 includes Figure 3 The pixel block 15 and the pixel circuit (readout circuit) 16 are shown.

[0033] like Figure 3 and Figure 4 As shown, pixel block 15 comprises a plurality of pixels 3. The pixel block 15 of the first embodiment is not limited to this, but may, for example, comprise four pixels 3 (3a, 3b, 3c, and 3d), which are arranged in a 2×2 configuration of two pixels side-by-side in both the X and Y directions of the planar view as a unit.Figure 3 and Figure 4 The example mainly illustrates a pixel block 15, but pixel block 15 is repeated in both the X and Y directions, thus forming... Figure 1 The pixel array section 2A shown.

[0034] like Figure 3 As shown, each of the four pixels 3a, 3b, 3c, and 3d in a pixel block 15 contains the same components. Specifically, each of the four pixels 3a, 3b, 3c, and 3d in a pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD (which serves as a charge holding unit for holding (accumulating) the signal charge generated by the photoelectric conversion unit 25 through photoelectric conversion), and a transmission transistor TRV (which transmits the signal charge generated by the photoelectric conversion unit 25 through photoelectric conversion to the floating diffusion region FD). Furthermore, each of the four pixels 3a, 3b, 3c, and 3d in a pixel block 15 further includes... Figure 5 , Figure 6A and Figure 6B The photoelectric conversion region (photoelectric conversion unit) 22 of the semiconductor layer 21 is shown. Then, as... Figure 5 , Figure 6A and Figure 6B As shown, each photoelectric conversion unit 25 and transmission transistor TRV are disposed within the photoelectric conversion region 22, while the floating diffusion region FD is disposed within the isolation region 31.

[0035] (Photoelectric conversion unit) Figure 3 Each photoelectric conversion unit 25 shown includes, for example, a pn junction photodiode (PD) and generates signal charge based on the amount of light received. Furthermore, the photoelectric conversion unit 25 temporarily retains (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transmission transistor TRV, and the anode side is electrically connected to a reference potential line (e.g., ground).

[0036] (Transmission transistor) Figure 3 Each transmission transistor (TRV) shown transfers the signal charge generated by the photoelectric conversion unit 25 through photoelectric conversion to the floating diffusion region FD. In the transmission transistor TRV, the source region is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. Furthermore, the gate electrode of the transmission transistor TRV is electrically connected to... Figure 2 The transmission transistor driving line in the pixel driving line 10 shown.

[0037] (Floating diffusion area) Figure 3Each floating diffusion region FD temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion unit 25 via the transmission transistor TRV.

[0038] <Pixel Circuit> like Figure 3 As shown, the input terminal of the pixel circuit 16 is electrically connected to the floating diffusion region FD. The pixel circuit 16 of the first embodiment is provided for each pixel block 15, and is shared by the four pixels 3 (3a, 3b, 3c and 3d) contained in a pixel block 15.

[0039] Here, in the first embodiment, as an example, a circuit configuration is employed in which a pixel circuit 16 is assigned to a pixel block 15 comprising four pixels 3 as a unit. However, the circuit configuration employed is not limited to the configuration in the first embodiment. For example, a circuit configuration in which a pixel circuit 16 is assigned to a pixel block 15 comprising two or more pixels 3 as a unit can be employed, or a circuit configuration in which a pixel circuit 16 is assigned to multiple pixel blocks 15 comprising multiple pixels 3 as a unit can be employed. Alternatively, a circuit configuration in which a pixel circuit 16 is assigned to a single pixel 3 can also be employed.

[0040] Figure 3 The input stage of the pixel circuit 16 shown is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) contained within a pixel block 15. The pixel circuit 16 then reads the signal charge held in the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and outputs a pixel signal based on the read signal charge. In other words, the pixel circuit 16 converts the signal charge generated by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on that signal charge and outputs it.

[0041] like Figure 3As shown, the pixel circuit 16 includes, but is not limited to, the amplifying transistor AMP, the selecting transistor SEL, the reset transistor RST, and the switching transistor FDG, which are pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, and FDG) and the aforementioned transmission transistor TRV are constructed as insulated-gate field-effect transistors, for example, from metal-oxide-semiconductor field-effect transistors (MOSFETs) with a silicon oxide (SiO2) film as the gate insulating film. Alternatively, each of these pixel transistors may also be a metal-insulator-semiconductor FET (MISFET) with a silicon nitride (Si3N4) film or a multilayer film of silicon nitride and silicon oxide films as the gate insulating film.

[0042] In the pixel transistors Q (AMP, SEL, RST, and FDG) included in the pixel circuit 16, the select transistor SEL, the reset transistor RST, and the switching transistor FDG are mainly used as switching elements. In addition, the remaining amplifying transistor AMP is mainly used as an amplifying element.

[0043] Figure 3 The source region of the amplifying transistor AMP is electrically connected to the drain region of the select transistor SEL, and its drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifying transistor AMP is electrically connected to the floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c and 3d) and the source region of the reset transistor RST.

[0044] Figure 3 The source region of the selected transistor SEL is electrically connected to the vertical signal line 11 (VSL), and its drain region is electrically connected to the source region of the amplifying transistor AMP. Furthermore, the gate electrode of the selected transistor SEL is electrically connected to... Figure 3 The selected transistor driving line in the pixel driving line 10 shown.

[0045] Figure 2 The source region of the reset transistor RST is electrically connected to the drain of the switching transistor FDG, and its drain region is electrically connected to the power supply line Vdd and the drain region of the amplifying transistor AMP. Then, the gate electrode of the reset transistor RST is electrically connected to... Figure 3 The reset transistor driving line in the pixel driving line 10 shown.

[0046] Figure 2The drain region of the switching transistor FDG shown is electrically connected to the source region of the reset transistor RST, and this drain region is also electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD of pixel 3. Furthermore, the gate electrode of the switching transistor FDG is electrically connected to... Figure 3 The switching transistor driving line in the pixel driving line 10 shown.

[0047] Please note that the selection transistor SEL and the switching transistor FDG can be omitted if needed. When the select transistor SEL is omitted, the source region of the amplifying transistor AMP is electrically connected to the vertical signal line 11 (VSL). Furthermore, when the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifying transistor AMP and the floating diffusion region FD.

[0048] When the transfer transistor TRV is turned on Figure 2 The transmission transistor TRV shown transmits the signal charge generated by the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0049] When the reset transistor RST is turned on Figure 3 The reset transistor RST shown resets the potential (signal charge) of the floating diffusion region FD to the potential of the power line Vdd. The select transistor SEL controls the output timing of the pixel signal from the pixel circuit 16.

[0050] Figure 3 The amplifying transistor AMP shown generates a signal as a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifying transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs the voltage corresponding to that potential to the column signal processing circuit 5 through the vertical signal line (VSL) 11.

[0051] Figure 3 The switching transistor FDG shown controls the charge retention of the floating diffusion region FD and adjusts the amplification factor of the voltage corresponding to the potential amplified by the amplifying transistor AMP.

[0052] During operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 25 of pixel 3 is held (accumulated) in the floating diffusion region FD by the transfer transistor TRV of pixel 3. Then, the signal charge held in the floating diffusion region FD is read out by pixel circuit 16 and applied to the gate electrode of amplification transistor AMP of pixel circuit 16. The vertical shift register supplies a horizontal row selection control signal to the gate electrode of selection transistor SEL of pixel circuit 16. Setting the selection control signal to a high (H) level turns on the selection transistor SEL, thereby allowing current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP to flow to the vertical signal line 11. In addition, setting the reset control signal applied to the gate electrode of reset transistor RST of pixel circuit 16 to a high (H) level turns on the reset transistor RST, thereby resetting the signal charge accumulated in the floating diffusion region FD.

[0053] Figure 3 The photoelectric conversion unit 25, the transmission transistor TRV, and the floating diffusion region FD shown are all mounted on the semiconductor layer 21 described later (see Figure 3 Furthermore, although not limited to this, for example, Figure 6A The pixel transistors Q (AMP, SEL, RST and FDG) included in the pixel circuit 16 shown are also disposed on the semiconductor layer 21.

[0054] <<Detailed Structure of Solid State Camera Devices>> Next, we will refer to Figure 3 The specific structure of the solid-state imaging device 1A (semiconductor chip 2) is explained. Figures 4-7B It is a schematic plan view showing the center line and diagonal of the photoelectric conversion region. Figure 7A It is a schematic plan view showing the center line of the photoelectric conversion region and the charge transport path.

[0055] like Figure 7B , Figure 5 and Figure 6A As shown, the solid-state imaging device 1A includes a semiconductor layer 21, which has a first facet S1 and a second facet S2 located on opposite sides in a thickness direction (Z direction). Furthermore, the solid-state imaging device 1A also includes a photoelectric conversion region 22 disposed on the semiconductor layer 21. The photoelectric conversion region 22 is adjacent to the isolation region 31 in a planar view and is formed into a rectangular planar shape. The photoelectric conversion region 22 includes a first facet S1 and a second facet S2 of the semiconductor layer 21. Furthermore, the solid-state imaging device 1A also includes: a photoelectric conversion unit 25 disposed in the photoelectric conversion region 22; and a transmission transistor TRV disposed in the photoelectric conversion region 22 and configured to transmit the signal charge obtained by photoelectric conversion by the photoelectric conversion unit 25 to a floating diffusion region FD, which serves as a charge holding unit. As will be described in detail later, the floating diffusion region FD is disposed in the isolation region 31. In addition, the solid-state imaging device 1A also includes a planarization film 61, a filter layer 63 and a lens layer 64, which are sequentially disposed on the second face S2 side of the semiconductor layer 21 from the second face S2 side. In addition, although not shown, the solid-state imaging device 1A also includes a multilayer wiring layer disposed on the first face S1 side of the semiconductor layer 21.

[0056] Here, the first surface S1 of the semiconductor layer 21 is also referred to as the main surface or element forming surface, and the second surface S2 is referred to as the back surface. Furthermore, in the solid-state imaging device 1A according to the first embodiment, the incident light incident from the second surface S2 side of the semiconductor layer 21 is photoelectrically converted in the photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is also referred to as the light incident surface.

[0057] Furthermore, in the first embodiment, the floating diffusion region FD corresponds to a specific example of the "charge holding section" of this technology.

[0058] <Planarization film, filter layer, and lens layer> like Figure 6B and Figure 6A As shown, the planarization film 61 is disposed on the second face S2 side of the semiconductor layer 21 in such a way as to cover the second face S2 side of the semiconductor layer 21, and the second face S2 side of the semiconductor layer 21 is planarized.

[0059] like Figure 6B and Figure 6A As shown, the filter layer 63 is disposed on the side of the planarization film 61 opposite to the semiconductor layer 21 side. The filter layer 63 performs color separation on incident light incident from the light incident surface side (second surface S2 side) of the solid-state imaging device 1A. In addition, for each pixel 3 (for each photoelectric conversion region 22), the filter layer 63 includes, but is not limited to, a filter section 63a that transmits light of a specific wavelength such as red (R), green (G), or blue (B).

[0060] like Figure 6B and Figure 6AAs shown, the lens layer 64 is disposed on the side of the filter layer 63 opposite to the planarization film 61 side. In addition, for each pixel 3 (for each photoelectric conversion region 22), the lens layer 64 includes a microlens (on-chip lens) 64a that converges the illumination light and effectively allows the converged light to enter the photoelectric conversion region 22.

[0061] That is, the pixel 3 in the first embodiment includes a photoelectric conversion region 22 and each of a planarization film 61, a filter portion 63a and a microlens 64 disposed on the second face S2 side of the photoelectric conversion region 22.

[0062] <Semiconductor layer> like Figure 6B As shown, the semiconductor layer 21 is provided with an isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 separated by the isolation region 31. Figure 6A As shown, the photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 can be a Si substrate, a SiGe substrate, an InGaAs substrate, etc. In the first embodiment, although not limited to these, a p-type semiconductor substrate containing monocrystalline silicon, for example, is used as the semiconductor layer 21.

[0063] <Quarantine Area> (Plane shape) like Figure 4 As shown, the isolation region 31 in the plan view includes a first extension 31x extending in the X direction and a second extension 31y extending in the Y direction. Additionally, the isolation region 31 also includes an intersection point 31xy where the first extension 31x and the second extension 31y intersect each other on the same plane. In the first embodiment, the first extension 31x and the second extension 31y are, for example, orthogonal to each other.

[0064] The first extension 31x is arranged repeatedly at predetermined intervals in the Y direction. The second extension 31y is arranged repeatedly at predetermined intervals in the X direction. That is, in the isolation region 31, the planar pattern in the plan view is a grid-like planar pattern.

[0065] like Figure 4 As shown in the plan view, the isolation region 31 corresponding to a photoelectric conversion region 22 has a rectangular annular planar pattern (annular planar pattern) and surrounds the photoelectric conversion region 22. On the other hand, as Figure 5 As shown, the isolation region 31 corresponding to a pixel block 15 is a composite planar pattern having a first extension 31x and a second extension 31y arranged orthogonally to each other in a rectangular annular planar pattern.

[0066] like Figure 4As shown, in the isolation region 31 corresponding to a pixel block 15, the intersection (intersection point) 31xy between the first extension 31x and the second extension 31y is located in the center of the pixel block 15. In addition, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c and 3d) are arranged in a matrix to surround the intersection 31xy.

[0067] (Longitudinal cross-sectional shape) like Figure 4 As shown, the isolation region 31 extends in the thickness direction (Z direction) of the semiconductor layer 21, and in the plan view, there are two photoelectric conversion regions 22 that are electrically isolated and optically isolated adjacent to each other. The isolation region 31 is, for example, a trench type in which a recess 32 is formed in the semiconductor layer 21 to separate and isolate the photoelectric conversion regions 22.

[0068] The isolation region 31 includes, for example, but is not limited to: a recess 32 extending across a first facet S1 and a second facet S2 of the semiconductor layer 21; and an insulating film 33 disposed in the recess 32. That is, the isolation region 31 extends across the first facet S1 and the second facet S2 of the semiconductor layer 21. In the first embodiment, the recess 32 is, for example, filled with the insulating film 33. As the insulating film 33, a silicon oxide film can be used, for example.

[0069] <Photoelectric conversion region> like Figure 6A and Figure 4 As shown, each photoelectric conversion region 22 is surrounded by an isolation region 31 in the plan view and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first extensions 31x that extend in the X direction and are separated from each other in the Y direction, and two second extensions 31y that extend in the Y direction and are separated from each other in the X direction. In addition, the photoelectric conversion region 22 is separated by the first extensions 31x and the second extensions 31y and is isolated from adjacent photoelectric conversion regions 22.

[0070] like Figure 5 As shown, each photoelectric conversion region 22 includes: a p-type well region 23, which spans the semiconductor layer 21 with a first face S1 and a second face S2 disposed in the semiconductor layer 21; and an n-type semiconductor region 24, which has a first face S1 away from the semiconductor layer 21 disposed in the p-type well region 23. In addition, the photoelectric conversion region 22 also includes a photoelectric conversion section 25, which includes a p-type well region 23 and an n-type semiconductor region 24 and is disposed in the semiconductor layer 21 with a first face S1 away from the semiconductor layer 21. In addition, such as Figure 6A and Figure 5As shown, the photoelectric conversion region 22 further includes: a transmission transistor TRV, which transmits the signal charge obtained by photoelectric conversion by the photoelectric conversion unit 25 to the floating diffusion region FD; and a pixel transistor Q included in the pixel circuit 16 described above. Additionally, although not shown, the photoelectric conversion region 22 also includes a power contact region, and further includes...

[0071] Note that in the first embodiment, as will be described in detail later, the n-type floating diffusion region FD is disposed in each of the first extensions 31x of the isolation region 31.

[0072] (p-type well region and n-type semiconductor region) like Figure 6A and Figure 5 As shown, a p-type well region 23 is disposed in the photoelectric conversion region 22, spanning a wide area from the first facet S1 side to the second facet S2 side of the semiconductor layer 21. Furthermore, the p-type well region 23 contacts the isolation region 31 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type well region 23 includes a p-type semiconductor region.

[0073] like Figure 6A and Figure 5 As shown, an n-type semiconductor region 24 is disposed within a p-type well region 23 in the photoelectric conversion region 22. That is, the six faces of the n-type semiconductor region 24, including a top face, a bottom face, and four side faces, are surrounded by the p-type well region 23. Furthermore, the n-type semiconductor region 24 is separated from the first face S1 and the second face S2 of the semiconductor layer 21, as well as the isolation region 31. In other words, the n-type semiconductor region 24 forms a pn junction with the p-type well region 23 at its six faces.

[0074] (Photoelectric conversion unit) like Figure 6A and Figure 4 As shown, a photoelectric conversion unit 25 is disposed in a photoelectric conversion region 22. The photoelectric conversion unit 25 includes a p-type well region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. Furthermore, the photoelectric conversion unit 25 is configured as a pn junction type photodiode (PD) containing a pn junction between the p-type well region 23 and the n-type semiconductor region 24.

[0075] The photoelectric conversion unit 25 converts light incident on the n-type semiconductor region 24 from the second facet S2 side of the semiconductor layer 21 into signal charge in the n-type semiconductor region 24, and temporarily retains (accumulates) the signal charge obtained due to photoelectric conversion in the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The first facet S1 of the photoelectric conversion unit 25 away from the semiconductor layer 21 is provided in the semiconductor layer 21.

[0076] (Pixel transistor) As described above, the photoelectric conversion region 22 of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in a pixel block 15 includes one of the pixel transistors Q included in a pixel circuit 16. In the first embodiment, although not limited thereto, for example, as... Figure 5 As shown, in a pixel block 15 containing four pixels 3 (3a, 3b, 3c and 3d), the photoelectric conversion region 22 of pixel 3a includes an amplifying transistor AMP as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3b includes a selection transistor SEL as a pixel transistor Q, the photoelectric conversion region 22 of pixel 3c includes a switching transistor FDG as a pixel transistor Q, and the photoelectric conversion region 22 of pixel 3d includes a reset transistor RST as a pixel transistor Q.

[0077] like Figure 6B and Figure 5 As shown, the pixel transistor Q included in the pixel circuit 16 includes an amplifying transistor AMP, which includes a gate electrode 54 disposed outside the first facet S1 of the semiconductor layer 21, and a gate insulating film 52 disposed between the gate electrode 54 and the first facet S1 of the semiconductor layer 21. Furthermore, the amplifying transistor AMP includes a pair of main electrode regions 55a and 55b, which are disposed on both sides of the gate electrode 54 in the gate length direction (direction of gate length Lg) in the semiconductor layer 21 and serve as a source region and a drain region; and a channel forming portion disposed between the pair of main electrode regions 55a and 55b.

[0078] Each of the pair of main electrode regions 55a and 55b includes, for example, an n-type semiconductor region disposed in the p-type well region 23. For example, the channel formation includes the p-type well region 23. The gate insulating film 52 includes, for example, a silicon oxide film. The gate electrode 54 includes, for example, a polycrystalline silicon film incorporating impurities to reduce resistance.

[0079] Note that the pixel transistors Q included in the pixel circuit 16, except for the amplifying transistor AMP, each of the select transistor SEL, the switching transistor FDG, and the reset transistor RST has a similar structure to the amplifying transistor AMP, so the description of these pixel transistors Q (SEL, FDG, and RST) is omitted.

[0080] (Power contact area) Although not shown, the power contact region is provided in the p-type well region 23 on the first face S1 side of the semiconductor layer 21, and includes a p-type semiconductor region with a higher impurity concentration than the p-type well region 23. Furthermore, the power contact region is electrically connected to the p-type well region 23.

[0081] During operation of the solid-state imaging device 1A, for example, a first reference potential (Vss potential) of 0V, which serves as the reference potential of the solid-state imaging device 1A, is applied to the power contact area. Furthermore, during operation of the solid-state imaging device 1A, the potential of the power contact area is fixed to the first reference potential.

[0082] (Transmission transistor) like Figure 6A and Figure 5 As shown, the transmission transistor TRV is disposed in the photoelectric conversion region 22 on the first facet S1 side of the semiconductor layer 21. The transmission transistor TRV includes a gate electrode 53 disposed on the first facet S1 side of the semiconductor layer 21 and a gate insulating film 52 disposed between the gate electrode 53 and the semiconductor layer 21. In addition, the transmission transistor TRV also includes a p-type well region 23 serving as a channel formation portion, and an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as source and drain regions.

[0083] like Figure 6A As shown in Figure 6, the gate electrode 53 of the transmission transistor TRV includes: a head 53a disposed outside the first facet S1 of the semiconductor layer 21; and a body 53b protruding from the head 53a into the interior of the semiconductor layer 21 and adjacent to the semiconductor layer 21 via a gate insulating film 52. Although not limited thereto, for example, in the first embodiment, the head 53a of the gate electrode 53 is wider than the body 53b. In other words, in a plan view, the external dimensions of the head 53a are larger than the external dimensions of the body 53b. The planar shape of the head 53a is, for example, rectangular. The planar shape of the body 53b is, for example, octagonal. The transmission transistor TRV is constructed in a vertical configuration.

[0084] Here, in the first embodiment, the main body portion 53b of the gate electrode 53 corresponds to a specific example of the "embedded portion" of this technology.

[0085] like Figure 4 As shown, the main body portion 53b of the gate electrode 53 is disposed in the recessed portion 51 of the semiconductor layer 21 through the gate insulating film 52, and its end reaches the n-type semiconductor region 24. The gate insulating film 52 includes, for example, a silicon oxide film. The gate electrode 53 includes, for example, a polysilicon film incorporating impurities to reduce resistance. The gate electrode 53 can be formed by forming a polysilicon film as a gate material in a cutout 51 provided in the semiconductor layer 21 on the first facet S1 side of the semiconductor layer 21, with the gate insulating film 52 in between, and then patterning the polysilicon film into a predetermined shape.

[0086] Note that the gate electrode 53 can be separated from the n-type semiconductor region 24.

[0087] <Planar pattern of pixels> like Figure 4 As shown, each of the four pixels 3 (3a, 3b, 3c and 3d) contained in a pixel block 15 has a different arrangement pattern of elements including a transmission transistor TRV and a pixel transistor Q in a planar view.

[0088] In the first embodiment, such as Figure 7A As shown, the planar patterns of pixels 3a and 3b arranged in the Y direction are inverted patterns with the boundary between pixels 3a and 3b as the inversion axis. Similarly, the planar patterns of pixels 3c and 3d arranged in the Y direction are inverted patterns with the boundary between pixels 3c and 3d as the inversion axis. Furthermore, the planar patterns of pixels 3a and 3c arranged in the X direction are inverted patterns with the boundary between pixels 3a and 3c as the inversion axis. Additionally, the planar patterns of pixels 3b and 3d arranged in the X direction are inverted patterns with the boundary between pixel 3b and image 3d as the inversion axis.

[0089] <Planar pattern of the photoelectric conversion area> like Figure 7A As shown, the photoelectric conversion region 22 with a rectangular planar shape has four outer peripheral portions 22a1, 22a2, 22a3 and 22a4, four corner portions 22S1, 22S2, 22S3 and 22S4, and two diagonals 22d1 and 22d2 in the plan view.

[0090] like Figure 7A As shown, of the four outer peripheral portions 22a1, 22a2, 22a3, and 22a4, two outer peripheral portions 22a1 and 22a2 extend along the X direction in the plan view and are located on the opposite side of the Y direction. Additionally, the remaining two outer peripheral portions 22a3 and 22a4 extend along the Y direction in the plan view and are located on the opposite side of the X direction.

[0091] like Figure 5 As shown, of the four corner portions 22S1, 22S2, 22S3, and 22S4, two corner portions 22S1 and 22S4 are located on opposite sides of the extension direction of diagonal 22d1 in the plan view. The remaining two corner portions 22S2 and 22S3 are located on opposite sides of the extension direction of diagonal 22d2 in the plan view.

[0092] Of the two diagonals 22d1 and 22d2, one diagonal 22d2 is the line segment connecting the two corners 22S1 and 22S4, and the other diagonal 22d2 is the line segment connecting the two corners 22S2 and 22S3.

[0093] Of the four corner portions 22S1, 22S2, 22S3, and 22S4, at corner 22S1, the two outer peripheral portions 22a1 and 22a3 intersect. At corner 22S2, the two outer peripheral portions 22a1 and 22a4 intersect. At corner 22S3, the two outer peripheral portions 22a2 and 22a3 intersect. At corner 22S4, the two outer peripheral portions 22a2 and 22a4 intersect.

[0094] Of the four outer peripheral portions 22a1, 22a2, 22a3, and 22a4, outer peripheral portion 22a1 is a line segment connecting corner portions 22S1 and 22S2. Outer peripheral portion 22a2 is a line segment connecting corner portions 22S3 and 22S4. Outer peripheral portion 22a3 is a line segment connecting corner portions 22S1 and 22S3. Outer peripheral portion 22a4 is a line segment connecting corner portions 22S2 and 22S4.

[0095] Here, each of the four outer peripheral portions 22a1, 22a2, 22a3, and 22a4 is located at the interface portion Lp between the semiconductor layer 21 and the isolation region 31 in the photoelectric conversion region 22. Therefore, the outer peripheral portions 22a1, 22a2, 22a3, and 22a4 in the planar view can also be referred to as the interface portion Lp.

[0096] <Floating Diffusion Area> like Figure 6A and Figure 6A As shown, the floating diffusion region FD is disposed in the isolation region 31 on the first face S1 side of the semiconductor layer 21. In the first embodiment, although not limited thereto, for example, in a pixel block 15, the floating diffusion region FD is disposed in the isolation region 31 (first extension 31x) between the photoelectric conversion regions 22 of two pixels 3a and 3c arranged in the Y direction, and the floating diffusion region FD is disposed in the isolation region 31 (first extension 31x) between the photoelectric conversion regions 22 of two pixels 3b and 3d arranged in the Y direction. Furthermore, the floating diffusion region FD between pixels 3a and 3c is shared by these two pixels 3a and 3c, and the floating diffusion region FD between pixels 3b and 3d is shared by these two pixels 3b and 3d.

[0097] like Figure 7A As shown, the floating diffusion region FD is disposed on the outer side of the side portion of the photoelectric conversion region 22 and is physically (structurally) connected to the side portion of the photoelectric conversion region 22 (the side portion of the semiconductor layer 21). The floating diffusion region FD includes, for example, a polycrystalline silicon film incorporating impurities to reduce resistance and has n-type conductivity.

[0098] <Layout of Floating Diffusion Region and Transport Transistor> like Figure 7AAs shown, the floating diffusion region FD is set in the isolation region 31 across the center line (virtual line) Lv1. In the plan view, the center line (virtual line) Lv1 is orthogonal to the outer periphery 22a1 of the two corners 22S1 and 22S2 of the photoelectric conversion region 22 and passes through the center 22c of the photoelectric conversion region 22.

[0099] In addition, such as Figure 7B As shown, in the plan view, the transmission transistor TRV is arranged relative to the center 22c of the photoelectric conversion region 22 at a position facing the floating diffusion region FD from the side. Furthermore, the gate electrode 53 of the transmission transistor TRV includes a main body 53b as a buried portion. The main body 53b is adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 via the gate insulating film 52, extends in the thickness direction (Z direction) of the semiconductor layer 21, and is positioned outside the centerline Lv1 of the photoelectric conversion region 22 in the plan view.

[0100] like Figure 6B As shown, the center line Lv1 overlaps with the main charge transport path R1, and the transfer transistor TRV transfers signal charge from the photoelectric conversion section 25 (n-type semiconductor region 24) to the floating diffusion region FD through the main charge transport path R1. That is, the floating diffusion region FD is located in the middle part of the outer peripheral portion 22a1 connecting the two corners 22S1 and 22S2 of the photoelectric conversion region 22 in the plan view. In addition, the gate electrode 53 of the transfer transistor TRV is included in the embedded part (body part 53b) in the plan view that connects the center portion 22c of the photoelectric conversion region 22 and the middle part of the outer peripheral portion 22a1 of the photoelectric conversion region 22 along the main charge transport path R1. Note that the center line Lv1 is also the perpendicular bisector of the line segment of the outer periphery 22a1 of the photoelectric conversion region 22.

[0101] <Signal charge in the photoelectric conversion region> like Figure 6B As shown, for example, the center portion 22c of the photoelectric conversion region 22 overlaps with the central axis 64a1 of the microlens 64a. In other words, the center portion 22c of the photoelectric conversion region 22 overlaps with the convergence point of the microlens 64a. Furthermore, the center portion 22c of the photoelectric conversion region 22 is also the center portion of the photoelectric conversion section 25. Therefore, since the potential tends to be highest at the center portion 22c of the photoelectric conversion region 22, and the signal charge converted by photoelectric conversion in the photoelectric conversion section 25 accumulates most at the center portion 22c of the photoelectric conversion region 22, effectively transferring the signal charge generated at the center portion 22c of the photoelectric conversion region 22 to the floating diffusion region FD is an important parameter for improving signal charge transfer characteristics. Note that the center 22c of the photoelectric conversion region 22 is the intersection point of the two diagonals 22d1 and 22d2 of the photoelectric conversion region 22 in the plan view.

[0102] Operation of the transfer transistor like Figure 7B and Figure 7A As shown, when a voltage is applied to the gate electrode 53 and the transfer transistor TRV is turned on, the main charge transport path R1, which electrically connects the center portion 22c of the photoelectric conversion region 22 and the floating diffusion region FD in the planar view, is formed in the p-type well region 23. Then, among the signal charges that have undergone photoelectric conversion in the n-type semiconductor region 24 of the photoelectric conversion section 25, the signal charges that have undergone photoelectric conversion in the center portion 22c of the photoelectric conversion region 22 are transported from the n-type semiconductor region 24 (photoelectric conversion section 25) to the n-type floating diffusion region FD via the main charge transport path R1.

[0103] <<Main Effects of the First Implementation>> Next, the main effects of the first embodiment will be explained. like Figure 6B As shown, in the solid-state imaging device 1A according to the first embodiment, the floating diffusion region FD is disposed in the isolation region 31. Therefore, compared with the prior art where the floating diffusion region FD is disposed in the photoelectric conversion region 22, even if the pixel 3 is miniaturized from the perspective of achieving higher resolution, the distance between the transmission transistor TRV and the floating diffusion region DF can be ensured, and concerns about white spots can be alleviated. Furthermore, in the first embodiment, the floating diffusion region FD is disposed in the isolation region 31 such that it crosses the center line Lv1, which is orthogonal to the outer peripheral portion 22a1 of the two corner portions 22S1 and 22S2 connecting the photoelectric conversion region 22 in the plan view and passes through the center line 22c of the photoelectric conversion region 22. Therefore, compared with the prior art where the transmission transistor TRV and the floating diffusion region FD are arranged in an inclined direction when viewed from the center portion 22c of the photoelectric conversion region 22, the distance from the center portion 22c of the photoelectric conversion region 22 to the floating diffusion region FD can be shortened, and the signal charge transmission characteristics can be improved. In addition, since the signal charge transmission characteristics can be improved, the maximum signal charge generated at the center 22c of the photoelectric conversion region 22 can be effectively transmitted to the floating diffusion region FD. Therefore, by using the solid-state imaging device 1A according to the first embodiment, image quality performance can be improved.

[0104] In addition, such as Figure 7AAs shown, since the floating diffusion region FD in the first embodiment is provided on the side surface of the photoelectric conversion region 22, compared with the conventional case where the floating diffusion region FD is provided in the photoelectric conversion region 22, the volume of the photoelectric conversion unit 25 can be increased in the photoelectric conversion region 22 with the same planar size, and the saturation signal level Qs can be increased. Therefore, the dynamic range can be expanded.

[0105] Note that, considering the transmission efficiency of the signal charge generated in the center 22c of the photoelectric conversion region 22, the transmission transistor TRV is preferably arranged in the plan view at a position facing the floating diffusion region FD relative to the center 22c of the photoelectric conversion region 22 (see reference). Figure 7A ).

[0106] Furthermore, since the gate electrode 53 of the transmission transistor TVR in the first embodiment includes a main body portion 53b as a buried portion, considering the transmission efficiency of the signal charge generated in the center portion 22c of the photoelectric conversion region 22, it is preferable to arrange the main body portion 53b at a position offset from the center line Lv1 of the photoelectric conversion region 22 in the plan view (see reference). Figure 8 ).

[0107] Furthermore, considering the influence of the electric field on the floating diffusion region FD (charge holding section) and the signal charge transmission efficiency, the transmission transistor TRV is preferably arranged such that the transmission transistor TRV is located closer to the floating diffusion region FD side than the center 22c of the photoelectric conversion region 22 in the plan view, and the main body 53b of the gate electrode 53 overlaps with the diagonal 22d1 in the plan view.

[0108] <<Modifications of the First Embodiment>> Next, a variation of the first embodiment will be described.

[0109] <Variation Example 1-1> Figure 8 This is a schematic plan view of a pixel of a variation 1-1 according to the first embodiment of the present technology. like Figure 9A As shown, in Modification 1-1, the planar pattern of the photoelectric conversion region 22 is rotated 90° relative to the planar pattern of the photoelectric conversion region 22 in the first embodiment. In Modification 1-1, the floating diffusion region FD is provided in the isolation region 31 (second extension 31y) on the outer peripheral portion 22a4 side of the photoelectric conversion region 22. Furthermore, the floating diffusion region FD in Modification 1-1 crosses the center line (virtual line) Lv, which is orthogonal to the outer peripheral portion 22a4 connecting the two corner portions 22S2 and 22S4 of the photoelectric conversion region 22 in the planar view and passes through the center portion 22c of the photoelectric conversion region 22. 11The method is set in the isolation area 31 (second extension 31y). In variation 1-1, similar effects as the first embodiment described above can also be obtained.

[0110] <Variations 1-2> Figure 9B This is a schematic plan view of a pixel of a variation 1-2 of the first embodiment of the present technology. Figure 9A It is an illustrative representation of the path along Figure 9A The longitudinal section diagram of the longitudinal section structure is taken from line a9-a9.

[0111] like Figure 9B and Figure 5 As shown, in variations 1-2, a transmission transistor TRV1 is provided instead of the one described in the first embodiment. Figure 6A and Figure 9A The transfer transistor TRV is shown. The transfer transistor TRV1 has a basically similar structure to the transfer transistor TRV of the first embodiment described above, but the structure of the gate electrode 56 is different. Other structures are generally similar to those of the transfer transistor TRV of the first embodiment described above.

[0112] That is, such as Figure 9B and Figure 10 As shown, the gate electrode 56 of Variation 1-2 includes: a head 56a disposed on the outer side of the first facet S1 of the semiconductor layer 21, separated by a gate insulating film 52; and a body portion 56b protruding from the head 56a into the interior of the semiconductor layer 21, and adjacent to the semiconductor layer 21 separated by the gate insulating film 52. Furthermore, the head 56a and the body portion 56b are offset in the plan view, with a portion (first portion) 56b1 of the body portion 56b overlapping the head 56a, and another portion (second portion) 56b2 of the body portion 56b located outside the head 56a. Sidewalls 57 are provided on the side portions of the head 56a and the side portions of the body portion 56b1. The other portion 56b2 of the body portion 56b has a generally regular octagonal planar shape.

[0113] Although not limited to this, in variations 1-2, the main body 56b is located closer to the floating diffusion region FD in the plan view than the head 56a. The sidewall 57 is, for example, made of a silicon oxide film.

[0114] In variations 1-2, similar effects to the first embodiment described above can also be obtained.

[0115] <Variations 1-3> Figure 10This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-3.

[0116] like Figure 11 As shown, Modification 1-3 is obtained by changing the planar shape of another portion 56b2 of the gate electrode 56 in Modification 1-2 to an elongated octagon. That is, in Modification 1-3, another portion 56b2 of the main body portion 56b of the gate electrode 56 is formed as an octagon whose width in the Y direction is wider than its width in the X direction in the planar view.

[0117] In variations 1-3, similar effects to the first embodiment described above can also be obtained.

[0118] <Variations 1-4> Figure 11 This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-4. like Figure 12 As shown, variations 1-4 are obtained by changing the planar shape of another part 56b2 of the gate electrode 56 in variations 1-2 above to a triangle.

[0119] Although not limited to this, for example, in the plan view, the main body 56b of the modified examples 1-4 is closer to the center line Lv1 of the photoelectric conversion region 22 than the head 56a, and one of the three side portions of the main body 56b is arranged in the direction along the center line Lv1 of the photoelectric conversion region 220.

[0120] In variations 1-4, similar effects to the first embodiment described above can also be obtained.

[0121] <Variations 1-5> Figure 12 This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-5.

[0122] like Figure 12 As shown, modifications 1-5 are obtained by changing the position of the main body portion 56b of the gate electrode 56 in the modifications 1-4 described above. That is, such as Figure 13 As shown, although not limited to this, in the modified examples 1-5, the main body 56b is located, for example, on the floating diffusion region FD side of the isolation region 31 and the center line Lv1 side of the photoelectric conversion region 22 relative to the head 56a in the plan view, and one of the three side portions of another part 56b2 of the main body 56b is arranged in a direction inclined relative to the extension direction of each of the first extension 31x and the second extension 31y of the isolation region 31.

[0123] In variations 1-5, similar effects to the first embodiment described above can also be obtained.

[0124] <Variations 1-6> Figure 13 This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-6.

[0125] like Figure 14A As shown, in variations 1-6, the arrangement pattern of the elements including the transmission transistor TRV and the pixel transistor Q in each of the four pixels 3 (3a, 3b, 3c and 3d) contained in a pixel block 15 is the same in the plan view.

[0126] This technology can also be applied to variations 1-6, and can achieve similar effects to the first embodiment described above.

[0127] <Variations 1-7> Figure 14B This is a schematic plan view of a pixel block according to variations 1-7 of the first embodiment of the present technology. Figure 14A It is an illustrative representation of the path along Figure 14A The longitudinal section diagram of the longitudinal section structure is taken from line a14-a14.

[0128] like Figure 14B and Figure 5 As shown, in variations 1-7, a transmission transistor TRV2 is used instead of the one described in the first embodiment. Figure 6A and Figure 14A The transfer transistor TRV2 is shown in the diagram. The transfer transistor TRV2 has a substantially similar structure to the transfer transistor TRV of the first embodiment described above, except for the structure of the gate electrode 58. Other structures are generally similar to those of the transfer transistor TRV of the first embodiment described above.

[0129] That is, such as Figure 14B and Figure 15A As shown, the gate electrode 58 of the variations 1-7 includes: a head 58a, which is disposed outside the first face S1 of the semiconductor layer 21 in the plan view through the gate insulating film 52 and extends through the center line Lv1 of the photoelectric conversion region 22 in the X direction; and two body portions (embedded portions) 58b, which protrude from the head 58a into the semiconductor layer 21, are adjacent to the semiconductor layer through the gate insulating film 52, and are disposed separately on both sides of the center line Lv1 of the photoelectric conversion region 22 in the plan view.

[0130] The same technology can also be applied to variations 1-7, and similar effects as the first embodiment described above can be obtained.

[0131] <Variations 1-8> Figure 15B This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-8. Figure 15A It is an illustrative representation of the path along Figure 15A The longitudinal section diagram of the longitudinal section structure is taken from line a15-a15.

[0132] like Figure 15B and Figure 16A As shown, in variations 1-8, in the plan view, the transmission transistors TRV are respectively arranged on both sides of the center line Lv1 of the photoelectric conversion region 22.

[0133] The same technology can also be applied to variations 1-8, and similar effects as the first embodiment described above can be obtained.

[0134] <Variations 1-9> Figure 16B This is a schematic plan view of a pixel of a variation of the first embodiment of the present technology, 1-9. Figure 16A It is an illustrative representation of the path along Figure 16A The longitudinal section diagram of the longitudinal section structure is taken from line a16-a16.

[0135] like Figure 16B and Figure 5 As shown, in variations 1-9, a transmission transistor TRL with a lateral structure is provided instead of the one described in the first embodiment. Figure 6A and Figure 16A The transmission crystal TRV shown has a vertical structure.

[0136] like Figure 16B and Figure 17A As shown, a transducer transistor (TRL) with a lateral structure is disposed on the first face S1 side of the semiconductor layer 21 in the photoelectric conversion region 22. The TRL includes a gate electrode 59 disposed outside the first face S1 of the semiconductor layer 21; and a gate insulating film 52 disposed between the gate electrode 59 and the semiconductor layer 21. Furthermore, the TRL also includes a p-type well region 23 serving as a channel formation portion, and an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as source and drain regions. The gate electrode 59 of the transducer transistor TRL with a lateral structure is positioned across the center line Lv1 of the photoelectric conversion region 22 in a planar view. The gate electrode 59, for example, has a rectangular planar shape.

[0137] The same technology can also be applied to variations 1-9, and similar effects as the first embodiment described above can be obtained.

[0138] <Variation Example 1-10A> Figure 5 This is a schematic plan view of a pixel of a variation 1-10A according to the first embodiment of the present technology. like Figure 17A As shown, the isolation region 31 of the first embodiment described above is constructed in a plan view as an annular shape that continuously surrounds the photoelectric conversion region 22. On the other hand, such as Figure 17A As shown, in Modification 1-10A, the isolation region 31 surrounds the photoelectric conversion region 22 in a plan view and is configured to be segmented at certain locations. In other words, the isolation region 31 in Modification 1-10A has the following configuration: the continuity of the isolation region 31 surrounding the photoelectric conversion region 22 in a plan view is partially interrupted. exist Figure 17B In the example, two discontinuous parts 35 are set, but the number of discontinuous parts 35 is not limited to two. This technology can also be applied to variations 1-10A, and can achieve similar effects to the first embodiment described above.

[0139] <Variation Example 1-10B> Figure 17B This is a schematic plan view of a pixel of a variation 1-10B according to the first embodiment of the present technology. like Figure 17B As shown, in modified example 1-10B, in the plan view, the discontinuity 35 is provided in the isolation region 31 on the corner side of the photoelectric conversion region 22. Figure 17C In this example, the discontinuity 35 is provided in the isolation region 31 (intersection 31xy) on the corner 22S4 side of the photoelectric conversion region 22. However, the discontinuity 35 may also be provided in the isolation region 31 (intersection 31xy) on the other corner 22S1, 22S2 or 22S3 side of the photoelectric conversion region 22. The same technology can also be applied to variations 1-10B, and similar effects as the first embodiment described above can be obtained.

[0140] <Variation 1-10C> Figure 17C This is a schematic diagram of a pixel block containing four pixels, according to a variation 1-10C of the first embodiment of the present technology. like Figure 17DAs shown, in variant 1-10C, among the four pixels 3a, 3b, 3c and 3d included in pixel block 15, in two adjacent pixels 3a and 3c (3b and 3d) in the X direction, the main electrode region 55b of the pixel transistor Q included in the photoelectric conversion region 22 of one pixel 3a (3b) and the main electrode region 55a of the pixel transistor Q included in the photoelectric conversion region 22 of another pixel 3c (3d) are electrically connected to each other via a side contact region 41 provided in the isolation region 31. Although not shown in detail, the side contact region 41 is electrically and mechanically connected to the main electrode regions 55b and 55a of the pixel transistor Q (AMP) and the pixel transistor Q (SEL) on the side surface of the photoelectric conversion region 22. Similarly, although not shown in detail, the side contact region 41 is electrically connected to the main electrode regions 55b and 55a of the pixel transistor Q (FDG) and the pixel transistor Q (RST) on the side surface of the photoelectric conversion region 22. Similar to the floating diffusion region FD, for example, the side contact region 41 is composed of a polycrystalline silicon film with impurities introduced to reduce resistance, and has an n-type conductivity, similar to the main electrode regions 55a and 55b. Modifications 1-10C can also apply this technology and achieve similar effects to the first embodiment described above. Furthermore, in variant 1-10C, the main electrode region 55b of the pixel transistor Q contained in the photoelectric conversion region 22 of one pixel 3a (3b) and the main electrode region 55a of the pixel transistor Q contained in the photoelectric conversion region 22 of another pixel 3c (3d) are electrically connected to each other via a side contact region 41 provided in the isolation region 31, thereby simplifying the wiring for electrically connecting the pixel transistor Q contained in the pixel block 15.

[0141] <Variation Example 1-10D> Figure 17D This is a schematic diagram of a pixel block comprising four pixels, according to a variation 1-10D of the first embodiment of the present technology. like Figure 18 As shown, in variant 1-10D, among the four pixels 3a, 3b, 3c and 3d contained in pixel block 15, in two adjacent pixels 3a and 3c (3b and 3d) in the X direction, the main electrode region 55b of the pixel transistor Q contained in the photoelectric conversion region 22 of one pixel 3a (3b) and the main electrode region 55a of the pixel transistor Q contained in the photoelectric conversion region 22 of another pixel 3c (3d) are shared by the side contact region 41 provided in the isolation region 31. The same technology can also be applied to variations 1-10D, and similar effects as the first embodiment described above can be obtained. Furthermore, in Modification 1-10D, the main electrode region 55b of the pixel transistor Q contained in the photoelectric conversion region 22 of one pixel 3a (3b) and the main electrode region 55a of the pixel transistor Q contained in the photoelectric conversion region 22 of another pixel 3c (3d) are shared by the side contact region 41 provided in the isolation region 31. Therefore, similar to Modification 1-10C described above, the wiring for electrically connecting the pixel transistor Q contained in the pixel block 15 can be simplified.

[0142] <Variation Example 1-11> Figure 6A This schematically shows a longitudinal cross-sectional view of the longitudinal cross-sectional structure of a pixel according to a variation 1-11 of the first embodiment of the present technology.

[0143] like Figure 19A As shown, the isolation region 31 of the first embodiment described above has a straight shape and has no steps on the first facet S1 and the second facet S2 of the semiconductor layer 21. On the other hand, the isolation region 31 of the modified examples 1-11 includes, in the thickness direction (Z direction) of the semiconductor layer 21, a first vertical portion 36 disposed on the first face S1 side of the semiconductor layer 21; and a second vertical portion 37 extending from the first vertical portion 36 toward the second face S2 side of the semiconductor layer 21 and having a width narrower than the width of the first vertical portion 36. Furthermore, due to the difference between the width of the first vertical portion 36 and the width of the second vertical portion 37, the isolation region 31 in Modification 1-11 includes a stepped portion 38. Although not limited thereto, the second vertical portion 37 in Modification 1-11, for example, reaches the second facet S2 of the semiconductor layer 21.

[0144] The second vertical portion 37 can be formed, for example, by forming a recess 37a extending in the thickness direction (Z direction) of the semiconductor layer 21 in the first face portion S1 of the semiconductor layer 21, and then selectively filling the recess 37a with an insulating film 37b. The first vertical portion 36 can be formed, for example, by forming a shallow trench portion 36a on the first face S1 side of the semiconductor layer 21 and then selectively filling the shallow trench portion 36a with an insulating film 36b. Then, by forming the second vertical portion 37 and the first vertical portion 36, an isolation region 31 including the second vertical portion 37 and the first vertical portion 36 is formed, and a photoelectric conversion region 22 separated by the isolation region 31 is formed. Either the second vertical portion 37 or the first vertical portion 36 can be formed first. In any case, the isolation region 31 including the second vertical portion 37 and the first vertical portion 36 is formed.

[0145] In the photoelectric conversion region 22, the first vertical portion 36 can also be formed as an inter-element isolation region (field isolation region) for selectively forming island-shaped element formation regions on the first surface S1 of the semiconductor layer 21.

[0146] The same technology can also be applied to variations 1-11, and similar effects as the first embodiment described above can be obtained.

[0147] [Second Implementation] In the second embodiment, as a stacked photoelectric detection device in which multiple semiconductor layers are stacked, an example of the application of this technology to a two-layer stacked solid-state imaging device, for example, in which two semiconductor layers are stacked. Figure 19B This is a plan view schematically illustrating a construction example of a pixel of a solid-state imaging device according to a second embodiment of the present technology. Figure 19A It is an illustrative representation of the path along Figure 19A The longitudinal section diagram of the longitudinal section structure is taken from line a19-a19.

[0148] like Figure 19B and Figure 19A As shown, the solid-state camera device 1B according to the second embodiment of the present technology has a structure that is basically similar to that of the solid-state camera device 1A according to the first embodiment described above, but differs in the following aspects.

[0149] That is, such as Figure 19B and Figure 3 As shown, the solid-state imaging device 1B according to the second embodiment further includes: a semiconductor layer 81 disposed on the first surface S1 side of the semiconductor layer 21, separated by an insulating layer 71; and an insulating layer 91 disposed on the side of the semiconductor layer 81 opposite to the insulating layer 71 side. Additionally, in the solid-state imaging device 1B of the second embodiment, the pixel circuit 16 (see reference...) Figure 19B The pixel transistor Q included in the image is disposed in the semiconductor layer 81. Figure 19A In the example shown, the amplifying transistor AMP is illustrated as one of the pixel transistors Q. Figure 19B and Figure 19B As shown, unlike the semiconductor layer 81, the photoelectric conversion unit 25, the transmission transistor TRV, and the floating diffusion region FD are each disposed on the semiconductor layer 21 side.

[0150] Here, in the second embodiment, semiconductor layer 21 corresponds to a specific example of the "first semiconductor layer" of the present technology, and semiconductor layer 81 corresponds to the "second semiconductor layer" of the present technology.

[0151] In addition, such as Figure 20AAs shown, the solid-state imaging device 1B according to the second embodiment further includes a conductive path 95, which electrically connects the floating diffusion region FD disposed on the semiconductor layer 21 side and the amplification transistor AMP disposed in the semiconductor layer 81.

[0152] The conductive path 95 includes: a through contact electrode 92 that extends from the insulating layer 91 to the floating diffusion region FD in the stacking direction (Z direction) of the semiconductor layers 21 and 81 and is connected to the floating diffusion region FD; a contact electrode 93 that is embedded in the insulating layer 91 and is connected to the gate electrode 55 of the amplifying transistor AMP; and a wiring 94 that is disposed on the side of the insulating layer 91 opposite to the semiconductor layer 81 and is electrically and mechanically connected to each of the through contact electrode 92 and the contact electrode 93.

[0153] For example, a metal film of aluminum (Al), copper (Cu), or an alloy film mainly containing Al or Cu can be used as wiring 94.

[0154] As the insulating layer 91, a silicon oxide film can be used, for example.

[0155] The insulating layer 71 includes, for example, two insulating films 72 and 75. As the two insulating films 72 and 75, silicon oxide films can be used, for example.

[0156] As the semiconductor layer 81, a Si substrate, a SiGe substrate, an InGaAs substrate, etc., can be used. In the eighth embodiment, although not limited to this, a p-type semiconductor substrate containing single-crystal silicon, for example, is used as the semiconductor layer 81.

[0157] The through-contact electrode 92 is electrically insulated from and separated from the semiconductor layer 81. For example, high-melting-point metal films such as titanium (Ti) and tungsten (W) can be used as the through-contact electrode 92 and the contact electrode 93.

[0158] The solid-state imaging device 1B according to the second embodiment can also produce effects similar to those produced by the solid-state imaging device 1A according to the first embodiment. That is, this technology can also be applied to a two-layer stacked solid-state imaging device 1B with two semiconductor layers 21 and 81 stacked together.

[0159] Furthermore, although not shown, this technology can also be applied to multilayer stacked solid-state imaging devices with three or more semiconductor layers stacked in three layers.

[0160] [Third Implementation Method] In this third embodiment, an example of applying the present technology to a solid-state imaging device including phase difference pixels will be described. Figure 20BThis is an equivalent circuit diagram schematically illustrating an example of the construction of the pixel 3X and pixel circuits (25L and 25R) of the solid-state imaging device 1C according to a second embodiment of the present technology. Figure 20C This is a plan view schematically showing an example of the construction of the pixel 3X of the solid-state imaging device 1C according to the second embodiment of the present technology. Figure 20B It is an illustrative representation of the path along Figure 20A The longitudinal section diagram of the longitudinal section structure cut by line a20-a20.

[0161] The solid-state camera device 1C according to the third embodiment of the present technology has a structure that is basically similar to that of the solid-state camera device 1A according to the first embodiment described above, except that the following structures are different.

[0162] That is, such as Figure 20B , Figure 20C and Figures 3-6B As shown, the solid-state imaging device 1C according to the third embodiment of the present technology includes pixels (sensor pixels) 3X and pixel circuitry 16X, instead of the first embodiment described above. Figure 20A Pixel 3 and pixel circuit 16 are shown.

[0163] In the third embodiment, the pixel circuit 16X is configured for each pixel block 3X containing four pixels 3X. Figures 3-6B The image shows one of the four pixels 3X.

[0164] like Figures 20A-20C As shown, the pixel 3 of the first embodiment has a structure in which a photoelectric conversion unit 25 is provided in a photoelectric conversion region 22.

[0165] On the other hand, such as Figure 20A As shown, the pixel 3X of the third embodiment has the following structure: for example, two photoelectric conversion units 25L and 25R are configured as multiple photoelectric conversion units in a photoelectric conversion unit 22X. The pixel 3X of the third embodiment is a phase difference pixel that detects the phase difference between two photoelectric conversion units 25L and 25R disposed in a photoelectric conversion unit 22X. This technology can also be applied to a solid-state imaging device 1C that includes such a phase pixel (pixel 3X).

[0166] <pixel> like Figure 20A As shown, pixel 3X includes photoelectric conversion unit 22X, which includes two photoelectric conversion regions 26L and 26R.

[0167] (Photoelectric conversion area) The photoelectric conversion region 26L includes: a photoelectric conversion unit 25L (PD1) that converts light into signal charge through photoelectric conversion; and a transmission transistor TRV1 that transmits the signal charge obtained by the photoelectric conversion unit 25L through photoelectric conversion to the floating diffusion region FD1. The floating diffusion region FD1 is disposed in the isolation region 31 and retains (accumulates) the signal charge transmitted from the photoelectric conversion unit 25L by the transmission transistor TRV1. Similarly, the photoelectric conversion region 26R includes: a photoelectric conversion unit 25R (PD2) that converts light into signal charge through photoelectric conversion; and a transmission transistor TRV2 that transmits the signal charge obtained by the photoelectric conversion unit 25R through photoelectric conversion to the floating diffusion region FD2. The floating diffusion region FD2 is also disposed in the isolation region 31 and retains (accumulates) the signal charge transmitted from the photoelectric conversion unit 25R by the transmission transistor TRV2.

[0168] (Photoelectric conversion unit) Similar to the photoelectric conversion unit 25 in the first embodiment described above, Figure 20A The photoelectric conversion units 25L and 25R shown include, for example, pn junction photodiodes (PD1 and PD2), which generate signal charges according to the amount of light received and temporarily retain (accumulate) the generated signal charges.

[0169] In the photoelectric conversion unit 25L, the cathode side is electrically connected to the source region of the transmission transistor TRV1, and the anode side is electrically connected to the reference potential line (e.g., ground).

[0170] In the photoelectric conversion unit 25R, the cathode side is electrically connected to the source region of the transmission transistor TRV2, and the anode side is electrically connected to the reference potential line (e.g., ground).

[0171] (Transmission transistor) Figure 2 The transmission transistor TRV1 shown transfers the signal charge obtained by the photoelectric conversion unit 25L through photoelectric conversion to the floating diffusion region FD1. In the transmission transistor TRV1, the source region is electrically connected to the cathode side of the photoelectric conversion unit 25L, and the drain region is electrically connected to the floating diffusion region FD1. Furthermore, the gate electrode of the transmission transistor TRV1 is electrically connected to... Figure 20A The transmission transistor driving line in the pixel driving line 10 shown.

[0172] Figure 2 The transmission transistor TRV2 shown transfers the signal charge obtained by the photoelectric conversion unit 25R through photoelectric conversion to the floating diffusion region FD2. In the transmission transistor TRV2, the source region is electrically connected to the cathode side of the photoelectric conversion unit 25R, and the drain region is electrically connected to the floating diffusion region FD2. Furthermore, the gate electrode of the transmission transistor TRV2 is electrically connected to...Figure 20A The transmission transistor driving line in the pixel driving line 10 shown.

[0173] (Floating diffusion area) Figure 20A The floating diffusion region FD1 temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion unit 25L via the transmission transistor TRV1.

[0174] Figure 20A The floating diffusion region FD2 temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion unit 25R via the transmission transistor TR2.

[0175] (Pixel circuit) Figure 20A The input stage of the pixel circuit 16X shown is electrically connected to the floating diffusion region FD1 on the side of the photoelectric conversion region 26L and the floating diffusion region FD2 on the side of the photoelectric conversion region 26R. Furthermore, the pixel circuit 16X reads the signal charge held in the floating diffusion regions FD1 and FD2 respectively, and outputs a pixel signal based on the read signal charge.

[0176] In other words, the pixel circuit 16X converts the signal charge obtained by the photoelectric conversion unit 25L (photodiode PD1) and the photoelectric conversion unit 25R (photodiode PD2) through photoelectric conversion into a pixel signal based on the signal charge, and outputs the pixel signal.

[0177] In the third embodiment, as an example, the pixel circuit 16X is assigned to each photoelectric conversion unit 22X, which includes two photoelectric conversion regions 26L and 26R, and reads the signal charge held in the floating diffusion region FD1 on the side of the photoelectric conversion region 25L and the signal charge held in the floating diffusion region FD2 on the side of the photoelectric conversion region 26R, respectively.

[0178] Although not limited to this, as an example, Figure 3 The pixel circuit 16X shown has the same characteristics as... Figure 20B The pixel circuit 16 of the first embodiment described above has a different circuit configuration. Specifically, the pixel circuit 16X of the third embodiment includes, for example, an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST as pixel transistor Q, and omits the switching transistor FDG of the first embodiment. In this case, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifying transistor AMP and the floating diffusion region FD. Other connection modes are similar to those of the pixel circuit 16 of the first embodiment described above, and therefore their description is omitted in the third embodiment.

[0179] <Detailed Structure of the Photoelectric Conversion Region> like Figure 20C andFigure 20B As shown, similar to the photoelectric conversion region 22 of the first embodiment described above, the photoelectric conversion unit 22X is disposed in the semiconductor layer 21. Furthermore, similar to the photoelectric conversion region 22 of the first embodiment described above, the photoelectric conversion unit 22X is surrounded by the isolation region 31 in the plan view (a plan view of the semiconductor layer 21 viewed from the thickness direction of the semiconductor layer 21), and has a rectangular planar shape.

[0180] Additionally, the photoelectric conversion unit 22X includes: an internal isolation barrier 39 extending in the thickness direction (Z direction) of the semiconductor layer 21; and two photoelectric conversion regions 26L and 26R isolated by the internal isolation barrier 39.

[0181] (Photoelectric conversion area) like Figure 20C and Figure 14A As shown, similar to the photoelectric conversion region 22 of the first embodiment described above, the photoelectric conversion region 26L includes a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25L, a transmission transistor TRV1, a pixel transistor Q, and a p-type power contact region (not shown). Similarly, similar to the photoelectric conversion region 22 of the first embodiment described above, the photoelectric conversion region 26R also includes a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25R, a transmission transistor TRV2, a pixel transistor Q, and a p-type power contact region (not shown). Each of the transmission transistors TRV1 and TRV2 has the same characteristics as in the modifications 1-7 described above. Figure 14B and Figure 20B The transmission transistor TRV2 shown has a similar construction.

[0182] (Internal isolation barrier) like Figure 20C and Figure 20B As shown, the internal isolation barrier 39 extends along the Y direction in the plan view and connects to the middle portion of each of the two isolation regions (second extensions 31x and 31x) located on the outer side of the photoelectric conversion unit 22X in the Y direction. Furthermore, the internal isolation barrier 39 is arranged between the photoelectric conversion region 26L and the photoelectric conversion region 26R to electrically and optically isolate the photoelectric conversion regions 26L and 26R. That is, the photoelectric conversion unit 22X is isolated into the photoelectric conversion regions 26L and 26R by the internal isolation barrier 39 extending along the Y direction.

[0183] The internal isolation barrier 39 includes: a recess 32 formed in the same process as the recess 32 of the isolation region 31; and an isolation insulating film 33 formed in the same process as the isolation insulating film 33 of the isolation region 31. That is, the internal isolation barrier 39 can be regarded as the isolation region 31.

[0184] like Figure 20C and Figure 20B As shown, the internal isolation barrier 39 extends along both the Z and Y directions in the photoelectric conversion unit 22X. Furthermore, the internal isolation barrier 39 protrudes from one of the two isolation regions 31 located on either side of the photoelectric conversion unit 22B in the Y direction towards the other isolation region 31, and is integrated with the other isolation region 31. Additionally, the internal isolation barrier 39 has a recess 39a that is recessed from the first surface S1 side of the semiconductor layer 21 towards the second surface S2 side, and connects the photoelectric conversion regions 26L and 26R to each other. That is, in the region of the recess 39a, the internal isolation barrier 39 is one step lower in height along the thickness direction (Z direction) of the semiconductor layer 21. The recess 39a is not limited to this, but may be provided, for example, at the middle portion of the internal isolation barrier 39 in the Y direction.

[0185] (Transmission transistor) like Figure 20C and Figure 20B As shown, the transmission transistor TRV1 is disposed on the first surface S1 side of the semiconductor layer 21 in the photoelectric conversion region 26L. The transmission transistor TRV2 is disposed on the first surface S1 side of the semiconductor layer 21 in the photoelectric conversion region 26R. Each of the transmission transistors TRV1 and TRV2 includes a gate electrode 58 disposed on the first surface S1 side of the semiconductor layer 21, and a gate insulating film 52 disposed between the gate electrode 58 and the semiconductor layer 21. In addition, each of the transmission transistors TRV1 and TR2 also includes a p-type well region 23 serving as a channel formation portion, and an n-type semiconductor region 24 and an n-type floating diffusion region (FD1 or FD2) serving as a source region and a drain region, respectively.

[0186] like Figure 20C and Figure 21A As shown, the gate electrode 58 of the transmission transistor TRV1 includes: a head 58a, which, in the plan view, is disposed outside the first facet S1 of the semiconductor layer 21 across the gate insulating film 52, and passes through the center line Lv2 of the photoelectric conversion region 26L (see reference). Figure 20B It extends in the X direction; and two main body portions (embedded portions) 58b, which protrude from the head 58a into the interior of the semiconductor layer 21, are adjacent to the semiconductor layer 21 through the gate insulating film 52, and are disposed on both sides of the center line Lv2 of the photoelectric conversion region 26L, which are separated from each other in the plan view.

[0187] like Figure 20C and Figure 21AAs shown, the gate electrode 58 of the transmission transistor TRV2 includes: a head 58a, which, in the plan view, is disposed outside the first facet S1 of the semiconductor layer 21 across the gate insulating film 52, and passes through the center line Lv3 of the photoelectric conversion region 26R (see reference). Figure 21A It extends in the X direction; and two main body portions (embedded portions) 58b, which protrude from the head 58a into the interior of the semiconductor layer 21, are adjacent to the semiconductor layer 21 through the gate insulating film 52, and are disposed on both sides of the center line Lv1 of the photoelectric conversion region 22 separately from each other in the plan view.

[0188] (Planar pattern of the photoelectric conversion area) like Figure 21A As shown, each of the photoelectric conversion regions 26L and 26R has, for example, a rectangular planar shape. Furthermore, each of the photoelectric conversion regions 26L and 26R has four outer peripheral portions 26a1, 26a2, 26a3, and 26a4, four corner portions 26s1, 26s2, 26s3, and 26s4, and two diagonals 26d1 and 26d2 in the planar view.

[0189] like Figure 21A As shown, in the two photoelectric conversion regions 26L and 26R, among the four outer peripheral portions 26a1, 26a2, 26a3, and 26a4, two outer peripheral portions 26a1 and 26a2 extend along the X direction in the plan view and are located on opposite sides in the Y direction. Additionally, the remaining two outer peripheral portions 22a3 and 22a4 extend along the Y direction in the plan view and are located on opposite sides in the X direction.

[0190] like Figure 20C As shown, in the two photoelectric conversion regions 26L and 26R, among the four corners 26s1, 26s2, 26s3, and 26s4, two corners 26s1 and 26s4 are located on opposite sides of the extension direction of diagonal 26d1 in the plan view. Additionally, the remaining two corners 26s2 and 26s3 are located on opposite sides of the extension direction of diagonal 26d2 in the plan view.

[0191] In the two photoelectric conversion regions 26L and 26R, one of the two diagonals 26d1 and 26d2 is a line segment connecting the two corners 26s1 and 26s4, and the other diagonal 26d2 is a line segment connecting the two corners 26s2 and 26s3.

[0192] In the four corners 26s1, 26s2, 26s3, and 26s4 of each of the two photoelectric conversion regions 26L and 26R, the two outer peripheral portions 26a1 and 26a3 intersect at corner 26s1. At corner 26s2, the two outer peripheral portions 26a1 and 26a4 intersect. At corner 26s3, the two outer peripheral portions 26a2 and 26a3 intersect. At corner 26s4, the two outer peripheral portions 26a2 and 26a4 intersect.

[0193] In each of the two photoelectric conversion regions 26L and 26R, there are four outer peripheral portions 26a1, 26a2, 26a3, and 26a4. Outer peripheral portion 26a1 is a line segment connecting corner portions 26s1 and 26s2. Outer peripheral portion 26a2 is a line segment connecting corner portions 26s3 and 26s4. Outer peripheral portion 26a3 is a line segment connecting corner portions 26s1 and 26s3. Outer peripheral portion 26a4 is a line segment connecting corner portions 26s2 and 26s4.

[0194] Here, the four outer perimeter parts 26a1, 26a2, 26a3 Each of the components 26a1, 26a2, 26a3, and 26a4 is located at the interface Lp between the semiconductor layer 21 and the isolation region 31 of the photoelectric conversion unit 22X. Therefore, the outer peripheral portions 26a1, 26a2, 26a3, and 26a4 in the planar view can also be referred to as the interface Lp.

[0195] Microlenses like Figure 21B As shown, similar to the first embodiment described above, the microlens 64a of the lens layer 64 is provided for each pixel 3X (for each photoelectric conversion unit 22X). That is, in the photoelectric conversion unit 22X, the two photoelectric conversion regions 26L and 26R share one microlens 64a.

[0196] <Floating Diffusion Area> like ​As shown in the plan view, the floating diffusion region FD1 is disposed in the isolation region 31 (first extension 31x) on the outer peripheral portion 26a1 side of the photoelectric conversion region 26L. The floating diffusion region FD2 is disposed in the isolation region 31 (first extension 31x) on the outer peripheral portion 26a1 side of the photoelectric conversion region 26R. Although not shown in detail, similar to the floating diffusion region FD of the first embodiment described above, the floating diffusion region FD1 is disposed on the outer side of the side portion of the photoelectric conversion region 26L and is physically (structurally) connected to the side portion of the photoelectric conversion region 26L (the side portion of the semiconductor layer 21). In addition, although not shown in detail, similar to the floating diffusion region FD of the first embodiment described above, the floating diffusion region FD2 is also disposed on the outer side of the side portion of the photoelectric conversion region 26R and is physically (structurally) connected to the side portion of the photoelectric conversion region 26R (the side portion of the semiconductor layer 21). Each of the floating diffusion regions FD1 and FD2 is, for example, composed of a polycrystalline silicon film incorporating impurities for reducing resistance, and has an n-type conductivity. In the third embodiment, the floating diffusion regions FD1 and FD2 are isolated from each other in the X direction.

[0197] <Layout of Floating Diffusion Region and Transport Transistor> like FIG. 21A As shown, the floating diffusion region FD1 is set in the isolation region 31 across the center line (virtual line) Lv2. In the plan view, the center line (virtual line) Lv2 is orthogonal to the outer peripheral portion 26a of the two corner portions 26s1 and 26s2 of the photoelectric conversion region 26L and passes through the center portion 26c of the photoelectric conversion region 26L.

[0198] In addition, such as FIG. 21A As shown, in the plan view, the transmission transistor TRV1 is positioned on the side of the floating diffusion region FD1, facing the floating diffusion region FD1, relative to the center portion 26c of the photoelectric conversion region 26L. Furthermore, the gate electrode 58 of the transmission transistor TRV1 includes a main body portion 58b as a buried portion. The main body portion 58b is adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 via a gate insulating film 52, extends in the thickness direction (Z direction) of the semiconductor layer 21, and is configured to be offset from the centerline Lv2 of the photoelectric conversion region 22 in the plan view.

[0199] like FIG. 21BAs shown, the center line Lv2 of the photoelectric conversion region 26L overlaps with the main charge transport path R2. The transmission transistor TRV1 transmits signal charge from the photoelectric conversion section 25 (n-type semiconductor region 24) to the floating diffusion region FD1 through the main charge transport path R2. That is, the floating diffusion region FD1 is located in the middle of the outer peripheral portion 26a connecting the two corner portions 26s1 and 26s2 of the photoelectric conversion region 26L in the plan view. In addition, the gate electrode 58 of the transmission transistor TRV1 includes a buried portion (main body portion 58b), which connects the center portion 26c of the photoelectric conversion region 26L and the middle portion of the outer peripheral portion 26a1 of the photoelectric conversion region 26L along the main charge transport path R2 in the plan view. Note that the center line Lv2 is also the perpendicular bisector of the line segment of the outer periphery 26a1 of the photoelectric conversion region 26L.

[0200] like FIG. 21A As shown, the floating diffusion region FD2 is set in the isolation region 31 across the center line (virtual line) Lv3. In the plan view, the center line (virtual line) Lv3 is orthogonal to the outer peripheral portion 26a of the two corners 26s1 and 26s2 of the photoelectric conversion region 26R and passes through the center line (virtual line) Lv3 of the center portion 22c of the photoelectric conversion region 26R.

[0201] In addition, such as FIG. 21A As shown, in the plan view, the transmission transistor TRV2 is arranged at a position lateral to the floating diffusion region FD2, with its center portion 26c relative to the photoelectric conversion region 26R. Furthermore, the gate electrode 58 of the transmission transistor TRV2 includes a main body portion 58b, which is embedded and adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 via a gate insulating film 52. The main body portion 58b extends in the thickness direction (Z direction) of the semiconductor layer 21 and is positioned offset from the centerline Lv3 of the photoelectric conversion region 22 in the plan view.

[0202] like FIG. 21B As shown, the center line Lv3 of the photoelectric conversion region 26R overlaps with the main charge transport path R3. The transmission transistor TRV2 transmits signal charge from the photoelectric conversion section 25 (n-type semiconductor region 24) to the floating diffusion region FD2 through the main charge transport path R3. That is, the floating diffusion region FD2 is disposed in the middle of the outer peripheral portion 26a connecting the two corner portions 26s1 and 26s2 of the photoelectric conversion region 26R in the plan view. In addition, the gate electrode 58 of the transmission transistor TRV2 includes a buried portion (main body portion 58b), which connects the center portion 26c of the photoelectric conversion region 26L and the middle portion of the outer peripheral portion 26a1 of the photoelectric conversion region 26L along the main charge transport path R3 in the plan view. Note that the center line Lv3 is also the perpendicular bisector of the line segment of the outer periphery 26a1 of the photoelectric conversion region 26R.

[0203] <Signal charge in the photoelectric conversion region> FIG. 21A The central portion 26c of the photoelectric conversion region 26L shown is also the central portion of the photoelectric conversion unit 25 included in the photoelectric conversion region 26L. Furthermore, FIG. 21A The center portion 26c of the photoelectric conversion region 26R shown is also the center portion of the photoelectric conversion unit 25 included in the photoelectric conversion region 26R.

[0204] On the other hand, such as FIG. 20C As shown, in the third embodiment, the two photoelectric conversion regions 26L and 26R share a single microlens 64A. Therefore, unlike the first embodiment described above, the center 26c of each of the two photoelectric conversion regions 26L and 26R does not overlap with the central axis of the microlens. However, even in this case, since the potential tends to be highest at the center 26c of each of the two photoelectric conversion regions 26L and 26R, and the signal charge generated by photoelectric conversion by photoelectric conversion units 25L and 25R accumulates most at the center 22c of each of the two photoelectric conversion regions 26R and 26L, even in the phase difference pixel 3X, effectively transferring the signal charge generated at the center 22c of each of the photoelectric conversion regions 26L and 26R to the floating diffusion regions FD1 and FD2 remains an important parameter for improving signal charge transfer characteristics.

[0205] Operation of the transfer transistor like FIG. 21B As shown, when a voltage is applied to the gate electrode 58 and the transfer transistor TRV1 is turned on, a main charge transport path R2 is formed in the p-type well region 23, connecting the center 22c of the photoelectric conversion region 26L and the floating diffusion region FD1 in the electrical connection plan view. Then, among the signal charges that have undergone photoelectric conversion in the n-type semiconductor region 24 of the photoelectric conversion section 25, the signal charges that have undergone photoelectric conversion in the center 22c of the photoelectric conversion region 26L are transported from the n-type semiconductor region 24 (photoelectric conversion section 25) to the n-type floating diffusion region FD1 via the main charge transport path R2.

[0206] like FIG. 21BAs shown, when a voltage is applied to the gate electrode 58 and the transfer transistor TRV2 is turned on, a main charge transport path R3 is formed in the p-type well region 23, connecting the center 22c of the photoelectric conversion region 26R and the floating diffusion region FD2 in the electrical connection plan view. Then, among the signal charges that have undergone photoelectric conversion in the n-type semiconductor region 24 of the photoelectric conversion unit 25, the signal charges that have undergone photoelectric conversion in the center 22c of the photoelectric conversion region 26R are transported from the n-type semiconductor region 24 (photoelectric conversion unit 25) to the n-type floating diffusion region FD2 via the main charge transport path R3.

[0207] Autofocus In the electronic device including the solid-state imaging device 1C of the third embodiment, the signal charge of two photoelectric conversion units 25L and 25R disposed in a photoelectric conversion unit 22X is read for each pixel 3X, and the phase difference between them is detected.

[0208] When the image is in focus, there is no difference in the amount of signal charge accumulated in the photoelectric conversion unit 25L and the photoelectric conversion unit 25R. In contrast, when the image is out of focus, a difference arises between the amount of signal charge Q1 accumulated in the photoelectric conversion unit 25L and the amount of information charge Q2 accumulated in the photoelectric conversion unit 25R. Then, when the image is out of focus, the electronic device performs an operation such as moving the objective lens to make Q1 and Q2 coincide with each other. This is autofocus.

[0209] <Flow of signal charge> In the photoelectric conversion unit 22X of the third embodiment, the photoelectric conversion regions 26L and 26R are separated by an internal isolation barrier 39 in the Y and Z directions of the photoelectric conversion unit 22X. Furthermore, although not shown in detail, the p-type well regions 23 of each of the photoelectric conversion regions 26L and 26R are connected by a recess 39a in the internal isolation barrier 39. Therefore, the p-type well region 23 in the recess 39a of the internal isolation barrier 39 serves as an overflow path.

[0210] Furthermore, a first potential barrier can be formed in the well region 23 of the recess 39a. When the transmission transistor TRV1 of the photoelectric conversion region 26L does not transfer signal charge from the photoelectric conversion section 25L to the floating diffusion region FD1, a second potential barrier higher than the first potential barrier can be formed. Similarly, when the transmission transistor TRV2 of the photoelectric conversion region 26R does not transfer signal charge from the photoelectric conversion section 25R to the floating diffusion region FD2, a second potential barrier higher than the first potential barrier can be formed.

[0211] Then, the photoelectric conversion sections 25L and 25R of the photoelectric conversion regions 26L and 26R can independently accumulate signal charge up to the height of the first potential barrier. Then, when the amount of accumulated signal charge exceeds the height of the first potential barrier, the signal charge flows from one of the photoelectric conversion sections 25L and 25R of the photoelectric conversion regions 26L and 26R to the other through the overflow path in the recess 39a of the internal isolation barrier 39.

[0212] Note that, as described above, the internal isolation barrier 39 protrudes from one of the two isolation regions 31 that are opposite each other in the plan view separated by the photoelectric conversion unit 22B toward the other isolation region 31, is integrated with the other isolation region 31, and has a recess 39a connecting the photoelectric conversion region 26L and the photoelectric conversion region 26R.

[0213] The solid-state camera device 1C according to the third embodiment can also apply this technology and can achieve similar effects to the solid-state camera device 1A according to the first embodiment.

[0214] [Modifications of the Third Embodiment] Next, a variation of the third embodiment will be described.

[0215] <Variation Example 3-1> FIG. 22 This is a schematic diagram of a pixel of a variation 3-1 according to the third embodiment of the present technology.

[0216] like FIG. 22 As shown, in Modification 3-1, a floating diffusion region FD is shared by two photoelectric conversion regions 26L and 26R. In Modification 3-1, the floating diffusion region FD is disposed in the isolation region 31 on the outer periphery 26a1 side of each of the two photoelectric conversion regions 26L and 26R, along the outer periphery 26a1 of each of the two photoelectric conversion regions 26L and 26R.

[0217] Modification 3-1 can also apply this technology and achieve similar effects to the third embodiment described above.

[0218] <Variation Example 3-2> FIG. 23 This is a schematic diagram of a pixel of a variation 3-2 according to the third embodiment of the present technology.

[0219] like FIG. 23As shown, in Modification 3-2, the middle portion of the floating diffusion region FD protrudes toward the inner isolation barrier 39 in the plan view of Modification 3-1. That is, the floating diffusion region FD of Modification 3-1 includes: a first portion disposed in the isolation region 31 located on the side of the outer periphery 26a1 of each of the two photoelectric conversion regions 26L and 26R; and a second portion protruding toward the inner isolation barrier 39 from the middle portion of the first portion. Modification 3-2 can also apply this technology and achieve similar effects to the third embodiment described above.

[0220] <Variation Example 3-3> FIG. 24 This is a schematic diagram of a pixel of a variation 3-3 according to the third embodiment of the present technology.

[0221] like FIG. 24 As shown, in Modification 3-3, the width W1 of the floating diffusion regions FD1 and FD2 along the X direction is narrower than that of the third embodiment. In Modification 3-3, the width W1 of each of the floating diffusion regions FD1 and FD2 is less than the isolation distance W2 between the two main body portions 58b of the gate electrode 58 (W1 < W2).

[0222] As described above, by narrowing the width W1 of the floating diffusion regions FD1 and FD2 along the X direction, it is possible to suppress the signal charge transmitted to the floating diffusion regions FD1 and FD2 via the side opposite to the side facing each other of the two main body portions 58b of the gate electrode 58, and to increase the signal charge transmitted to the floating diffusion regions FD1 and FD2 via the main charge transmission paths R2 and R3 between the two main body portions 58b. In other words, the main charge transmission paths can be narrowed to the center lines Lv1 and Lv2 of the photoelectric conversion regions 26L and 26R, thereby further improving the signal charge transmission characteristics.

[0223] <Variations 3-4> FIG. 25 This is a schematic plan view of a pixel of a variation 3-4 according to the third embodiment of the present technology.

[0224] like FIG. 25 As shown, in variations 3-4, the power contact region WC, including the p-type semiconductor region, is located at the corner of the photoelectric conversion unit 22X in the plan view. The power contact region WC can be easily formed by providing a discontinuity 35 at the corner of the isolation region 31.

[0225] The same technology can also be applied to variations 3-4, and similar effects as the third embodiment described above can be obtained.

[0226] <Variations 3-5> FIG. 26 This is a schematic plan view of a pixel of a variation 3-5 according to the third embodiment of the present technology.

[0227] like FIG. 26 As shown in variations 3-5, in the two isolation regions 31 located on both sides of the photoelectric conversion unit 22X in the plan view, the power contact region WC containing the p-type semiconductor region is provided in the discontinuity 35 surrounded by the isolation region 31 (first extension 31x) which is different from the isolation region 31 where the floating diffusion regions FD1 and FD2 are provided, and the internal isolation barrier 39. The same technology can also be applied to variations 3-5, and similar effects as the third embodiment described above can be obtained.

[0228] <Variations 3-6> FIG. 27 This is a schematic plan view of a pixel of a variation 3-6 according to the third embodiment of the present technology. like FIG. 27 As shown, in modifications 3-6, in the plan view, the above-mentioned modifications 1-4 are respectively set on both sides of the center line Lv1 of each photoelectric conversion region 26L and 26R. FIG. 11 The transmission transistor shown in the diagram is TRV1, not... FIG. 20B The transmission transistors TRV1 and TRV2 are shown. The same technology can also be applied to variations 3-6, and similar effects as the third embodiment described above can be obtained.

[0229] <Variation Example 3-7> FIG. 28 This is a schematic plan view of a pixel of a variation 3-7 according to the third embodiment of the present technology. like FIG. 28 As shown, in modifications 3-7, in the plan view, the aforementioned modifications 1-5 are respectively arranged on both sides of the center line Lv2 or Lv3 of each photoelectric conversion region 26L and 26R. FIG. 12 The transmission transistor TRV shown is not... FIG. 20B The transmission transistors TRV1 and TRV2 are shown. The same technology can also be applied to variations 3-7, and similar effects as the third embodiment described above can be obtained.

[0230] <Variation Example 3-8> FIG. 29 This is a schematic diagram of a pixel of a variation 3-8 of the third embodiment of the present technology. like FIG. 29 As shown, in variations 3-8, in the transmission transistors TRV1 and TRV2, the two main body portions 58b of the gate electrode 58 have different shapes from each other and are asymmetrical. That is, in the gate electrode 58 of modifications 3-8, one of the two main body portions 58b (on the side of the internal isolation barrier 39) is configured to have the same characteristics as in modifications 1-2. FIG. 9A The main body portion 56b shown has a similar shape (the planar shape is approximately a regular octagon), and another main body portion 58b (on the side of the second extension 31y) is constructed to have the same shape as the modified examples 1-3 described above. FIG. 10 The main body 56b shown has a similar shape (the planar shape is an elongated octagon). The same technology can also be applied to variations 3-8, and similar effects as the third embodiment described above can be obtained.

[0231] <Variation Example 3-9> FIG. 30 This is a schematic diagram of a pixel of a variation 3-9 of the third embodiment of the present technology. like FIG. 30 As shown, Modifications 3-9 have the following structure: In Modifications 3-8, the head 58a and body 58b of each gate electrode 58 contact the side surface of the isolation region 31 containing the internal isolation barrier 39, and are formed in a self-aligned manner. Specifically, in the head 58a of each gate electrode 58, one end of each of the two opposite ends in the longitudinal direction (X direction) contacts the side surface of the internal isolation barrier 39, and the other end contacts the second extension 31y of the isolation region 31. Furthermore, one of the two body portions 58b of each gate electrode 58 contacts the side surface of the internal isolation barrier 39, and the other body portion 58b contacts the side surface of the second extension 31y of the isolation region 31. The same technology can also be applied to variations 3-9, and similar effects as the third embodiment described above can be obtained.

[0232] <Variation Example 3-10> FIG. 31A This is a schematic diagram of a pixel block comprising four pixels, according to a variation 3-10 of the third embodiment of the present invention. FIG. 31B It is shown schematically. FIG. 31A A planar diagram illustrating the construction example of pixels contained within a pixel block. like FIG. 31A and FIG. 31BAs shown, in Variation 3-10, in the four pixels 3X (3Xa, 3Xb, 3Xc, and 3Xd) included in a pixel block 15X, floating diffusion regions FD1 and FD2 are disposed in the isolation region 31 (first extension 31x) located between the photoelectric conversion regions 26L and 26R of the two pixels 3Xa and 3Xb arranged along the Y direction. Furthermore, floating diffusion regions FD1 and FD2 are disposed in the isolation region 31 (first extension 31x) located between the photoelectric conversion regions 26L and 26R of the two pixels 3Xc and 3Xd arranged along the Y direction. Additionally, the floating diffusion region FD1 between pixels 3Xa and 3Xb is shared by the photoelectric conversion regions 26L of these two pixels 3Xa and 3Xb, and the floating diffusion region FD2 between pixels 3Xa and 3Xb is shared by the photoelectric conversion regions 26R of these two pixels 3Xa and 3Xb. Furthermore, the floating diffusion region FD1 between pixel 3Xc and pixel 3Xd is shared by the photoelectric conversion region 26L of the two pixels 3Xc and 3Xd, and the floating diffusion region FD2 between pixel 3Xc and pixel 3Xd is shared by the photoelectric conversion region 26R of the two pixels 3Xc and 3Xd. Furthermore, in variations 3-10, such as FIG. 31B As shown, in the pixel transistor Q disposed in each photoelectric conversion region 26L and 26R, one of the main electrode regions (e.g., 55a) of a pair of main electrodes 55a and 55b is constituted by a side contact region 41 disposed in the isolation region 31. The same technology can also be applied to variations 3-10, and similar effects as the third embodiment described above can be obtained. <Variation Example 3-11> Although not shown, it can be used with FIG. 16A and FIG. 16B The transmission transistor TRL shown is a transverse structure, instead of the transmission transistor TRV1 in the photoelectric conversion region 26L and the transmission transistor TRV2 in the photoelectric conversion region 26R.

[0233] [Fourth Implementation Method] In the fourth embodiment, as a stacked photoelectric detection device having multiple stacked semiconductor layers, an example of the application of this technology to, for example, a three-layer stacked solid-state imaging device containing a three-layer substrate with three stacked semiconductor layers will be described. FIG. 32 This is an exploded view schematically illustrating a construction example of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 33 This is an equivalent circuit diagram showing an example of the construction of pixels and pixel circuits of a solid-state imaging device according to a fourth embodiment of the present technology.

[0234] like FIG. 32 As shown, the solid-state imaging device 1D according to the fourth embodiment of the present technology includes three substrates (a first substrate (first base plate) 210, a second substrate (second base plate) 220, and a third substrate (third base plate) 230). The solid-state imaging device 1D has a three-dimensional structure in which the three substrates (first substrate 210, second substrate 220, and third substrate 230) are stacked. The first substrate 210, the second substrate 220, and the third substrate 230 are stacked sequentially. The first substrate 210 includes a plurality of sensor pixels 212 performing photoelectric conversion in a semiconductor layer 211. The semiconductor layer 211 corresponds to a specific example of the "first semiconductor layer" of the present technology (according to the present disclosure). The plurality of sensor pixels 212 are arranged in a matrix in a pixel region 213 of the first substrate 210. The second substrate 220 includes a pixel circuit (readout circuit) 222 for each of the four sensor pixels 212 within the semiconductor layer 221. The pixel circuit outputs a pixel signal based on the charge output from the corresponding sensor pixel 212. The semiconductor layer 221 corresponds to a specific example of the "second semiconductor layer" of this technology. The second substrate 220 includes a plurality of pixel driving lines 223 extending in the row direction and a plurality of vertical signal lines 224 extending in the column direction. The third substrate 230 includes logic circuitry 232 for processing pixel signals within the semiconductor layer 231. Logic circuitry 232 includes, for example, a vertical drive circuitry 233, a column signal processing circuitry 234, a horizontal drive circuitry 235, and a system control circuitry 236. Logic circuitry 232 (specifically, the horizontal drive circuitry) outputs the output voltage Vout for each sensor pixel 212 to the outside. Within logic circuitry 232, for example, a low-resistance region comprising silicide formed using a self-aligned silicide (self-aligned polysilicide) process, can be formed on the surface of the impurity diffusion region in contact with the source and drain.

[0235] The vertical drive circuit 233 selects, for example, multiple sensor pixels 212 row by row sequentially. The column signal processing circuit 234 performs, for example, correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 212 in the row selected by the vertical drive circuit 233. The column signal processing circuit 234 extracts the signal level of the pixel signal by performing CDS processing and stores pixel data based on the amount of light received by each sensor pixel 212. The horizontal drive circuit 235 outputs the pixel data held in the column signal processing circuit 234 to the outside sequentially. The system control circuit 236 controls the driving of each block of the logic circuit 232 (vertical drive circuit 233, column signal processing circuit 234, and horizontal drive circuit 235).

[0236] FIG. 33 An example of sensor pixel 212 and pixel circuit 222 is shown. In the fourth embodiment, as... FIG. 28 As shown, the case where four sensor pixels 212 share a single pixel circuit 222 will be explained. Here, "shared" means that the outputs of the four sensor pixels 212 are input to the shared pixel circuit 222.

[0237] Each sensor pixel 212 shares a common component. FIG. 28 In the figure, identification numbers (1, 2, 3, and 4) are added to the end of the reference numerals of the components of sensor pixel 212 to distinguish the components of sensor pixel 212 from each other. In the following description, when it is necessary to distinguish the components of sensor pixel 212 from each other, the identification numbers are added to the end of the reference numerals of the components of sensor pixel 212; however, when it is not necessary to distinguish the components of sensor pixel 212 from each other, the identification numbers at the end of the reference numerals of the components of sensor pixel 212 are omitted.

[0238] Each sensor pixel 212 includes, for example, a photodiode PD, a transmission transistor TR electrically connected to the photodiode PD, and a floating diffusion region FD that temporarily holds the signal charge output from the photodiode PD via the transmission transistor TR as a charge holding part.

[0239] The photodiode PD corresponds to specific examples of the photoelectric conversion unit 25 described in the first to fourth embodiments. The photodiode PD generates charge based on the amount of light received by performing photoelectric conversion. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion region FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 223. Similar to the first embodiment described above, the logic circuit 232 includes, for example, a complementary MOS (CMOS) circuit.

[0240] The floating diffusion regions FD of sensor pixels 212 sharing a single pixel circuit 222 are electrically connected to each other and to the input of the shared pixel circuit 222. The pixel circuit 222 includes, for example, a reset transistor RST, a select transistor SEL, and an amplifying transistor AMP. Note that the select transistor SEL can be omitted if necessary. The source of the reset transistor RST (the input of the pixel circuit 222) is electrically connected to the floating diffusion region FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplifying transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 223 (see reference 222). FIG. 32The source of the amplifying transistor AMP is electrically connected to the drain of the select transistor SEL, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. The source of the select transistor SEL (the output of pixel circuit 322) is electrically connected to the vertical signal line 224, and the gate of the select transistor SEL is electrically connected to the pixel drive line 223 (see reference). FIG. 32 ).

[0241] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion region FD. The reset transistor RST resets the potential of the floating diffusion region FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion region FD is reset to the potential of the power supply line VDD. The select transistor SEL controls the output timing of the pixel signal from the pixel circuit 122. The amplifying transistor AMP generates a signal as the pixel signal, corresponding to the level of charge held in the diffusion region FD. The amplifying transistor AMP constitutes a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of charge generated in each photodiode PD. When the select transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to that potential via the nematic signal processing circuit 234 on the vertical signal line 224. The reset transistor RST, the amplifying transistor AMP, and the select transistor SEL are, for example, CMOS transistors.

[0242] Although not shown in detail, reference is made to the second embodiment described above. FIG. 19B In the fifth embodiment, the floating diffusion region FD disposed in the semiconductor layer 211 of the first substrate 210 and the gate electrode 54 of the amplification transistor AMP disposed in the semiconductor layer 221 of the second substrate 220, which is different from the first substrate 210, are electrically connected via a conductive path 95. Furthermore, the transfer transistor TR in the fifth embodiment can be any of the transfer transistors TRV, TRV1, TRV2, TRV1, TRV2, TRL, etc., described in the above embodiments (first to third embodiments) and their variations.

[0243] Therefore, in the solid-state imaging device 1D according to the fourth embodiment, similar effects to those of the above-described embodiments and their variations can also be obtained. That is, this technology can also be applied to the solid-state imaging device 1D having a three-dimensional structure with three substrates (first substrate 210, second substrate 220 and third substrate 230) stacked.

[0244] [Fifth Implementation] In this fifth embodiment, the case in which two transmission transistors with a lateral structure are provided as transmission transistors in a photoelectric conversion region will be described. FIG. 34This is an equivalent circuit diagram schematically illustrating an example of the construction of pixels and pixel circuits in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 35 This is a plan view schematically showing an example of the construction of a pixel block included in the pixel array section of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 36 It is shown schematically. FIG. 35 A planar diagram illustrating the construction example of pixels contained within a pixel block. FIG. 37 It is an illustrative representation of the path along FIG. 36 The longitudinal section diagram of the longitudinal section structure cut by line a36-a36. FIG. 38 This is a timing diagram illustrating a first operational example of the pixel circuit and the transmission transistor. FIG. 39 This is a timing diagram illustrating a second operational example of the pixel circuit and the transmission transistor. FIG. 40A It is an illustrative representation of the path along FIG. 36 The longitudinal section diagram of the longitudinal section structure taken from the center line. FIG. 40B This is a schematic plan view showing the diagonal of the photoelectric conversion region.

[0245] Each camera device 1E according to the fifth embodiment of the present technology has a structure that is basically similar to that of each camera device 1A according to the first embodiment described above, but the structure of the pixel 3 is different. That is, such as FIG. 34 to FIG. 37 As shown, the pixel 3 in the fifth embodiment includes two transmission transistors TRL-1 and TRL-2 with a lateral structure, instead of those in the first embodiment described above. FIG. 3 to FIG. 6B The transmission transistor TRV shown has a vertical structure. Other configurations are generally similar to those of the first embodiment described above. However, as FIG. 37 As shown, the upper part of the n-type semiconductor region 24 has a slightly different structure. Specifically, the n-type semiconductor region 24 in the fifth embodiment includes a main semiconductor portion 24a, which is separated from the first facet S1 of the semiconductor layer 21 and extends from the first facet S1 side toward the second facet S2 side (see reference). FIG. 6A The semiconductor portion 24b extends from the upper side of the main semiconductor portion 24a toward the first face S1 side of the semiconductor layer 21 and is separated from the first face S1 of the semiconductor layer 21.

[0246] In the fifth embodiment, each of the two transmission transistors TRL-1 and TRL-2 has the same characteristics as in the modifications 1-9 described above. FIG. 16A andFIG. 16B The transmission transistor TRL with a lateral structure shown has a roughly similar construction. That is, such as FIG. 36 and FIG. 37 As shown, in the fifth embodiment, each of the two transmission transistors TRL-1 and TRL-2 is disposed in the photoelectric conversion region 22 on the first facet S1 side of the semiconductor layer 21. Each of the two transmission transistors TRL-1 and TRL-2 includes a gate electrode 59 disposed outside the first facet S1 of the semiconductor layer 21, and a gate insulating film 52 disposed between the gate electrode 59 and the semiconductor layer 21. Furthermore, each of the two transmission transistors TRL-1 and TRL-2 also includes a p-type well region 23 serving as a channel formation portion, and an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as the source and drain regions, respectively. The two transmission transistors TRL-1 and TRL-2 share the n-type semiconductor region 24 and the n-type floating diffusion region FD serving as the source and drain regions, and as shown... FIG. 34 The parallel connection is shown.

[0247] like FIG. 36 As shown, the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 is located on the floating diffusion region FD side relative to the center portion 22c of the photoelectric conversion region 22 in the plan view, and is respectively disposed on both sides of the center line Lv1 of the photoelectric conversion region 22. In other words, in the plan view, the gate electrode 59 of one of the two transmission transistors TRL-1 and TRL-2, transmission transistor TRL-1, is disposed on one side of the center line Lv1 of the photoelectric conversion region 22. FIG. 36 (Left side of center line Lv1 in the photoelectric conversion region 22), the gate electrode 59 of another transmission transistor TRL-2 is located on the other side of center line Lv1 in the photoelectric conversion region 22. FIG. 36 (Right side of the center line Lv1 in the diagram). Additionally, in the plan view, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2 are arranged along a direction orthogonal to the center line Lv1 of the photoelectric conversion region 22.

[0248] The gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 has, for example, a rectangular planar shape. The planar dimension of the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 is smaller than that of the modified examples 1-9 described above. FIG. 16A and FIG. 16B The planar dimensions of the gate electrode 59 of the transfer transistor TRL shown are shown. That is, the planar dimensions of each of the two transfer transistors TRL-1 and TRL-2 are smaller than the planar dimensions of the transfer transistor TRL.

[0249] Note that, as described in the first embodiment above, the floating diffusion region FD is disposed in the isolation region 31 on the first face S1 side of the semiconductor layer 21 (refer to...). FIG. 36 and FIG. 40A Additionally, such as FIG. 40A As shown, the floating diffusion region FD is disposed on the outer side of the side portion of the photoelectric conversion region 22 and is physically (structurally) connected to the side portion of the photoelectric conversion region 22 (the side portion of the semiconductor layer 21). Furthermore, the floating diffusion region FD is, for example, composed of a polycrystalline silicon film incorporating impurities to reduce resistance, and has an n-type conductivity. In this case, as... FIG. 40A As shown, impurities diffuse from the polycrystalline silicon film in the isolation region 31 toward the photoelectric conversion region 22 through heat treatment or the like, and the diffused impurities form an n-type semiconductor region 27 on the side surface of the photoelectric conversion region 22. Therefore, the region containing the n-type semiconductor region 27 can naturally be defined as the floating diffusion region FD.

[0250] <<Main Effects of the Fifth Implementation>> Next, the main effects of the fifth embodiment will be explained. like FIG. 36 As shown, in the solid-state imaging device 1E according to the fifth embodiment, similar to the first embodiment described above, the floating diffusion region FD is provided in the isolation region 31. Therefore, compared to the prior art where the floating diffusion region FD is provided in the photoelectric conversion region 22, even if the pixel 3 is miniaturized from the perspective of achieving higher resolution, the distance between the transmission transistor TRV and the floating diffusion region FD can be ensured, and concerns about white spots can be alleviated. Furthermore, similar to the first embodiment described above, in the fifth embodiment, the floating diffusion region FD is disposed across the center line Lv1 in the isolation region 31. In the plan view, the center line Lv1 is orthogonal to the outer periphery 22a1 connecting the two corners 22S1 and 22S2 of the photoelectric conversion region 22 and passes through the center 22c of the photoelectric conversion region 22. Therefore, compared to the prior art where the transmission transistor and the floating diffusion region FD are arranged in an inclined direction when viewed from the center 22c of the photoelectric conversion region 22, the distance from the center 22c of the photoelectric conversion region 22 to the floating diffusion region FD can be shortened, and the signal charge transmission characteristics can be improved. Furthermore, since the signal charge transmission characteristics can be improved, the signal charge generated in the center 22c of the photoelectric conversion region 22 can be effectively transmitted to the floating diffusion region FD. Therefore, similar to the solid-state imaging device 1A according to the first embodiment described above, the solid-state imaging device 1E according to the first embodiment can improve image quality performance.

[0251] In addition, such asFIG. 40A As shown, since the floating diffusion region FD in the fifth embodiment is similarly provided on the side portion of the photoelectric conversion region 22 as in the first embodiment, compared to the conventional case where the floating diffusion region FD is provided in the photoelectric converter region 22 (inside), the volume of the photoelectric conversion unit 25 can be increased in the photoelectric conversion region 22 with the same planar size, and the saturation signal level Qs can be increased. Therefore, the dynamic range can be expanded.

[0252] Note that, considering the transmission efficiency of the signal charge generated in the center 22c of the photoelectric conversion region 22, each of the two transmission transistors TRL-1 and TRL-2 is preferably arranged in the plan view at a position facing the floating diffusion region FD on the side of the floating diffusion region FD relative to the center 22c of the photoelectric conversion region 22c (see reference). FIG. 36 ).

[0253] Furthermore, in the fifth embodiment, considering the transmission efficiency of the signal charge generated in the center portion 22c of the photoelectric conversion region 22, the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 is preferably arranged at a position offset from the center line Lv1 of the photoelectric conversion region 22 in the plan view (see reference). FIG. 36 ).

[0254] Furthermore, considering the influence of the electric field on the floating diffusion region FD and the signal charge transmission efficiency, such as FIG. 40B As shown, the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 is preferably located on the floating diffusion region FD side relative to the center 22c of the photoelectric conversion region 22 in the plan view, and is preferably arranged to overlap with diagonals 22d1 and 22d2 in the plan view. Specifically, preferably, each of the two transmission transistors TRL-1 and TRL-2 is arranged such that the gate electrode 59 of transmission transistor TRL-1 overlaps with diagonal 22d1, and the gate electrode 59 of transmission transistor TRL-2 overlaps with diagonal 22d2.

[0255] Here, the transmission performance of a pixel 3 (the transmission performance of transferring signal charge from the photoelectric conversion unit 25 (PD) to the floating diffusion region FD) depends on the size expansion of the gate electrode of the transmission transistor. In the above... FIG. 16A and FIG. 16BIn pixel 3 of the variations 1-9 shown, the signal charge generated by the photoelectric conversion unit 25 due to photoelectric conversion is transferred to the floating diffusion region FD through a transfer transistor TRL (i.e., a gate electrode TRL). Typically, when a gate voltage (driving voltage) is applied to the gate electrode 59 to excite (drive) the transfer transistor TRL, the modulation below the gate electrode 59 becomes non-uniform, resulting in a potential barrier below the gate electrode 59. This barrier increases with the size of the gate electrode 59. Therefore, by increasing the size of the gate electrode 59, the modulation region is increased, and the transmission performance is improved. However, increasing the size of the gate electrode 59 also leads to an increase in the potential barrier below the gate electrode 59, resulting in a trade-off.

[0256] On the other hand, in the fifth embodiment, such as FIG. 36 and FIG. 37 As shown, the signal charge generated by photoelectric conversion in the photoelectric conversion unit 25 is transferred to the floating diffusion region FD through two transfer transistors TRL-1 and TRL-2 (i.e., two gate electrodes 59). When the signal charge is transferred by two gate electrodes 59, compared to the case where the signal charge is transferred by one gate electrode 59 as described in variations 1-9 above, the potential barrier generated below the gate electrode 59 due to non-uniform modulation when the voltage is applied can be suppressed. In other words, by dividing the gate electrode into two gate electrodes 59 instead of forming a single gate electrode with the same area, the potential barrier below the gate electrode 59 can be increased. Furthermore, this is advantageous for adjusting the saddle point. In addition, by increasing the size of each of the two gate electrodes 59, the modulation performance is improved, and the transmission performance is also improved.

[0257] Furthermore, in pixel 3 of the fifth embodiment, such as FIG. 38 As shown, by applying a gate voltage to the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL-2 in the same timing sequence to simultaneously drive the two transmission transistors TRL-1 and TRL-2, the same operation as described in the modifications 1-9 above can be performed. FIG. 16A and FIG. 16B The case shown is equivalent to charge transfer, where a large gate electrode 59 is used to transfer signal charge.

[0258] Furthermore, in pixel 3 of the fifth embodiment, such as FIG. 39 As shown, by first driving one of the two transmission transistors TRL-1 and TRL-2 ( FIG. 39 The TRL-1 in the diagram can drive another transmission transistor using a low gate voltage (gate signal). FIG. 39(TRL-2), and in general, it can reduce the power required to drive the two transmission transistors TRL-1 and TRL-2 (the timing of the gate signals is different, but the level is similar).

[0259] [Sixth Implementation Method] In the sixth embodiment, the case in which two transmission transistors with a vertical structure are provided as transmission transistors in an electrical conversion region will be described. FIG. 41 This is a plan view schematically showing an example of the structure of pixels included in the pixel array section of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 42 It is an illustrative representation of the path along FIG. 41 The longitudinal section diagram of the longitudinal section structure cut by line a41-a41.

[0260] The solid-state camera device 1F according to the sixth embodiment of the present technology has a structure that is basically similar to that of the solid-state camera device 1A according to the first embodiment described above, but the structure of the pixel 3 is different. That is, such as FIG. 41 and FIG. 42 As shown, pixel 3 in the sixth embodiment includes two transmission transistors TRV-1 and TRV-2 with a vertical structure. Other configurations are generally similar to those in the first embodiment described above.

[0261] According to the sixth embodiment, each of the two transmission transistors TRV-1 and TRV-2 has the same characteristics as described in the first embodiment. FIG. 5 to FIG. 6B The transmission transistor TRV with a vertical structure shown has a roughly similar construction. That is, such as FIG. 41 and FIG. 42 As shown, according to the sixth embodiment, each of the two transmission transistors TRV-1 and TRV-2 is disposed in the photoelectric conversion region 22 on the first facet S1 side of the semiconductor layer 21. Furthermore, each of the two transmission transistors TRV-1 and TRV-2 includes a gate electrode 53 disposed on the first facet S1 side of the semiconductor layer 21, and a gate insulating film 52 disposed between the gate electrode 53 and the semiconductor layer 21. In addition, each of the two transmission transistors TRV-1 and TRV-2 also includes a p-type well region 23 serving as a channel formation portion, and an n-type semiconductor region 24 and an n-type floating diffusion region FD serving as the source and drain regions, respectively. The two transmission transistors TRV-1 and TRV-2 share the n-type semiconductor region 24 and the n-type floating diffusion region FD serving as the source and drain regions, and are connected in parallel.

[0262] Similar to the gate electrode 53 in the first embodiment described above, such as FIG. 41 andFIG. 42 As shown, the gate electrode 53 of each of the two transmission transistors TRV-1 and TRV-2 includes: a head 53a disposed outside the first facet S1 of the semiconductor layer 21 across a gate insulating film 52; and a body 53b protruding from the head 53a toward the interior of the semiconductor layer 21 (photoelectric conversion region 22) and adjacent to the semiconductor layer 21 across the gate insulating film 52. However, the sixth embodiment differs from the first embodiment described above in the shape of the head 53a and the body 53b of the gate electrode 53.

[0263] like FIG. 41 As shown, the gate electrode 53 of each of the two transmission transistors RV-1 and TRV-2 is located on the floating diffusion region FD side relative to the center portion 22c of the photoelectric conversion region 22 in the plan view, and is respectively disposed on both sides of the center line Lv1 of the photoelectric conversion region 220. In other words, in the plan view, the gate electrode 53 of one of the two transmission transistors TRV-1 and TRV-2, transmission transistor TRV-1, is disposed on one side of the center line Lv1 of the photoelectric conversion region 22. FIG. 41 (Left side of the center line Lv1 in the photoelectric conversion region 22), and the gate electrode 53 of another transmission transistor TRV-2 is disposed on the other side of the center line Lv1 in the photoelectric conversion region 22. FIG. 42 (Right side of the center line Lv1 in the diagram). In addition, the gate electrodes 53 of the two transmission transistors TRV-1 and TRV-2 are arranged in the plan view along a direction orthogonal to the center line Lv1 of the photoelectric conversion region 22.

[0264] The planar dimensions of the gate electrode 53 of each of the two transmission transistors TRV-1 and TRV-2 are smaller than those of the first embodiment described above. FIG. 5 and FIG. 6A The planar dimensions of the gate electrode 53 of the transmission transistor TRV shown are as follows. That is, the planar dimensions of each of the two transmission transistors TRV-1 and TRV-2 are smaller than the planar dimensions of the transmission transistor TRV.

[0265] The solid-state camera device 1F according to the sixth embodiment can also produce effects similar to those produced by the solid-state camera device 1E according to the fifth embodiment. Furthermore, in the two transmission transistors TRV-1 and TRV-2, since the legs 53b of the gate electrode 53 are arranged in parallel, the transmission of signal charge from the photoelectric conversion section 25 to the floating diffusion region FD in the vertical direction can be enhanced (read performance). Furthermore, in pixel 3 of the sixth embodiment, since each of the two transmission transistors TRV-1 and TRV-2 can be driven individually and the stabilization process is accelerated, the parasitic capacitance applied to each main body portion 53 is reduced, the voltage can be reduced, and the driving time can be shortened.

[0266] [Seventh Implementation Method] FIG. 43 This is a plan view schematically showing an example of the structure of pixels included in the pixel array section of a solid-state imaging device according to a seventh embodiment of the present technology. FIG. 44 It is an illustrative representation of the path along FIG. 43 A longitudinal cross-sectional view of the longitudinal section structure taken from the centerline a43-a43.

[0267] The solid-state camera device 1G according to the seventh embodiment of the present technology has a structure that is basically similar to that of the solid-state camera device 1E according to the fifth embodiment described above, but the structure of the pixel 3 is different. That is, such as FIG. 43 and FIG. 44 As shown, the pixel 3 in the seventh embodiment also includes an impurity diffusion isolation region 28, which is disposed in the semiconductor layer 21 (photoelectric conversion region 22) between two transmission transistors TRL-1 and TRL-2 having a lateral structure in a plan view. Other structures are generally similar to those in the fifth embodiment described above.

[0268] like FIG. 43 As shown, the impurity diffusion isolation region 28 overlaps with the center line Lv1 of the photoelectric conversion region 22 in the plan view, and extends across the center portion 22c of the photoelectric conversion region and the floating diffusion region FD. Furthermore, this impurity diffusion isolation region 28 traverses between the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2 in the plan view. Additionally, as... FIG. 44 As shown, the impurity diffusion isolation region 28 is separated from the first facet S1 of the semiconductor layer 21 and extends from the first facet S1 of the semiconductor layer 21 toward the opposite side (the second facet S2 side). The impurity diffusion isolation region 28 is composed of a p-type semiconductor region with a higher impurity concentration than the p-type well region 23.

[0269] The solid-state camera device 1G according to the seventh embodiment can also produce effects similar to those produced by the solid-state camera device 1E according to the fifth embodiment.

[0270] Furthermore, by providing an impurity diffusion isolation region 28 in the semiconductor layer 21 (photoelectric conversion region 22) between the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2, a main charge transport path can be provided in the thickness direction (Z direction) of the semiconductor layer 21, extending from the middle of the photoelectric conversion region 22 (photoelectric conversion section 25) to below the gate electrode 59. This main charge transport path serves to guide the signal charge, thereby suppressing the retention of signal charge in the semiconductor layer 21 between the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2.

[0271] Furthermore, by providing an impurity diffusion isolation region 28 in the semiconductor layer 21 (photoelectric conversion region 22) between the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2, damage to the photoelectric conversion unit can be prevented even when the charge accumulation capability in the photoelectric conversion unit 25 (photodiode PD) is increased.

[0272] [Eighth Implementation Method] In the first to seventh embodiments described above, it has been explained that the floating diffusion region FD is set in the isolation region 31 across the center line Lv1 of the photoelectric conversion region 22 in the plan view. However, in the eighth embodiment, it will be explained that the floating diffusion region FD is set in the isolation region 31 adjacent to the corner of the photoelectric conversion region 22.

[0273] FIG. 45 This is a plan view schematically showing an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the eighth embodiment of the present technology. FIG. 46 It is shown schematically. FIG. 45 A planar diagram illustrating the construction example of pixels contained within a pixel block.

[0274] The solid-state imaging device 1H according to the eighth embodiment of the present technology has a structure that is basically similar to that of the solid-state imaging device 1E according to the fifth embodiment described above, but differs in the following aspects. That is, in the solid-state imaging device 1H according to the eighth embodiment, the two transmission transistors TRL-1 and TRL2 are arranged differently, and the four pixels 3 (3a, 3b, 3c and 3d) contained in a pixel block 15 share a floating diffusion region FD3.

[0275] like FIG. 46As shown, the floating diffusion region FD3 of the eighth embodiment is disposed at the intersection point 31xy where the first extension 31x and the second extension 31y of the isolation region 31, which is the central part of the pixel block 15, intersect. Furthermore, the floating diffusion region FD3 of the eighth embodiment has a cross-shaped planar shape extending along each of the first extension 31x and the second extension 31y of the isolation region 31. That is, as... FIG. 45 and FIG. 46 As shown, the floating diffusion region FD3 of the eighth embodiment is disposed in the isolation region 31 adjacent to the corner 22S2 of each of the four photoelectric conversion regions 22 contained in the pixel block 15 in the plan view.

[0276] In addition, such as FIG. 45 and FIG. 46 As shown, in the eighth embodiment, in the four pixels 3 (3a, 3b, 3c, and 3d) included in the pixel block 15, the two transmission transistors TRL-1 and TRL2 of each pixel 3 are disposed on the corner 22S2 side relative to the center 22c of each photoelectric conversion region 22 in the plan view, that is, on the floating diffusion region FD side. Furthermore, in the four pixels 3 (3a, 3b, 3c, and 3d), as... FIG. 46 As shown, the gate electrodes 59 of each of the two transmission transistors TRL-1 and TRL2 are disposed on the floating diffusion region FD side (corner 22S2 side of photoelectric conversion region 22) in the plan view, and are arranged along a direction Cd intersecting the diagonal 22d2 extending inward from the corner 22S2 of the floating diffusion region FD side of photoelectric conversion region 22. In the eighth embodiment, for example, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged along a direction Cd orthogonal to the diagonal 22d2. Furthermore, the gate electrodes 59 of each of the two transmission transistors TRL-1 and TRL2 are arranged such that a rectangular side of each gate electrode 59 is parallel to the diagonal 22d2 in the plan view.

[0277] The solid-state imaging device 1H according to the eighth embodiment can also produce effects similar to those produced by the solid-state imaging device 1E according to the fifth embodiment. Furthermore, by setting a floating diffusion region FD in the isolation region 31 adjacent to the corner 22S2 of the photoelectric conversion region 22, the four pixels 3 (3a, 3b, 3c and 3d) contained in the pixel block 15 can share a single floating diffusion region FD.

[0278] Note, as referenced FIG. 46The arrangement direction of the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2 can be defined as the extension direction of a virtual line that intersects at a 45-degree angle with each of the two sides 26a1 and 26a4 of the corner 22S2 on the side of the floating diffusion region FD3 constituting the electrical conversion region 22.

[0279] [Ninth Implementation Method] FIG. 47 This is a plan view schematically showing an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 48 It is shown schematically. FIG. 47 A planar diagram illustrating the construction example of pixels contained within a pixel block.

[0280] The solid-state imaging device 1I according to the ninth embodiment of the present technology has a structure that is basically similar to that of the solid-state imaging device 1H according to the eighth embodiment described above, but the shapes of the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are different. That is, such as FIG. 47 and FIG. 48 As shown, the planar shape of the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL2 of the four pixels 3 (3a, 3b, 3c, and 3d) contained in a pixel block 15 is, for example, constructed as an isosceles right triangle. Furthermore, the two transmission transistors TRL-1 and TRL2 are arranged such that the base of the isosceles right triangle of each gate electrode 59 is located on the isolation region 31 side in the plan view, and is arranged along a direction Cd intersecting the diagonal 22d2 extending inward from the corner 22S2 of the photoelectric conversion region 22 located on the floating diffusion region FD side.

[0281] Similarly, in the solid-state camera device 1I according to the ninth embodiment, similar effects as those of the solid-state camera device 1H according to the eighth embodiment can be obtained. Note, as referenced FIG. 48 In the ninth embodiment, the arrangement direction of the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2 can also be defined as the extension direction of a virtual line that intersects at a 45-degree angle with each of the two sides 26a1 and 26a4 of the corner 22S2 on the side of the floating diffusion region FD3 constituting the electrical conversion region 22.

[0282] [Tenth Implementation Method] In the tenth embodiment, an example of applying this technology to a solid-state imaging device that includes phase difference pixels will be described. FIG. 49This is a plan view schematically showing an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the tenth embodiment of the present technology. FIG. 50 It is shown schematically. FIG. 49 A planar diagram illustrating the construction example of pixels contained within a pixel block. FIG. 51 It shows FIG. 50 A plan view showing the arrangement direction of the gate electrodes in the photoelectric conversion region.

[0283] The solid-state imaging device 1J according to the tenth embodiment of the present technology has a structure that is basically similar to that of the solid-state imaging device 1C according to the third embodiment described above, but differs in the structure of the pixel block, the floating diffusion region, and the pixel. That is, such as FIG. 49 and FIG. 50 As shown, the pixel block 15J according to the tenth embodiment includes two pixels 3X (3X1 and 3X2) arranged in the Y direction, and the planar pattern of the two pixels 3X (3X1 and 3X2) is a flip pattern with the boundary of the two pixels as the flip axis. Furthermore, each pixel 3X according to the tenth embodiment includes those having those described in the ninth embodiment. FIG. 47 and FIG. 48 The two transmission transistors TRL-1 and TRL-2 in the lateral structure shown are instead of those in the third embodiment described above. FIG. 20B and FIG. 20C The vertically structured transmission transistor TRV is shown. Furthermore, in the tenth embodiment, a floating diffusion region FD4 is provided instead of the one in the third embodiment described above. FIG. 20B The floating diffusion regions FD1 and FD2 are shown. According to the tenth embodiment, the pixel 3X (3X1 and 3X2) is a phase difference pixel that detects the phase difference between two photoelectric conversion units 25L and 25R disposed in a photoelectric conversion unit 22X.

[0284] The floating diffusion region FD4 of the tenth embodiment is disposed in the center of the pixel block 15J and in the portion where the isolation region 31 (first extension 31x) between the two pixels 3X (3X1 and 3X2) arranged in the Y direction intersects with the internal isolation barrier 39 of each of the two pixels 33X (3X1 and 3X2) arranged in the Y direction. Furthermore, the floating diffusion region FD4 of the tenth embodiment has a cross-shaped planar form extending along the direction of the first extension 31x of the isolation region 31 in the center of the pixel block 15J and along the internal isolation barrier 39 of each of the two pixels 3X (3X1 and 3X2) arranged in the Y direction. That is, as... FIG. 49 and FIG. 50As shown, in the two pixels 3X (3X1 and 3X2) included in the pixel block 15 in the plan view, the floating diffusion region FD4 of the tenth embodiment is disposed in the first extension 31x of the isolation region 31 adjacent to the corner 22S2 of each of the two photoelectric conversion regions 26L and 26R included in one pixel 3X1 and the corner 22S2 of each of the two photoelectric conversion regions 26L and 26R included in the other pixel 3X2.

[0285] like FIG. 50 As shown, in the photoelectric conversion regions 26L and 26R of the two pixels 3X (3X1 and 3X2) contained in pixel block 15J, two transmission transistors TRL-1 and TRL2 are disposed on the corner side 26S2, i.e. the floating diffusion region FD4 side, relative to the center 26c of the photoelectric conversion regions 26L and 26R in the plan view. In addition, such as FIG. 51 As shown, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 in the photoelectric conversion region 26L, which are located within the photoelectric conversion regions 26L and 26R, are positioned on the floating diffusion region FD4 side (corner 22S2 side of the photoelectric conversion region 26L) in the plan view, and are arranged along the direction Cd1 intersecting the virtual line 29L extending inward from the corner 22S2 on the floating diffusion region FD4 side of the photoelectric conversion region 26L. Additionally, as... FIG. 51 As shown in the plan view, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 disposed in the photoelectric conversion region 26R are disposed on the floating diffusion region FD4 side (corner 22S2 side of the photoelectric conversion region 26R), and are arranged along a direction Cd2 intersecting the virtual line 29R extending inward from the corner 22S2 of the floating diffusion region FD4 side of the photoelectric conversion region 26R. In the tenth embodiment, for example, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged along directions Cd1 and Cd2 orthogonal to the virtual lines 29L and 29R. In addition, the gate electrodes 59 of each of the two transmission transistors TRL-1 and TRL2 are arranged along a rectangular side in the plan view, parallel to the virtual line 29L or 29R.

[0286] This technology can also be applied to the solid-state camera device 1J according to the tenth embodiment, and can achieve similar effects to the solid-state camera device 1E according to the fifth embodiment described above.

[0287] Note, as referenced FIG. 50The arrangement direction of the gate electrodes 59 of the two transmission transistors TRL-1 and TRL-2 can be defined as the extension direction of a virtual line that intersects at a 45-degree angle with each of the two sides 26a1 and 26a4 of the corner 26S2 located on the side of the floating diffusion region FD4 that constitutes the electrical conversion region 26L or 22R.

[0288] [Eleventh Implementation Method] FIG. 52 This is a plan view schematically showing an example of the structure of a pixel block included in the pixel array section of a solid-state imaging device according to the eleventh embodiment of the present technology. FIG. 53 It is shown schematically. FIG. 52 A planar diagram illustrating the construction of pixels included in a pixel block.

[0289] The solid-state imaging device 1K according to the eleventh embodiment of the present technology has a structure that is basically similar to that of the solid-state imaging device 1H according to the eighth embodiment described above, but the planar shapes of the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are different. That is, such as FIG. 52 and FIG. 53 As shown, according to the eleventh embodiment, the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL2 is, for example, formed as a right-angled triangle with three sides of different lengths. Additionally, as... FIG. 53 As shown, according to the eleventh embodiment, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged along the extension direction of a virtual line 29 that intersects at a 45-degree angle with each of the two sides 22a1 and 22a4 of the corner 22S2 on the side of the floating diffusion region FD3 constituting the photoelectric conversion region 22. Furthermore, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged such that the hypotenuses of the right-angled triangles are adjacent to and parallel to each other in the plan view.

[0290] This technology can also be applied to the solid-state camera device 1K according to the tenth embodiment, and can achieve similar effects to the solid-state camera device 1H according to the eighth embodiment described above.

[0291] [Twelfth Implementation Method] FIG. 54 This is a plan view schematically showing an example of the structure of the pixel block included in the pixel array section of a solid-state imaging device according to the twelfth embodiment of the present technology. FIG. 55 It is shown schematically. FIG. 54 A planar diagram illustrating the construction of pixels included in a pixel block.

[0292] The solid-state imaging device 1L according to the twelfth embodiment of the present technology has a structure that is basically similar to that of the solid-state imaging device 1J according to the tenth embodiment described above, but the planar shape of the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL2 is different. That is, such as FIG. 54 and FIG. 55 As shown, similar to the eleventh embodiment described above, the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL2 according to the twelfth embodiment is, for example, formed as a right-angled triangle with three sides of different lengths. In addition, such as FIG. 55 As shown, the gate electrodes 59 of each of the two transmission transistors TRL-1 and TRL2 disposed on the photoelectric conversion region 26L side are disposed on the floating diffusion region FD4 side (corner 26S2 side of photoelectric conversion region 26L) in the plan view, and are arranged along the extension direction of the virtual line 29L1 that intersects at a 45-degree angle with each of the two sides 26a1 and 26a4 of the corner 26S2 on the floating diffusion region FD4 side of photoelectric conversion region 26L. Furthermore, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged such that the hypotenuses of the right-angled triangles of the gate electrodes 59 are adjacent to and parallel to each other in the plan view.

[0293] In addition, such as FIG. 55 As shown, the gate electrodes 59 of each of the two transmission transistors TRL-1 and TRL2 disposed on the photoelectric conversion region 26R side are disposed on the floating diffusion region FD4 side (corner 26S2 side of photoelectric conversion region 26L) in the plan view, and are arranged along the extension direction of the virtual line 29L2 that intersects at a 45-degree angle with each of the two sides 26a1 and 26a4 of the corner 26S2 on the floating diffusion region FD4 side constituting photoelectric conversion region 26R. Furthermore, the gate electrodes 59 of the two transmission transistors TRL-1 and TRL2 are arranged such that the hypotenuses of the right-angled triangles of the gate electrodes 59 are adjacent to and parallel to each other in the plan view.

[0294] This technology can also be applied to the solid-state camera device 1L according to the twelfth embodiment, and can achieve similar effects to the solid-state camera device 1J according to the tenth embodiment described above.

[0295] Furthermore, according to the tenth embodiment, there is a difference in the distance between the gate electrode 59 of each of the two transmission transistors TRL-1 and TRL2 and the center 26c of the photoelectric conversion region 26L or 26R, and there are gate electrodes 59 that are close to the center 26c of the photoelectric conversion region 26L or 26R and gate electrodes 59 that are far away. Therefore, it is possible to drive according to the environment, such as in a bright environment, driving the transmission transistor only in the direction where the gate electrode 59 is close to the center 26c of the photoelectric conversion region 26L or 26R. FIG. 55 The transfer transistor TRL-1 is used to drive two transfer transistors TRL-1 and TRL2 to transfer signal charge in a dark environment, which can reduce power consumption and improve the read speed of the signal charge held in the floating diffusion region FD.

[0296] [Other Implementation Methods] In the fifth to ninth and eleventh embodiments described above, it has been described that two transmission transistors TRL-1 and TRL-2 (TRV-1 and TRV-2) with a common source region and drain region (n-type semiconductor region 24 and n-type floating diffusion region FD or FD3) are provided in a photoelectric conversion region 22. However, the number of transmission transistors is not limited to two, and may be more than two.

[0297] Furthermore, in the tenth and twelfth embodiments described above, it has been described that two transmission transistors TRL-1 and TRL-2 with a common source region and drain region (n-type semiconductor region 24 and n-type floating diffusion region FD4) are provided in each of the photoelectric conversion regions 26L and 26R. However, the number of transmission transistors is not limited to two, and may be more than two.

[0298] [Thirteenth Implementation Method] <<Examples of Electronic Device Applications>> This technology (the technology disclosed herein) can be applied, for example, to various electronic devices such as camera devices such as digital cameras or digital video cameras, mobile phones with camera functions, or other devices with camera functions.

[0299] FIG. 56 This is a diagram illustrating a schematic construction of an electronic device (e.g., a camera) according to a fifth embodiment of the present technology.

[0300] like FIG. 56As shown, the electronic device 300 includes a solid-state imaging device 301, an optical lens 302, a shutter device 303, a drive circuit 304, and a signal processing circuit 305. The electronic device 300 is an embodiment in which one of the solid-state imaging devices 1A to 1L according to the first to fifth embodiments of the present technology and a solid-state imaging device according to a variation of the above embodiments is used as the solid-state imaging device 301 in an electronic device (e.g., a camera).

[0301] Optical lens 302 forms an image of the image light (incident light 306) from the subject on the imaging surface of solid-state imaging device 301. Therefore, signal charge accumulates in solid-state imaging device 301 for a certain period of time. Shutter device 303 controls the light illumination period and light blocking period of solid-state imaging device 301. Drive circuit 304 supplies drive signals for controlling the transmission operation of solid-state imaging device 301 and the shutter operation of shutter device 303. Based on the drive signal (timing signal) supplied from drive circuit 304, solid-state imaging device 301 performs charge transfer. Signal processing circuit 305 performs various types of signal processing on the signal (pixel signal (image signal)) output from solid-state imaging device 301. The video signal obtained after signal processing is stored in a storage medium such as a memory, or output to a monitor.

[0302] By utilizing this structure, the image quality performance of the electronic device 300 of the sixth embodiment can be improved because the image quality performance is improved in the solid-state imaging device 301.

[0303] Note that the electronic device 300 to which the solid-state imaging device according to the above embodiment can be applied is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to imaging devices such as camera modules of mobile devices such as mobile phones or tablet terminals.

[0304] Furthermore, this technology can be applied to any photoelectric detection device, including not only the aforementioned solid-state imaging device as an image sensor, but also range sensors such as time-of-flight (ToF) sensors that measure distance. Such a range sensor emits illumination light toward an object, detects the reflected light as illumination light reflected from the object's surface, and calculates the distance to the object based on the time of flight from emitting the illumination light to receiving the reflected light. The aforementioned pixel transistors can also be used in this range sensor.

[0305] Note that this technology can have the following configuration. (1) A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed on the semiconductor layer such that it is adjacent to the isolation region in a planar view, and the photoelectric conversion region has a rectangular planar shape; A photoelectric conversion unit is disposed in the photoelectric conversion region; and A transmission transistor is disposed in the photoelectric conversion region and transmits the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge holding portion is disposed in the isolation region in a manner that crosses the center line, which in the plan view is orthogonal to the outer periphery of the two corners of the photoelectric conversion region and passes through the center of the photoelectric conversion region. (2) According to the photoelectric detection device of (1), the transmission transistor is arranged in a position in the plan view that is closer to the charge holding portion than the center portion of the photoelectric conversion region and opposite to the charge holding portion. (3) According to the photoelectric detection device described in (1) or (2), the transmission transistor has a gate electrode, and The gate electrode includes a buried portion disposed adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film, the buried portion extending along the one direction and offset from the center line in a plan view. (4) According to the photoelectric detection device described in (1) or (2), the transmission transistor has a gate electrode, and The gate electrode includes a buried portion that is adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film. The buried portion extends along the one direction and is disposed on both sides of the center line in a plan view. (5) According to the photoelectric detection device described in (1) or (2), the transmission transistors are respectively arranged on both sides of the center line in the plan view. (6) According to the photoelectric detection device described in (1) or (2), the transmission transistor has a gate electrode disposed on the outer side of the first facet of the semiconductor layer, separated by a gate insulating film, and The gate electrode is configured to cross the center line in a planar view. (7) According to any one of (1) to (6) the photoelectric detection device, wherein the charge holding part is connected to the side part of the photoelectric conversion region. (8) According to any one of (1) to (7) the photoelectric detection device, wherein the center line is the main transmission path, and the transmission transistor transmits signal charge from the photoelectric conversion unit to the charge holding unit through the main transmission path. (9) According to any one of (1) to (8) the photoelectric detection device, wherein the center of the photoelectric conversion region is the intersection point of the two diagonals of the photoelectric conversion region. (10) The photoelectric detection apparatus according to any one of (1) to (9) further includes a pixel circuit that reads a signal charge held in the charge holding section and outputs a pixel signal based on the read signal charge, wherein... The pixel transistors included in the pixel circuit are disposed in the photoelectric conversion region. (11) According to the photoelectric detection device described in (1), with the semiconductor layer as the first semiconductor layer, the photoelectric detection device further includes: A second semiconductor device, the second semiconductor device being disposed such that it overlaps with the first semiconductor layer in said one direction; and A pixel circuit reads the signal charge held in the charge holding section and outputs a pixel signal based on the read signal charge, wherein... The pixel transistors included in the pixel circuit are disposed on the second semiconductor layer. (12) A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion unit is disposed on the semiconductor layer in a planar view adjacent to an isolation region, and includes two photoelectric conversion regions formed in a rectangular planar shape; A photoelectric conversion unit, which is disposed in each of the two photoelectric conversion regions; and A transmission transistor is disposed on the first facet side of the semiconductor layer in each of the two photoelectric conversion regions, and transmits the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge holding portion is disposed in the isolation region in a manner that crosses the center line, which in the plan view is orthogonal to the outer periphery of the two corners of the photoelectric conversion region and passes through the center of the photoelectric conversion region. (13) According to the photoelectric detection device of (12), the transmission transistor is arranged in a position in the plan view that is closer to the charge holding portion than the center portion of the photoelectric conversion region and opposite to the charge holding portion. (14) According to the photoelectric detection device described in (12) or (13), the transmission transistor has a gate electrode, and The gate electrode includes a buried portion disposed adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film, the buried portion extending along the one direction and offset from the center line in a plan view. (15) According to the photoelectric detection device described in (12) or (13), the transmission transistor has a gate electrode, and The gate electrode includes a buried portion that is adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film. The buried portion extends along the one direction and is disposed on both sides of the center line in a plan view. (16) According to the photoelectric detection device described in (12) or (13), the transmission transistors are respectively arranged on both sides of the center line in the plan view. (17) According to the photoelectric detection device described in (12) or (13), the transmission transistor includes a gate electrode disposed on the outer side of the first facet of the semiconductor layer through a gate insulating film, and The gate electrode is configured to cross the center line in the plan view. (18) According to any one of (12) to (17) the photoelectric detection device, wherein the charge holding part is connected to the side part of the photoelectric conversion region. (19) A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed on the semiconductor layer such that it is adjacent to the isolation region in a planar view, and the photoelectric conversion region has a rectangular planar shape; A photoelectric conversion unit is disposed in the photoelectric conversion region; and Multiple transmission transistors are disposed in the photoelectric conversion region and transmit the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge-retaining portion is disposed in the isolation region such that it is adjacent to the corner of the photoelectric conversion region in a plan view, and The gate electrodes of each of the plurality of transmission transistors are arranged along a direction intersecting a diagonal line extending inward from the corner of the charge holding portion side of the photoelectric conversion region. (20) An electronic device comprising: The photoelectric detection device described in any one of (1) to (19) above; An optical lens that forms an image of the image light from the subject on the imaging surface of the photoelectric detection device; and A signal processing circuit that performs signal processing on the signal output from the photoelectric detection device.

[0306] The scope of this technology is not limited to the exemplary embodiments shown in the accompanying drawings and described above, but includes all embodiments that produce effects equivalent to those intended to be produced by this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention as defined by the claims, but can be defined by any desired combination of specific features among all disclosed features. List of reference numerals

[0307] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L Solid-state imaging devices 2 Semiconductor chips 2A pixel array section 2B Peripheral Department 3 pixels 4 Vertical drive circuit 5-column signal processing circuits 6. Horizontal drive circuit 7 Output Circuit 8. Control Circuit 10-pixel drive line 11 Vertical signal lines 12 Horizontal Signal Lines 13 Logic Circuits 14. Bonding pads 15-pixel block 16-pixel circuit 21 Semiconductor layer 22 Photoelectric conversion region 22a1, 22a2, 22a3, 22a4 External perimeter 22c Central part 22d1, 22d2 diagonals 22S1, 22S2, 22S3, 22S4 corners 22X photoelectric conversion unit 23 p-type trap region 24 n-type semiconductor region 24a Main Semiconductor Division 24b Prominent Semiconductor Section 25, 25L, 25R Photoelectric Conversion Unit 26 photoelectric conversion units 26L and 26R photoelectric conversion regions 27 n-type semiconductor region 28 Impurity diffusion isolation area 29, 29R1, 29R2 virtual lines 31. Quarantine Area 31x First Extension 31y Second Extension 31xy intersection (intersection point) 32 Excavation section 33 Insulating film 35 Discontinuities 36 First vertical section 36a Shallow groove section 36b Insulating film 37 Second vertical section 37a Excavation Section 37b Insulating film 38 Steps 39 Internal isolation barrier 41 Side contact area 51 Excavation Section 52 Gate insulating film 53, 54 Gate electrodes 55a, 55b Main electrode regions 56 Gate electrode 56a Head 56b Main part (embedded part) 56b1 (part) 56b2 Another part 57 Sidewall 58 Gate electrode 58a Head 58b Main body 59 Gate electrode 61 Planarization film 63 Filter layers 63a Filter Section 64 Lens layers 64a microlens 64a1 central axis 210 First matrix 211 Semiconductor layer (first semiconductor layer) 212 sensor pixels 213 pixel area 220 Second matrix 221 Semiconductor layer (second semiconductor layer) 222-pixel circuit (readout circuit) 223 pixel drive line 224 Vertical drive line 230 Third matrix 231 Semiconductor Layer 232 Logic Circuits 233 Vertical Drive Circuit 234-column signal processing circuit 235 Horizontal Drive Circuit 236 System Control Circuit 300 electronic devices 301 Solid-state camera device 302 Optical Lens (Optical System) 303 shutter mechanism 304 drive circuit 305 Signal Processing Circuit 306 Incident light AMP amplification transistor Cd, Cd1, Cd2 directions FD, FD1, FD2, FD3, FD4 n-type floating diffusion regions Q pixel transistor RST reset transistor SEL selects transistors S1 First Face S2 Second Face TRL, TRL-1, and TRL-2 are transmission transistors with lateral structures. TRV, TRV1, TRV2, TRV1, TRV2, TRV-1, TRV-2 are vertically oriented transmission transistors. WC power contact area Lv1, Lv2, Lv3 center lines R1, R2, R3 main charge transport paths

Claims

1. A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed on the semiconductor layer such that it is adjacent to the isolation region in a planar view, and the photoelectric conversion region has a rectangular planar shape; A photoelectric conversion unit is disposed in the photoelectric conversion region; as well as A transmission transistor is disposed in the photoelectric conversion region and transmits the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge holding portion is disposed in the isolation region in a manner that crosses the center line, which in the plan view is orthogonal to the outer periphery of the two corners of the photoelectric conversion region and passes through the center of the photoelectric conversion region.

2. The photoelectric detection device according to claim 1, wherein, The transmission transistor is arranged in a position in the plan view that is closer to the charge holding portion than the center of the photoelectric conversion region and opposite to the charge holding portion.

3. The photoelectric detection device according to claim 1, wherein, The transmission transistor has a gate electrode, and The gate electrode includes a buried portion disposed adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film, the buried portion extending along the one direction and offset from the center line in a plan view.

4. The photoelectric detection device according to claim 1, wherein, The transmission transistor has a gate electrode, and The gate electrode includes a buried portion that is adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film. The buried portion extends along the one direction and is disposed on both sides of the center line in a plan view.

5. The photoelectric detection device according to claim 1, wherein, The transmission transistors are individually arranged on both sides of the center line in the plan view.

6. The photoelectric detection device according to claim 1, wherein, The transmission transistor has a gate electrode disposed on the outer side of the first facet of the semiconductor layer, separated by a gate insulating film, and The gate electrode is configured to cross the center line in a planar view.

7. The photoelectric detection device according to claim 1, wherein, The charge retention section is connected to the side portion of the photoelectric conversion region.

8. The photoelectric detection device according to claim 1, wherein, The center line is the main transmission path, through which the transmission transistor transmits signal charge from the photoelectric conversion unit to the charge holding unit.

9. The photoelectric detection device according to claim 1, wherein, The center of the photoelectric conversion region is the intersection point of the two diagonals of the photoelectric conversion region.

10. The photoelectric detection device according to claim 1, further comprising a pixel circuit, the pixel circuit reading a signal charge held in the charge holding portion, and outputting a pixel signal based on the read signal charge, wherein, The pixel transistors included in the pixel circuit are disposed in the photoelectric conversion region.

11. The photoelectric detection device according to claim 1, wherein the semiconductor layer is used as the first semiconductor layer, and the photoelectric detection device further comprises: A second semiconductor device is disposed such that it overlaps with the first semiconductor layer in the one direction; and A pixel circuit reads the signal charge held in the charge holding section and outputs a pixel signal based on the read signal charge, wherein... The pixel transistors included in the pixel circuit are disposed on the second semiconductor layer.

12. A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion unit is disposed on the semiconductor layer in a planar view adjacent to an isolation region, and includes two photoelectric conversion regions formed in a rectangular planar shape; A photoelectric conversion unit is disposed in each of the two photoelectric conversion regions; as well as A transmission transistor is disposed on the first facet side of the semiconductor layer in each of the two photoelectric conversion regions, and transmits the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge holding portion is disposed in the isolation region in a manner that crosses the center line, which in the plan view is orthogonal to the outer periphery of the two corners of the photoelectric conversion region and passes through the center of the photoelectric conversion region.

13. The photoelectric detection device according to claim 12, wherein, The transmission transistor is arranged in a position in the plan view that is closer to the charge holding portion than the center of the photoelectric conversion region and opposite to the charge holding portion.

14. The photoelectric detection device according to claim 12, wherein, The transmission transistor has a gate electrode, and The gate electrode includes a buried portion disposed adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film, the buried portion extending along the one direction and offset from the center line in a plan view.

15. The photoelectric detection device according to claim 12, wherein, The transmission transistor has a gate electrode, and The gate electrode includes a buried portion that is adjacent to the semiconductor layer of the photoelectric conversion region through a gate insulating film. The buried portion extends along the one direction and is disposed on both sides of the center line in a plan view.

16. The photoelectric detection device according to claim 12, wherein, The transmission transistors are individually arranged on both sides of the center line in the plan view.

17. The photoelectric detection device according to claim 12, wherein, The transmission transistor includes a gate electrode disposed on the outer side of the first facet of the semiconductor layer, separated by a gate insulating film, and The gate electrode is configured to cross the center line in the plan view.

18. The photoelectric detection device according to claim 12, wherein, The charge retention section is connected to the side portion of the photoelectric conversion region.

19. An electronic device comprising: Photoelectric detection device; An optical lens that forms an image of the light from the subject on the imaging surface of the photoelectric detection device; as well as The signal processing circuit performs signal processing on the signal output from the photoelectric detection device, wherein... The photoelectric detection device includes: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed on the semiconductor layer such that it is adjacent to the isolation region in a planar view, and the photoelectric conversion region has a rectangular planar shape; A photoelectric conversion unit is disposed in the photoelectric conversion region; and A transmission transistor is disposed in the photoelectric conversion region and transmits the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge holding portion is disposed in the isolation region in a manner that crosses the center line, which in the plan view is orthogonal to the outer periphery of the two corners of the photoelectric conversion region and passes through the center of the photoelectric conversion region.

20. A photoelectric detection device, comprising: A semiconductor layer having a first facet and a second facet located on opposite sides of each other in one direction; A photoelectric conversion region is disposed on the semiconductor layer such that it is adjacent to the isolation region in a planar view, and the photoelectric conversion region has a rectangular planar shape; A photoelectric conversion unit is disposed in the photoelectric conversion region; as well as Multiple transmission transistors are disposed in the photoelectric conversion region and transmit the signal charge generated by the photoelectric conversion unit through photoelectric conversion to the charge holding unit, wherein... The charge-retaining portion is disposed in the isolation region such that it is adjacent to the corner of the photoelectric conversion region in a plan view, and The gate electrodes of each of the plurality of transmission transistors are arranged along a direction intersecting a diagonal line extending inward from the corner of the charge holding portion side of the photoelectric conversion region.

21. The photoelectric detection device according to claim 20, wherein, The gate electrode of each of the plurality of transmission transistors is located in the plan view closer to the charge holding portion than the center of the photoelectric conversion region.

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