Long-distance moving target millimeter wave radar detection system

Abstract

The invention discloses a long-distance moving target millimeter wave radar detection system, which belongs to the technical field of microwave antennas and comprises a radio frequency front-end module, a transmitting antenna module, a receiving antenna module and a rear-end control and baseband signal processing platform. The radio frequency front-end module comprises a ramp generator, a path phase shifter, a power amplifier, a frequency mixer, a low-noise amplifier and an analog-to-digital converter which are in communication connection in sequence; the transmitting antenna unit is used for transmitting millimeter wave signals; the receiving antenna unit is used for receiving an echo signal reflected from the target object; the rear-end control and baseband signal processing platform comprises a PS-end ARM unit and a PL-end FPGA unit, the output end of the PS-end ARM unit is in communication connection with the input end SPI of the ramp generator of the radio frequency front-end module, and the input end of the PL-end FPGA unit is in communication connection with the analog-to-digital converter of the radio frequency front-end module.

Description

Technical Field

[0001] This invention relates to the field of microwave antenna technology, and in particular to a millimeter-wave radar detection system for long-range moving targets. Background Technology

[0002] In recent years, with the development of new technologies such as autonomous driving, vehicle-to-everything (V2X) communication, and intelligent transportation, millimeter-wave radar has gradually become an indispensable functional sensor in the transportation field. Compared with other sensors such as cameras and loop coils, millimeter-wave radar has advantages such as strong penetration through rain, snow, and smoke, immunity to light and illumination, high measurement accuracy, and long detection range. It also possesses all-weather, all-domain detection capabilities and continuous multi-target tracking capabilities, and its raw data carries target speed information. Currently, the mainstream millimeter-wave radar detection range in the transportation field is generally around 300-500 meters. In long-distance road sections, this presents problems such as excessive deployment and high maintenance costs, while also increasing the difficulty of edge processors fusing multi-radar data. With the emergence of concepts such as smart highways, long-range detection millimeter-wave radar has become one of the research hotspots in the radar field to reduce the construction costs of smart highways. Long-range millimeter-wave radar can demonstrate significant advantages in urban expressways and highways.

[0003] Based on the above analysis, the existing technology has the following problems and shortcomings: short-range radar has low spatial coverage and cannot effectively cover long-distance road sections, thus increasing deployment and maintenance costs. Therefore, how to better achieve coverage of long and wide road sections using long-range millimeter-wave radar and significantly reduce construction costs is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a long-range roadside millimeter-wave radar detection system that can better cover longer and farther road sections and detect moving targets, thereby significantly reducing construction costs.

[0005] This invention addresses the need for long-range moving target detection by completing the research and design of a frequency modulated continuous wave (FMCW) phased array millimeter-wave radar; it addresses the radar detection capability issue by completing the design of a multi-chip cascaded radar RF front-end and back-end control and processing platform; and it addresses the moving target detection problem by designing a beam scanning-based radar signal processing scheme and implementing the target detection algorithm on a Zynq series back-end processor.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a long-range moving target millimeter-wave radar detection system, comprising a radio frequency front-end module, a transmitting antenna module, a receiving antenna module, and a back-end control and baseband signal processing platform;

[0007] The radio frequency front-end module includes a ramp generator, a path phase shifter, a power amplifier, a mixer, a low-noise amplifier, and an analog-to-digital converter, which are connected in sequence via communication.

[0008] The transmitting antenna unit is used to transmit millimeter-wave signals;

[0009] The receiving antenna unit is used to receive the echo signal reflected back from the target object;

[0010] The back-end control and baseband signal processing platform includes a PS-side ARM unit and a PL-side FPGA unit. The PS-side ARM unit and the PL-side FPGA unit transmit data through an internal high-speed interface AXI bus. The output of the PS-side ARM unit is connected to the input of the ramp generator of the RF front-end module via SPI communication, and the input of the PL-side FPGA unit is connected to the analog-to-digital converter of the RF front-end module via communication.

[0011] RF Front-End Module: The millimeter-wave radar RF front-end adopts an 8-chip cascaded ADT2011 scheme, including one master chip and seven slave chips, as shown in the attached diagram. Figure 1 As shown in the diagram, the main chip and three slave chips located at the bottom of the architecture diagram are configured as transmitter chips via the SPI interface. All 16 channels of each chip transmit FMCW signals, forming the transmitter section of the RF front-end. The other four chips are configured as receiver chips via the SPI interface. All 16 channels of each chip receive FMCW signals, forming the receiver section of the RF front-end, and outputting four intermediate frequency (IF) IQ signals.

[0012] Transmitter and Antenna Receiver Module: Based on the RF front-end design, the antennas are arrayed, as shown in the attached diagram. Figure 2 As shown. A single radar antenna is a 12*1 microstrip patch linear array fed in series.

[0013] Back-end control and signal processing platform: The processor module selected is the XILINX Zynq7100 series SoC processor as the radar baseband processor, as shown in the attached diagram. Figure 3 As shown in the attached diagram, the radar hardware platform consists of a processor system (PS) and programmable logic (PL). The PS is composed of a dual-core ARM Cortex-A9 application processor unit, and the PL is the FPGA part. Data transmission between the two is achieved through the AXI bus of the internal high-speed interface (HP). Based on the baseband signal processing requirements of long-range millimeter-wave radar, a millimeter-wave radar back-end control and processing hardware platform was designed, as detailed in the attached diagram. Figure 4 As shown. Each ADT2011 receiver chip outputs one IQ intermediate frequency analog signal. According to the RF front-end design, there are a total of 4 receiver chips. Therefore, an ADC module is needed to sample the intermediate frequency signals output by the RF front-end and input them into the processor module for signal processing. The ADC module system block diagram is attached. Figure 5 As shown.

[0014] Specific system solution: The processor module controls the RF frequency synthesizer of the RF front-end via the SPI interface to generate a linear frequency modulated (LFM) signal of a specified frequency. This LFM signal is then up-converted to the specified frequency output via a x4 frequency multiplier. In the RF front-end's transmitting module, the up-converted signal is phase-shifted, amplified by a power amplifier, and radiated to the external environment via a transmitting antenna. In the RF front-end's receiving module, the up-converted LFM signal serves as the local oscillator signal for the mixer. This signal, along with the echo signal received by the receiving antenna (amplified by a low-noise amplifier and phase-shifted), is down-converted by the mixer to obtain the intermediate frequency (IF) IQ signal. This IF signal is sampled by an ADC and sent to the processor module for radar signal processing and data processing, ultimately obtaining information such as the target's distance, speed, and angle.

[0015] Radar Signal and Processing Scheme: The radar beam's main lobe points in different directions during scanning. Target detection is performed once during the dwell time in each beam direction. The 128 chirp signals received in each beam direction are processed using a two-dimensional FFT algorithm to obtain the target's range and velocity information. Based on the different detection power of the target under different beam directions, the target's angle information can be estimated, ultimately yielding the target's position and velocity information. A flowchart is attached. Figure 6 As shown. The design and specific functional implementation process of each module are as follows:

[0016] Beam control module: The beam scanning configuration of the RF chip is implemented by the beam control module at the PS end of the processor module. The beam control module calls the register read and write functions at the PS end, configures the RF chip registers through SPI, controls the waveform information of the transmitted chirp signal, and controls the processor to write phase shifter codes to the RF chip to switch different beam directions.

[0017] Time-domain coherent accumulation processing: After each beam pointing switch, the beam control module triggers the intermediate frequency (IF) synchronization acquisition module in the PL terminal of the processor module. The IF synchronization acquisition module triggers a frame of 128 chirp signals through the RF front-end's I / O port, and simultaneously triggers the PL terminal to acquire and process the IF signal. Time-domain coherent accumulation completes the non-coherent accumulation of the IF data output from the four receiving chips in the time domain, combining the four data streams into a single output.

[0018] Two-dimensional FFT processing: The merged ADC data is processed by a two-dimensional FFT algorithm to obtain the RDM matrix of a frame of Chirp signal on each beam. First, the data is processed by the range dimension FFT through the IP core. The processed data is transposed through the buffer Bram and then input into the velocity dimension FFT module for a second FFT processing. The power information of each complex signal output is obtained by summing the squares to obtain the RDM matrix of a frame of Chirp intermediate frequency signal.

[0019] Constant False Alarm Rate (CFAR) Detection: The two-dimensional CFAR detection algorithm includes CFAR detection in both the velocity and range dimensions. The output of the velocity-dimensional FFT serves as the input for the velocity-dimensional CFAR detection; simultaneously, after buffering, it is transposed to obtain the input data for the range-dimensional CFAR algorithm. After performing CFAR detection in both the range and velocity dimensions on each target in the RDM matrix, a beam pointing upwards is obtained to detect the true target information.

[0020] Point clustering algorithm: The PL end transmits the CFAR data pointing to each beam to the DDR of the PS end via the AXI interface. After the PS end receives the CFAR data pointing to all beams, it performs clustering algorithm processing on the data pointing to all beams to filter out false alarm noise points in constant false alarm detection and to identify the same target detected by beams at different angles. This completes the intermediate frequency signal processing flow of one beam scan. Specifically, the DBSCAN algorithm is used for clustering processing. Based on the distance, amplitude, angle, signal strength, and other information of the target point data, the point data is classified. While removing noise points, the classified data is also processed. The information of targets belonging to the same class is weighted according to the signal strength to obtain more accurate target motion state information.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] 1. The front-end system and antenna array were designed based on the cascaded RF chip scheme, which improved the radar detection power and effectively enhanced the radar antenna transmit and receive gain.

[0023] 2. To address the increased bandwidth and data volume of the ADC raw data caused by cascading multiple RF chips, a baseband processing hardware platform based on the Zynq7100 SoC processor and high-speed memory such as DDR3L was designed to improve the processing capability and efficiency of radar baseband signals.

[0024] 3. For the detection of long-range moving targets in traffic under beam scanning, a signal processing scheme based on beam scanning is designed, and the temporal coherent accumulation method is verified. This method can improve the signal-to-noise ratio for real target detection.

[0025] 4. The coherently accumulated ADC data was processed by a two-dimensional FFT algorithm, and the two-dimensional CFAR constant false alarm rate detection algorithm and DBSCAN clustering algorithm were used to detect traffic targets and perform subsequent processing, proving the effectiveness of the beam scanning scheme for target detection. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the phased array millimeter-wave radar radio frequency front-end architecture in this embodiment.

[0027] Figure 2 This is a schematic diagram of the antenna array design in this embodiment.

[0028] Figure 3 This is a schematic diagram of the Zynq7100 SoC architecture in this embodiment.

[0029] Figure 4 This is a hardware schematic diagram of the millimeter-wave radar baseband processing platform in this embodiment.

[0030] Figure 5 This is a system block diagram of the ADC module in this embodiment.

[0031] Figure 6 This is a schematic diagram of the beam scanning-based signal processing scheme in this embodiment.

[0032] Figure 7 This is a hardware diagram of the millimeter-wave radar radio frequency front-end in this embodiment.

[0033] Figure 8 This is a schematic diagram of the RF front-end power tree in this embodiment.

[0034] Figure 9 This is a simulation diagram of a single antenna HFSS in this embodiment.

[0035] Figure 10 This is a hardware diagram of the millimeter-wave radar baseband processing board in this embodiment.

[0036] Figure 11 This is a schematic diagram of the single-chip ADC design in this embodiment.

[0037] Figure 12 This is a schematic diagram of the baseboard power tree design in this embodiment.

[0038] Figure 13 This is the SPI timing diagram in this embodiment.

[0039] Figure 14 This is a schematic diagram of the SPI state machine configuration in this embodiment.

[0040] Figure 15 This is a schematic diagram of the ADC data output format in this embodiment.

[0041] Figure 16 This is a flowchart of the time-domain coherent accumulation module in this embodiment.

[0042] Figure 17 This is a flowchart of the two-dimensional FFT module in this embodiment.

[0043] Figure 18 This is a flowchart of the constant false alarm detection module in this embodiment.

[0044] Figure 19 This is a schematic diagram for calculating the average noise in this embodiment.

[0045] Figure 20 This is a schematic diagram of the two-dimensional CFAR detection simulation in this embodiment.

[0046] Figure 21 This is a schematic diagram of the target structure array in this embodiment.

[0047] Figure 22 This is a schematic diagram of the core point discrimination module in this embodiment.

[0048] Figure 23 This is a schematic diagram of the extended operation in this embodiment. Detailed Implementation

[0049] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0050] This embodiment discloses a long-range moving target millimeter-wave radar detection system, starting with the design of the radio frequency (RF) front-end. Based on the internal architecture, interface pins, and power supply requirements of the ADT2011 chip, the hardware architecture of the long-range millimeter-wave radar RF front-end is designed as shown in the attached figure. Figure 1 As shown in the diagram. Based on the radar RF front-end cascade schematic, the designed millimeter-wave radar RF front-end hardware is as follows. Figure 7 As shown. The main hardware components of the RF board include: 8 ADT2011 chips, 64 transmit antennas, 64 receive antennas, 2 ERM5-040 connectors, 3 LTM4644IY DC / DC buck regulators, 8 MAX15103EWL low dropout linear regulators, 4 ADP150AUJZ low dropout linear regulators, 7 Wilkinson power dividers, and one DXA2570003-125MHz passive crystal oscillator.

[0051] According to the design of the RF front-end cascade architecture, this main chip is connected to a passive crystal oscillator to generate a local oscillator (LO) signal (19GHz to 20.25GHz) shared by all chips in the cascade system. The LO signal is buffered and amplified locally on the chip. Except for the chip at the end of the cascade design, the LO signal of each chip is split by a 20GHz Wilkinson LO power divider and introduced through the LO input to drive two RF chips.

[0052] The two connectors serve as the control interface for leading out eight ADT2011 chips and the four IQ intermediate frequency outputs for four receiver chips, and are connected to the 12V power rail.

[0053] The LTM4644IY buck regulator (4A maximum current per channel, supports 4 outputs) serves as the PMIC for the RF board. Two PMICs generate eight 1.5V power rails, which are then converted to 1.35V by a MAX15103EWL low-dropout linear regulator (4A maximum current per channel) to power eight ADT2011 RF chips. One PMIC generates two 5.5V power rails, which are converted to one 3.3V power rail by an ADP150AUJZ low-dropout linear regulator to power the digital section of the chip and the DXA2570003-125MHz passive crystal oscillator. Three ADP150AUJZ low-dropout linear regulators generate three 1.2V power rails to power the RF, baseband, and analog sections of the ADT2011 chip. The RF front-end power tree design is as follows: Figure 8 As shown.

[0054] Further, the design of the transceiver antenna is discussed. Simulations were performed on the bandwidth and beam pattern of a single-wire series-fed 12*1 microstrip patch antenna, and the results are as follows: Figure 9 As shown in the figure. Simulation results show that the operating bandwidth of a single antenna is around 2GHz (-10dB), the S11 at 77GHz is -21.71dB, and the maximum gain is 17.51dBi. The gain of a single antenna does not meet the system's requirements for the antenna array gain, therefore an array is required.

[0055] The RF front-end has four transmitter chips and four receiver chips, each with 16 channels, resulting in 64 elements for both transmission and reception, with an array spacing of λ / 2. The theoretical total transmit and receive gains of the antenna array can be derived from the antenna gain of a single antenna. The final total transmit gain is 29.061 dB, and the total receive gain is also 29.061 dB. The sum of these two values ​​meets the performance specifications, verifying the feasibility of the design.

[0056] Further, the design of the back-end control and processing platform is discussed. The millimeter-wave radar back-end control and processing platform uses the XC7Z100-FFG900-2I as the main processor chip and integrates an ADC module to process multiple intermediate frequency data streams. The processing board's hardware resources also include: four Micron DDR3L memory chips, four AD9251 chips, two QSPI FLASH chips, one 88E1518 Gigabit Ethernet chip, one SD card, one eMMC chip, one serial port, and two ERM5-040 connectors. The millimeter-wave radar baseband processing board hardware is as follows... Figure 10 As shown.

[0057] In the design, two ERM5-040 connectors serve as the control interface for leading out eight ADT2011 chips and four IQ intermediate frequency outputs for four receiver chips, and also output a 12V power supply. The control interface is used for SPI communication between the processor and the RF chip, as well as for inputting FMCW synchronization signals and resetting the control chip.

[0058] Simultaneously, the connector sends four analog IQ signals to four AD9251 chips for analog-to-digital conversion. The digital output signal of the ADC is sent to the processor module for baseband signal processing. The four ADC chips are connected to the same clock to achieve sampling synchronization. The four ADC chips operate on a 1.8V power rail, support two pairs of differential analog signal inputs, and control all internal conversion cycles through a 30MHz differential clock input.

[0059] The chip's digital outputs include two pairs of data clock outputs and two 14-bit parallel data outputs. The analog input pins of the four chips are connected to the RF analog output pins via connectors, and the digital outputs and SPI configuration pins are connected to the processor via LVCMOS pins. The schematic diagram of the AD9251 chip is attached. Figure 11 As shown. The overall hardware platform has an external input voltage of 12V, and internally, a multi-channel power supply module converts the external input voltage to the operating voltage of each component. The power tree design of the baseboard is attached. Figure 12 As shown.

[0060] Furthermore, the engineering implementation of millimeter-wave radar signal processing for long-range traffic target detection is based on a back-end control and processing platform. First, the ADC module driver needs to be configured to establish the data link. Based on the chip's SPI timing, a state machine is used to configure the ADC chip's registers. The driver configures the ADC chip's output data format to binary two's complement, with a clock duty cycle of 50%. The chip's SPI timing and state machine flow are shown in the attached figure. Figure 13 , 14 As shown in the attached diagram. The ADC driver module continuously acquires intermediate frequency signals during operation, and the four channels of IQ data output by the synchronization control module are shown in the attached diagram. Figure 15 As shown.

[0061] Furthermore, the time-domain coherent accumulation module is implemented using an FPGA. This module primarily performs coherent accumulation of the intermediate frequency (IF) data output from the four receiving chips in the time domain, combining the four data streams into a single output to improve the signal-to-noise ratio for target detection. The coherent accumulation is performed in a pipelined manner to enhance the efficiency of IF signal detection. Its input and related processes are shown in the attached figure. Figure 16 As shown, the four I and Q signals of the four IQ signals are expanded and then directly added together by a combinational logic adder module to generate a single 17-bit IQ signal.

[0062] In the DC component acquisition module, the effective ADC data within each chirp is expanded and continuously accumulated, stored in a register. A counter counts the number of accumulated data points for each chirp signal. When the accumulated count equals Nfft, the register is averaged by truncation to obtain the DC component of the effective ADC data within each chirp signal, and the register is then cleared to 0. The DC removal operation, under combinational logic, subtracts the DC component of the corresponding effective data from the data buffer FIFO. The de-DC signal requires truncating one most significant data bit to eliminate signal interference caused by near-field antenna coupling and improve the signal-to-noise ratio of the reflected echo signal from distant targets.

[0063] The cross-clock domain output module merges a pair of 16-bit IQ data after DC removal into 32 bits and then converts them from the 60MHz ADC data clock to the 100MHz signal processing clock domain via an asynchronous FIFO. Since it is a conversion from a slow clock domain to a fast clock domain, the asynchronous FIFO IP core is used to control the cross-clock domain data read and write, which improves the generation of metastability.

[0064] Further, we present the FPGA implementation of the 2D FFT module. The two-dimensional FFT algorithm is used to process the coherently accumulated ADC data to obtain the RDM matrix. The design flow of the 2D FFT module is attached. Figure 17 As shown, the distance-dimensional FFT module performs windowing processing on a frame of signal, then processes the windowed IQ data through the FFT operation IP core. The output is then output to the velocity-dimensional FFT module after the data arrangement order is adjusted through the data buffer RAM. The output of the FFT IP core is used to perform spectrum shifting and zero-velocity data removal through the BRAM, and finally output to the constant false alarm rate detection module.

[0065] Furthermore, the FPGA implementation of the constant false alarm rate (CFAR) detection algorithm includes distance-dimensional CFAR and velocity-dimensional CFAR modules. Each module operates in a pipelined manner to improve the speed of target detection.

[0066] The flowchart for the constant false alarm detection module is attached. Figure 18As shown. The data buffer RAM1 stores the results of the radar velocity-dimensional FFT. After the data order is adjusted, it is used for range-dimensional CFAR detection. There are a total of 512*128 data points. When reading data, under the control of the enable signal, starting from the address of the starting data, 512 data points are read from the RAM buffer each time, and after reading 128 data points, starting from the next data point of the starting data, one data point is read from the RAM buffer each time, and a total of 128 data points are read. This operation continues until all data in one frame is read, completing the data transpose.

[0067] The threshold of the CA-CFAR algorithm is the product of the average noise of the training units near the tested unit and the threshold factor. The number of training units and guard units are set to 8 and 1, respectively. The threshold value is calculated using a shift register. First, the average noise data of every 8 units is calculated. The input data is saved with a delay using a shift register array. The unshifted data is subtracted from the data after a delay of 8 clock cycles, triggered by the rising edge of the clock, to obtain the intermediate value of the noise calculation. This intermediate value is then cyclically accumulated with itself, and the last 3 bits are truncated for averaging. This yields the average noise data of every 8 units. The calculation process is shown in the attached figure. Figure 19 As shown.

[0068] The average noise data is stored in a shift register array. The average noise of the training units on the left and right sides of the unit under test differs by 12 clock cycles in timing (for example, for the 10th unit, the left average noise is the sum of the average noise of the 1st to 8th units, and the right average noise is the sum of the average noise of the last 8 units starting from the 12th unit). Therefore, the unshifted average noise data is added to the average noise data after a delay of 12 clock cycles to obtain the sum of the average noise of the left and right training units of the unit under test. Multiplying this by a threshold factor yields the threshold value.

[0069] The tested unit is compared with a threshold value. If it is greater than the threshold value, the unit is confirmed as a target and the output is 1; otherwise, the output is 0. After all tested units have been detected, a one-dimensional CFAR detection result is output. To ensure the timing synchronization of the velocity and distance dimension CFAR output results, the velocity dimension CFAR output result is cached in RAM2 and transposed to the distance dimension using the same write order as RAM1 before output. After a delay and synchronization, the two CFAR results are logically ANDed to output the final detection result. Single-target data is collected, and timing simulation is performed on the Vivado platform to verify the performance of the CFAR detection algorithm on the FPGA. The simulation results are attached. Figure 20 As shown. After time synchronization, both distance and velocity dimension detections will distinguish the target and output it synchronously.

[0070] Further, the implementation of the point clustering algorithm is described. The DBSCAN clustering algorithm is used to process the target point data detected by the CFAR algorithm. The CFAR-processed data is written to the PS-side DDR memory via DMA. Following the CFAR algorithm's output data format, the position indices of the target in the range and velocity dimensions are read, and a target data structure array is constructed, storing the information of each target in the array. The structure contains the target's range index, velocity index, beam angle index, and power information detected in the velocity FFT, clustering state, etc., such as... Figure 21 As shown.

[0071] In this process, targets grouped into the same cluster after DBSCAN processing have a cluster state of 0 for the first cluster, a cluster state of -1 for unprocessed targets, and a cluster state of -2 for targets classified as noise after processing. The DBSCAN algorithm runs once after the radar completes one beam scan and the detected targets for each beam are stored in the data structure. The specific process is as follows:

[0072] (1) Select the first target detected after one beam scan as the starting point, and search for all targets in the domain by traversing the neighborhood relationships between this point and each of the remaining target points. Update the linked list with the points that pass the neighborhood relationship judgment using the tail insertion method. The core point discrimination module is shown in the figure below. Figure 22 As shown.

[0073] (2) After traversing all remaining target points, a linked list 1 is obtained. If the number of targets in the linked list is less than the threshold, the tested point is judged to be noise. At this time, return to step 1 and cluster the next target. If the number of targets in the linked list is greater than the threshold, update the clustering status of each point in the linked list and continue to check whether the target points in its neighborhood are core points to realize the expansion of the cluster. Traverse the neighborhood relationship between each target point in the linked list and all remaining unclustered targets, and construct a linked list 2 to connect the point with all target points in its neighborhood. The illustration of the expansion from the targets in linked list 1 is attached. Figure 23 As shown.

[0074] (3) Detect the clustering status of each target point in linked list 2, find points with an unclassified or noisy clustering status, update the status of these points to match the clustering status of the targets in linked list 1, and insert each target in linked list 2 into the original linked list 1. After completing the above expansion operation for all target points corresponding to all nodes in linked list 1, the clustering operation of one target is completed. Perform the same operation on the next unclustered point. Repeat this process until all target information in one beam scan is clustered.

[0075] The power of targets in the same cluster is summed to obtain the power sum information of that cluster. The beam angle of each target is multiplied by the power information of that target and then summed to obtain the weighted angle sum information of the targets. The angle sum information is divided by the power sum information to obtain the weighted average angle information. The range index of targets in the same cluster is summed to obtain the range sum information. The velocity index of each target is summed to obtain the velocity sum information. The range sum information and velocity sum information of the targets are divided by the number of targets in that cluster to finally obtain the range and velocity information of the targets relative to the radar.

[0076] Although the present invention has been disclosed above with reference to preferred embodiments, the embodiments and accompanying drawings are not intended to limit the invention. Any person skilled in the art can make various changes or modifications without departing from the spirit and scope of the invention, and these changes will also be within the protection scope of the invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims of this application.

Claims

1. A millimeter-wave radar detection system for long-range moving targets, characterized in that: It includes an RF front-end module, a transmitting antenna module, a receiving antenna module, and a back-end control and baseband signal processing platform; The radio frequency front-end module includes a ramp generator, a path phase shifter, a power amplifier, a mixer, a low-noise amplifier, and an analog-to-digital converter, which are connected in sequence via communication. The transmitting antenna unit is used to transmit millimeter-wave signals; The receiving antenna unit is used to receive the echo signal reflected back from the target object; The back-end control and baseband signal processing platform includes a PS-side ARM unit and a PL-side FPGA unit. The PS-side ARM unit and the PL-side FPGA unit transmit data through an internal high-speed interface AXI bus. The output of the PS-side ARM unit is connected to the input of the ramp generator of the RF front-end module via SPI communication, and the input of the PL-side FPGA unit is connected to the analog-to-digital converter of the RF front-end module via communication.

2. The long-range moving target millimeter-wave radar detection system according to claim 1, characterized in that: The RF front-end module uses eight ADT2011 chips cascaded together, including one master chip and seven slave chips. The master chip and three slave chips located below the RF board are configured as transmitter chips through the SPI interface. All 16 channels of each chip transmit FMCW signals, forming the transmitter part of the RF front-end. In addition, four chips located on the top of the RF board are configured as receiver chips via the SPI interface. All 16 channels of each chip receive FMCW signals, forming the receiver section of the RF front end, and outputting four intermediate frequency IQ signals.

3. The long-range moving target millimeter-wave radar detection system according to claim 2, characterized in that: In the RF front-end module, the main chip is connected to a passive crystal oscillator to generate a local oscillator signal shared by all chips in the cascade system. The local oscillator signal is buffered and amplified locally on the chip. Except for the end chip in the cascade design, the local oscillator signal of each chip is split by a 20GHz local oscillator power divider and introduced into the local oscillator input to drive two RF chips. Two connectors serve as control interfaces for leading out eight ADT2011 chips and four IQ intermediate frequency outputs for four of the receiving chips, and are connected to a 12V power rail. The step-down regulator serves as the PMIC for the RF board. The eight 1.5V power rails generated by the two RF board PMICs are converted into 1.35V power by a low-dropout linear regulator to power the eight ADT2011 RF chips. The two 5.5V power rails generated by the one RF board PMIC are converted into one 3.3V power rail by a low-dropout linear regulator to power the digital section of the chip and the passive crystal oscillator. The three 1.2V power rails generated by three ADP150AUJZ low-dropout linear regulators power the RF, baseband and analog sections of the ADT2011 chip.

4. A long-range moving target millimeter-wave radar detection system according to claim 1, characterized in that: In the transmitting antenna unit and the receiving antenna unit, a single radar antenna is a 12*1 microstrip patch linear array that is fed in series.

5. A long-range moving target millimeter-wave radar detection system according to claim 1, characterized in that: The back-end control and baseband signal processing platform uses the XC7Z100-FFG900-2I as the main processor chip and integrates an ADC module to process multiple intermediate frequency data. The hardware of the processing board also includes: 4 Micron DDR3L memory chips, 4 AD9251 chips, 2 QSPIFLASH chips, 1 88E1518 Gigabit Ethernet chip, one SD card, one EMMC chip, one serial port, and 2 ERM5-040 connectors. Two ERM5-040 connectors serve as the control interface for leading out eight ADT2011 chips and four IQ intermediate frequency outputs from four of the receiving chips, and also output a 12V power supply. The control interface is used for SPI communication between the processor and the RF chip, as well as inputting FMCW synchronization signals and controlling chip reset. Simultaneously, the ERM5-040 connectors send four analog IQ signals to four AD9251 chips for analog-to-digital conversion, and the digital output signals of the ADCs are sent to the processor module for baseband signal processing. The four ADC chips are connected to the same clock to achieve sampling synchronization. The four AD chips operate on a 1.8V power rail, supporting two pairs of differential analog signal inputs. All internal conversion cycles are controlled by a 30MHz differential clock input. The chips' digital outputs include two pairs of data clock outputs and two 14-bit parallel data outputs. The analog input pins of the four chips are connected to the RF analog output pins via connectors, and the digital outputs and SPI configuration pins are connected to the processor via LVCMOS pins. The overall hardware platform has an external input voltage of 12V, and internally, a multi-channel power supply module converts the external input voltage to the operating voltage of each device.

6. A long-range moving target millimeter-wave radar detection system according to claim 5, characterized in that: The back-end control and baseband signal processing platform completes the processing of long-range millimeter-wave radar signals. The radar beam main lobe points in different directions during scanning. The target is detected once during the dwell time in each beam direction. The range and velocity information of the target can be obtained after processing the 128 chirp signals received in each beam direction by a two-dimensional FFT algorithm. The angle information of the target can be estimated based on the different detection power of the target under different beam directions. Finally, the position and velocity information of the target are obtained.

7. A long-range moving target millimeter-wave radar detection system according to claim 6, characterized in that: The processing of long-range millimeter-wave radar signals is accomplished based on a back-end control and baseband signal processing platform, using the following modules: Beam control module: The beam scanning configuration of the RF chip is implemented by the beam control module at the PS end of the processor module. The beam control module calls the register read and write functions at the PS end, configures the RF chip registers through SPI, controls the waveform information of the transmitted chirp signal, and controls the processor to write phase shifter codes to the RF chip to switch different beam directions. Time-domain coherent accumulation processing module: After each beam pointing switch, the beam control module triggers the intermediate frequency synchronous acquisition module in the PL terminal of the processor module. The intermediate frequency synchronous acquisition module triggers a frame of 128 chirp signals through the IO port of the RF front end, and simultaneously triggers the PL terminal to acquire and process the intermediate frequency signal; through time-domain coherent accumulation, the non-coherent accumulation of the intermediate frequency data output by the four receiving chips in the time domain is completed, and the four data are combined into one output; Two-dimensional FFT processing module: The merged ADC data is processed by a two-dimensional FFT algorithm to obtain the RDM matrix of a frame of Chirp signal on each beam. First, the data is processed by the IP core for distance dimension FFT. The processed data is then transposed by the buffer Bram and input into the velocity dimension FFT module for secondary FFT processing. The power information of each complex signal output is obtained by summing the squares to obtain the RDM matrix of a frame of Chirp intermediate frequency signal. Constant False Alarm Rate (CFAR) Detection Module: The two-dimensional CFAR detection algorithm includes CFAR detection in the velocity and range dimensions. The output of the velocity dimension FFT serves as the input for the velocity dimension CFAR detection. Simultaneously, after buffering, the output is transposed to obtain the input data for the range dimension CFAR algorithm. After performing CFAR detection in the range and velocity dimensions on each target in the RDM matrix, a beam pointing upwards is obtained to detect the true target information. Point clustering algorithm module: The PL end transmits the CFAR data pointing to each beam to the DDR of the PS end through the AXI interface. After the PS end receives the CFAR data pointing to all beams, it performs clustering algorithm processing on the data pointing to all beams to filter out false alarm noise points in constant false alarm detection and complete the identification of the same target detected by beams at different angles. This completes the intermediate frequency signal processing flow of one beam scan.

8. A long-range moving target millimeter-wave radar detection system according to claim 7, characterized in that: Implementation of the point clustering algorithm: The DBSCAN clustering algorithm is used to process the target point data detected by the CFAR algorithm. The data after CFAR processing is written to the DDR memory of the PS end via DMA. According to the output data format of the CFAR algorithm, the position index of the target in the range dimension and velocity dimension is read out, and a target data structure array is constructed to save the information of each target into the array. The structure contains the target's range dimension index, velocity dimension index, beam angle index, power information detected in the velocity dimension FFT, and clustering state. Among them, the clustering state is marked as the target that is classified into the same class after DBSCAN processing. The clustering state of the first class is 0, the clustering state of the unprocessed target is -1, and the clustering state of the target that is classified as a noise point after processing is -2.

9. A long-range moving target millimeter-wave radar detection system according to claim 8, characterized in that: The DBSCAN algorithm runs once after the radar completes one beam scan and stores the detected targets in each beam into a data structure. The specific process is as follows: The first target detected after a beam scan is selected as the starting point. All targets in the domain are searched by traversing the neighborhood relationships between this point and each of the remaining target points. Points that pass the neighborhood relationship judgment are updated to the linked list using the tail insertion method. After traversing all remaining target points, a first linked list is obtained. If the number of targets in the first linked list is less than a threshold, the tested point is judged to be noise, and the process returns to step 1 to cluster the next target. If the number of targets in the first linked list is greater than a threshold, the clustering state of each point in the first linked list is updated, and the target points in its neighborhood are checked to see if they are core points, thus expanding the cluster. The neighborhood relationship between each target point in the linked list and all remaining unclustered targets is traversed, and a second linked list is constructed to connect the point with all target points in its neighborhood. The clustering status of each target point in the second linked list is detected, and points with an unclassified or noisy clustering status are identified. The status of these points is updated to match the clustering status of the targets in the first linked list. Each target in the second linked list is then inserted into the original first linked list. After the above expansion operation is completed for all target points corresponding to all nodes in the first linked list, the clustering operation for one target is completed. The same operation is then performed on the next unclustered point. This process is repeated until all target information in one beam scan is clustered. The power of targets in the same cluster is summed to obtain the power sum information of that cluster. The beam angle of each target is multiplied by the power information of that target and then summed to obtain the weighted angle sum information of the targets. The angle sum information is divided by the power sum information to obtain the weighted average angle information. The range index of targets in the same cluster is summed to obtain the range sum information. The velocity index of each target is summed to obtain the velocity sum information. The range sum information and velocity sum information of the targets are divided by the number of targets in that cluster to finally obtain the range and velocity information of the targets relative to the radar.

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