Resource management method and heterogeneous chip

Abstract

The invention relates to a resource management method, a heterogeneous chip and computer equipment. The method is applied to a bridging unit connected between a processor unit and a neural network accelerator, and comprises the following steps: acquiring physical state data and calculation state data of the neural network accelerator; according to the task queue data, priority arbitration is carried out on tasks of a to-be-executed task queue of the neural network accelerator, an arbitration result is obtained, and the arbitration result comprises existence of high-priority hard real-time tasks or absence of the high-priority hard real-time tasks; calculating state data and an arbitration result according to the physical state data, and generating a voltage regulation signal and a frequency regulation signal; and adjusting the voltage, the frequency and the clock switching state of the neural network accelerator according to the voltage adjusting signal and the frequency adjusting signal. By adopting the method, the energy efficiency, the real-time performance and the management uniformity of the heterogeneous computing system can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a resource management method, heterogeneous chips, and computer equipment. Background Technology

[0002] With the rapid development of the Internet of Things, autonomous driving and edge computing, heterogeneous computing systems based on RISC-V architecture and General Purpose Neural Processing Unit (GPNPU) have become mainstream. Such systems need to handle high-concurrency and bursty AI inference tasks in edge devices with limited power consumption, facing the contradiction between high-performance real-time response and low-power operation.

[0003] Traditional energy consumption and real-time management solutions mainly adopt two approaches: one is software management based on the operating system, which adjusts the voltage and frequency by periodically sampling the load and driving the phase-locked loop; the other is independent hardware thermal / power throttling, which forces frequency reduction or clock gating when the temperature or current exceeds the threshold through hardware protection circuits.

[0004] However, traditional technologies suffer from problems such as software-adjusted latency failing to adapt to sudden tasks, or passive hardware protection lacking task awareness, leading to accidental frequency reduction during critical task execution, thus failing to balance physical safety and real-time requirements. Summary of the Invention

[0005] Therefore, it is necessary to provide a resource management method, heterogeneous chips, and computer equipment that can improve the energy efficiency, real-time performance, and unified management of heterogeneous computing systems, in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a resource management method applied to a bridging unit connecting a processor unit and a neural network accelerator, comprising:

[0007] The physical state data and computational state data of the neural network accelerator are obtained. The physical state data includes temperature data and power consumption data, and the computational state data includes task queue data and activity data.

[0008] Based on the task queue data, priority arbitration is performed on the tasks in the task queue to be executed by the neural network accelerator to obtain an arbitration result, which includes whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task.

[0009] Based on the physical state data, the calculated state data, and the arbitration result, a voltage regulation signal and a frequency regulation signal are generated.

[0010] The voltage, frequency, and clock switching state of the neural network accelerator are adjusted according to the voltage adjustment signal and the frequency adjustment signal.

[0011] In one embodiment, generating the voltage regulation signal and the frequency regulation signal based on the physical state data, the calculated state data, and the arbitration result includes:

[0012] Extract the task queue depth from the task queue data, classify the load level according to the task queue depth, and determine the reference voltage value and reference frequency value corresponding to the current load level;

[0013] Based on the reference voltage value, the reference frequency value, the arbitration result, and the physical state data, a voltage adjustment signal and a frequency adjustment signal are generated.

[0014] In one embodiment, generating the voltage adjustment signal and the frequency adjustment signal based on the reference voltage value, the reference frequency value, the arbitration result, and the physical state data includes:

[0015] If the arbitration result indicates the existence of a high-priority hard real-time task and the temperature data does not exceed a preset safety threshold, a voltage adjustment signal and a frequency adjustment signal of the first level are generated.

[0016] If the arbitration result indicates that there are no high-priority hard real-time tasks and the load level is higher than a preset load threshold, a second-level voltage adjustment signal and frequency adjustment signal are generated based on the reference voltage value, the reference frequency value, and the power consumption data; wherein, the second-level voltage adjustment signal and frequency adjustment signal are obtained by dynamically correcting the reference voltage value and the reference frequency value.

[0017] When the task queue is empty, a clock gating control signal and a third-level voltage adjustment signal are generated according to the low-power level corresponding to the reference voltage value; wherein the third level is lower than the second level, and the second level is lower than the first level.

[0018] In one embodiment, the step of prioritizing the tasks in the task queue to be executed by the neural network accelerator based on the task queue data, and obtaining the arbitration result, includes:

[0019] The task queue data is parsed to obtain the priority label and deadline of each task in the task queue to be executed by the neural network accelerator, and the tasks in the task queue are sorted according to the priority label, or the tasks in the task queue are sorted according to the deadline if the priority labels are the same.

[0020] In response to detecting that the priority flag of a newly entered task in the task queue is higher than the priority flag of the currently executing task, and that the priority flag of the newly entered task in the task queue is a preset hard real-time flag, a task preemption signal is issued and an arbitration result is output indicating that a high-priority hard real-time task exists.

[0021] In response to the detection that the priority flag of a newly entered task in the task queue is not higher than the priority flag of the currently executing task, or the priority flag of a newly entered task in the task queue does not include a preset hard real-time flag, or no newly entered task in the task queue is detected, the arbitration result is output as no high-priority hard real-time task exists.

[0022] In one embodiment, adjusting the voltage, frequency, and clock switching state of the neural network accelerator according to the voltage adjustment signal and the frequency adjustment signal includes:

[0023] Based on the energy consumption control requirements corresponding to the activity data, the voltage adjustment signal, and the frequency adjustment signal, independent clock switching state control is performed on the computing processing unit array and static random access memory storage block inside the neural network accelerator.

[0024] Based on the voltage adjustment signal and the frequency adjustment signal, adjust the frequency division coefficient of the phase-locked loop associated with the bridging unit and the voltage domain configuration of the neural network accelerator;

[0025] Based on the updated clock frequency obtained by adjusting the frequency division coefficient, the estimated completion time of the current task is recalculated and compared with the task deadline in the task queue data. The voltage or frequency of the neural network accelerator is adjusted according to the comparison result.

[0026] In one embodiment, the method further includes:

[0027] If the temperature data exceeds a preset safety threshold, the hardware thermal protection logic is triggered to perform a frequency reduction operation or a shutdown operation, and an interrupt signal is sent to the main control core.

[0028] In one embodiment, the method further includes:

[0029] Software configuration instructions are received via an extended control and status register, the software configuration instructions including at least one of a safe temperature threshold, a maximum power budget, and a real-time weighting parameter.

[0030] The decision logic is adjusted based on the software configuration instructions. The decision logic includes at least one of the following: weight allocation rules for task priority arbitration, upper limit limit rules for voltage / frequency adjustment, trigger threshold determination rules for clock gating, and start-up condition rules for abnormal protection. The decision logic is forcibly executed by the hardware state machine within the bridging unit.

[0031] Secondly, this application also provides a heterogeneous chip, including a processor unit, a neural network accelerator, and a bridging unit connected between the processor unit and the neural network accelerator, wherein the bridging unit includes a real-time scheduling arbitrator and a dynamic power management unit.

[0032] The bridging unit is used to acquire physical state data and computational state data of the neural network accelerator. The physical state data includes temperature data and power consumption data, and the computational state data includes task queue data and activity data.

[0033] The real-time scheduling arbitrator is used to perform priority arbitration on the tasks in the task queue to be executed by the neural network accelerator according to the task queue data, and obtain an arbitration result, the arbitration result including whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task.

[0034] The dynamic energy management unit is used to generate voltage regulation signals and frequency regulation signals based on the physical state data, the calculated state data, and the arbitration result.

[0035] The bridging unit is also used to adjust the voltage, frequency, and clock switching state of the neural network accelerator according to the voltage adjustment signal and the frequency adjustment signal.

[0036] In one embodiment, the bridging unit further includes an energy consumption sensor and a performance counter;

[0037] The energy consumption sensor is used to collect physical state data of the neural network accelerator, including temperature data and power consumption data, and transmit the collected physical state data to the dynamic energy consumption management unit.

[0038] The performance counter is used to collect the computational status data of the neural network accelerator, including task queue data and activity data, and transmits the collected computational status data to the real-time scheduling arbitrator and the dynamic energy consumption management unit.

[0039] Thirdly, this application also provides a computer device including any of the heterogeneous chips described above.

[0040] The aforementioned resource management methods, heterogeneous chips, and computer equipment, through hardware-based status monitoring and parameter control, can eliminate context switching latency caused by software protocol stacks, achieving rapid response and avoiding scheduling delays. By combining task priority judgment and thermal status awareness, reasonable thermal management can be achieved, preventing blind frequency reduction that could cause critical tasks to stall and ensuring the normal execution of core tasks. By constructing a hardware closed-loop feedback mechanism combined with fine-grained energy consumption control, the operating status can be dynamically matched, reducing energy consumption while ensuring performance. Through collaborative scheduling, unified management of heterogeneous units is achieved, balancing control flexibility and execution enforceability, solving the problem of disconnected power management between the main controller and accelerator in heterogeneous systems. Therefore, it can improve chip energy efficiency, ensure response speed and task stability, solve the problem of resource waste in heterogeneous architectures, and meet the battery life and operational reliability requirements of edge devices. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart illustrating a resource management method in one embodiment;

[0043] Figure 2 This is a flowchart illustrating step S206 in one embodiment;

[0044] Figure 3 This is a flowchart illustrating step S202 in one embodiment;

[0045] Figure 4 This is a flowchart illustrating the resource management method in another embodiment;

[0046] Figure 5 This is a schematic diagram of the framework of a heterogeneous chip in one embodiment;

[0047] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0049] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0050] The RISC-V main control unit and the GPNPU accelerator belong to different power domains and are managed by different drivers. Related technologies lack unified hardware bridging and scheduling. For example, the RISC-V main control unit may be in a high-frequency waiting state while the GPNPU accelerator has not yet completed its computation, or the GPNPU accelerator may be awakened but, limited by bus bandwidth, cannot obtain effective operating resources and remains in a waiting state. This loose coupling results in low overall chip energy efficiency, making it difficult to meet the optimal battery life requirements of edge devices such as battery-powered edge devices.

[0051] Based on this, embodiments of this application provide a resource management method that can be applied to a bridging unit connecting a processor unit (such as a RISC-V core) and a neural network accelerator (such as a GPNPU accelerator). This bridging unit can be entirely implemented in hardware and runs independently of the operating system kernel. The bridging unit may include a dynamic power management unit, a real-time scheduling arbitrator, a dynamic voltage and frequency adjustment unit (DVFS), a clock gating interface, power consumption sensors, and performance counters. Figure 1 As shown, the method includes steps S202 to S208. Wherein:

[0052] S202, acquire physical state data and computational state data of the neural network accelerator. The physical state data includes temperature data and power consumption data, and the computational state data includes task queue data and activity data.

[0053] Physical status data can be collected by energy consumption sensors, including temperature data collected by on-chip temperature sensors and power consumption data converted from current collected by current monitors. Computational status data can be collected by performance counters, including task queue data such as task descriptors and the number of tasks, as well as activity data reflecting the operational activity of the PE array and memory blocks.

[0054] For example, the bridging unit can acquire data in real time via a built-in power sensor interface (connecting an on-chip temperature sensor and a current monitor) and a performance counter, triggered periodically every 1 microsecond. All data is directly aggregated to the dynamic power management unit via hardware lines, without the need for operating system kernel intervention.

[0055] S204. Based on the task queue data, perform priority arbitration on the tasks in the task queue to be executed by the neural network accelerator to obtain the arbitration result, which includes whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task.

[0056] For example, the real-time scheduling arbiter within the bridging unit can parse task descriptors using hardware logic to extract the priority identifier and task type information for each task. It then uses a built-in hardware comparator network to sort the tasks, while simultaneously identifying whether they carry a "Critical" hard real-time flag. If a task with the highest priority and a hard real-time flag exists, the system outputs that a high-priority hard real-time task exists; otherwise, it outputs that no high-priority hard real-time task exists.

[0057] S206 generates voltage regulation signals and frequency regulation signals based on physical state data, calculated state data, and arbitration results.

[0058] Among them, the voltage adjustment signal is a hardware control signal that controls the magnitude of the voltage in the voltage domain of the neural network accelerator, and the frequency adjustment signal is a hardware control signal that controls the clock frequency of the neural network accelerator.

[0059] For example, the dynamic energy management unit within the bridging unit can receive physical state data and computational state data from energy consumption sensors and performance counters, as well as arbitration results from the real-time scheduling arbitrator. Through internally preset hardware decision logic (such as lookup logic based on a configurable mapping table or hardware algorithm), it comprehensively judges the current load intensity, physical operating status, and task urgency of the neural network accelerator, determines the optimal voltage and frequency values ​​suitable for the current scenario, and converts them into hardware-executable voltage and frequency adjustment signals. This process can be driven by a hardware state machine without the participation of a software protocol stack.

[0060] S208 adjusts the voltage, frequency, and clock switching state of the neural network accelerator based on the voltage adjustment signal and the frequency adjustment signal.

[0061] For example, the DVFS and clock gating interface within the bridging unit can receive adjustment signals. Clock frequency regulation is achieved by adjusting the phase-locked loop (PLL) divider coefficient via a standard hardware interface; simultaneously, the external power management chip (PMIC) or on-chip low-dropout linear regulator (LDO) is controlled to adjust the voltage domain supply voltage. For the PE array and static random access memory (SRAM) blocks, combining activity data and power consumption control requirements, the clock switch is independently controlled via integrated clock gating (ICG) logic to shut down the clock of idle modules to reduce static power consumption.

[0062] Among the aforementioned resource management methods, hardware-based status monitoring and parameter control eliminate context switching latency caused by software protocol stacks, enabling rapid response and avoiding scheduling delays. Combining task priority judgment and thermal status awareness achieves reasonable thermal management, preventing blind frequency reduction that could cause critical tasks to stall and ensuring the normal execution of core tasks. Constructing a hardware closed-loop feedback mechanism, combined with fine-grained energy consumption control, dynamically matches operating states, reducing energy consumption while ensuring performance. Cooperative scheduling enables unified management of heterogeneous units, balancing control flexibility and execution enforceability, and resolving the disconnect between main control and accelerator power management in heterogeneous systems. Therefore, it improves chip energy efficiency, ensures response speed and task stability, solves resource waste in heterogeneous architectures, and meets the battery life and operational reliability requirements of edge devices.

[0063] In one exemplary embodiment, such as Figure 2 As shown, S206 above includes:

[0064] S301: Extract the task queue depth from the task queue data, classify the load level according to the task queue depth, and determine the reference voltage value and reference frequency value corresponding to the current load level.

[0065] The task queue depth reflects the computational load density of the neural network accelerator (i.e., the GPNPU accelerator). Load levels can be defined using a configurable mapping table built into the dynamic power management unit. This mapping table can preset at least three load levels: low, medium, and high. Each level corresponds to a fixed range of task queue depths, and the table pre-stores the reference voltage and frequency values ​​for each load level. Based on the currently defined load level, the corresponding reference voltage and frequency values ​​can be determined via hardware lookup.

[0066] S302 generates voltage regulation signals and frequency regulation signals based on reference voltage value, reference frequency value, arbitration result and physical state data.

[0067] For example, the task queue depth in the task queue data can be extracted using a performance counter to achieve hardware awareness of load density calculation. The extracted task queue depth is compared with a preset depth range using a configurable mapping table built into the dynamic power management unit to classify load levels and directly look up the corresponding reference voltage and frequency values ​​for the current load level. Furthermore, the dynamic power management unit can receive the arbitration result from the real-time scheduling arbitrator, temperature data from energy sensors, and power consumption data. The hardware state machine drives the built-in decision logic to adapt and adjust the reference voltage and frequency values, generating hardware-executable voltage and frequency adjustment signals.

[0068] Optionally, step S302 above may include:

[0069] S3021, if the arbitration result indicates the existence of a high-priority hard real-time task and the temperature data does not exceed the preset safety threshold, generates the first-level voltage adjustment signal and frequency adjustment signal.

[0070] The preset safety threshold can be a temperature value configured by extending the RISC-V Control and Status Register (CSR). The first setting can be the preset highest performance setting, used to meet the microsecond-level response requirements of hard real-time tasks.

[0071] For example, the hardware comparator network of the real-time scheduling arbitrator can parse the task descriptors in the task queue data, identify high-priority hard real-time tasks marked with "Critical," and output an arbitration result indicating the existence of such high-priority hard real-time tasks. Simultaneously, temperature data is collected in real-time by an energy sensor and transmitted to the dynamic energy management unit (Dynamic Energy Management Unit). The hardware logic of the Dynamic Energy Management Unit determines whether the temperature data exceeds a preset safety threshold. When the temperature does not exceed the threshold, the Dynamic Energy Management Unit can ignore conventional power consumption limits and directly output the first-level voltage and frequency adjustment signals. The first level is the preset highest performance level, used to meet the microsecond-level response requirements of hard real-time tasks.

[0072] S3022, when the arbitration result is that there is no high-priority hard real-time task and the load level is higher than the preset load threshold, generates a second-level voltage adjustment signal and frequency adjustment signal based on the reference voltage value, reference frequency value and power consumption data; wherein, the second-level voltage adjustment signal and frequency adjustment signal are obtained by dynamically correcting the reference voltage value and reference frequency value.

[0073] The preset load threshold can be set through a configurable mapping table, corresponding to medium or high load levels.

[0074] For example, the real-time scheduling arbitrator can output an arbitration result indicating that there are no high-priority hard real-time tasks. The dynamic energy management unit, in conjunction with a configurable mapping table, determines that the current load level is higher than a preset load threshold. Real-time power consumption data is collected by energy sensors and transmitted to the dynamic energy management unit. The hardware algorithm of the dynamic energy management unit calculates the per-watt performance of the neural network accelerator. With the goal of optimal per-watt performance, the reference voltage and reference frequency values ​​are dynamically corrected to generate a second-level voltage adjustment signal and frequency adjustment signal, making the second level the most energy-efficient voltage and frequency combination under the current typical high-load scenario.

[0075] S3023 generates a clock gating control signal and a voltage adjustment signal for the third level based on the low power level corresponding to the reference voltage value when the task queue is empty; wherein, the third level is lower than the second level, and the second level is lower than the first level.

[0076] The first voltage level can be the maximum voltage frequency within a preset safe temperature range. The second voltage level can be the voltage frequency after logical correction based on optimal performance per watt. The third voltage level can be the minimum voltage frequency at which the module maintains operation. The rules for dynamically correcting the reference voltage and frequency values ​​can include adjusting the reference voltage / frequency to the optimal value based on the deviation between the current power consumption data and the preset performance per watt threshold. The clock gating control signal can be a hardware signal that independently shuts down the clock on the computational processing unit (PE) array and static random access memory blocks within the neural network accelerator.

[0077] For example, after the performance counter detects that the task queue is empty, the status data is transmitted to the dynamic power management unit. The dynamic power management unit generates a third-level voltage regulation signal (the third level is the lowest voltage frequency for the neural network accelerator to maintain operation) based on the reference voltage value corresponding to the low load level in the configurable mapping table, and at the same time generates a clock gating control signal. The clock gating control signal is received through integrated clock gating logic, and independent clock switching control is performed on the computing processing unit array and static random access memory block inside the neural network accelerator. When a module is idle for more than 10 clock cycles (this threshold can be configured through the extended RISC-V control and status register), the hardware automatically shuts off its clock input to minimize static power consumption.

[0078] In this embodiment, by dividing the load levels according to the task queue depth and setting a reference voltage frequency value, the voltage frequency adjustment is made to fit the actual computing load of the neural network accelerator. Then, by combining the task arbitration results and the hardware physical state to generate adjustment signals, the generation of adjustment signals conforms to the actual needs of hardware closed-loop feedback, improving the accuracy and adaptability of signal generation and avoiding blind adjustment. Furthermore, by generating multi-level adjustment signals for different scenarios, high-priority hard real-time tasks are adapted to high-performance levels, ensuring rapid task response and preventing accidental stalls, matching the task's perceived operational needs; in regular high-load scenarios, the reference value is dynamically corrected, finding the optimal energy-efficient operating point based on hardware operating data, conforming to the energy-efficiency optimization logic of hardware closed-loop feedback; and when tasks are idle, a low-power level is used in conjunction with clock gating to minimize energy consumption.

[0079] In one exemplary embodiment, such as Figure 3 As shown, step S202 above includes:

[0080] S401, parse the task queue data to obtain the priority label and deadline of each task in the task queue to be executed by the neural network accelerator, and sort the tasks in the task queue according to the priority label, or sort the tasks in the task queue according to the deadline if the priority labels are the same.

[0081] For example, the hardware parsing module of the real-time scheduling arbitrator within the bridging unit can perform parallel hardware-level parsing of the task descriptors in the task queue data, directly extracting the priority flag (e.g., numerical priority 1 to 10) and deadline (e.g., the latest completion time of the task in clock cycles) for each task to be executed. Through the hardware comparator network built into the real-time scheduling arbitrator, the priority flags of all tasks to be executed are sorted in hardware. When multiple task priority flags are detected to be the same, the system automatically switches to the deadline comparison logic, and performs a secondary sorting based on the rule that the earlier the deadline, the higher the priority, thus forming an ordered task execution queue.

[0082] S402, in response to detecting that the priority flag of a newly entered task in the task queue is higher than the priority flag of the currently executing task, and the priority flag of the newly entered task in the task queue is a preset hard real-time flag, a task preemption signal is issued, and the arbitration result is output that there is a high-priority hard real-time task.

[0083] The preset hard real-time identifier can be a specific value of a preset field in the task descriptor (such as the character marker Critical or a numerical priority ≥8).

[0084] For example, the task monitoring hardware unit of the real-time scheduling arbitrator can continuously scan the task queue interface at one clock cycle interval to detect whether a new task has entered the execution queue in real time. When a new task is detected, the priority flag of the new task is immediately compared with the priority flag of the currently executing task in real time through a hardware comparator. At the same time, the hardware identifier recognition module determines whether the priority flag of the new task is a preset hard real-time identifier. If the comparison result is that the priority flag of the new task is higher than that of the currently executing task, and the identifier recognition result is a preset hard real-time identifier, then a task preemption signal is immediately issued through a hardware trigger circuit to suspend the execution of the current low-priority task. At the same time, the arbitration result of the existence of a high-priority hard real-time task is output through the hardware signal output interface.

[0085] S403, in response to the detection that the priority flag of a newly entered task in the task queue is not higher than the priority flag of the currently executing task, or the priority flag of a newly entered task in the task queue does not include the preset hard real-time flag, or no newly entered task in the task queue is detected, the arbitration result is output as no high-priority hard real-time task exists.

[0086] For example, the task monitoring hardware unit of the real-time scheduling arbitrator can continuously monitor the task queue status: if a new task is detected, and the priority flag of the new task is not higher than that of the currently executing task after comparison by the hardware comparator, or if the hardware flag recognition module determines that the new task has no preset hard real-time flag, then the arbitration result that there is no high-priority hard real-time task is directly output through the hardware logic, and the current task continues to execute; if the task monitoring hardware unit does not detect any newly entered tasks within several consecutive clock cycles, then the current task execution status is maintained, and the arbitration result that there is no high-priority hard real-time task is continuously output.

[0087] In this embodiment, task data is parsed at the hardware level and sorted by priority and deadline, making task scheduling more orderly. The hardware also monitors the status of new tasks in real time, eliminating response latency caused by the software protocol stack. High-priority hard real-time tasks are accurately identified and preempted, ensuring rapid response and preventing unintended delays for critical tasks, thus meeting the intelligent management requirements of task awareness. Maintaining the original execution rhythm for non-hard real-time or low-priority tasks ensures accurate arbitration results.

[0088] In an exemplary embodiment, step S208 includes:

[0089] S501 performs independent clock switching state control on the computational processing unit array and static random access memory block inside the neural network accelerator based on the energy consumption control requirements corresponding to the activity data, voltage regulation signal, and frequency regulation signal.

[0090] For example, when the idle time of the computing processing unit array or static random access memory block exceeds a preset threshold (the threshold is configurable, with a default of 10 clock cycles), or when the activity data is lower than the preset threshold, the clock input of the corresponding module can be turned off.

[0091] Specifically, the performance counter within the bridging unit can collect real-time activity data of the computational processing unit array and static random access memory (SRAM) blocks inside the neural network accelerator. Simultaneously, it receives voltage and frequency adjustment signals from the dynamic power management unit, extracting the power consumption control requirements. Through an integrated clock gating logic module, the activity data is compared with a preset idle threshold (10 clock cycles by default, configurable via an extended RISC-V control and status register). Based on the power consumption control requirements, independent clock switching control is implemented for each computational processing unit array and SRAM block. When the activity data of a module falls below the preset threshold and is determined to be idle, the clock input of that module is automatically shut off via hardware logic. When the module is scheduled to execute a task, the clock is immediately turned on via hardware trigger.

[0092] S502 adjusts the frequency division coefficient of the phase-locked loop associated with the bridging unit and the voltage domain configuration of the neural network accelerator based on the voltage regulation signal and the frequency regulation signal.

[0093] For example, the voltage regulation signal and frequency regulation signal output by the dynamic power management unit can be received through the dynamic voltage and frequency adjustment unit in the bridging unit; through the phase-locked loop control interface, the frequency division coefficient of the phase-locked loop is adjusted in hardware according to the target frequency value in the frequency regulation signal to achieve precise control of the clock frequency of the neural network accelerator; at the same time, through the voltage domain control interface, the voltage regulation signal is transmitted to the external power management chip (PMIC) or the on-chip low dropout linear regulator, and the power supply voltage of the corresponding voltage domain of the neural network accelerator is configured in hardware to ensure the coordinated adaptation of voltage and frequency.

[0094] S503 recalculates the estimated completion time of the current task based on the updated clock frequency obtained by adjusting the frequency division coefficient, compares it with the task deadline in the task queue data, and adjusts the voltage or frequency of the neural network accelerator based on the comparison result.

[0095] For example, the updated clock frequency after adjusting the phase-locked loop frequency division coefficient can be obtained through the dynamic voltage and frequency adjustment unit, and this frequency data can be transmitted to the real-time scheduling arbitrator. The hardware calculation module built into the real-time scheduling arbitrator calculates the estimated completion time of the current task based on the updated clock frequency and the remaining number of instructions of the current task. At the same time, the deadline of the current task is extracted from the task queue data by the hardware parsing module, and the estimated completion time is compared with the deadline in real time by the hardware comparator. If the comparison result is that the estimated completion time is later than the deadline, the real-time scheduling arbitrator sends a performance improvement request to the dynamic energy management unit. The dynamic energy management unit regenerates a higher level voltage adjustment signal and frequency adjustment signal, and further increases the clock frequency and supply voltage through the dynamic voltage and frequency adjustment unit. If the estimated completion time is earlier than the deadline and there is room for energy consumption optimization, a lower level adjustment signal is generated to appropriately reduce the voltage and frequency to save energy and ensure the balance between task real-time performance and energy efficiency.

[0096] In this embodiment, fine-grained independent clock switching control of the accelerator's internal modules reduces ineffective energy consumption; precise and coordinated voltage and frequency regulation is achieved through hardware-level adjustment of the phase-locked loop frequency division coefficient and voltage domain configuration, ensuring rapid response; and voltage and frequency adjustment is made to match task deadline requirements by recalculating the estimated task completion time and making secondary adjustments, avoiding critical task delays and achieving dynamic regulation based on task awareness. Simultaneously, multi-dimensional regulation forms a hardware closed-loop feedback, allowing for deep adaptation of resource management, task execution, and hardware status, improving the precision and real-time performance of heterogeneous system regulation.

[0097] In one exemplary embodiment, the resource management method described above further includes:

[0098] When the temperature data exceeds the preset safety threshold, the S210 triggers the hardware thermal protection logic, performs frequency reduction or shutdown, and sends an interrupt signal to the main control core.

[0099] The preset safety threshold can be a temperature value (e.g., 105°C) configured through extended control and status registers. Frequency reduction operations can include: reducing the voltage frequency to the second level; and performing a shutdown operation if the temperature continues to exceed the threshold.

[0100] For example, the temperature data of the neural network accelerator can be collected in real time by a power consumption sensor (connected to an on-chip temperature sensor) within the bridging unit, and the collected temperature data can be transmitted to the dynamic power management unit in real time. The dynamic power management unit uses a built-in hardware comparator to perform a real-time hardware-level comparison between the real-time temperature data and a preset safety threshold (the preset safety threshold is a temperature value configured through an extended RISC-V control and status register). If the comparison result shows that the temperature data exceeds the preset safety threshold, the dynamic power management unit immediately triggers hardware thermal protection logic. This hardware thermal protection logic operates independently of the software protocol stack and prioritizes frequency reduction operations. For example, the voltage and frequency of the neural network accelerator can be adjusted to the second level (the energy-efficient level under normal high-load scenarios) through the dynamic voltage and frequency adjustment unit. If the temperature data collected by the power consumption sensor still exceeds the preset safety threshold after the frequency reduction operation, or if the temperature data rises sharply in a short period of time, the hardware thermal protection logic triggers a shutdown operation, cutting off the non-essential power supply modules of the neural network accelerator through hardware circuitry. Meanwhile, the dynamic power management unit sends a high-priority interrupt signal to the main control core (RISC-V main control unit) through the hardware interrupt interface to synchronously inform it of the abnormal temperature status.

[0101] In this embodiment, temperature data is monitored at the hardware level. When the temperature exceeds a preset safety threshold, thermal protection logic is triggered in a timely manner to perform frequency reduction or shutdown operations. This effectively prevents the neural network accelerator from malfunctioning due to overheating, ensuring hardware operational safety. The tiered implementation of frequency reduction and shutdown protection measures makes the thermal protection operation more closely reflect actual temperature anomalies, resulting in more rational control. Simultaneously, an interrupt signal is sent to the main control core to synchronize the accelerator's state with the main control core, allowing the main control core to promptly grasp the device's operating status and improving the overall system stability.

[0102] In one exemplary embodiment, the resource management method described above further includes:

[0103] S212 receives software configuration instructions via an extended control and status register. The software configuration instructions include at least one of a safe temperature threshold, a maximum power consumption budget, and a real-time weighting parameter.

[0104] Among them, the real-time weight parameter can be used to adjust the weight allocation of task priority arbitration. The larger the weight value, the higher the power budget preemption priority of high-priority hard real-time tasks.

[0105] For example, software configuration commands issued by the M-Mode software can be received through the extended RISC-V control and status register interface within the bridging unit. This interface is a dedicated hardware-level interface, ensuring the security and reliability of configuration command transmission. In the software configuration commands, a safe temperature threshold is used to define the chip's thermal safety boundary, a maximum power budget is used to limit the upper limit of the neural network accelerator's power consumption, and a real-time weight parameter is used to adjust the priority of real-time performance versus energy efficiency. All configuration commands are transmitted in a hardware-recognizable binary data format.

[0106] S214, adjusts the decision logic based on software configuration instructions. The decision logic includes at least one of the following: weight allocation rules for task priority arbitration, upper limit limit rules for voltage / frequency regulation, trigger threshold determination rules for clock gating, and start condition rules for abnormal protection. The decision logic is enforced by the hardware state machine in the bridging unit.

[0107] The adjustment method of the decision logic may include: updating the comparison rules of priority arbitration according to the weight parameter values ​​and a preset mapping relationship.

[0108] For example, the configuration parsing hardware module built into the dynamic power management unit and the real-time scheduling arbitrator can perform hardware-level parsing of the received software configuration instructions, extract key configuration information such as safe temperature threshold, maximum power budget, and real-time weight parameters, and write them into the corresponding hardware configuration registers. Based on the parsed configuration information, the corresponding decision logic is automatically adjusted through hardware logic: if real-time weight parameters are configured, the weight allocation rules for task priority arbitration are updated through the hardware comparator network of the real-time scheduling arbitrator; the larger the weight parameter value, the higher the arbitration priority of high-priority hard real-time tasks. If voltage / frequency adjustment level limit rules are configured, the voltage and frequency level limits in the configurable mapping table are adjusted through the dynamic power management unit to avoid exceeding the preset power budget. If clock gating trigger threshold determination rules are configured, the idle threshold parameters in the integrated clock gating logic are updated to adapt to the power consumption control requirements of different scenarios. If abnormal protection activation condition rules are configured, the trigger threshold (such as safe temperature threshold) of the hardware thermal protection logic in the dynamic power management unit is adjusted. All adjusted decision logic is forcibly loaded and executed by the hardware state machine within the bridging unit. The software is only responsible for issuing configuration parameters and cannot interfere with the execution process of the decision logic, thus ensuring the rigidity and reliability of the decision logic and avoiding hardware operation risks caused by software errors.

[0109] In this embodiment, multiple software configuration instructions are received through extended control and status registers, enabling flexible configuration of relevant parameters and rules for neural network accelerator resource management to adapt to different operational needs. Based on instruction-based adjustments to core decision-making logic such as arbitration and voltage / frequency regulation, the system's control logic aligns with actual configuration requirements, improving the adaptability of the control.

[0110] In one possible implementation, the bridging unit is a pure hardware implementation (running independently of the operating system kernel), including a dynamic power management unit, a real-time scheduling arbitrator, a DVFS unit, a clock gating interface, power sensors, and performance counters. Please refer to [reference needed]. Figure 4 Step S202 above may include: the bridging unit periodically triggers the acquisition of physical status data (temperature data, power consumption data) of the GPNPU accelerator through a built-in power sensor interface (connected to an on-chip temperature sensor and current monitor); simultaneously, it acquires computational status data (task queue data, activity data of the PE array and SRAM storage blocks) through a performance counter. All data is directly aggregated to the dynamic power management unit through hardware lines, without the intervention of the operating system kernel.

[0111] Step S204 above may include: the real-time scheduling arbitrator in the bridging unit performs an operation; the hardware parsing module parses the task descriptors in the task queue data in parallel and extracts the priority flag and deadline of each task; the hardware comparator network sorts the tasks according to the priority flag, and sorts them according to the deadline when the priorities are the same; the task monitoring hardware unit detects that a newly entered task in the queue has a Critical preset hard real-time flag and has a higher priority than the currently pending task, and immediately sends a task preemption signal through the hardware trigger circuit, and outputs the arbitration result that there is a high-priority hard real-time task.

[0112] Step S206 above may include: extracting the task queue depth from the task queue data, dividing the load level through a configurable mapping table, looking up the reference voltage value and reference frequency value corresponding to the current load level; combining the arbitration result (the existence of a high-priority hard real-time task) and physical state data (temperature not exceeding the preset safety threshold), determining it as scenario A (sudden critical task), and generating the first-level voltage adjustment signal and frequency adjustment signal; if it is a normal high load, determining it as scenario B, and correcting the reference value to generate the second-level signal with the goal of optimal performance per watt; if the task queue is empty, determining it as scenario C, and generating the third-level signal and clock gating control signal.

[0113] Step S208 above may include: the DVFS and clock gating interface in the bridging unit perform operations, based on activity data and energy consumption control requirements, and perform independent clock switching control on the PE array and SRAM storage block through integrated clock gating logic; the DVFS unit adjusts the phase-locked loop frequency division coefficient and GPNPU voltage domain configuration through a standard hardware interface to achieve coordinated adjustment of frequency and voltage; the real-time scheduling arbitrator calculates the estimated completion time of the current task based on the updated clock frequency, compares it with the task deadline, and adjusts the voltage or frequency according to the result.

[0114] Step S210 above may include: the dynamic power management unit has a built-in hardware comparator that continuously monitors temperature data. If the temperature data exceeds a preset safety threshold, the hardware thermal protection logic is immediately triggered, and frequency reduction is performed first. If the temperature continues to exceed the limit, a shutdown operation is triggered, and a high-priority interrupt signal is sent to the RISC-V main control core through the hardware interrupt interface.

[0115] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0116] Based on the same inventive concept, please refer to Figure 5 This application also provides a heterogeneous chip, including a processor unit, a neural network accelerator, and a bridging unit connecting the processor unit and the neural network accelerator. The bridging unit includes a real-time scheduling arbitrator and a dynamic power management unit. Wherein:

[0117] The bridging unit is used to acquire physical state data and computational state data of the neural network accelerator. The physical state data includes temperature data and power consumption data, while the computational state data includes task queue data and activity data.

[0118] The real-time scheduling arbitrator is used to arbitrate the priority of tasks in the task queue of the neural network accelerator based on task queue data, and obtain the arbitration result, which includes whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task.

[0119] The dynamic energy management unit is used to generate voltage regulation signals and frequency regulation signals based on physical state data, calculated state data, and arbitration results.

[0120] The bridging unit is also used to adjust the voltage, frequency, and clock switching state of the neural network accelerator based on the voltage regulation signal and the frequency regulation signal.

[0121] In one embodiment, the dynamic energy management unit is further configured to:

[0122] Extract the task queue depth from the task queue data, classify the load level according to the task queue depth, and determine the reference voltage value and reference frequency value corresponding to the current load level;

[0123] Based on the reference voltage value, reference frequency value, arbitration result, and physical state data, voltage regulation signal and frequency regulation signal are generated.

[0124] In one embodiment, the dynamic energy management unit is further configured to:

[0125] If the arbitration result indicates the existence of a high-priority hard real-time task and the temperature data does not exceed the preset safety threshold, then the first-level voltage regulation signal and frequency regulation signal are generated.

[0126] If the arbitration result indicates that there are no high-priority hard real-time tasks and the load level is higher than the preset load threshold, a second-level voltage adjustment signal and frequency adjustment signal are generated based on the reference voltage value, reference frequency value, and power consumption data; wherein, the second-level voltage adjustment signal and frequency adjustment signal are obtained by dynamically correcting the reference voltage value and reference frequency value.

[0127] When the task queue is empty, a clock gating control signal and a voltage adjustment signal for the third level are generated based on the low power level corresponding to the reference voltage value; wherein, the third level is lower than the second level, and the second level is lower than the first level.

[0128] In one embodiment, the above-described real-time scheduling arbitrator is further used for:

[0129] The task queue data is parsed to obtain the priority label and deadline of each task in the task queue to be executed by the neural network accelerator. The tasks in the task queue are sorted according to the priority label, or according to the deadline if the priority labels are the same.

[0130] In response to the detection that the priority flag of a newly entered task in the task queue is higher than the priority flag of the currently executing task, and the priority flag of the newly entered task in the task queue is a preset hard real-time flag, a task preemption signal is issued and the arbitration result is output as a high-priority hard real-time task exists.

[0131] In response to the detection that the priority flag of a newly entered task in the task queue is not higher than the priority flag of the currently executing task, or the priority flag of a newly entered task in the task queue does not include the preset hard real-time flag, or no newly entered task in the task queue is detected, the arbitration result is output as no high-priority hard real-time task exists.

[0132] In one embodiment, please refer to... Figure 5 The aforementioned bridging unit also includes a clock gating interface and a dynamic voltage and frequency adjustment unit; wherein:

[0133] The clock gating interface is used to perform independent clock switching state control on the computing processing unit array and static random access memory block inside the neural network accelerator based on the energy consumption control requirements corresponding to the activity data in the computing state data, the voltage regulation signal and the frequency regulation signal generated by the dynamic energy consumption management unit.

[0134] The dynamic voltage and frequency adjustment unit is used to adjust the frequency division coefficient of the phase-locked loop associated with the bridging unit and the voltage domain configuration of the neural network accelerator according to the voltage adjustment signal and frequency adjustment signal generated by the dynamic power management unit; and recalculate the estimated completion time of the current task in conjunction with the real-time scheduling arbitrator based on the updated clock frequency obtained by adjusting the frequency division coefficient; and after the real-time scheduling arbitrator compares the recalculated estimated completion time of the current task with the task deadline in the task queue data, adjust the voltage or frequency of the neural network accelerator according to the comparison result.

[0135] In one embodiment, the bridging unit is further configured to:

[0136] If the temperature exceeds the preset safety threshold, the hardware thermal protection logic is triggered, which performs frequency reduction or shutdown operations and sends an interrupt signal to the main control core.

[0137] In one embodiment, the bridging unit is further configured to:

[0138] Software configuration instructions are received via an extended control and status register. These instructions include at least one of a safe temperature threshold, a maximum power budget, and a real-time weighting parameter.

[0139] The decision logic is adjusted based on software configuration instructions. The decision logic includes at least one of the following: weight allocation rules for task priority arbitration, upper limit limit rules for voltage / frequency adjustment, trigger threshold determination rules for clock gating, and start-up condition rules for abnormal protection. The decision logic is enforced by the hardware state machine in the bridging unit.

[0140] In one embodiment, please refer to... Figure 5 The aforementioned bridging unit also includes an energy consumption sensor and a performance counter; wherein:

[0141] The energy sensor is used to collect physical state data of the neural network accelerator, including temperature data and power consumption data, and transmits the collected physical state data to the dynamic energy management unit.

[0142] The performance counter is used to collect computational status data of the neural network accelerator, including task queue data and activity data, and transmits the collected computational status data to the real-time scheduling arbitrator and dynamic power management unit.

[0143] In one exemplary embodiment, a computer device is provided, including the heterogeneous chips described in the above embodiments.

[0144] In one exemplary embodiment, the computer device may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. The display unit is used to create a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0145] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0146] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0147] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0148] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A resource management method, characterized in that, The method, applied to a bridging unit connecting a processor unit and a neural network accelerator, includes: The physical state data and computational state data of the neural network accelerator are obtained. The physical state data includes temperature data and power consumption data, and the computational state data includes task queue data and activity data. Based on the task queue data, priority arbitration is performed on the tasks in the task queue to be executed by the neural network accelerator to obtain an arbitration result, which includes whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task. Based on the physical state data, the calculated state data, and the arbitration result, a voltage regulation signal and a frequency regulation signal are generated. The voltage, frequency, and clock switching state of the neural network accelerator are adjusted according to the voltage adjustment signal and the frequency adjustment signal.

2. The method according to claim 1, characterized in that, The step of generating voltage regulation signals and frequency regulation signals based on the physical state data, the calculated state data, and the arbitration result includes: Extract the task queue depth from the task queue data, classify the load level according to the task queue depth, and determine the reference voltage value and reference frequency value corresponding to the current load level; Based on the reference voltage value, the reference frequency value, the arbitration result, and the physical state data, a voltage adjustment signal and a frequency adjustment signal are generated.

3. The method according to claim 2, characterized in that, The step of generating voltage adjustment signals and frequency adjustment signals based on the reference voltage value, the reference frequency value, the arbitration result, and the physical state data includes: If the arbitration result indicates the existence of a high-priority hard real-time task and the temperature data does not exceed a preset safety threshold, a voltage adjustment signal and a frequency adjustment signal of the first level are generated. If the arbitration result indicates that there are no high-priority hard real-time tasks and the load level is higher than a preset load threshold, a second-level voltage adjustment signal and frequency adjustment signal are generated based on the reference voltage value, the reference frequency value, and the power consumption data; wherein, the second-level voltage adjustment signal and frequency adjustment signal are obtained by dynamically correcting the reference voltage value and the reference frequency value. When the task queue is empty, a clock gating control signal and a third-level voltage adjustment signal are generated according to the low-power level corresponding to the reference voltage value; wherein the third level is lower than the second level, and the second level is lower than the first level.

4. The method according to claim 1, characterized in that, The step of prioritizing the tasks in the task queue to be executed by the neural network accelerator based on the task queue data, and obtaining the arbitration result, includes: The task queue data is parsed to obtain the priority label and deadline of each task in the task queue to be executed by the neural network accelerator, and the tasks in the task queue are sorted according to the priority label, or the tasks in the task queue are sorted according to the deadline if the priority labels are the same. In response to detecting that the priority flag of a newly entered task in the task queue is higher than the priority flag of the currently executing task, and that the priority flag of the newly entered task in the task queue is a preset hard real-time flag, a task preemption signal is issued and an arbitration result is output indicating that a high-priority hard real-time task exists. In response to the detection that the priority flag of a newly entered task in the task queue is not higher than the priority flag of the currently executing task, or the priority flag of a newly entered task in the task queue does not include a preset hard real-time flag, or no newly entered task in the task queue is detected, the arbitration result is output as no high-priority hard real-time task exists.

5. The method according to claim 1, characterized in that, The step of adjusting the voltage, frequency, and clock switching state of the neural network accelerator according to the voltage adjustment signal and the frequency adjustment signal includes: Based on the energy consumption control requirements corresponding to the activity data, the voltage adjustment signal, and the frequency adjustment signal, independent clock switching state control is performed on the computing processing unit array and static random access memory storage block inside the neural network accelerator. Based on the voltage adjustment signal and the frequency adjustment signal, adjust the frequency division coefficient of the phase-locked loop associated with the bridging unit and the voltage domain configuration of the neural network accelerator; Based on the updated clock frequency obtained by adjusting the frequency division coefficient, the estimated completion time of the current task is recalculated and compared with the task deadline in the task queue data. The voltage or frequency of the neural network accelerator is adjusted according to the comparison result.

6. The method according to claim 1, characterized in that, The method further includes: If the temperature data exceeds a preset safety threshold, the hardware thermal protection logic is triggered to perform a frequency reduction operation or a shutdown operation, and an interrupt signal is sent to the main control core.

7. The method according to claim 1, characterized in that, The method further includes: Software configuration instructions are received via an extended control and status register, the software configuration instructions including at least one of a safe temperature threshold, a maximum power budget, and a real-time weighting parameter. The decision logic is adjusted based on the software configuration instructions. The decision logic includes at least one of the following: weight allocation rules for task priority arbitration, upper limit limit rules for voltage / frequency adjustment, trigger threshold determination rules for clock gating, and start-up condition rules for abnormal protection. The decision logic is forcibly executed by the hardware state machine within the bridging unit.

8. A heterogeneous chip, characterized in that, It includes a processor unit, a neural network accelerator, and a bridging unit connecting the processor unit and the neural network accelerator. The bridging unit includes a real-time scheduling arbitrator and a dynamic power management unit. The bridging unit is used to acquire physical state data and computational state data of the neural network accelerator. The physical state data includes temperature data and power consumption data, and the computational state data includes task queue data and activity data. The real-time scheduling arbitrator is used to perform priority arbitration on the tasks in the task queue to be executed by the neural network accelerator according to the task queue data, and obtain an arbitration result, the arbitration result including whether there is a high-priority hard real-time task or whether there is no high-priority hard real-time task. The dynamic energy management unit is used to generate voltage regulation signals and frequency regulation signals based on the physical state data, the calculated state data, and the arbitration result. The bridging unit is also used to adjust the voltage, frequency, and clock switching state of the neural network accelerator according to the voltage adjustment signal and the frequency adjustment signal.

9. The heterogeneous chip according to claim 8, characterized in that, The bridging unit also includes a clock gating interface and a dynamic voltage and frequency adjustment unit; The clock gating interface is used to perform independent clock switching state control on the computing processing unit array and static random access memory storage block inside the neural network accelerator based on the activity data in the computing state data, the voltage adjustment signal generated by the dynamic energy consumption management unit, and the energy consumption control requirements corresponding to the frequency adjustment signal. The dynamic voltage and frequency adjustment unit is used to adjust the frequency division coefficient of the phase-locked loop associated with the bridging unit and the voltage domain configuration of the neural network accelerator according to the voltage adjustment signal and frequency adjustment signal generated by the dynamic energy management unit. Based on the updated clock frequency obtained by adjusting the frequency division coefficient, the estimated completion time of the current task is recalculated in conjunction with the real-time scheduling arbitrator. After the real-time scheduling arbitrator compares the recalculated estimated completion time of the current task with the task deadline in the task queue data, the voltage or frequency of the neural network accelerator is adjusted according to the comparison result.

10. The heterogeneous chip according to claim 9, characterized in that, The bridging unit also includes an energy consumption sensor and a performance counter; The energy consumption sensor is used to collect physical state data of the neural network accelerator, including temperature data and power consumption data, and transmit the collected physical state data to the dynamic energy consumption management unit. The performance counter is used to collect the computational status data of the neural network accelerator, including task queue data and activity data, and transmit the collected computational status data to the real-time scheduling arbitrator and the dynamic energy consumption management unit.

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