Power stage package and manufacturing method thereof, voltage regulating module and electronic device

Abstract

This disclosure provides a power stage package and its manufacturing method, as well as a voltage regulation module and electronic device including the power stage package. The power stage package includes: a printed circuit board; a transistor array, wherein the first electrode of the low-side transistor is connected to the second electrode of the high-side transistor via a first trace in a first wiring layer, a first via penetrating an insulating layer, and a second trace in a second wiring layer; a first encapsulation layer covering the low-side transistor; a second encapsulation layer covering the high-side transistor; and a first rewiring layer exposed for receiving input signals, including a first rewiring portion covering a portion of a first side surface of the first encapsulation layer; a second rewiring portion covering a portion of a second side surface of the first encapsulation layer; a third rewiring portion covering a portion of a third side surface of the second encapsulation layer; a fourth rewiring portion covering a portion of a fourth side surface of the second encapsulation layer; and a fifth rewiring portion covering a portion of the second encapsulation layer away from the printed circuit board. The power stage package has good heat dissipation and helps to reduce resistance.

Description

Technical Field

[0001] This disclosure relates to the field of power devices, and more particularly to a power stage package and its manufacturing method, a voltage regulation module, and electronic equipment. Prior Technology

[0002] The voltage regulator module (VRM) can provide the appropriate supply voltage to the processor. Because the supply voltage can be adjusted, processors with different supply voltages can be installed on the same motherboard.

[0003] A voltage regulation module typically includes a power stage circuit and a control integrated circuit (IC). Summary of the Invention

[0004] In related technologies, packaged power stage circuits have high resistance and poor heat dissipation. Therefore, the embodiments disclosed herein propose the following technical solutions.

[0005] According to one aspect of the present disclosure, a power stage package is provided, comprising: a printed circuit board including a first wiring layer, a second wiring layer, and an insulating layer located between the first wiring layer and the second wiring layer; two transistor groups, each transistor group including: a low-side transistor located on a first side of the printed circuit board, and a high-side transistor located on a second side of the printed circuit board opposite to the first side, wherein a first electrode of the low-side transistor is sequentially connected to a second electrode of the high-side transistor via a first trace in the first wiring layer, a first via penetrating the insulating layer, and a second trace in the second wiring layer; a first encapsulation layer located on the first side of the printed circuit board and covering the low-side transistor; a second encapsulation layer located on the second side of the printed circuit board and covering the high-side transistor; and an exposed first rewiring layer configured to receive an input signal. The first wiring layer includes: a first wiring portion covering a portion of a first side surface of the first package layer; a second wiring portion covering a portion of a second side surface of the first package layer; a third wiring portion covering a portion of a third side surface of the second package layer, and the first wiring portion being connected to the third wiring portion sequentially via a third trace in the first wiring layer, a second via penetrating an insulating layer, and a fourth trace in the second wiring layer; a fourth wiring portion covering a portion of a fourth side surface of the second package layer, and the second wiring portion being connected to the fourth wiring portion sequentially via a fifth trace in the first wiring layer, a third via penetrating an insulating layer, and a sixth trace in the second wiring layer; and a fifth wiring portion covering a portion of the surface of the second package layer away from the printed circuit board, adjacent to the third wiring portion and the fourth wiring portion respectively, and connected to the first electrode of the high-side transistor in each transistor group via a fourth via penetrating the second package layer.

[0006] In some embodiments, the two high-side transistors of the two transistor groups are arranged along a first direction, and the first wiring layer further includes: a sixth wiring section adjacent to the first wiring section and extending in the first direction; and a seventh wiring section adjacent to the second wiring section and extending in the first direction, wherein the first wiring section is connected to the third wiring section in sequence via the sixth wiring section, the third trace, the second via, the fourth trace and the seventh wiring section.

[0007] In some embodiments, the first wiring layer further includes: an eighth wiring section adjacent to the second wiring section and extending in a first direction; and a ninth wiring section adjacent to the fourth wiring section and extending in a first direction, wherein the second wiring section is connected to the fourth wiring section sequentially via the eighth wiring section, the fifth trace, the third via, the sixth trace and the ninth wiring section.

[0008] In some embodiments, the first rewiring layer further includes at least one of the following: a tenth rewiring portion adjacent to the first rewiring portion and covering a portion of the surface of the first encapsulation layer away from the printed circuit board; and an eleventh rewiring portion adjacent to the second rewiring portion and covering another portion of the surface of the first encapsulation layer away from the printed circuit board.

[0009] In some embodiments, the power stage package further includes: a second wiring layer exposed on the surface of the package, configured to receive a ground signal, covering a portion of the surface of the first package layer away from the printed circuit board, and connected to a second electrode of the low-side transistor via a fifth via through the first package layer.

[0010] In some embodiments, the area of ​​a portion of the surface of the second encapsulation layer covered by the fifth redistribution portion that is away from the printed circuit board is greater than half the area of ​​the surface of the second encapsulation layer that is away from the printed circuit board.

[0011] In some embodiments, the power stage package further includes: a driver located on the second side of the printed circuit board and covered by a second packaging layer, the driver being connected to the gate of the high-side transistor via a seventh trace in the second wiring layer, and being connected to the gate of the low-side transistor via a sixth via through an insulating layer, a seventh via through a first packaging layer, an eighth trace located on the surface of the first packaging layer away from the printed circuit board, and an eighth via through a first packaging layer.

[0012] In some embodiments, the two high-side transistors of the two transistor groups are arranged along a first direction, and the driver and the two transistor groups are arranged in a second direction, which is perpendicular to the first direction and parallel to the surface of the printed circuit board.

[0013] In some embodiments, the driver is configured to drive two transistor groups in a time-division manner.

[0014] According to another aspect of the present disclosure, a voltage regulation module is provided, comprising: a power stage package of any of the above embodiments.

[0015] According to another aspect of the present disclosure, an electronic device is provided, comprising: a voltage regulation module of any of the above embodiments.

[0016] According to another aspect of the present disclosure, a method for manufacturing a power stage package is provided, comprising: providing a printed circuit board, the printed circuit board including a first wiring layer, a second wiring layer, and an insulating layer located between the first wiring layer and the second wiring layer; forming two transistor groups, each transistor group including a low-side transistor located on a first side of the printed circuit board and a high-side transistor located on a second side of the printed circuit board opposite to the first side, wherein a first electrode of the low-side transistor is sequentially connected to a second electrode of the high-side transistor via a first trace in the first wiring layer, a first via penetrating the insulating layer, and a second trace in the second wiring layer; forming a first encapsulation layer and a second encapsulation layer, the first encapsulation layer being located on the first side of the printed circuit board and covering the low-side transistor, and the second encapsulation layer being located on the second side of the printed circuit board and covering the high-side transistor; and forming an exposed first rewiring layer. The first wiring layer is configured to receive an input signal and includes: a first wiring portion covering a portion of a first side surface of the first package layer; a second wiring portion covering a portion of a second side surface of the first package layer; a third wiring portion covering a portion of a third side surface of the second package layer, wherein the first wiring portion is connected to the third wiring portion sequentially via a third trace in the first wiring layer, a second via penetrating an insulating layer, and a fourth trace in the second wiring layer; a fourth wiring portion covering a portion of a fourth side surface of the second package layer, wherein the second wiring portion is connected to the fourth wiring portion sequentially via a fifth trace in the first wiring layer, a third via penetrating an insulating layer, and a sixth trace in the second wiring layer; and a fifth wiring portion covering a portion of the surface of the second package layer away from the printed circuit board, adjacent to the third wiring portion and the fourth wiring portion respectively, and connected to the first electrode of the high-side transistor in each transistor group via a fourth via penetrating the second package layer.

[0017] In some embodiments, the two transistor groups are arranged in a first direction, and the first wiring layer further includes: a sixth wiring portion adjacent to the first wiring portion and extending in the first direction; and a seventh wiring portion adjacent to the third wiring portion and extending in the first direction, wherein the first wiring portion is connected to the third wiring portion in sequence via the sixth wiring portion, the third trace, the second via, the fourth trace and the seventh wiring portion.

[0018] In some embodiments, the first wiring layer further includes: an eighth wiring section adjacent to the second wiring section and extending in a first direction; and a ninth wiring section adjacent to the fourth wiring section and extending in a first direction, wherein the second wiring section is connected to the fourth wiring section sequentially via the eighth wiring section, the fifth trace, the third via, the sixth trace and the ninth wiring section.

[0019] In some embodiments, the first rewiring layer further includes at least one of the following: a tenth rewiring portion adjacent to the first rewiring portion and covering a portion of the surface of the first encapsulation layer away from the printed circuit board; and an eleventh rewiring portion adjacent to the second rewiring portion and covering another portion of the surface of the first encapsulation layer away from the printed circuit board.

[0020] In some embodiments, the area of ​​a portion of the surface of the second encapsulation layer covered by the fifth redistribution portion that is away from the printed circuit board is greater than half the area of ​​the surface of the second encapsulation layer that is away from the printed circuit board.

[0021] In the power stage package provided in this disclosure embodiment, a first rewiring layer for receiving input signals is exposed on the surface of the power stage package. The first rewiring layer covers a portion of two side surfaces of the first package layer and a portion of two side surfaces of the second package layer. Furthermore, the first rewiring layer extends from one side surface (i.e., the third side surface) of the second package layer to the top surface of the second package layer, and then to the other side surface (i.e., the fourth side surface) of the second package layer. Thus, the area of ​​the first rewiring layer exposed on the package surface is large, resulting in good heat dissipation and helping to reduce resistance.

[0022] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Simple Explanation of the Diagram

[0023] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the disclosure. This disclosure can be more clearly understood with reference to the accompanying drawings and the following detailed description, in which: Figure 1 is a circuit diagram illustrating a power stage package according to some embodiments of the present disclosure. Figure 2A is a side view showing a power stage package according to some embodiments of the present disclosure. Figure 2B is a top view showing a perspective view of the power stage package portion structure according to some embodiments of the present disclosure. Figure 2C is a bottom view showing a perspective view of a power stage package portion structure according to some embodiments of the present disclosure. Figure 3A is a schematic diagram showing a cross section taken along A-A' as shown in Figures 2B and 2C. Figure 3B is a schematic diagram showing a cross section taken along B-B' as shown in Figures 2B and 2C. Figure 4A is a top view schematic diagram showing the appearance of a power stage package according to some embodiments of the present disclosure. Figure 4B is a bottom view schematic diagram showing the appearance of a power stage package according to some embodiments of the present disclosure. Figure 5 is a schematic flowchart illustrating a method for manufacturing a power stage package according to some embodiments of the present disclosure. Implementation

[0024] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as merely exemplary and not as limiting.

[0025] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships; when the absolute position of the described object changes, this relative positional relationship may also change accordingly.

[0026] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0027] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0028] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0029] Figure 1 is a circuit diagram illustrating a power stage package according to some embodiments of the present disclosure.

[0030] As shown in Figure 1, the power stage package includes two transistor groups 12, each transistor group 12 including a high-side transistor HS and a low-side transistor LS connected in series. In each transistor group 12, the high-side transistor HS is connected between the input terminal VIN of the power stage package and the low-side transistor LS, and the low-side transistor LS is connected between the high-side transistor HS and the ground terminal VGND. As some implementations, the high-side transistor HS and the low-side transistor LS can be metal-oxide-semiconductor field-effect transistors (MOSFETs), such as N-type MOSFETs or P-type MOSFETs.

[0031] Driver 17 is connected to the high-side transistor HS and low-side transistor LS in each transistor group 12, respectively. Driver 17 can control the high-side transistor HS and low-side transistor LS in each transistor group 12 to be turned on or off according to the pulse width modulation (PWM) signal from the control IC. Specifically, driver 17 can be configured to control the low-side transistor LS in each transistor group 12 to be turned off when the high-side transistor HS is turned on, and to be turned on when the high-side transistor HS is turned off, so as to ensure that the high-side transistor HS and low-side transistor LS in each transistor group 12 are not turned on at the same time, avoiding a short circuit between the input terminal VIN and the ground terminal VGND.

[0032] In the two transistor groups 12, nodes SW1 and SW2 between the high-side transistor HS and the low-side transistor LS can be connected to the output terminal VOUT via inductors L, respectively.

[0033] Figure 2A is a side view showing a power stage package according to some embodiments of the present disclosure. Figure 2B is a top view showing a power stage package according to some embodiments of the present disclosure. Figure 2C is a bottom view showing a power stage package according to some embodiments of the present disclosure.

[0034] Figure 3A is a schematic diagram showing a cross-section taken along A-A' as shown in Figures 2B and 2C. Figure 3B is a schematic diagram showing a cross-section taken along B-B' as shown in Figures 2B and 2C.

[0035] The power stage package according to some embodiments of this disclosure will now be described with reference to Figures 2A-2C and 3A-3B. In Figures 2A, 3A, and 3B, the current path is shown by arrows.

[0036] As shown in Figures 1, 2A and 3A, the power stage package includes a printed circuit board (PCB) 11, two transistor groups 12, a first packaging layer 13, a second packaging layer 14 and an exposed first redistribution layer (RDL) 15.

[0037] Referring to Figures 2A and 3A, the printed circuit board 11 includes a first wiring layer 111, a second wiring layer 112, and an insulating layer 113 located between the first wiring layer 111 and the second wiring layer 112. The first wiring layer 111 and the second wiring layer 112 are located on the upper and lower surfaces of the insulating layer 113, respectively.

[0038] In each transistor group 12, the low-side transistor LS is located on the first side of the printed circuit board 11 (the lower side in Figures 2A and 3A), and the high-side transistor HS is located on the second side of the printed circuit board 11 opposite to the first side (the upper side in Figures 2A and 3A). The first electrode E1 of the low-side transistor LS is connected to the second electrode E2 of the high-side transistor HS via the first trace SW11 in the first wiring layer 111, the first via V1 penetrating the insulating layer 113, and the second trace SW12 in the second wiring layer 112. The second electrode E2 of the low-side transistor LS is connected to the ground terminal VGND.

[0039] The first encapsulation layer 13 is located on a first side of the printed circuit board 11 and covers the low-side transistor LS. The second encapsulation layer 14 is located on a second side of the printed circuit board 11 and covers the high-side transistor HS. In some embodiments, the first encapsulation layer 13 and the second encapsulation layer 14 are made of epoxy molding compound.

[0040] The exposed first multi-layer wiring 15 is configured to receive the input signal Vin, i.e., the input signal Vin is input to the first electrode E1 of the high-side transistor HS through the first multi-layer wiring 15. It should be understood that the entire exposed surface of the power stage package includes the surface of the first multi-layer wiring 15. For example, the material of the first multi-layer wiring 15 includes Cu, Ag, Sn, or a Ni / Au alloy.

[0041] Referring to Figure 3A, the first wiring layer 15 includes a first wiring section 151, a second wiring section 152, a third wiring section 153, a fourth wiring section 154, and a fifth wiring section 155.

[0042] The first rewiring portion 151 covers a portion of the first side surface S1 of the first encapsulation layer 13, and the second rewiring portion 152 covers a portion of the second side surface S2 of the first encapsulation layer 13. Here, the first side surface S1 and the second side surface S2 are two opposite side surfaces of the first encapsulation layer 13.

[0043] The third wiring section 153 covers a portion of the third side surface S3 of the second encapsulation layer 14, and the fourth wiring section 154 covers a portion of the fourth side surface S4 of the second encapsulation layer 14. Similarly, the third side surface S3 and the fourth side surface S4 are two opposite side surfaces of the second encapsulation layer 14.

[0044] The first wiring section 151 is connected to the third wiring section 153 via the third trace SW13 in the first wiring layer 111, the second through-hole V2 penetrating the insulation layer 113, and the fourth trace SW14 in the second wiring layer 112. The second wiring section 152 is connected to the fourth wiring section 154 via the fifth trace SW15 in the first wiring layer 111, the third through-hole V3 penetrating the insulation layer 113, and the sixth trace SW16 in the second wiring layer 112.

[0045] The fifth wiring section 155 covers a portion of the surface of the second encapsulation layer 14 away from the printed circuit board 11, and is adjacent to the third wiring section 153 and the fourth wiring section 154, respectively. In other words, the fifth wiring section 155 extends from the third wiring section 153 across the surface of the second encapsulation layer 14 away from the printed circuit board 11, and then extends to the fourth wiring section 154.

[0046] The fifth wiring section 155 is connected to the first electrode E1 of the high-side transistor HS in each transistor group 12 via the fourth through hole V4 that penetrates the second encapsulation layer 14.

[0047] In the above embodiment, on one hand, a first rewiring layer 15 for receiving the input signal Vin is exposed on the surface of the power stage package. The first rewiring layer 15 covers a portion of two side surfaces of the first package layer 13 and a portion of two side surfaces of the second package layer 14. Furthermore, the first rewiring layer 15 extends from one side surface (i.e., the third side surface S3) of the second package layer 14 to the upper surface of the second package layer 14, and further to the other side surface (i.e., the fourth side surface S4) of the second package layer 14. Thus, the area of ​​the first rewiring layer 15 exposed on the package surface is large, resulting in good heat dissipation and helping to reduce resistance.

[0048] On the other hand, the first wiring section 151 is connected to the third wiring section 153 via a second through-hole V2 penetrating the insulating layer 113, and the second wiring section 152 is connected to the fourth wiring section 154 via a third through-hole V3 penetrating the insulating layer 113. Thus, the printed circuit board 11 extends laterally, and the first wiring layer 15 does not extend to the side of the printed circuit board 11. When subjected to external impact or when the power stage package is clamped by automated equipment, it may impact or contact the side of the printed circuit board 11 without damaging the first wiring layer 15.

[0049] On the other hand, the two transistor groups 12 are integrated into a single power stage package, and each transistor group 12 includes two stacked transistors, which helps to reduce the size of the power stage package.

[0050] In some embodiments, the area of ​​a portion of the second encapsulation layer 14 covered by the fifth rewiring portion 155 on the surface away from the printed circuit board 11 is greater than half the area of ​​the second encapsulation layer 14 on the surface away from the printed circuit board 11. Thus, the area of ​​the first rewiring layer 15 exposed on the encapsulation surface is larger, resulting in better heat dissipation and further reducing resistance.

[0051] In some embodiments, referring to FIG3A, the two transistor groups 12 are arranged in a first direction. The first redistribution layer 15 further includes a sixth redistribution portion 156 and a seventh redistribution portion 157. The sixth redistribution portion 156 is adjacent to the first redistribution portion 151 and extends in the first direction. The seventh redistribution portion 157 is adjacent to the third redistribution portion 153 and extends in the first direction.

[0052] The first wiring section 151 is connected to the third wiring section 153 sequentially via the sixth wiring section 156, the third trace SW13, the second via V2, the fourth trace SW14, and the seventh wiring section 157. In this case, the connection between the first wiring section 151 and the third wiring section 153 is more reliable, and the first wiring layer 15 has a larger area exposed on the package surface, resulting in better heat dissipation and further reducing resistance.

[0053] In other embodiments, referring to FIG3A, the first rewiring layer 15 further includes an eighth rewiring section 158 and a ninth rewiring section 159. The eighth rewiring section 158 is adjacent to the second rewiring section 152 and extends in a first direction. The ninth rewiring section 159 is adjacent to the fourth rewiring section 154 and extends in a first direction.

[0054] The second wiring section 152 is connected to the fourth wiring section 154 sequentially via the eighth wiring section 158, the fifth trace SW15, the third via V3, the sixth trace SW16, and the ninth wiring section 159. In this case, the connection between the second wiring section 152 and the fourth wiring section 154 is more reliable, and the first wiring layer 15 has a larger area exposed on the package surface, resulting in better heat dissipation and further reducing resistance.

[0055] In some other embodiments, referring to FIG3A, the first wiring layer 15 further includes a sixth wiring section 156, a seventh wiring section 157, an eighth wiring section 158, and a ninth wiring section 159. Thus, the connection between the first wiring section 151 and the third wiring section 153 is more reliable, the connection between the second wiring section 152 and the fourth wiring section 154 is more reliable, and the first wiring layer 15 has a larger area exposed on the package surface, resulting in better heat dissipation and further reducing resistance.

[0056] In some embodiments, referring to FIG3A, the first rewiring layer 15 further includes at least one of a tenth rewiring portion 1510 and an eleventh rewiring portion 1511, for example, including a tenth rewiring portion 1510 and an eleventh rewiring portion 1511. The tenth rewiring portion 1510 is adjacent to the first rewiring portion 151 and covers a portion of the surface of the first encapsulation layer 13 away from the printed circuit board 11. The eleventh rewiring portion 1511 is adjacent to the second rewiring portion 152 and covers a portion of the surface of the first encapsulation layer 13 away from the printed circuit board 11. In this way, it is easier to mount the power stage package to input the input signal Vin into the first rewiring layer 15. In addition, the first rewiring layer 15 has a larger area exposed on the package surface, resulting in better heat dissipation and helping to further reduce resistance.

[0057] In some embodiments, referring to Figures 3A and 3B, the power stage package further includes an exposed second rewiring layer 16. The second rewiring layer 16 is configured to receive a ground signal Vgnd. The second rewiring layer 16 covers a portion of the surface of the first package layer 13 remote from the printed circuit board 11 and is connected to the second electrode E2 of the low-side transistor LS via a fifth via V5 through the first package layer 13. It should be understood that the second rewiring layer 16 is spaced apart from the first rewiring layer 15.

[0058] In this way, both the first wiring layer 15 and the second wiring layer 16 are exposed on the package surface, resulting in better heat dissipation and further reducing resistance.

[0059] In some embodiments, referring to Figures 2A and 3B, the power stage package further includes a driver 17 located on a second side of the printed circuit board 11 and covered by a second package layer 14.

[0060] Driver 17 is connected to the gate G of high-side transistor HS via the seventh trace SW17 in the second wiring layer 112. Furthermore, driver 17 is connected to the gate G of low-side transistor LS via, in sequence, a sixth via V6 through insulating layer 113, a seventh via V7 through first package layer 13, an eighth trace SW18 located on the surface of first package layer 13 away from printed circuit board 11, and an eighth via V8 through first package layer 13. For example, the eighth trace SW18 belongs to the second rewiring layer 16.

[0061] Figure 2A also shows solder SO in several locations. For example, driver 17 is connected to the seventh trace SW17 via solder SO, the seventh trace SW17 is connected to the gate G of the high-side transistor HS via solder SO, the second electrode E2 of the high-side transistor HS is connected to the second trace SW12 via solder SO, the first electrode E1 of the low-side transistor LS is connected to the first trace SW11 via solder SO, and so on.

[0062] In some embodiments, referring to FIG2A, the power stage package further includes a shielding layer GND located on the surface of the second package layer 14 away from the printed circuit board 11. The shielding layer GND can be configured to be grounded to reduce the adverse effects of external signals on the driver 17. In some embodiments, in a top view, the shielding layer GND completely covers the driver 17 to more effectively reduce the adverse effects of external signals on the driver 17.

[0063] In some embodiments, referring to FIG2A, the driver 17 in the power stage package can also output other signals through vias through the printed circuit board 11. For example, the driver 17 outputs current signals flowing through the high-side transistor HS and the low-side transistor LS via the ninth via V9 through the printed circuit board 11 and the tenth via V10 through the first package layer 13, for example, via the ninth trace SW19. For example, the ninth trace SW19 belongs to the second rewiring layer 16.

[0064] In some embodiments, referring to Figures 3A and 3B, the two high-side transistors HS of the two transistor groups 12 are arranged along a first direction, and the two low-side transistors LS are also arranged along the first direction. The driver 17 is arranged with the two transistor groups 12 in a second direction, which is perpendicular to the first direction and parallel to the surface of the printed circuit board 11. This helps to reduce the size of the power stage package.

[0065] In some embodiments, the driver 17 is configured to drive the two transistor groups 12 in a time-division manner.

[0066] For example, the driver 17 determines two drive signals to drive the two transistor groups 12 respectively based on the PWM signal from the control IC. The two drive signals are complementary, that is, when one drive signal is at a high potential, the other signal is at a low potential. In some embodiments, the signal formed by superimposing the two drive signals is the PWM signal from the control IC. The driver 17 drives the corresponding transistor group 12 to work during the period when the drive signal is at a high potential, thus realizing time-division driving of the two transistor groups 12.

[0067] In this way, a single control IC can drive more transistor groups 12 to work, rather than being limited by the number of pins of the control IC.

[0068] Figure 4A is a top view schematic diagram showing the power stage package according to some embodiments of the present disclosure. Figure 4B is a bottom view schematic diagram showing the power stage package according to some embodiments of the present disclosure.

[0069] As can be seen from Figure 4A, in some embodiments, the fifth wiring portion 155 of the first wiring layer 15 can cover most of the surface of the second encapsulation layer 14 away from the printed circuit board 11 to improve heat dissipation.

[0070] As can be seen from Figure 4B, in some embodiments, the second rewiring layer 16 can cover most of the surface of the first encapsulation layer 13 away from the printed circuit board 11 to improve heat dissipation.

[0071] In some embodiments, the voltage of the input signal of the power stage package is 0.1V to 100V, and the voltage of the output signal of the power stage package is, for example, 0.1V to 100V.

[0072] This disclosure also provides a voltage regulation module, including one or more power stage packages according to any of the above embodiments. In some embodiments, the voltage regulation module further includes a control IC that provides a PWM signal.

[0073] This disclosure also provides an electronic device, including: a voltage regulation module of any of the above embodiments.

[0074] Figure 5 is a schematic flowchart illustrating a method for manufacturing a power stage package according to some embodiments of the present disclosure.

[0075] In step 502, a printed circuit board 11 is provided. The printed circuit board 11 includes a first wiring layer 111, a second wiring layer 112, and an insulating layer 113 located between the first wiring layer 111 and the second wiring layer 112.

[0076] In step 504, two transistor groups 12 are formed, each transistor group 12 including a low-side transistor LS and a high-side transistor HS.

[0077] The low-side transistor LS is located on the first side of the printed circuit board 11, and the high-side transistor HS is located on the second side of the printed circuit board 11 opposite to the first side. The first electrode E1 of the low-side transistor LS is connected to the second electrode E2 of the high-side transistor HS via the first trace SW11 in the first wiring layer 111, the first via V1 through the insulating layer 113, and the second trace SW12 in the second wiring layer 112.

[0078] In step 506, a first encapsulation layer 13 and a second encapsulation layer 14 are formed.

[0079] The first encapsulation layer 13 is located on the first side of the printed circuit board 11 and covers the low-side transistor LS. The second encapsulation layer 14 is located on the second side of the printed circuit board 11 and covers the high-side transistor HS. After the first encapsulation layer 13 and the second encapsulation layer 14 are formed, the aforementioned vias can be formed in the first encapsulation layer 13 and the second encapsulation layer 14 by means of laser or the like.

[0080] In step 508, an exposed first rewiring layer 15 is formed, which is configured to receive input signals.

[0081] The first wiring layer 15 includes a first wiring section 151, a second wiring section 152, a third wiring section 153, a fourth wiring section 154, and a fifth wiring section 155, as shown in FIG3A. The relationships between the different parts are described above and will not be repeated here.

[0082] In some embodiments, the area of ​​a portion of the surface of the second encapsulation layer 14 covered by the fifth redistribution portion 155 away from the printed circuit board 11 is greater than half the area of ​​the surface of the second encapsulation layer 14 away from the printed circuit board 11.

[0083] In some embodiments, the two transistor groups 12 formed are arranged in a first direction, and the first redistribution layer 15 formed further includes a sixth redistribution section 156 and a seventh redistribution section 157 as shown in FIG3A.

[0084] In some embodiments, the first rewiring layer 15 further includes an eighth rewiring section 158 and a ninth rewiring section 159 as shown in FIG3A.

[0085] In some embodiments, the first rewiring layer 15 further includes at least one of the tenth rewiring section 1510 and the eleventh rewiring section 1511 shown in FIG3A.

[0086] The connection relationships between the sixth rewiring section 156, the seventh rewiring section 157, the eighth rewiring section 158, the ninth rewiring section 159, the tenth rewiring section 1510, and the eleventh rewiring section 1511 and other rewiring sections can be referred to the description above.

[0087] In some embodiments, the manufacturing method of the power stage package further includes forming an exposed second rewiring layer 16 as shown in FIG3A, configured to receive a ground signal.

[0088] In some embodiments, the manufacturing method of the power stage package further includes forming a driver 17 located on the second side of the printed circuit board 11 and covered by a second packaging layer 14. Specific connections between the driver 17 and the gate G of the high-side transistor HS and the gate G of the low-side transistor LS can be referred to the description above.

[0089] The embodiments disclosed herein have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0090] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0091] 11: Printed Circuit Board 12: Transistor Group 13: First encapsulation layer 14: Second encapsulation layer 15: First Rewiring Layer 151: First Re-wiring Department 152: Second Rewiring Department 153: Third Cabling Department 154: Fourth Re-wiring Department 155: Fifth Cabling Department 156: Sixth Cabling Department 157: Seventh Cabling Department 158: Eighth Cabling Department 159: Ninth Cabling Department 1510: Tenth Cabling Department 1511: Eleventh Rewiring Department 16: Second wiring layer 17: Drive 111: First wiring layer 112: Second wiring layer 113: Insulation layer E1: First electrode E2: Second electrode G: Gate GND: Shielding layer HS: High-side transistor LS: Low-side transistor S1: First side surface S2: Second side surface S3: Third side surface S4: Fourth side surface SO: Solder SW11: First routing SW12: Second route SW13: Third routing SW14: Fourth route SW15: Fifth Route SW16: Sixth route SW17: Seventh Route SW18: Eighth route SW19: Ninth Route V1: First through hole V2: Second through hole V3: Third through hole V4: Fourth through hole V5: Fifth through hole V8: Eighth through hole V9: Ninth through hole V10: Tenth through hole VGND: Ground terminal Vgnd: Ground signal VIN: Input terminal Vin: Input signal VOUT: Output terminal

Claims

1. A power stage package, comprising: A printed circuit board includes a first wiring layer, a second wiring layer, and an insulating layer located between the first wiring layer and the second wiring layer; Each of the two transistor groups includes: a low-side transistor located on a first side of the printed circuit board, and a high-side transistor located on a second side of the printed circuit board opposite to the first side; a first electrode of the low-side transistor being connected to a second electrode of the high-side transistor via a first trace in the first wiring layer, a first via through the insulating layer, and a second trace in the second wiring layer; a first encapsulation layer located on the first side of the printed circuit board and covering the low-side transistor; a second encapsulation layer located on the second side of the printed circuit board and covering the high-side transistor; and an exposed first redistribution layer configured to receive an input signal, and including: a first redistribution portion covering a portion of a first side surface of the first encapsulation layer; and a second redistribution portion covering a portion of a second side surface of the first encapsulation layer. A third wiring section covers a portion of a third side surface of the second encapsulation layer, and the first wiring section is connected to the third wiring section sequentially via a third trace in the first wiring layer, through a second via in the insulating layer, and a fourth trace in the second wiring layer. A fourth wiring section covers a portion of a fourth side surface of the second encapsulation layer, and the second wiring section is connected to the fourth wiring section sequentially via a fifth trace in the first wiring layer, through a third via in the insulating layer, and a sixth trace in the second wiring layer. A fifth wiring section covers a portion of a surface of the second encapsulation layer away from the printed circuit board, is adjacent to the third wiring section and the fourth wiring section respectively, and is connected to a first electrode of the high-side transistor in each transistor group via a fourth via in the second encapsulation layer.

2. The power stage package as described in claim 1, wherein, The two high-side transistors of the transistor group are arranged along a first direction. The first rewiring layer further includes: a sixth rewiring section adjacent to the first rewiring section and extending in the first direction; and a seventh rewiring section adjacent to the second rewiring section and extending in the first direction, wherein the first rewiring section is connected to the third rewiring section in sequence via the sixth rewiring section, the third trace, the second via, the fourth trace, and the seventh rewiring section.

3. The power stage package as described in claim 2, wherein, The first wiring layer further includes: an eighth wiring section adjacent to the second wiring section and extending in the first direction; and a ninth wiring section adjacent to the fourth wiring section and extending in the first direction, wherein the second wiring section is connected to the fourth wiring section sequentially via the eighth wiring section, the fifth trace, the third via, the sixth trace and the ninth wiring section.

4. The power stage package as described in any one of claims 1-3, wherein, The first wiring layer further includes at least one of the following: a tenth wiring portion adjacent to the first wiring portion and covering a portion of the surface of the first encapsulation layer away from the printed circuit board; and an eleventh wiring portion adjacent to the second wiring portion and covering another portion of the surface of the first encapsulation layer away from the printed circuit board.

5. The power stage package as described in any one of claims 1-3, further comprising: An exposed second wiring layer, configured to receive a ground signal, covers a portion of the surface of the first package layer away from the printed circuit board and is connected to a second electrode of the low-side transistor via a fifth via through the first package layer.

6. The power stage package as described in any one of claims 1-3, wherein, The area of ​​the portion of the second encapsulation layer covered by the fifth redistribution section that is away from the surface of the printed circuit board is greater than half the area of ​​the second encapsulation layer away from the surface of the printed circuit board.

7. The power stage package as described in any one of claims 1-3, further comprising: A driver, located on the second side of the printed circuit board and covered by the second encapsulation layer, is connected to a gate of the high-side transistor via a seventh trace in the second wiring layer, and is connected to a gate of the low-side transistor in sequence via a sixth via through the insulating layer, a seventh via through the first encapsulation layer, an eighth trace located on the surface of the first encapsulation layer away from the printed circuit board, and an eighth via through the first encapsulation layer.

8. The power stage package as described in claim 7, wherein, The two high-side transistors of the transistor group are arranged along a first direction, and the driver and the transistor group are arranged along a second direction, which is perpendicular to the first direction and parallel to the surface of the printed circuit board.

9. The power stage package as described in claim 7, wherein, The driver is configured to drive the transistor group in a time-division manner.

10. A voltage regulation module comprising a power stage package as described in any one of claims 1-3.

11. A method for manufacturing a power stage package, comprising: A printed circuit board is provided, the printed circuit board including a first wiring layer, a second wiring layer and an insulating layer located between the first wiring layer and the second wiring layer; A dual transistor group is formed, each transistor group comprising: a low-side transistor located on a first side of the printed circuit board, and a high-side transistor located on a second side of the printed circuit board opposite to the first side; a first electrode of the low-side transistor being connected to a second electrode of the high-side transistor via a first trace in the first wiring layer, a first via penetrating the insulating layer, and a second trace in the second wiring layer; a first encapsulation layer and a second encapsulation layer are formed, the first encapsulation layer being located on the first side of the printed circuit board and covering the low-side transistor, and the second encapsulation layer being located on the second side of the printed circuit board and covering the high-side transistor; and an exposed first rewiring layer is formed, the first rewiring layer being configured to receive an input signal and comprising: a first rewiring portion covering a portion of a first side surface of the first encapsulation layer, and a second rewiring portion covering a portion of a second side surface of the first encapsulation layer. A third wiring section covers a portion of a third side surface of the second encapsulation layer, and the first wiring section is connected to the third wiring section sequentially via a third trace in the first wiring layer, a second via penetrating the insulating layer, and a fourth trace in the second wiring layer. A fourth wiring section covers a portion of a fourth side surface of the second encapsulation layer, and the second wiring section is connected to the fourth wiring section sequentially via a fifth trace in the first wiring layer, a third via penetrating the insulating layer, and a sixth trace in the second wiring layer. A fifth wiring section covers a portion of the surface of the second encapsulation layer away from the printed circuit board, is adjacent to the third wiring section and the fourth wiring section respectively, and is connected to a first electrode of the high-side transistor in each transistor group via a fourth via penetrating the second encapsulation layer.

12. A method for manufacturing a power stage package as described in claim 11, wherein, The two transistor groups are arranged in a first direction, and the first wiring layer further includes: a sixth wiring section adjacent to the first wiring section and extending in the first direction; and a seventh wiring section adjacent to the third wiring section and extending in the first direction, wherein the first wiring section is connected to the third wiring section sequentially via the sixth wiring section, the third trace, the second via, the fourth trace, and the seventh wiring section.

13. A method for manufacturing a power stage package as described in claim 12, wherein, The first wiring layer further includes: an eighth wiring section adjacent to the second wiring section and extending in the first direction; and a ninth wiring section adjacent to the fourth wiring section and extending in the first direction, wherein the second wiring section is connected to the fourth wiring section sequentially via the eighth wiring section, the fifth trace, the third via, the sixth trace and the ninth wiring section.

14. A method of manufacturing a power stage package as described in any one of claims 11-13, wherein, The first wiring layer further includes at least one of the following: a tenth wiring portion adjacent to the first wiring portion and covering a portion of the surface of the first encapsulation layer away from the printed circuit board; and an eleventh wiring portion adjacent to the second wiring portion and covering another portion of the surface of the first encapsulation layer away from the printed circuit board.

15. A method of manufacturing a power stage package as described in any one of claims 11-13, wherein, The area of ​​the portion of the second encapsulation layer covered by the fifth redistribution section that is away from the surface of the printed circuit board is greater than half the area of ​​the second encapsulation layer away from the surface of the printed circuit board.

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