Three-dimensional memory device and method of forming the same

Abstract

A memory device, a memory system, and a manufacturing method are provided. The memory device includes a first semiconductor structure including an array of memory cells in a memory array region of the first semiconductor structure. The array of memory cells includes an array of transistors and an array of storage components connected to corresponding transistors. The first semiconductor structure further includes an isolation structure between the memory array region and a contact region of the first semiconductor structure. The isolation structure isolates the array of storage components in the memory array region from the contact region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to international application PCT / CN2024 / 134870, filed on November 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, this disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and methods of manufacturing them. Background Technology

[0004] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and expensive. As a result, the storage density of planar memory cells is approaching its upper limit.

[0005] Three-dimensional (3D) storage architectures can address the density limitations of planar storage cells. A 3D storage architecture includes a storage array and peripheral circuitry to facilitate the operation of the storage array. Summary of the Invention

[0006] In one aspect, a storage device includes a first semiconductor structure comprising an array of memory cells in a memory array region of the first semiconductor structure. The memory cell array includes an array of transistors and an array of storage components, the storage components being connected to corresponding transistors. The first semiconductor structure further includes an isolation structure located between the memory array region and a contact region of the first semiconductor structure. The isolation structure isolates the array of storage components in the memory array region from the contact region.

[0007] In some embodiments, the first semiconductor structure further includes a stacked structure comprising alternating first layers and first dielectric layers in the contact region.

[0008] In some embodiments, the first dielectric layer includes a first dielectric material, and the first layer includes a second dielectric layer, the second dielectric layer including a second dielectric material.

[0009] In some embodiments, the first dielectric layer includes a first dielectric material, and the first layer includes at least a second dielectric layer and a third dielectric layer, wherein the second dielectric layer includes a second dielectric material and the third dielectric layer includes a third dielectric material.

[0010] In some embodiments, the first semiconductor structure further includes a first contact structure extending through the stacked structure in a first direction. The end surface of the first contact structure on the first portion of the first layer is flush with the end surface of the isolation structure on the first portion of the first layer.

[0011] In some embodiments, the first semiconductor structure further includes: a second contact structure extending through the stacked structure in the first direction and coupled to a word line; and a third contact structure extending through the stacked structure in the first direction and coupled to a word line. The end surface of the second contact structure on the first terminator in the first layer is flush with the end surface of the third contact structure on the first terminator in the first layer.

[0012] In some embodiments, the size of the end surface of the second contact structure is equal to the size of the end surface of the third contact structure.

[0013] In some embodiments, the size of the end surface of the first contact structure is greater than the size of the end surface of the second contact structure and the end surface of the third contact structure; or, the size of the end surface of the isolation structure is greater than the size of the end surface of the second contact structure and the end surface of the third contact structure.

[0014] In some embodiments, the size of the end surface of the first contact structure is equal to the size of the end surface of the isolation structure.

[0015] In some embodiments, the dimensions of the end surface of the first contact structure are different from the dimensions of the end surface of the isolation structure.

[0016] In some embodiments, the isolation structure includes a dielectric material, and the first contact structure includes a conductive material.

[0017] In some embodiments, the storage device further includes a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the storage cell array.

[0018] In some embodiments, the transistor includes a vertical transistor, and the storage component includes a vertical capacitor.

[0019] In some embodiments, the vertical capacitor includes: a first electrode structure coupled to a corresponding vertical transistor; and a second electrode structure isolated from the first electrode structure. The end surface of the first electrode structure located on the first electrode in the first layer is flush with the end surfaces of the second contact structure and the third contact structure.

[0020] In some embodiments, the size of the end surface of the first electrode structure is equal to the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

[0021] In another aspect, a storage device is disclosed. The storage device includes a first semiconductor structure comprising an array of memory cells in a memory array region of the first semiconductor structure. The memory cell array includes an array of vertical transistors and an array of vertical capacitors connected to corresponding vertical transistors. The first semiconductor structure further includes a stacked structure comprising alternating first layers and first dielectric layers in a contact region of the first semiconductor structure. The first semiconductor structure also includes an isolation structure located between the memory array region and the contact region to isolate the array of vertical capacitors from the stacked structure.

[0022] In some embodiments, the first dielectric layer includes a first dielectric material, and the first layer includes a second dielectric layer, the second dielectric layer including a second dielectric material.

[0023] In some embodiments, the first dielectric layer includes a first dielectric material, and the first layer includes at least a second dielectric layer and a third dielectric layer, wherein the second dielectric layer includes a second dielectric material and the third dielectric layer includes a third dielectric material.

[0024] In some embodiments, the first semiconductor structure further includes a first contact structure extending through the stacked structure in a first direction. The end surface of the first contact structure on the first portion of the first layer is flush with the end surface of the isolation structure on the first portion of the first layer.

[0025] In some embodiments, the first semiconductor structure further includes: a second contact structure extending through the stacked structure in the first direction and coupled to a word line; and a third contact structure extending through the stacked structure in the first direction and coupled to a word line. The end surface of the second contact structure on the first terminator in the first layer is flush with the end surface of the third contact structure on the first terminator in the first layer.

[0026] In some embodiments, the size of the end surface of the second contact structure is equal to the size of the end surface of the third contact structure.

[0027] In some embodiments, the size of the end surface of the first contact structure is greater than the size of the end surface of the second contact structure and the end surface of the third contact structure; or, the size of the end surface of the isolation structure is greater than the size of the end surface of the second contact structure and the end surface of the third contact structure.

[0028] In some embodiments, the size of the end surface of the first contact structure is equal to the size of the end surface of the isolation structure.

[0029] In some embodiments, the dimensions of the end surface of the first contact structure are different from the dimensions of the end surface of the isolation structure.

[0030] In some embodiments, the isolation structure includes a dielectric material, and the first contact structure includes a conductive material.

[0031] In some embodiments, the storage device further includes a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the storage cell array.

[0032] In some embodiments, the vertical capacitor includes: a first electrode structure coupled to the corresponding vertical transistor; and a second electrode structure isolated from the first electrode structure. The end surface of the first electrode structure located on the first electrode in the first layer is flush with the end surfaces of the second contact structure and the third contact structure.

[0033] In some embodiments, the size of the end surface of the first electrode structure is equal to the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

[0034] In another aspect, a method for forming a memory device is disclosed. The method includes forming a first semiconductor structure by forming an array of memory cells in a memory array region of a first semiconductor structure. Forming the memory cell array includes forming an array of transistors in the memory array region; and forming an array of storage components in the memory array region, the storage components being connected to corresponding transistors. Forming the first semiconductor structure further includes forming an isolation structure between the memory array region and a contact region of the first semiconductor structure to isolate the array of storage components in the memory array region from the contact region.

[0035] In some embodiments, forming the first semiconductor structure further includes forming a stacked structure comprising alternating first layers and first dielectric layers across the memory array region and the contact region.

[0036] In some embodiments, forming the first semiconductor structure further includes: forming a first contact opening, a second contact opening, and a third contact opening extending through the stacked structure in a first direction in the contact region; forming a storage opening extending through the stacked structure in the first direction in the storage array region; and forming an isolation opening extending through the stacked structure in the first direction between the storage array region and the contact region.

[0037] In some embodiments, forming the isolation structure includes forming the isolation structure in the isolation opening.

[0038] In some embodiments, forming the first semiconductor structure further includes: forming a first contact structure in the first contact opening; forming a second contact structure in the second contact opening to couple to a word line; and forming a third contact structure in the third contact opening to couple to a word line. The end surface of the first contact structure on the first party in the first layer is flush with the end surface of the isolation structure on the first party in the first layer. The end surface of the second contact structure on the first party in the first layer is flush with the end surface of the third contact structure on the first party in the first layer.

[0039] In some embodiments, the storage component includes a vertical capacitor, and the array forming the storage component includes: forming first electrode structures in the storage openings, wherein the first electrode structures are coupled to the transistors respectively; and forming second electrode structures isolated from the first electrode structures. The vertical capacitor includes a corresponding first electrode structure and a corresponding second electrode structure.

[0040] In some embodiments, forming a second electrode structure isolated from the first electrode structure includes: forming a storage recess in the storage array region; and forming a second electrode structure isolated from the first electrode structure in the storage recess.

[0041] In some embodiments, forming the storage recess in the storage array region includes: forming a first mesh opening extending through a first element in the first layer of the storage array region; removing a first portion of the first element in the first dielectric layer of the storage array region through the first mesh opening, wherein the remaining portion of the first element in the first dielectric layer of the contact region is isolated by the isolation structure and remains intact; forming a second mesh opening extending through a second element in the first layer of the storage array region; and removing a portion of the second element in the first dielectric layer of the storage array region through the second mesh opening, wherein the remaining portion of the second element in the first dielectric layer of the contact region is isolated by the isolation structure and remains intact.

[0042] In some embodiments, forming a second electrode structure isolated from the first electrode structure includes: forming a storage dielectric layer to cover the first electrode structure in the storage recess; and forming the second electrode structure in the storage recess by depositing a conductive layer over the storage dielectric layer.

[0043] In some embodiments, the method further includes: forming a second semiconductor structure; and bonding the second semiconductor structure to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the memory cell array. Attached Figure Description

[0044] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0045] Figure 1A A schematic diagram of a cross-section of a 3D storage device according to some aspects of this disclosure is shown.

[0046] Figure 1B A schematic circuit diagram of a storage device including peripheral circuitry and an array of dynamic random access memory (DRAM) cells, according to some aspects of this disclosure, is shown.

[0047] Figure 2A A side view of a cross-section of a storage device according to some examples of this disclosure is shown.

[0048] Figure 2B A plan view of a cross-section of a storage device according to some examples of this disclosure is shown.

[0049] Figures 3A to 3M The present disclosure illustrates some examples of manufacturing processes for forming storage devices.

[0050] Figure 4A A side view of a cross-section of a storage device according to some aspects of this disclosure is shown.

[0051] Figure 4B A plan view of a cross-section of a storage device according to some aspects of this disclosure is shown.

[0052] Figure 4C An enlarged view of a vertical capacitor according to some aspects of this disclosure is shown.

[0053] Figure 4D Another side view of a cross-section of a storage device according to some aspects of this disclosure is shown.

[0054] Figures 5A to 5Z and Figures 6A to 6B A manufacturing process for forming a storage device is shown, according to some aspects of this disclosure.

[0055] Figure 7A A flowchart illustrating a method for forming a 3D storage device according to some aspects of this disclosure is shown.

[0056] Figure 7B A flowchart of a method for forming a first semiconductor structure according to some aspects of this disclosure is shown.

[0057] Figure 8 A block diagram of an exemplary system having a 3D storage device is shown, according to some aspects of this disclosure.

[0058] Figure 9A An illustration of an exemplary memory card with a 3D storage device is shown, according to some aspects of this disclosure.

[0059] Figure 9B An illustration of an exemplary solid-state drive (SSD) with 3D storage device is shown, according to some aspects of this disclosure.

[0060] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0061] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically described in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0062] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can also be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can be at least partly depending on the context, allowing for the presence of other factors that are not necessarily explicitly described.

[0063] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” in the case of a layer with an intermediate feature or in between; and “above” or “above” means not only “on” or “above” but also “on” or “above” in the case of a layer without an intermediate feature or in between (i.e., directly on).

[0064] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to describe the relationship of one element or feature to another (or more) element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0065] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0066] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0067] In some examples, the storage device can be divided into storage array regions and contact regions, wherein the storage array regions are separated from each other by contact regions (e.g., the storage array regions are surrounded by contact regions). Storage cell arrays can be formed in the respective storage array regions, and the entire contact region can be filled with a dielectric material (e.g., silicon oxide) to isolate the storage cell arrays from each other. However, in order to fill the contact regions with dielectric material, it is necessary to remove the stacked structures previously formed in the contact regions (e.g., as shown below). Figures 3H to 3J (As shown). This removal of the stacked structure in the contact area and the refilling of the contact area with dielectric material can lead to high manufacturing costs. Additionally, the lateral width used to remove the stacked structure in the contact area (e.g., Figure 3J The large horizontal width (330) shown may lead to wasted space between storage cell arrays.

[0068] To address one or more of the aforementioned problems, this disclosure describes a solution in which an isolation structure can be formed between a storage array region and a contact region of a storage device to isolate the storage array region from the contact region. The storage cell array can be formed in the storage array region, while the contact structure can be formed within a stacked structure in the contact region. Because of the isolation structure, it is not necessary to remove the stacked structure in the contact region (e.g., the stacked structure in the contact region remains intact), and therefore it is not necessary to refill the contact region with dielectric material to achieve isolation of the storage cell array. Thus, manufacturing costs can be reduced, and space between storage cell arrays can be saved.

[0069] Figure 1AA schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. Components of the 3D memory device 100 (e.g., memory cell array 130 and peripheral circuitry 132) may be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 104 (also referred to as a memory structure) and a second semiconductor structure 102 (also referred to as a circuit structure). The first semiconductor structure 104 may include the memory cell array 130 in the memory array region 110 and contact structures 125 in one or more contact regions 112 (e.g., referred to below). Figures 4A to 4D The contact structures 402, 408, 410, and 485 are described. The second semiconductor structure 102 may include peripheral circuitry 132 of the memory cell array 130.

[0070] Peripheral circuitry 132 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 130. For example, peripheral circuitry 132 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component (e.g., transistors, diodes, resistors, or capacitors) of the circuitry. According to some embodiments, peripheral circuitry 132 in the second semiconductor structure 102 uses complementary metal-oxide-semiconductor (CMOS) technology, which may be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0071] In some embodiments, the first semiconductor structure 104 may include an array of memory cells (memory cell array 130) that can use transistors as switching and selection devices. In some embodiments, the memory cell array 130 includes an array of DRAM cells. For ease of description, a DRAM cell array may be used as an example to describe the memory cell array 130 in this disclosure. However, it should be understood that the memory cell array 130 is not limited to a DRAM cell array and may include any other suitable type of memory cell array that can use transistors as switching and selection devices, such as a phase-change memory (PCM) cell array, a static random access memory (SRAM) cell array, a ferroelectric random access memory (FRAM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin-transfer torque (STT) memory cell array, or any combination thereof.

[0072] In some embodiments, the first semiconductor structure 104 may be a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells. A DRAM cell includes a capacitor for storing data bits as positive or negative charges and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to it. In some embodiments, the DRAM cell is a single-transistor single-capacitor (1T1C) cell. Since transistors always leak a small amount of charge, the capacitor will slowly discharge, causing the information stored therein to be depleted. Therefore, according to some embodiments, the DRAM cell must be refreshed (e.g., via peripheral circuitry 132 in the second semiconductor structure 102) to retain the data.

[0073] like Figure 1A As shown, the 3D storage device 100 also includes a vertically positioned (in the vertical direction, for example, Figure 1AThe bonding interface 106 (in the z-direction) is located between the second semiconductor structure 102 and the first semiconductor structure 104. As described in more detail below, the first semiconductor structure 104 and the second semiconductor structure 102 can be manufactured separately (and in some embodiments in parallel) such that the thermal budget for manufacturing one of the semiconductor structures 102 and 104 does not limit the process for manufacturing the other of the semiconductor structures 102 and 104. Furthermore, in contrast to long-distance (e.g., millimeter or centimeter-scale) chip-to-chip data buses on circuit boards (such as printed circuit boards (PCBs)), a large number of interconnects 115 (e.g., bonding contacts) can be formed through the bonding interface 106 to provide direct, short-distance (e.g., micrometer-scale) electrical connections between the second semiconductor structure 102 and the first semiconductor structure 104, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array 130 in the first semiconductor structure 104 and the peripheral circuitry 132 in the second semiconductor structure 102 can be performed via the interconnects 115 (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first semiconductor structure 104 and the second semiconductor structure 102, the chip size can be reduced and the memory cell density can be increased.

[0074] In such Figure 1A In some embodiments shown, the first semiconductor structure 104 may further include a contact region 112 surrounding the memory array region 110. One or more contact structures 125 may extend vertically within the contact region 112. A first end of the contact structure 125 may be electrically connected to a corresponding interconnect 115 or any other interconnect structure in the first semiconductor structure 104. A second end of the contact structure 125 may be electrically connected to a contact pad 150 via a pad output interconnect layer (not shown). In some embodiments, the pad output interconnect layer and the contact pad 150 may transmit electrical signals between the 3D memory device 100 and external circuitry, for example, for pad output purposes.

[0075] It should be understood that the relative positions of the stacked first semiconductor structure 104 and second semiconductor structure 102 are not limited. According to some embodiments, a bonding interface 106 is formed vertically between the first semiconductor structure 104 and the second semiconductor structure 102 in the 3D memory device 100, and the first semiconductor structure 104 and the second semiconductor structure 102 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding (also referred to as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide to silicon oxide) bonding. Data transfer between the memory cell array 130 in the first semiconductor structure 104 and the peripheral circuitry 132 in the second semiconductor structure 102 can be performed via interconnects 115 (e.g., bonding contacts) across the bonding interface 106.

[0076] It should be noted that, Figure 1A The x, y, and z axes are included to further illustrate the spatial relationships of the components in the 3D memory device 100. The substrate of the 3D memory device includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of a wafer on which a semiconductor device may be formed, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to the x and y axes. As used herein, when the substrate is positioned in the lowest plane of the 3D memory device in the z-direction, whether a component (e.g., a layer or device) is “above,” “on top of,” or “below” another component (e.g., a layer or device) of the 3D memory device is determined relative to the substrate of the 3D memory device in the z-direction (a direction perpendicular to the xy plane, e.g., the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0077] Figure 1BA schematic diagram of a storage device 160, including peripheral circuitry 132 and a storage cell array 130 (e.g., an array of storage cells 170), is shown according to some aspects of this disclosure. The peripheral circuitry 132 is coupled to the storage cell array 130. The storage device 160 can be an example of a 3D storage device 100. The storage cell array 130 can be any suitable storage cell array, wherein the storage cells 170 include vertical transistors 172 and storage components 174 coupled to the vertical transistors 172. In some embodiments, the storage cell array 130 is a DRAM cell array, and the storage components 174 are capacitors for storing charge as binary information stored by the respective DRAM cells. In some embodiments, the storage cell array 130 is a PCM cell array, and the storage components 174 are PCM elements (e.g., including chalcogenide alloys) for storing binary information of the respective PCM cells based on the different resistivities of the PCM elements in amorphous and crystalline phases. In some implementations, the memory cell array 130 is an FRAM cell array, and the storage component 174 is a ferroelectric capacitor used to store binary information of the corresponding FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0078] like Figure 1B As shown, the memory cells 170 can be arranged as a two-dimensional (2D) array with rows and columns. The memory device 160 may include: word lines 166 coupled to the peripheral circuitry 132 and the memory cell array 130 for controlling the switching of vertical transistors 172 in the memory cells 170 located in a row; and bit lines 168 coupled to the peripheral circuitry 132 and the memory cell array 130 for sending data to and / or receiving data from the memory cells 170 located in a column. That is, word lines 166 are coupled to the corresponding rows of memory cells 170, and bit lines 168 are coupled to the corresponding columns of memory cells 170.

[0079] Consistent with the scope of this disclosure, a vertical transistor 172 (such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) can replace a conventional planar transistor with a transfer transistor in the memory cell 170 to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. Figure 1B As shown, in some embodiments, unlike planar transistors where the active region is formed in a substrate, the vertical transistor 172 includes a semiconductor body 175 extending vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body 175 may extend above the top surface of the substrate to expose not only the top surface of the semiconductor body 175 but also one or more of its side surfaces. Figure 1AAs shown, for example, the semiconductor body 175 may have a cuboid shape to expose its four sides. It should be understood that the semiconductor body 175 may have any suitable 3D shape, such as a polyhedral or cylindrical shape. That is, the cross-section of the semiconductor body 175 in a planar view (e.g., in the xy plane) may have a square, rectangular (or trapezoidal), circular (or elliptical) shape, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body having a circular or elliptical shape in a planar view, the semiconductor body may still be considered to have multiple sides, such that the gate structure contacts more than one side of the semiconductor body. The semiconductor body 175 may be formed from a substrate (e.g., by etching or epitaxy) and therefore have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0080] In some embodiments, the vertical transistor 172 may further include a gate structure 178 that contacts one or more sides of the semiconductor body 175 (i.e., in one or more planes of the side surfaces(s) of the active region). In other words, the active region (i.e., the semiconductor body 175) of the vertical transistor 172 may be at least partially surrounded by the gate structure 178. Note that... Figure 1B The diagram shows that the gate structure 178 can be a full-wrap gate structure that laterally surrounds all sides of the semiconductor body 175. Figure 1B In some other embodiments not shown, the gate structure 178 may include one or more flat or curved sides that partially surround the semiconductor body 175.

[0081] The gate structure 178 may include a gate dielectric layer 177 over one or more sides of the semiconductor body 175 (e.g., in contact with the four side surfaces of the semiconductor body 175), such as Figure 1BAs shown. The gate structure 178 may also include a gate electrode 176 located above and in contact with the gate dielectric layer 177. The gate dielectric layer 177 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 177 may include silicon oxide, i.e., a gate oxide. The gate electrode 176 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 176 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 176 includes multiple conductive layers, such as a W layer above a TiN layer. It should be understood that in some examples, the gate electrode 176 and the word line 166 may be a continuous conductive structure. In other words, the gate electrode 176 can be considered as part of the word line 166 forming the gate structure 178, or the word line 166 can be considered as an extension of the gate electrode 176 to couple to the peripheral circuit 132.

[0082] like Figure 1B As shown, the vertical transistor 172 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed at opposite ends of the semiconductor body 175 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (such as boron (B) or gallium (Ga)) or any suitable N-type dopant (such as phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 178. In other words, the gate structure 178 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 176 of the gate structure 178 is higher than the threshold voltage of the vertical transistor 172, one or more channels (not shown) of the vertical transistor 172 can be formed vertically between the source and drain electrodes in the semiconductor body 175. That is, according to some embodiments, the channels of the vertical transistor 172 are also formed in the semiconductor body 175 along the vertical direction in which it extends.

[0083] In some implementations, such as Figure 1B As shown, the vertical transistor 172 is a multi-gate transistor. That is, the gate structure 178 can be connected to more than one side of the semiconductor body 175 (e.g., Figure 1BThe four sides of the transistor 172 are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. It should be understood that the vertical transistor 172 disclosed herein may also include a single-gate transistor. That is, the gate structure 178 may be contacted on one side of the semiconductor body 175, for example, for increasing transistor and memory cell density. It should also be understood that although the gate dielectric layer 177 is shown as separate from other gate dielectrics of adjacent vertical transistors (not shown) (i.e., a separated structure), the gate dielectric layer 177 may be part of a continuous dielectric layer of multiple gate dielectric layers having the vertical transistor 172.

[0084] According to some embodiments, in the vertical transistor 172, the semiconductor body 175 extends vertically (in the z-direction), and the source and drain are disposed in different lateral planes. In some embodiments, the source and drain are formed at opposite ends of the semiconductor body 175 in the vertical direction (z-direction), thereby overlapping in a planar view. As a result, the area occupied (in the xy-plane) of the vertical transistor 172 can be reduced compared to planar transistors and lateral multi-gate transistors. Moreover, the metal wiring coupled to the vertical transistor 172 can also be simplified because the interconnects can be wired in different planes. For example, bit line 168 and storage component 174 can be formed on opposite sides of the vertical transistor 172. In one example, bit line 168 can be coupled to a source or drain at the upper end of the semiconductor body 175, while storage component 174 can be coupled to another source or drain at the lower end of the semiconductor body 175.

[0085] like Figure 1B As shown, storage component 174 can be coupled to the source or drain of vertical transistor 172. Storage component 174 may include any means capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some embodiments, vertical transistor 172 controls the selection and / or state switching of the corresponding storage component 174 coupled to vertical transistor 172. Figure 1B In some embodiments shown, the memory cell 170 includes a vertical transistor 172 and a capacitor (e.g., Figure 1B Example of a DRAM cell (storage component 174 in the example). In some embodiments, the capacitor is a vertical capacitor. See below for reference. Figure 4A and Figure 4C A more detailed description of an example structure for a vertical capacitor.

[0086] Peripheral circuitry 132 may be coupled to memory cell array 130 via bit line 168, word line 166, and any other suitable metal wiring. As described above, peripheral circuitry 132 may include any suitable circuitry for facilitating operation of memory cell array 130 by applying voltage and / or current signals to memory cells 170 via word line 166 and bit line 168, and by sensing voltage and / or current signals from memory cells 170 via word line 166 and bit line 168.

[0087] Figure 2A A side view of a cross section of a storage device 200 according to some examples of this disclosure is shown. Figure 2B A plan view of a cross section of a storage device 200 according to some examples of the present disclosure is shown. Figure 2B The cross section of the storage device 200 in the middle can be along Figure 2A Line A1-A1 in the middle. Figure 2A The cross section of the storage device 200 in the middle can be along Figure 2B Line B1-B1 in the diagram. Describe together. Figure 2A and Figure 2B .

[0088] Storage device 200 can be Figure 1A An example of a 3D storage device 100. (e.g.) Figure 2A As shown, the storage device 200 may include a first semiconductor structure 104. The first semiconductor structure 104 includes a transistor structure 202 and a storage structure 204 stacked above the transistor structure 202. The transistor structure 202 may include an array of transistors (e.g., an array of vertical transistors 172). The storage structure 204 may include an array of memory cells 130 in a memory array region 110. The memory cell array 130 may include an array of vertical capacitors 274, which includes a GeSi layer 210. A W layer 208 may cover the GeSi layer 210. The storage structure 204 may also include a dielectric structure 206, which is formed by filling contact regions 112 with a dielectric material (e.g., silicon oxide). A portion of the dielectric structure 206 may be formed on top of the W layer 208 to cover the W layer 208. Figure 2B As shown, the memory cell array 130 in the memory device 200 is separated and isolated by the dielectric structure 206.

[0089] Figures 3A to 3M The following are examples of manufacturing processes for forming storage device 200 according to this disclosure. Reference Figure 3A and Figure 3B (For example, Figure 3B yes Figure 3AA plan view of the structure is provided, forming a transistor structure 202 comprising an array of vertical transistors 172. A stacked structure 302 is formed on the transistor structure 202. The stacked structure 302 can be formed by depositing alternating first layers 304 (304A, 304B, 304C) and first dielectric layers 306 (306A, 306B) across the memory array region 110 and contact region 112 on the transistor structure 202 using one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). The first dielectric layers 306 may comprise the same dielectric material, while the first layers 304 may comprise the same dielectric material or different dielectric materials. The dielectric material(s) of the first layers 304 may be different from the dielectric material of the first dielectric layers 306. For example, the first dielectric layers 306A and 306B may comprise silicon oxide. The first layer 304A may comprise silicon nitride (SiN) or silicon boron nitride (SiBN). The first layer 304B may include silicon carbide (SiCN). The first layer 304C may include SiN or SiCN.

[0090] Hard masks 308 and 310 may be formed on top of the stacked structure 302. Hard mask 308 may comprise polysilicon, while hard mask 310 may comprise silicon oxide. Hard mask 310 may be etched to form openings 312 in the memory array region 110. In some embodiments, the fabrication process for forming openings 312 includes wet etching and / or dry etching, such as deep ion reactive etching (DRIE).

[0091] refer to Figure 3C Hard mask 308 can be etched to form through in memory array region 110. Figure 3A The hard mask 310 has an opening 312 and an opening 314. In some embodiments, the manufacturing process for forming the opening 314 includes wet etching and / or dry etching, such as DRIE. The covering material of the hard mask 308 can then be removed. Figure 3A Hard mask 310.

[0092] refer to Figure 3D The stacked structure 302 can be etched to form a storage opening 316 that extends through the stacked structure 302 in the storage array region 110. In some embodiments, the fabrication process for forming the storage opening 316 includes wet etching and / or dry etching, such as DRIE. The covering material on the stacked structure 302 can then be removed. Figure 3C Hard mask 308.

[0093] refer to Figure 3E ,exist Figure 3DA first electrode structure 318 for a vertical capacitor 274 is formed in the storage opening 316. The first electrode structure 318 can be formed by depositing one or more conductive layers into the storage opening 316 using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof). For example, the first electrode structure 318 can be formed by filling the storage opening 316 with titanium nitride (TiN). The first electrode structure 318 can be coupled to a corresponding vertical transistor 172 in the transistor structure 202.

[0094] refer to Figure 3F and Figure 3G (For example, Figure 3G yes Figure 3F (Planar diagram of the structure), the mesh hard mask 320 can be deposited on Figure 3E On top of the stacked structure 302. A photoresist layer 321 can be deposited on top of the mesh hard mask 320. The photoresist layer 321 can be patterned to form openings 322 to expose the mesh hard mask 320 through the openings 322 in the memory array region 110. A portion of the photoresist layer 321 in the contact region 112 can also be removed to expose the mesh hard mask 320 in the contact region 112. A portion of the mesh hard mask 320 exposed by the photoresist layer 321 can be etched to expose the first layer 304C, such that the exposed portion of the first layer 304C can be etched away, as shown below. Figure 3H As shown.

[0095] refer to Figure 3H and Figure 3I (For example, Figure 3I yes Figure 3H (A plan view of the structure), the first layer of 304C can be etched to pass through Figure 3F The openings 322 in the mesh hard mask 320 form mesh openings 324 in the memory array region 110. A portion of the mesh hard mask 320 and a portion of the first layer 304C in the contact region 112 are completely removed. Then, wet etching and / or dry etching (such as DRIE) are used to remove ( Figure 3F (As shown) The entire first dielectric layer 306B between the first layer 304C and the first layer 304B.

[0096] refer to Figure 3J The first layer 304B can be etched to form a grid opening 326 in the memory array region 110 through openings 322 and grid openings 324 in the grid hard mask 320. A portion of the first layer 304B in the contact region 112 is completely removed. Then, wet etching and / or dry etching (such as DRIE) are used to remove ( Figure 3H (As shown) The entire first dielectric layer 306A between the first layer 304B and the first layer 304A.

[0097] refer to Figure 3K A second electrode structure corresponding to the vertical capacitor 274 can be formed in the memory array region 110 by depositing a high dielectric constant (high k) dielectric layer 328 to cover the first electrode structure 318 and depositing one or more conductive layers (e.g., depositing a TiN layer 329 and a GeSi layer 210 over the high k dielectric layer 328, and depositing a W layer 208 over the GeSi layer 210) on top of the high k dielectric layer 328. The high k dielectric layer 328, TiN layer 329, GeSi layer 210, and W layer 208 can also extend across the contact region 112 and the memory array region 110.

[0098] refer to Figure 3L This allows etching away a portion of the high-k dielectric layer 328, a portion of the TiN layer 329, a portion of the GeSi layer 210, and a portion of the W layer 208 in the contact region 112. (Reference) Figure 3M The dielectric structure 206 can be formed by filling the contact region 112 with a dielectric material (e.g., silicon oxide). Figure 3M As shown, the dielectric structure 206 can also cover the W layer 208 in the storage array region 110.

[0099] As mentioned above Figures 3H to 3J As shown, in order to form the dielectric structure 206, a portion of the stacked structure 302 in the contact region 112 needs to be completely removed. This removal of the stacked structure 302 in the contact region 112 and the refilling of the contact region 112 with dielectric material to form the dielectric structure 206 can result in high manufacturing costs. Additionally, the lateral width 330 ( ) used for removing the stacked structure 302 in the contact region 112... Figure 3J The value shown is relatively large, which may lead to wasted space between storage cell arrays.

[0100] Figure 4A A side view of a cross section of a storage device 400 according to some aspects of this disclosure is shown. Figure 4B A plan view of a cross section of a storage device 400 according to some aspects of this disclosure is shown. Figure 4A The cross section along Figure 4B Lines B2-B2 and CC, and Figure 4B The cross section along Figure 4A Line A2-A2. Describe together. Figure 4A and Figure 4B It should be understood that Figure 4A and Figure 4B This is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnections) in practice.

[0101] Storage device 400 can be a DRAM storage device comprising an array of DRAM cells. For example... Figure 4A As shown, the storage device 400 may include a first semiconductor structure 104, which includes a transistor structure 202 and a storage structure 204. In some embodiments, the transistor structure 202 includes an array of vertical transistors 172, and the storage structure 204 includes an array of vertical capacitors 274 in the storage array region 110. That is, a DRAM cell may include a vertical capacitor 274 and a vertical transistor 172 coupled to the vertical capacitor 274. In some embodiments, an array of source node contact (SNC) structures 480 is coupled between the array of vertical transistors 172 and the array of vertical capacitors 274. In some examples, the array of vertical transistors 172 and the array of vertical capacitors 274 may form a memory cell array 130 in the storage array region 110.

[0102] In some embodiments, the vertical transistor 172 (e.g., a MOSFET) can be configured to switch a corresponding DRAM cell. The vertical transistor 172 includes a semiconductor body 175 extending vertically (in the z-direction) (i.e., an active region where multiple channels can be formed) and a gate structure located at one or more lateral sides of the semiconductor body 175. In some embodiments, the semiconductor body 175 can include any suitable semiconductor material, such as monocrystalline silicon, polycrystalline silicon, or silicon-germanium. In some other embodiments, the leakage value of the semiconductor body 175 is below picoamperes. For example, the semiconductor body 175 can include a metal-oxide-semiconductor material, such as In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zny Sn z O、Yb x Ga y Zn z O、In x Ga y O, etc. In some embodiments, adjacent semiconductor bodies 175 can be laterally separated from each other by an isolation member 423 including a transducer oxide (TISO) and / or an air gap.

[0103] In some embodiments, the semiconductor body 175 extends in a vertical direction (z-direction) and includes source and drain electrodes respectively disposed at both ends (upper and lower ends) of the semiconductor body 175. The source and drain electrodes may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, the source electrodes are coupled to a vertical capacitor 274 via an SNC structure 480, and the drain electrodes are coupled to a bit line (not shown). In some embodiments, the sources of adjacent semiconductor bodies 175 may be laterally separated from each other by an insulating layer 439 comprising any suitable dielectric material (e.g., silicon oxide). In some embodiments, the drain electrodes of the semiconductor bodies 175 of a column of DRAM cells along the bit line direction (i.e., y-direction) may be laterally connected to each other to form a common drain electrode coupled to a common bit line (not shown) extending in the bit line direction (y-direction).

[0104] In some embodiments, the gate structure of the vertical transistor 172 includes a gate dielectric and a gate electrode 176. In some embodiments, the gate dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. In some embodiments, the gate electrode 176 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 176 includes multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure may be a “gate oxide / gate polysilicon” gate, wherein the gate dielectric includes silicon oxide and the gate electrode 176 includes doped polysilicon. In another example, the gate structure may be a high-k metal gate (HKMG), wherein the gate dielectric includes a high-k dielectric and the gate electrode 176 includes metal. In some embodiments, the gate structures of adjacent semiconductor bodies 175 may be laterally separated from each other by an insulating layer 439.

[0105] In some embodiments, the gate electrode 176 may be part of a word line or extend as a word line in the word line direction (x-direction). The word line may extend in the word line direction (x-direction) and be coupled to a row of DRAM cells. That is, the bit line and word line may extend in two perpendicular lateral directions, and the semiconductor body 175 of the vertical transistor 172 may extend in a vertical direction perpendicular to the two lateral directions in which the bit line and word line extend.

[0106] In some embodiments, the SNC structure 480 may include a conductive layer in contact with the corresponding vertical capacitor 274. In some embodiments, the conductive layer may include any suitable conductive material, such as polysilicon, Al, Cu, W, etc.

[0107] The vertical capacitor 274 may include a first electrode structure 403 and a second electrode structure 411 (in Figure 4C (as shown in the diagram) and a storage dielectric layer 405 formed between the first electrode structure 403 and the second electrode structure 411. Figure 4C The image shows an enlarged view of the vertical capacitor 274, where the dashed circle 493 indicates... Figure 5U The grid opening 538 is in Figure 4B The projection on the cross-section. Four vertical capacitors 274 are formed around the projection of the grid opening 538. Reference Figure 4A The first electrode structure 403 may have a cylindrical structure fixed within the first layers 304A, 304B, and 304C. The first electrode structure 403, the second electrode structure 411, and the storage dielectric layer 405 extend vertically (in the z-direction), and the storage dielectric layer 405 may be sandwiched between the first electrode structure 403 and the second electrode structure 411. In some embodiments, the second electrode structures 411 are interconnected and act as a common electrode, while the first electrode structure 403 is coupled to the source of a corresponding vertical transistor 172 in the same DRAM cell via an SNC structure 480.

[0108] In some embodiments, the first electrode structure 403 and / or the second electrode structure 411 may include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the first electrode structure 403 and / or the second electrode structure 411 may include a single-layer structure or a multilayer structure, wherein one layer of the multilayer structure includes one of TiN, TaN, carbon, polysilicon, metal, metal compound, or silicide. For example, the first electrode structure 403 may include a TiN layer or another suitable conductive layer. Alternatively, the first electrode structure 403 may include a polysilicon layer and a TiN layer. The second electrode structure 411 may include a first conductive layer 407 (e.g., a TiN layer) and a second conductive layer 409 (e.g., a GeSi layer). A third conductive layer 419 (e.g., a W layer) may be deposited on the second conductive layer 409. In some embodiments, the storage dielectric layer 405 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof.

[0109] like Figures 4A to 4B As shown, the storage device 400 may further include a stacked structure 302 in the contact region 112 and an isolation structure 404 located between the storage array region 110 and the contact region 112. The isolation structure 404 isolates the array of vertical capacitors 274 in the storage array region 110 from the stacked structure 302 in the contact region 112. The isolation structure 404 may include a dielectric material, including but not limited to silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon boron nitride (SiBN), or any combination thereof. The dielectric material of the isolation structure 404 may be different from the dielectric material of the first dielectric layer 306. Figure 4B As shown, the isolation structure 404 can surround the memory cell array 130.

[0110] The stacked structure 302 may include alternating first layers 304 (e.g., 304A, 304B, 304C) and first dielectric layers 306 (e.g., 306A, 306B) in the contact region 112. In some embodiments, the first dielectric layer 306 may include a first dielectric material, and the first layer 304 may include a second dielectric layer comprising a second dielectric material. That is, the first layer 304 is formed of the same second dielectric material. The first dielectric material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The second dielectric material may include, but is not limited to, silicon nitride, silicon carbon nitride (SiCN), or silicon boron nitride (SiBN), or any combination thereof. The first dielectric material may differ from the second dielectric material. For example, the first dielectric material may include silicon oxide. The second dielectric material may include silicon nitride, SiCN, or SiBN.

[0111] In some embodiments, the first dielectric layer 306 may include a first dielectric material. The first layer 304 may include at least (1) a second dielectric layer including a second dielectric material and (2) a third dielectric layer including a third dielectric material. The third dielectric material may include, but is not limited to, silicon nitride, silicon oxynitride, SiCN, SiBN, or any combination thereof. The third dielectric material is different from the first dielectric material and the second dielectric material. That is, different first layers 304 may be formed of different dielectric materials. For example, the first dielectric material may include silicon oxide. The second dielectric material may include one of silicon nitride, SiCN, or SiBN, while the third dielectric material may include another of silicon nitride, SiCN, or SiBN.

[0112] In one example, the first dielectric layers 306A and 306B may comprise silicon oxide. The first layer 304A may comprise silicon nitride or SiBN. The first layer 304B may comprise SiCN. The first layer 304C may comprise silicon nitride or SiCN.

[0113] like Figures 4A to 4BAs shown, the first semiconductor structure 104 may further include a first contact structure 402 extending through the stacked structure 302 in the contact region 112 in a vertical direction (e.g., the z-direction). The end surface of the first contact structure 402 on the first layer 304 (e.g., first layer 304C) is flush with the end surface of the isolation structure 404 on the first layer 304 (e.g., first layer 304C). For example, the top surface of the first contact structure 402 on the first layer 304C is flush with the top surface of the isolation structure 404. In some embodiments, an opening is provided in the first layer 304A (e.g., a SiBN layer) such that the first contact structure 402 can extend not only through the stacked structure 302 but also through the transistor structure 202 to connect to the peripheral circuitry 132, such as... Figure 4D As shown. In some other embodiments, no opening is provided in the first layer 304A, such that the first contact structure 402 extends only into or through the stacked structure 302 (e.g., the first contact structure 402 does not extend into the transistor structure 202).

[0114] In some embodiments, the first contact structure 402 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the first contact structure 402 may include a single-layer structure or a multilayer structure, wherein one layer of the multilayer structure includes one of TiN, TaN, carbon, polysilicon, a metal, a metal compound, or a silicide. For example, the first contact structure 402 may include a TiN layer or another suitable metal layer. Alternatively, the first contact structure 402 may include a polysilicon layer and a TiN layer.

[0115] refer to Figure 4B The first semiconductor structure 104 may also include a stacked structure 302 extending vertically through the contact region 112 and coupled to a word line (e.g., Figure 1B The second contact structure 410 of the word line 166). The first semiconductor structure 104 may also include a stacked structure 302 extending vertically through the contact region 112 and coupled to the bit line (e.g., the word line 166). Figure 1B The third contact structure 408 of the bit line 168. It is contemplated that the first semiconductor structure 104 may also include a dummy contact structure or other contact structures in the contact region 112, which is not limited herein.

[0116] The end surface of the second contact structure 410 on the first (e.g., first layer 304C) of the first layer 304 is flush with the end surface of the third contact structure 408 on the first (e.g., first layer 304C) of the first layer 304. For example, the top surface of the second contact structure 410 on the first layer 304C is flush with the top surface of the third contact structure 408 on the same first layer 304C. In some embodiments, the size of the end surface of the second contact structure 410 may be equal to the size of the end surface of the third contact structure 408. The size of the end surface of the second contact structure 410 or the third contact structure 408 may be, for example, the diameter or area of ​​the end surface of the second contact structure 410 or the third contact structure 408. For example, as follows... Figure 5R As shown, the end surface of the second contact structure 410 can have a circular shape, and the end surface of the third contact structure 408 can have the same circular shape. The diameter 599 of the end surface of the second contact structure 410 can be equal to the diameter 597 of the end surface of the third contact structure 408.

[0117] In some embodiments, on the first layer 304C, the dimension of the end surface of the first contact structure 402 is larger than the dimension of the end surface of the second contact structure 410 and the dimension of the end surface of the third contact structure 408. The dimension of the end surface of the first contact structure 402 can be, for example, the diameter or area of ​​the end surface of the first contact structure 402. For example, as follows... Figure 5R As shown, on the same first layer 304C, the diameter 598 of the circular end surface of the first contact structure 402 is greater than the diameter 599 of the circular end surface of the second contact structure 410 and the diameter 597 of the circular end surface of the third contact structure 408.

[0118] Similarly, on the first layer 304C, the dimension of the end surface of the isolation structure 404 is larger than the dimension of the end surface of the second contact structure 410 and the dimension of the end surface of the third contact structure 408. For example, the dimension of the end surface of the isolation structure 404 can be as follows: Figure 4B or Figure 5R The isolation structure 404 shown has a width of 413. The width 413 of the isolation structure 404 can be greater than the diameter 599 of the circular end surface of the second contact structure 410 and the diameter 597 of the circular end surface of the third contact structure 408.

[0119] In some embodiments, on the first layer 304C, the dimension of the end surface of the first contact structure 402 is equal to the dimension of the end surface of the isolation structure 404. Alternatively, the dimension of the end surface of the first contact structure 402 is different from the dimension of the end surface of the isolation structure 404. For example, as Figure 5RAs shown, the diameter 598 of the circular end surface of the first contact structure 402 may be equal to or different from the width 413 of the isolation structure 404.

[0120] As referenced above Figures 4A to 4C As described, the vertical capacitor 274 may include (1) a first electrode structure 403 coupled to a corresponding vertical transistor 172 and (2) a second electrode structure 411 isolated from the first electrode structure 403. On the same first layer 304C, the end surface of the first electrode structure 403 is flush with at least one of the end surfaces of the first contact structure 402, the isolation structure 404, the second contact structure 410, or the third contact structure 408. In some embodiments, the size of the end surface of the first electrode structure 403 is equal to the size of the end surface of the second contact structure 410 and the end surface of the third contact structure 408. The size of the end surface of the first electrode structure 403 may be, for example, the diameter or area of ​​the end surface of the first electrode structure 403. For example, refer to... Figure 5R On the same first layer 304C, the diameter 596 of the circular end surface of the first electrode structure 403 is equal to the diameter 599 of the circular end surface of the second contact structure 410 and the diameter 597 of the circular end surface of the third contact structure 408.

[0121] refer to Figure 4A The first semiconductor structure 104 may further include a dielectric layer 406 covering at least one of the memory cell array 130 in the memory array region 110, the isolation structure 404, or the stacked structure 302 in the contact region 112. The dielectric layer 406 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0122] In some embodiments, the storage device 400 may further include Figures 4A to 4CAny other suitable components not shown. For example, in some embodiments, the memory device 400 may also include one or more interconnect layers, which include interconnect structures for electrically connecting word lines, bit lines, first electrode structures and second electrode structures of capacitors, etc., to transmit electrical signals. In some embodiments, one or more interconnect layers may include lateral interconnects and vertical interconnect access (VIA) contacts. In some embodiments, one or more interconnect layers may also include local interconnects, such as bit line contacts, word line contacts and capacitor contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as mid-stage process (MEOL) interconnects and back-end process (BEOL) interconnects. One or more interconnect layers may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers") in which interconnects and via contacts may be formed. That is, one or more interconnect layers may include interconnects and via contacts in a plurality of ILD layers. Interconnects in one or more interconnect layers may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides or any combination thereof. The ILD layer can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0123] Figure 4D Another side view of a cross section of a storage device 400 according to some aspects of this disclosure is shown. Figure 4D The cross section can be along Figure 4B The lines CC and DD are shown in Figure 4. It should be understood that Figure 4 is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnections) in practice. As per the above regarding... Figures 1A to 1B The described example of a 3D storage device 100 is that the storage device 400 may be a bonded chip including a first semiconductor structure 104 and a second semiconductor structure 102, wherein the first semiconductor structure 104 is stacked on top of the second semiconductor structure 102. According to some embodiments, the first semiconductor structure 104 and the second semiconductor structure 102 are bonded at a bonding interface 106 therebetween. Figure 4D As shown, the second semiconductor structure 102 may include a substrate 470, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0124] The second semiconductor structure 102 may include peripheral circuitry 132 on substrate 470. In some embodiments, peripheral circuitry 132 includes a plurality of transistors 474 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 474) may also be formed on or in substrate 470.

[0125] In some embodiments, the second semiconductor structure 102 further includes an interconnect layer 476 above the peripheral circuit 132 for transmitting electrical signals to and from the peripheral circuit 132. The interconnect layer 476 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. The interconnect layer 476 may also include one or more ILD layers, in which interconnects, via contacts, and bonding contacts may be formed. That is, the interconnect layer 476 may include interconnects, via contacts, and bonding contacts in multiple ILD layers. In some embodiments, the peripheral circuit 132 is coupled to each other through interconnects in the interconnect layer 476. The interconnects in the interconnect layer 476 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed with dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0126] The first semiconductor structure 104 can be bonded face-to-face to the top of the second semiconductor structure 102 at the bonding interface 106. In some embodiments, the bonding interface 106 is the result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding.

[0127] In some embodiments, the first semiconductor structure 104 further includes an interconnect layer 481 for transmitting electrical signals. The interconnect layer 481 includes bit lines 482, interconnect lines, via contacts, and bonding contacts. The interconnect layer 481 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 481 also include local interconnects, such as bit lines 482 (e.g., Figure 1BExamples of bit lines 168 in interconnect 481 and word line contacts (not shown). Interconnect layer 481 may also include one or more ILD layers in which interconnects and via contacts may be formed. Interconnects in interconnect layer 481 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, peripheral circuitry 132 includes word line drivers / row decoders coupled to word line contacts in interconnect layer 481 via interconnects, via contacts, and bonding contacts in interconnect layers 476 and 481. In some embodiments, peripheral circuitry 132 includes bit line drivers / column decoders coupled to bit lines 482 and bit line contacts (if any) in interconnect layer 481 via interconnects, via contacts, and bonding contacts in interconnect layers 476 and 481.

[0128] In some embodiments, the first semiconductor structure 104 includes a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells above interconnect layer 481. An array of DRAM cells is provided in memory array region 110. A first contact structure 402, a second contact structure 410, and a third contact structure 408 are provided in contact region 112. Figure 4D (Not shown in the image) Fourth contact structure 485. The fourth contact structure 485 can be coupled to the second electrode structure 411 (e.g., common electrode) of the vertical capacitor 274 via the third conductive layer 419. The isolation structure 404 is located between the storage array region 110 and the contact region 112.

[0129] A DRAM cell may include a vertical transistor 172 and a vertical capacitor 274 coupled to the vertical transistor 172. In some embodiments, one of the source and drain terminals of the vertical transistor 172 (e.g., in...) Figure 4D At the upper end of the vertical transistor 172, the other of the source and drain terminals (e.g., at the upper end of the vertical transistor 172) is coupled to the vertical capacitor 274, and ... Figure 4D (At the lower end of the DRAM cell) is coupled to bit line 482. A DRAM cell can be a 1T1C cell including a transistor and a capacitor. It should be understood that a DRAM cell can have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc.

[0130] Figures 5A to 5Z and Figures 6A to 6B The manufacturing process for forming the storage device 400 according to some aspects of this disclosure is shown. (Reference) Figure 5A and Figure 5B (For example, Figure 5B yes Figure 5AA plan view of the structure is provided, forming a transistor structure 202 comprising an array of vertical transistors 172. In some embodiments, forming the transistor structure 202 may include forming a plurality of semiconductor bodies 175 extending vertically on a semiconductor layer. In some embodiments, the plurality of semiconductor bodies 175 may be formed by patterning a semiconductor substrate using any suitable patterning process (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.) to form trenches extending laterally along the x and y directions, with the remaining vertical portions of the semiconductor substrate between the trenches forming the semiconductor bodies 175, and the remaining lateral portions of the semiconductor substrate below the trenches forming the semiconductor layer. In some embodiments, a TISO structure 503 may be formed in the trenches to laterally separate adjacent semiconductor bodies 175.

[0131] The semiconductor body 175 can be used to form the channel of the vertical transistor 172. In some embodiments, the semiconductor body 175 can be formed using any suitable semiconductor material, such as monocrystalline silicon, polycrystalline silicon, or silicon-germanium. In other embodiments, the semiconductor body 175 can be formed using any suitable metal-oxide-semiconductor material, such as In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O etc.

[0132] In some embodiments, a gate structure for the vertical transistor 172 may be formed. For example, forming the gate structure includes forming a gate dielectric layer and forming a gate electrode 176. In some embodiments, the gate dielectric layer and the gate electrode 176 may be formed by any suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). In some embodiments, forming the gate dielectric layer may include depositing any suitable dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, forming the gate electrode 176 includes depositing one or more layers of conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

[0133] In some embodiments, forming the transistor structure 202 further includes forming an insulating layer 439 to fill trenches between adjacent gate structures and / or adjacent semiconductor bodies 175. In some embodiments, forming the transistor structure 202 further includes forming SNC structures 480 on top of the semiconductor bodies 175 respectively.

[0134] Next, a stacked structure 302 is formed on the transistor structure 202. The stacked structure 302 can be formed by depositing alternating first layers 304 (304A, 304B, 304C) and first dielectric layers 306 (306A, 306B) across the memory array region 110 and contact region 112 on the transistor structure 202 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). The first dielectric layers 306 may include the same dielectric material, while the first layers 304 may include the same dielectric material or different dielectric materials. The dielectric material(s) of the first layers 304 may be different from the dielectric material of the first dielectric layers 306. For example, the first dielectric layers 306A and 306B may include silicon oxide. The first layer 304A may include silicon nitride (SiN) or SiBN. The first layer 304B may include SiCN. The first layer 304C may include SiN or SiCN.

[0135] Hard masks 308 and 310 can be formed on top of the stacked structure 302. For example, hard mask 308 may comprise polysilicon, while hard mask 310 may comprise silicon oxide. Hard masks 308 and 310 can be formed using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Hard mask 310 can be etched to form opening 502 in the memory array region 110 and openings 504 and 506 in the contact region 112 (in... Figure 5B(as shown in the figure). In some embodiments, the manufacturing processes used to form openings 502, 504, 506 include wet etching and / or dry etching, such as DRIE.

[0136] refer to Figure 5C and Figure 5D (For example, Figure 5D yes Figure 5C (A plan view of the structure), a photoresist layer 507 can be formed on top of the hard mask 310. The photoresist layer 507 can be patterned to form the first trench opening 508 and opening 510.

[0137] refer to Figure 5E and Figure 5F (For example, Figure 5F yes Figure 5E (A plan view of the structure), it can be seen through the first trench opening 508 and the opening 510 of the photoresist layer 507 (in Figure 5C (As shown in the diagram) Etching of a hard mask 310 to form second trench openings 512 and 514, respectively, within the hard mask 310. In some embodiments, the fabrication process for forming the second trench openings 512 and 514 includes wet etching and / or dry etching, such as DRIE. Figure 5C The photoresist layer 507 shown is used to expose openings 502, 504 and 506.

[0138] refer to Figure 5G It can be seen through the opening 502, the second groove opening 512, and the opening 514 of the hard mask 310 (in Figures 5E to 5F (As shown in the diagram) Etching the hard mask 308 to form openings 516, the third trench opening 518, and opening 520 in the hard mask 308, respectively. Simultaneously, openings 504 and 506 of the hard mask 310 (as shown in the diagram) can also be used to form openings 516, the third trench opening 518, and opening 520. Figures 5E to 5F (As shown) Etching the hard mask 308 to form a first corresponding opening and a second corresponding opening, respectively, in the hard mask 308. In some embodiments, the manufacturing process for forming the openings in the hard mask 308 includes wet etching and / or dry etching, such as DRIE. After the openings are formed in the hard mask 308, the hard mask 310 can be removed.

[0139] refer to Figure 5H and Figure 5I (For example, Figure 5I yes Figure 5H (A plan view of the structure), it can be seen through the opening 516 of the hard mask 308, the third groove opening 518, and the opening 520 (in the plan view of the structure). Figure 5G(As shown in the diagram) The stacked structure 302 is etched to form a storage opening 522, an isolation opening 524, and a first contact opening 526, respectively, within the stacked structure 302. The transistor structure 202 can also be etched so that the first contact opening 526 can also extend through the transistor structure 202. Simultaneously, it is also possible to... Figure 5G The first and second corresponding openings in the hard mask 308 are etched into the stacked structure 302 to form a second contact opening 528 and a third contact opening 530, respectively, in the stacked structure 302. In some embodiments, the manufacturing process for forming the openings in the stacked structure 302 includes wet etching and / or dry etching, such as DRIE. After the openings are formed in the stacked structure 302, the hard mask 308 can be removed.

[0140] The first contact opening 526, the second contact opening 528, and the third contact opening 530 may be located in the contact region 112. The storage opening 522 may be located in the storage array region 110. The isolation opening 524 may be located between the storage array region 110 and the contact region 112, and may surround the storage array region 110. In some embodiments, the isolation opening 524 may have a trench shape.

[0141] refer to Figure 5J A sacrificial layer 533 can be deposited on the stacked structure 302 (e.g., on top of the first layer 304C). The openings 522, 524, 526, 528, and 530 in the stacked structure 302 can be filled with the sacrificial layer 533. For example, a sacrificial layer 523 (such as a polysilicon layer or a carbon layer), different from the first layer 304 and the first dielectric layer 306, can be deposited into the openings 522, 524, 526, 528, and 530 and on top of the first layer 304C using one or more thin-film deposition processes (such as CVD, PVD, ALD, or any combination thereof).

[0142] refer to Figure 5K and Figure 5L (For example, Figure 5L yes Figure 5K (A plan view of the structure) can be used to pattern the sacrificial layer 523 using photolithography and wet etching and / or dry etching to remove a portion of the sacrificial layer 523 in the isolation opening 524 to expose the isolation opening 524. At the same time, another portion of the sacrificial layer 523 in the contact region 112 can also be removed.

[0143] refer to Figure 5M and Figure 5N (For example, Figure 5N yes Figure 5MThe isolation structure 404 can be formed in the isolation opening 524 by depositing a dielectric material into the isolation opening 524 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). The dielectric material of the isolation structure 404 may include silicon nitride, silicon oxynitride, SiCN, or SiBN, or any combination thereof.

[0144] refer to Figure 5O and Figure 5P (For example, Figure 5P yes Figure 5O (A plan view of the structure) can be completely removed using wet etching and / or dry etching. Figure 5M The sacrificial layer 523 shown exposes the storage opening 522, the first contact opening 526, the second contact opening 528, and the third contact opening 530.

[0145] refer to Figure 5Q and Figure 5R (For example, Figure 5R yes Figure 5Q (Plan view of the structure), the first electrode structure 403 of the vertical capacitor 274 can be formed in the storage opening 522 (in Figure 5O As shown in the diagram, the first contact structure 402 can be formed in the first contact opening 526. Figure 5O As shown in the diagram, a second contact structure 410 can be formed in the second contact opening 528. Figure 5O (as shown in the diagram), and a third contact structure 408 can be formed in the third contact opening 530 (in Figure 5O (As shown in the figure). For example, the first electrode structure 403, the first contact structure 402, the second contact structure 410, and the third contact structure 408 can be formed by depositing one or more conductive layers into the storage opening 522, the first contact opening 526, the second contact opening 528, and the third contact opening 530, respectively, using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof). In one example, the one or more conductive layers may include a TiN layer.

[0146] It is contemplated that by performing operations similar to those described above for forming the first contact structure 402 or for forming the second contact structure 410 and the third contact structure 408, one or more other contact structures or dummy contact structures extending through the stacked structure 302 in the z-direction can also be formed in the contact region 112.

[0147] refer to Figure 5S and 5T (For example, Figure 5T yes Figure 5S (Planar diagram of the structure), the mesh hard mask 532 can be deposited on Figure 5QOn top of the stacked structure 302. A photoresist layer 534 may be deposited on top of the mesh hard mask 532. The photoresist layer 534 may be patterned to form openings 536 to expose the mesh hard mask 532 through the openings 536 in the storage array region 110.

[0148] refer to Figure 5U and Figure 5V (For example, Figure 5V yes Figure 5U (A plan view of the structure), portions of the mesh hard mask 532 exposed by the photoresist layer 534 can be etched to expose the first layer 304C. The exposed portions of the first layer 304C can be etched away using wet etching and / or dry etching (such as DRIE) to form the first mesh opening 538 in the memory array region 110.

[0149] refer to Figure 5W A first portion of the first dielectric layer 306B in the storage array region 110 can be removed through the first grid opening 538 using wet etching and / or dry etching (such as DRIE) to form the first groove 540. The remaining portion of the first dielectric layer 306B in the contact region 112 is isolated by the isolation structure 404 and remains intact.

[0150] refer to Figure 5X Using the mesh hard mask 532, wet etching and / or dry etching (such as DRIE) can also be used to etch away portions of the first layer 304B to form a second mesh opening 542 in the storage array region 110.

[0151] refer to Figure 5Y A first portion of the first dielectric layer 306A in the memory array region 110 can be removed through the second grid opening 542 using wet etching and / or dry etching (such as DRIE) to form the second groove 544. The remaining portion of the first dielectric layer 306A in the contact region 112 is isolated by the isolation structure 404 and remains intact. Thus, a memory groove is formed in the memory array region 110, comprising a first grid opening 538, a first groove 540, a second grid opening 542, and a second groove 544.

[0152] refer to Figure 5ZA second electrode structure 411, isolated from the first electrode structure 403, is formed in the storage trench by: forming a storage dielectric layer 405 covering the first electrode structure 403 in the storage trench; and depositing a first conductive layer 407 (e.g., a TiN layer) and a second conductive layer 409 (e.g., a GeSi layer) over the storage dielectric layer 405. For example, the second electrode structure 411 can be formed by depositing a high-k dielectric layer to cover the first electrode structure 403 using one or more thin-film deposition processes (such as CVD, PVD, ALD, or any combination thereof) and depositing a TiN layer and a GeSi layer over the high-k dielectric layer. The storage dielectric layer 405, the first conductive layer 407, and the second conductive layer 409 can extend across the storage array region 110 and the contact region 112. A third conductive layer 419 (e.g., a W layer) can also be formed over the second conductive layer 409. This third conductive layer 419 can also extend across the storage array region 110 and the contact region 112.

[0153] refer to Figure 6A Dry etching and / or wet etching can be used to etch away a portion of the storage dielectric layer 405, a portion of the first conductive layer 407, a portion of the second conductive layer 409, and a portion of the third conductive layer 419, which are located in the contact region 112 and above the isolation structure 404.

[0154] refer to Figure 6B The dielectric layer 406 can be formed by depositing a dielectric material (e.g., silicon oxide) across the contact region 112 and the memory array region 110 (e.g., over the stacked structure 302, the isolation structure 404 in the contact region 112, and the third conductive layer 419 in the memory array region 110) using one or more thin-film deposition processes (such as CVD, PVD, ALD, or any combination thereof). Chemical mechanical planarization (CMP) can be performed on the dielectric layer 406.

[0155] Figure 7A A flowchart of a method 700 for forming a 3D storage device according to some aspects of this disclosure is shown. The 3D storage device can be any storage device disclosed herein, such as storage device 100, 160, or 400. It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with… Figure 7A The different orders shown are executed sequentially.

[0156] like Figure 7AAs shown, method 700 can begin at operation 702, where a first semiconductor structure can be formed. For example, the first semiconductor structure 104 can be formed by performing the above-referenced... Figures 5A to 5Z and Figures 6A to 6B The operations described are similar to those used to form the operation.

[0157] like Figure 7A As shown, method 700 can proceed to operation 704, where a second semiconductor structure can be formed. In some embodiments, a second semiconductor structure can be formed. Figure 1A or Figure 4D The second semiconductor structure 102. For example, refer to... Figure 4D Peripheral circuitry 132 can be formed on substrate 470. Interconnect layer 476 can be formed above peripheral circuitry 132 to transmit electrical signals to and from peripheral circuitry 132.

[0158] like Figure 7A As shown, method 700 can proceed to operation 706, where the second semiconductor structure can be bonded to the first semiconductor structure. For example, as Figure 4D As shown, hybrid bonding can be used to bond the first semiconductor structure 104 and the second semiconductor structure 102.

[0159] Figure 7B A flowchart of a method 750 for forming a first semiconductor structure (e.g., first semiconductor structure 104) according to some aspects of this disclosure is shown. It should be understood that the operations shown in method 750 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 7B The different execution orders shown.

[0160] like Figure 7B As shown, method 750 can begin at operation 752, where an array of memory cells can be formed in the memory array region of the first semiconductor structure. For example, an array of transistors can be formed in the memory array region. An array of storage components can be formed in the memory array region, with the storage components connected to corresponding transistors.

[0161] like Figure 7B As shown, method 750 can proceed to operation 754, where an isolation structure can be formed between contact regions of the first semiconductor structure in the memory array region to isolate the memory array region from the contact regions. For example, the isolation structure isolates the array of storage components in the memory array region from the contact regions.

[0162] In some embodiments, forming the first semiconductor structure in method 750 further includes forming a stacked structure comprising alternating first layers and first dielectric layers across a memory array region and a contact region. For example, a stacked structure 302 comprising alternating first layers 304 and first dielectric layers 306 can be formed by performing the same steps as described above. Figure 5A The operations described are similar to those used to form the operation.

[0163] In some embodiments, forming the first semiconductor structure in method 750 further includes: forming a first contact opening, a second contact opening, and a third contact opening extending through the stacked structure in a first direction in the contact region; forming a storage opening extending through the stacked structure in a first direction in the storage array region; and forming an isolation opening extending through the stacked structure in a first direction between the storage array region and the contact region. For example, this can be achieved by performing the above-referenced... Figures 5A to 5I The operations described are similar to those used to form the first contact opening 526, the second contact opening 528, the third contact opening 530, the storage opening 522, and the isolation opening 524.

[0164] In some implementations, forming the isolation structure in operation 754 includes forming the isolation structure in the isolation opening. For example, this can be achieved by performing the steps described above. Figures 5J to 5N The operation described is similar to the operation used to form an isolation structure 404 in the isolation opening 524.

[0165] In some embodiments, forming the first semiconductor structure in method 750 further includes: forming a first contact structure in a first contact opening; forming a second contact structure in a second contact opening to couple to a word line; and forming a third contact structure in a third contact opening to couple to a word line. The end surface of the first contact structure on the first party in the first layer is flush with the end surface of the isolation structure on the first party in the first layer. The end surface of the second contact structure on the first party in the first layer is flush with the end surface of the third contact structure on the first party in the first layer. For example, this can be achieved by performing the above-referenced... Figures 5O to 5R The operations described are similar to those used to form the first contact structure 402, the second contact structure 410, and the third contact structure 408. The end surface of the first contact structure 402 located on the first layer 304C is flush with the end surface of the isolation structure 404 located on the first layer 304C. The end surface of the second contact structure 410 located on the first layer 304C is flush with the end surface of the third contact structure 408 located on the first layer 304C.

[0166] In some embodiments, the storage components include vertical capacitors, and forming an array of storage components in operation 752 includes forming first electrode structures in storage openings. The first electrode structures are respectively coupled to transistors. Forming the array of storage components in operation 752 further includes forming second electrode structures isolated from the first electrode structures. The vertical capacitor includes a corresponding first electrode structure and a corresponding second electrode structure. For example, this can be achieved by performing the same steps as described above. Figures 5O to 5R The operations described are similar to those described above, used to form the first electrode structure 403 in the storage opening 522. This can be achieved by performing operations similar to those described above. Figures 5S to 5Z and Figure 6A The operation described is similar to the operation used to form the second electrode structure 411.

[0167] In some embodiments, forming a second electrode structure isolated from the first electrode structure includes: forming a storage recess in the storage array region; and forming a second electrode structure isolated from the first electrode structure in the storage recess.

[0168] In some embodiments, forming a storage recess in the storage array region includes: forming a first mesh opening extending through a first layer in the storage array region; removing a first portion of the first element in the first dielectric layer in the storage array region through the first mesh opening, wherein the remaining portion of the first element in the first dielectric layer in the contact region is isolated by an isolation structure and remains intact; forming a second mesh opening extending through a second element in the first layer in the storage array region; and removing a portion of the second element in the first dielectric layer in the storage array region through the second mesh opening, wherein the remaining portion of the second element in the first dielectric layer in the contact region is isolated by an isolation structure and remains intact.

[0169] For example, it can be done by executing the above reference. Figures 5S to 5V The described operation is similar to the operation used to form a first grid opening 538 extending through the first layer 304C in the storage array region 110. This can be achieved by performing the operation described in the reference above. Figure 5W The described operation is similar to removing a first portion of the first dielectric layer 306B in the storage array region 110 through the first grid opening 538. The remaining portion of the first dielectric layer 306B in the contact region 112 is isolated by the isolation structure 404 and remains intact, as... Figure 5W As shown. By executing the above reference. Figure 5X The described operation is similar to the operation used to form a second grid opening 542 extending through the first layer 304B in the storage array region 110. This is achieved by performing the operation described above. Figure 5YThe described operation is similar to removing a portion of the first dielectric layer 306A in the storage array region 110 through the second mesh opening 542. The remaining portion of the first dielectric layer 306A in the contact region 112 is isolated by the isolation structure 404 and remains intact, as... Figure 5Y As shown.

[0170] In some embodiments, forming a second electrode structure isolated from the first electrode structure includes: forming a storage dielectric layer to cover the first electrode structure in the storage trench; and forming the second electrode structure in the storage trench by depositing a conductive layer over the storage dielectric layer. For example, this can be achieved by performing the same steps as described above. Figure 5Z and Figure 6A The operations described are similar to those described above for forming the storage dielectric layer 405. This can be achieved by performing operations similar to those referenced above. Figure 5Z and Figure 6A The operations described are similar to those used to form the conductive layers 407 and 409 of the second electrode structure 411. A conductive layer 419 may also be formed to cover the conductive layer 409, as shown below. Figure 5Z and Figure 6A As shown.

[0171] Figure 8 A block diagram of an exemplary system 800 with a 3D storage device according to some aspects of this disclosure is shown. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, system 800 may include a host 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. The host 808 may be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host 808 may be configured to send data to or receive data from the 3D memory device 804.

[0172] 3D storage device 804 can be any 3D storage device disclosed herein, such as Figure 1A 3D storage device 100 Figure 1B storage device 160 or Figures 4A to 4D Storage device 400. In some embodiments, 3D storage device 804 includes NAND flash memory or DRAM storage device.

[0173] According to some embodiments, a memory controller 806 (also referred to as controller circuitry) is coupled to the 3D storage device 804 and the host 808 and is configured to control the 3D storage device 804. For example, the memory controller 806 may be configured to operate a multi-channel structure via word lines. The memory controller 806 may manage data stored in the 3D storage device 804 and communicate with the host 808. In some embodiments, the memory controller 806 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 806 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMC) used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.), and in enterprise storage arrays. The memory controller 806 may be configured to control the operation of the 3D storage device 804, such as read, erase, and program operations. The memory controller 806 can also be configured to manage various functions relating to data stored or to be stored in the 3D storage device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is also configured to handle error correction codes (ECC) relating to data read from or written to the 3D storage device 804. Any other suitable functions may also be performed by the memory controller 806, such as formatting the 3D storage device 804. The memory controller 806 may communicate with external devices (e.g., host 808) according to specific communication protocols. For example, the memory controller 806 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0174] The memory controller 806 and one or more 3D storage devices 804 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 802 can be implemented and packaged into different types of end electronic products. Figure 9AIn one example shown, the memory controller 806 and a single 3D storage device 804 can be integrated into a memory card 902. The memory card 902 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 902 can also include a connection between the memory card 902 and a host computer (e.g., Figure 8 The host (808) is electrically coupled to the memory card connector 904. Figure 9B In another example shown, the memory controller 806 and multiple 3D storage devices 804 can be integrated into the SSD 906. The SSD 906 may also include components for connecting the SSD 906 to a host computer (e.g., Figure 8 The host 808 is electrically coupled to the SSD connector 908. In some embodiments, the storage capacity and / or operating speed of the SSD 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0175] The foregoing description of a particular implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance provided herein, such modifications and alterations are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments.

[0176] The breadth and scope of this disclosure should not be limited by any of the implementations in the above exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: A first semiconductor structure, the first semiconductor structure comprising: The memory cell array in the memory array region of the first semiconductor structure includes: An array of transistors; and An array of storage components, wherein the storage components are connected to corresponding transistors; and An isolation structure located between the memory array region and the contact region of the first semiconductor structure, wherein the isolation structure isolates the array of storage components in the memory array region from the contact region.

2. The storage device according to claim 1, wherein, The first semiconductor structure further includes: A stacked structure comprising alternating first layers and first dielectric layers in the contact region.

3. The storage device according to claim 2, wherein, The first dielectric layer includes a first dielectric material, and the first layer includes a second dielectric layer, the second dielectric layer including a second dielectric material.

4. The storage device according to claim 2, wherein: The first dielectric layer comprises a first dielectric material; and The first layer includes at least a second dielectric layer and a third dielectric layer, wherein the second dielectric layer includes a second dielectric material and the third dielectric layer includes a third dielectric material.

5. The storage device according to claim 2, wherein, The first semiconductor structure further includes: A first contact structure extending through the stacked structure in a first direction, wherein the end surface of the first contact structure on the first one in the first layer is flush with the end surface of the isolation structure on the first one in the first layer.

6. The storage device according to claim 5, wherein, The first semiconductor structure further includes: A second contact structure, the second contact structure extending through the stacked structure in the first direction and coupled to a word line; and A third contact structure extends through the stacked structure in the first direction and couples to a positioning line. Wherein, the end surface of the second contact structure located on the first one in the first layer is flush with the end surface of the third contact structure located on the first one in the first layer.

7. The storage device according to claim 6, wherein, The size of the end surface of the second contact structure is equal to the size of the end surface of the third contact structure.

8. The storage device according to claim 6, wherein: The dimension of the end surface of the first contact structure is larger than the dimension of the end surface of the second contact structure and the dimension of the end surface of the third contact structure; or The size of the end surface of the isolation structure is greater than the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

9. The storage device according to claim 5, wherein, The size of the end surface of the first contact structure is equal to the size of the end surface of the isolation structure.

10. The storage device according to claim 5, wherein, The dimensions of the end surface of the first contact structure are different from the dimensions of the end surface of the isolation structure.

11. The storage device according to claim 5, wherein, The isolation structure includes a dielectric material, and the first contact structure includes a conductive material.

12. The storage device according to claim 1, further comprising: A second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the memory cell array.

13. The storage device according to claim 6, wherein, The transistor includes a vertical transistor, and the storage component includes a vertical capacitor.

14. The storage device according to claim 13, wherein, The vertical capacitor includes: The first electrode structure coupled to the corresponding vertical transistor; and A second electrode structure isolated from the first electrode structure. Wherein, the end surface of the first electrode structure located on the first part of the first layer is flush with the end surfaces of the second contact structure and the third contact structure.

15. The storage device according to claim 14, wherein, The size of the end surface of the first electrode structure is equal to the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

16. A storage device, comprising: A first semiconductor structure, the first semiconductor structure comprising: The memory cell array in the memory array region of the first semiconductor structure includes: An array of vertical transistors; and An array of vertical capacitors, wherein the vertical capacitors are connected to corresponding vertical transistors; A stacked structure comprising alternating first layers and first dielectric layers in a contact region of the first semiconductor structure; and An isolation structure is located between the storage array region and the contact region to isolate the array of vertical capacitors from the stacked structure.

17. The storage device according to claim 16, wherein, The first dielectric layer includes a first dielectric material, and the first layer includes a second dielectric layer, the second dielectric layer including a second dielectric material.

18. The storage device according to claim 16, wherein: The first dielectric layer comprises a first dielectric material; and The first layer includes at least a second dielectric layer and a third dielectric layer, wherein the second dielectric layer includes a second dielectric material and the third dielectric layer includes a third dielectric material.

19. The storage device according to claim 16, wherein, The first semiconductor structure further includes: A first contact structure extending through the stacked structure in a first direction, wherein the end surface of the first contact structure on the first one in the first layer is flush with the end surface of the isolation structure on the first one in the first layer.

20. The storage device according to claim 19, wherein, The first semiconductor structure further includes: A second contact structure, the second contact structure extending through the stacked structure in the first direction and coupled to a word line; and A third contact structure extends through the stacked structure in the first direction and couples to a positioning line. Wherein, the end surface of the second contact structure located on the first one in the first layer is flush with the end surface of the third contact structure located on the first one in the first layer.

21. The storage device according to claim 20, wherein, The size of the end surface of the second contact structure is equal to the size of the end surface of the third contact structure.

22. The storage device according to claim 20, wherein: The dimension of the end surface of the first contact structure is larger than the dimension of the end surface of the second contact structure and the dimension of the end surface of the third contact structure; or The size of the end surface of the isolation structure is greater than the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

23. The storage device according to claim 19, wherein, The size of the end surface of the first contact structure is equal to the size of the end surface of the isolation structure.

24. The storage device according to claim 19, wherein, The dimensions of the end surface of the first contact structure are different from the dimensions of the end surface of the isolation structure.

25. The storage device according to claim 19, wherein, The isolation structure includes a dielectric material, and the first contact structure includes a conductive material.

26. The storage device of claim 16, further comprising: A second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the memory cell array.

27. The storage device according to claim 20, wherein, The vertical capacitor includes: The first electrode structure coupled to the corresponding vertical transistor; and A second electrode structure isolated from the first electrode structure. Wherein, the end surface of the first electrode structure located on the first part of the first layer is flush with the end surfaces of the second contact structure and the third contact structure.

28. The storage device according to claim 27, wherein, The size of the end surface of the first electrode structure is equal to the size of the end surface of the second contact structure and the size of the end surface of the third contact structure.

29. A method for forming a storage device, comprising: The first semiconductor structure is formed by at least the following operations: A memory cell array is formed in the memory array region of the first semiconductor structure, including: An array of transistors is formed in the memory array region; and An array of storage components is formed in the storage array region, and the storage components are connected to corresponding transistors; and An isolation structure is formed between the storage array region and the contact region of the first semiconductor structure to isolate the array of storage components in the storage array region from the contact region.

30. The method according to claim 29, wherein, The formation of the first semiconductor structure further includes: A stacked structure is formed comprising alternating first layers and first dielectric layers across the memory array region and the contact region.

31. The method according to claim 30, wherein, The formation of the first semiconductor structure further includes: A first contact opening, a second contact opening, and a third contact opening extending through the stacked structure in a first direction are formed in the contact area; A storage opening extending through the stacked structure in the first direction is formed in the storage array region; and An isolation opening extending through the stacked structure in the first direction is formed between the storage array region and the contact region.

32. The method according to claim 31, wherein, Forming the isolation structure includes: The isolation structure is formed in the isolation opening.

33. The method according to claim 31, wherein, The formation of the first semiconductor structure further includes: A first contact structure is formed in the first contact opening; A second contact structure is formed in the second contact opening to couple to the word line; and A third contact structure is formed in the third contact opening to couple to the positioning line. Wherein, the end surface of the first contact structure located on the first member of the first layer is flush with the end surface of the isolation structure located on the first member of the first layer, and Wherein, the end surface of the second contact structure located on the first one in the first layer is flush with the end surface of the third contact structure located on the first one in the first layer.

34. The method according to claim 31, wherein, The storage component includes a vertical capacitor, and the array forming the storage component includes: First electrode structures are formed in the storage openings, respectively, wherein the first electrode structures are coupled to the transistors; and A second electrode structure is formed that is isolated from the first electrode structure. The vertical capacitor includes a corresponding first electrode structure and a corresponding second electrode structure.

35. The method according to claim 34, wherein, Forming a second electrode structure isolated from the first electrode structure includes: Storage recesses are formed in the storage array region; and A second electrode structure, isolated from the first electrode structure, is formed in the storage groove.

36. The method according to claim 35, wherein, Forming the storage recess in the storage array region includes: Forming a first grid opening that extends through the first layer in the storage array region; The first portion of the first of the first dielectric layer in the storage array region is removed through the first grid opening, wherein the remaining portion of the first of the first dielectric layer in the contact region is isolated by the isolation structure and remains intact; Forming a second grid opening extending through the second of the first layer in the storage array region; and A portion of the second element in the first dielectric layer in the storage array region is removed through the second mesh opening, wherein the remaining portion of the second element in the first dielectric layer in the contact region is isolated by the isolation structure and remains intact.

37. The method of claim 35, wherein, Forming a second electrode structure isolated from the first electrode structure includes: A storage dielectric layer is formed to cover the first electrode structure in the storage groove; and The second electrode structure is formed in the storage groove by depositing a conductive layer over the storage dielectric layer.

38. The method of claim 29, further comprising: Forming a second semiconductor structure; as well as The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure includes peripheral circuitry coupled to the memory cell array.

Images