A method and system for parallel data out triggering synchronization of multiple phase clocks
By generating and synchronizing multi-phase clock signals within the FPGA, the problem of ambiguity in the sampling points of the parallel output structure of the ADC under the control of external trigger signals in high-speed data acquisition systems is solved. This achieves precise positioning and time alignment between the external trigger signals and the ADC sampling points, thereby improving data stability and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU MAISHUO ELECTRIC CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-06-19
AI Technical Summary
In high-speed data acquisition systems, when using an analog-to-digital converter (ADC) with parallel output structure controlled by an external trigger signal, existing technologies cannot solve the problem of sampling point ambiguity, resulting in waveform jitter and unstable measurement data, especially in high sampling rate and multi-phase systems.
By generating multi-phase clock signals inside the FPGA, sampling external trigger signals using a phase-locked loop, and performing synchronization processing through a three-stage D flip-flop chain, the multi-path trigger state sequence is analyzed, and the ADC sampling point position corresponding to the edge of the external trigger signal is accurately located to achieve time alignment.
It effectively suppresses trigger jitter caused by timing uncertainty between asynchronous trigger signals and system clock, improving the stability and reliability of measurement data. All calculation logic is implemented internally on the FPGA, requiring no external hardware, which facilitates integration and maintenance.
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Figure CN121858019B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data sampling and output technology, specifically to a multi-phase clock parallel data external triggering synchronization method and system. Background Technology
[0002] In high-speed data acquisition systems, analog-to-digital converters (ADCs) typically employ a parallel output structure, transmitting multiple sampling points within a single clock cycle to reduce system clock frequency and improve system stability. In practical applications, one scenario where an ADC acquires useful data is enabled by an external trigger signal; once enabled, this trigger signal acquires a segment of data as input to subsequent stages.
[0003] When a system uses an external trigger signal to control data acquisition, traditional synchronization methods typically map the external trigger signal directly to the ADC transmitted value. However, the ADC transmitted value contains multiple sampling points, making it unclear which sampling point will be triggered first. This causes waveform jitter in the acquired data, resulting in poor measurement quality. Current technologies often use simple triggers or synchronization chains to synchronize the external trigger signal in a single clock domain. However, this method cannot solve the "sampling point ambiguity" problem introduced by the parallel output structure of the ADC, especially in high sampling rate, multi-phase systems where trigger jitter is more pronounced. Summary of the Invention
[0004] The purpose of this invention is to provide a multi-phase clock parallel data external trigger synchronization method and system, which uses an ADC sampling clock to sample external trigger signals through different phase shifts, so that the trigger output is accurate to a certain sampling point, reducing waveform jitter and increasing data stability.
[0005] To achieve the above objectives, this application provides the following solution:
[0006] On one hand, the present invention provides a multi-phase clock parallel data external trigger synchronization method, specifically including the following steps:
[0007] Step 1: Receive the external trigger signal, the ADC sampling clock signal, and the data from each sampling point of the ADC;
[0008] Step 2: Generate a multiphase clock signal within the FPGA using a phase-locked loop based on the ADC sampling clock signal;
[0009] Step 3: Simultaneously sample the external trigger signal at each edge of the multiphase clock signal to obtain the synchronized multi-channel trigger state sequence;
[0010] Step 4: Analyze the synchronized multi-path trigger state sequence to determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC.
[0011] In some specific implementations, the phase difference between any two adjacent phase clock signals in the multiphase clock signal is equal, and the multiphase clock signal subdivides the clock period of the ADC sampling clock signal into multiple equally spaced time slices.
[0012] In some specific implementation schemes, the process of obtaining the synchronized multi-path trigger state sequence is as follows:
[0013] The external trigger signal is sampled in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data.
[0014] A three-stage D flip-flop chain is used to synchronously process the multi-channel sampled data to obtain multiple stable sampled values;
[0015] The multiple stable sampled values are arranged in order to obtain the multiple trigger state sequence.
[0016] In some specific implementation schemes, the process of parsing the synchronized multi-path trigger state sequence is as follows:
[0017] Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position;
[0018] Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.
[0019] In some specific implementation schemes, the specific process of locating the level transition position is as follows:
[0020] Set a sliding window with a size of 2 and a step value of 1. Use the sliding window to traverse the edges of the multi-path trigger state sequence. When the state of two adjacent edges within the sliding window changes, it is determined that a level jump has occurred.
[0021] If the edge state change is from low level to high level, then determine that the level change is a rising edge change and record the rising edge change position in the multi-trigger state sequence at this time.
[0022] If the edge state change is from high level to low level, then determine that the level change is a falling edge change and record the falling edge change position in the multi-trigger state sequence.
[0023] In some specific implementations, the process of mapping the level transition position to the corresponding sampling point time window is as follows:
[0024] Based on the rising edge transition position in the multi-trigger state sequence, locate the time window in which the rising edge transition occurs at the edge of the multi-phase clock signal;
[0025] Based on the known timing relationship between the edges of the multiphase clock signal and the location of the ADC sampling points, the time window corresponding to the edges of the multiphase clock signal for each sampling point of the ADC is obtained.
[0026] Based on the time window in which the rising edge transition occurs at the edge of the multiphase clock signal and the time window of the multiphase clock signal corresponding to each sampling point of the ADC, the position of the ADC sampling point corresponding to the rising edge transition degree is located.
[0027] In some specific implementations, the step of changing the state of two adjacent edges within the sliding window is further included:
[0028] If the state of two adjacent edges in the current sliding window changes, move the sliding window. If the state of two adjacent edges in the next sliding window also changes, and the state changes of the edges in the current sliding window and the next sliding window are in opposite directions, then determine whether the state of several edges after the next sliding window remains unchanged relative to the last edge in the next sliding window. If so, then determine that the level in the next sliding window has changed.
[0029] Secondly, this application provides a multi-phase clock parallel data external trigger synchronization system, including:
[0030] The receiving module is used to receive external trigger signals, ADC sampling clock signals, and data from each sampling point of the ADC.
[0031] The multiphase clock generation module is used to generate multiphase clock signals within the FPGA based on the ADC sampled clock signal through a phase-locked loop.
[0032] The synchronous sampling module is used to synchronously sample the external trigger signal at each edge of the multi-phase clock signal to obtain the synchronized multi-path trigger state sequence.
[0033] The trigger parsing module is used to parse the synchronized multi-channel trigger state sequence, determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC.
[0034] In some specific implementations, the synchronous sampling module includes:
[0035] The sampling unit is used to simultaneously sample the external trigger signal in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data.
[0036] The synchronization unit is used to synchronize multiple sampled data using a three-level D flip-flop chain to obtain multiple stable sampled values;
[0037] The encoding unit is used to arrange the multiple stable sampled values in order to obtain a multiple trigger state sequence.
[0038] In some specific implementations, the trigger parsing module is also used for:
[0039] Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position;
[0040] Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.
[0041] The beneficial effects of this invention are as follows:
[0042] This invention utilizes the ADC sampling clock to generate a multi-phase sampling clock through the phase-locked loop inside the FPGA. The multi-phase sampling clock is used to perform high-density sampling and synchronization of external trigger signals, and the trigger state at multiple time points can be obtained within one ADC clock cycle, thereby accurately locating the specific sampling point corresponding to the trigger edge.
[0043] Based on the known timing relationship between the multiphase clock edge and the ADC sampling point, the trigger signal is mapped to the corresponding sampling point time window. Through multiphase sampling and a three-level synchronous timing alignment mechanism, the external trigger signal can be accurately mapped to the sampling point, effectively suppressing the trigger jitter caused by the timing uncertainty between the asynchronous trigger signal and the system clock, improving the consistency and reliability of the measurement data. Furthermore, all calculation logic is implemented internally on the FPGA, requiring no additional external hardware, which facilitates integration and maintenance. Attached Figure Description
[0044] Figure 1 This is a flowchart of a multi-phase clock parallel data external trigger synchronization method provided in an embodiment of the present invention;
[0045] Figure 2 A timing diagram of the multiphase clock signal downsampling external trigger signal provided in an embodiment of the present invention;
[0046] Figure 3 This is a schematic diagram illustrating the correspondence between sampling points and multi-path trigger state sequences provided in an embodiment of the present invention.
[0047] Figure 4 This is a schematic diagram of multiphase clock signal generation provided in an embodiment of the present invention. Detailed Implementation
[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0049] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps described in these embodiments do not limit the scope of the invention.
[0050] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.
[0051] Furthermore, for clarity and brevity, descriptions of well-known structures, functions, and configurations may have been omitted. Those skilled in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of this disclosure.
[0052] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0053] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0054] Example 1
[0055] like Figure 1 As shown, this embodiment provides a multi-phase clock parallel data external trigger synchronization method, which specifically includes the following steps:
[0056] Step 1: Receive the external trigger signal, the ADC sampling clock signal, and the data from each sampling point of the ADC;
[0057] Step 2: Generate a multiphase clock signal within the FPGA using a phase-locked loop based on the ADC sampling clock signal;
[0058] In a multiphase clock signal, the phase difference between the frequencies of two adjacent clock signals is equal, and the multiphase clock signal subdivides the clock period of the ADC sampling clock signal into multiple equally spaced time slices.
[0059] Step 3: Simultaneously sample the external trigger signal at each edge of the multiphase clock signal to obtain the synchronized multi-channel trigger state sequence;
[0060] The specific process of obtaining the synchronized multi-path trigger state sequence is as follows:
[0061] The external trigger signal is sampled in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data.
[0062] A three-stage D flip-flop chain is used to synchronously process the multi-channel sampled data to obtain multiple stable sampled values;
[0063] The stable sampled values from multiple channels are arranged in sequence to obtain a multi-channel trigger state sequence. The stable sampled values from each branch are then arranged in chronological order to form an N-bit binary sequence (e.g., an 8-bit sequence). This sequence encodes the level changes of the external trigger signal within one ADC clock cycle.
[0064] Step 4: Analyze the synchronized multi-path trigger state sequence to determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC.
[0065] The specific process of parsing the synchronized multi-path trigger state sequence is as follows:
[0066] Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position;
[0067] The specific process of locating the level transition position is as follows:
[0068] Set a sliding window with a size of 2 and a step value of 1. Use the sliding window to traverse the edges of the multi-path trigger state sequence. When the state of two adjacent edges within the sliding window changes, it is determined that a level jump has occurred.
[0069] To avoid noise interference, the multi-path trigger state sequence is filtered, and a valid trigger is only determined when multiple consecutive states are stable. That is, when the states of two adjacent edges within the sliding window change, the following steps are also included:
[0070] If the state of two adjacent edges within the current sliding window changes, the sliding window is moved. If the state of two adjacent edges within the next sliding window also changes, and the direction of the state change of the edges within the current and next sliding windows is opposite, then it is determined whether the states of several edges after the next sliding window remain unchanged relative to the last edge within the next sliding window. If so, it is determined that a level transition has occurred within the next sliding window. For example, when the multi-path trigger state sequence is [0 1 0 1 1 1 0 0], a level transition is determined only when multiple consecutive 1s or 0s are detected. Since a valid trigger is a rising edge, the rising edge corresponding to the first 1 among multiple consecutive 1s is the rising edge transition position of the valid trigger.
[0071] If the edge state change is from low level to high level, then determine that the level change is a rising edge change and record the rising edge change position in the multi-trigger state sequence at this time.
[0072] If the edge state change is from high level to low level, then determine that the level change is a falling edge change and record the falling edge change position in the multi-trigger state sequence.
[0073] Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.
[0074] The specific process of mapping the level transition position to the corresponding sampling point time window is as follows:
[0075] Based on the rising edge transition position in the multi-trigger state sequence, locate the time window in which the rising edge transition occurs at the edge of the multi-phase clock signal;
[0076] Based on the known timing relationship between the edges of the multiphase clock signal and the location of the ADC sampling points, the time window of the multiphase clock signal edge corresponding to each sampling point of the ADC is obtained;
[0077] Based on the time window in which the rising edge transition occurs at the edge of the multiphase clock signal and the time window of the multiphase clock signal edge corresponding to each sampling point of the ADC, the position of the ADC sampling point corresponding to the rising edge transition degree is located.
[0078] It is understood that the signals mentioned in this embodiment are:
[0079] External trigger signal (din): An asynchronous trigger pulse (such as a rising edge) from outside the system, used to start or control data acquisition. The external trigger signal is a single-ended, asynchronous digital pulse signal with random edge arrival times. That is, its edge arrival time is completely independent of the ADC clock and is an object that needs to be synchronized and located.
[0080] ADC sampling clock: The system clock from the analog-to-digital converter, serving as the time reference for the entire acquisition system. It defines the acquisition times from sampling points S1 to Sn.
[0081] Multiphase clock signals: These are clock groups derived from the ADC sampling clock by the FPGA's internal PLL. They have the same frequency but sequentially offset phases (e.g., clk-0°, clk-45°, clk-90°, clk-135° and their falling edges). These clock groups form a high-resolution time scale used to "oversample" the time axis of external trigger signals, allowing for precise measurement of the occurrence times of the external trigger signal edges.
[0082] Multi-trigger state sequence (e.g., Y3(7:0)): This is a binary sequence of eight stable state values obtained by sampling and synchronizing the external trigger signal using the eight edges of the multi-phase clock signal, arranged in chronological order. This sequence encodes a "waveform snapshot" of the external trigger signal within one ADC clock cycle, particularly the position information of the edge transitions on the fine time axis.
[0083] The purpose of this embodiment is to discretize a continuous ADC clock cycle into multiple fine phase intervals using a multi-phase clock. The multi-trigger state sequence is the set of sampled values of the external trigger signal across these phase intervals. By analyzing the level change patterns in this sequence, the precise phase of the external trigger signal edge relative to the ADC sampling time can be deduced, thereby achieving synchronization with a specific sampling point. In other words, by analyzing the multi-trigger state sequence, it is possible to determine within which sampling point's time window the transition edge of the external trigger signal falls, thus locking and aligning the external trigger event with a specific ADC sampling point (such as S2).
[0084] To better understand the concept of this embodiment, when the ADC sampling clock signal ADC_CLK frequency is 250MHz (sampling period T_adc = 4ns), each ADC clock sampling period outputs 8 sampling points in chronological order: S1~S8, with a sampling interval of 4ns / 2=0.5ns between adjacent sampling points; assuming the multiphase clock signal generated by the PLL is a four-phase clock with four different phases: clk-0°, 45°, 90°, 135°. Its 8 edges are evenly distributed within one T_adc period, further subdividing the time into 8 0.5 ns intervals. Assuming that after system calibration, the first edge of the multiphase clock (clk-0° rising edge, time T0) roughly aligns with the time when the ADC sampling point S1 is latched into the FPGA. Then, the subsequent edges of the multiphase clock sequentially cover the time windows of the subsequent sampling points. The known timing relationship between the edges of the multiphase clock signal and the positions of the ADC sampling points is shown in Table 1:
[0085] Table 1. Time Series Mapping Table (relative to t=0)
[0086]
[0087] The external trigger signal din is an asynchronous pulse that transitions from low to high. Assuming its rising edge actually occurs 0.4ns after the rising edge of the ADC clock (t=0), the specific process is as follows:
[0088] 1. The FPGA receives the asynchronous external trigger signal din. At the same time, the FPGA receives the ADC sampling clock signal ADC_CLK (250MHz) sent by the ADC. ADC_CLK will be used as the frequency and phase reference for all subsequent processing.
[0089] 2. For example Figure 4 As shown, the PLL inside the FPGA uses ADC_CLK as a reference to generate four clocks with the same frequency (250MHz) and phases that differ by 45°: clk-0° (0° phase clock of the sampling clock), clk-45° (45° phase clock of the sampling clock), clk-90° (90° phase clock of the sampling clock), and clk-135° (135° phase clock of the sampling clock). The eight edges of these four clocks (the rising and falling edges of each clock) are evenly distributed within one ADC_CLK period (4ns), subdividing the 4ns time window into eight 0.5ns "sub-intervals," providing eight precise sampling moments (T0~T7). Its time resolution (0.5 ns) is higher than that of a single sampling point time window, which is the basis for achieving precise positioning.
[0090] 3. Use a multi-phase clock to sample and synchronize external trigger signals.
[0091] An independent three-stage D flip-flop sampling synchronization chain is set up for each multi-phase clock edge. The sampling process (taking the rising edge of din at t=0.4 ns as an example, it can be known that the rising edge occurs between T0 and T1), assuming the multi-path trigger state sequence obtained after sampling the external trigger signal din is as follows:
[0092] T0 (0.0 ns): The external trigger signal din is low (because 0.0 ns < 0.4 ns) → sampling yields Y1(T0) = 0;
[0093] T1 (0.5 ns): External trigger signal din is high (because 0.5 ns > 0.4 ns) → Y1(T1) = 1;
[0094] T2 (1.0 ns): External trigger signal din is high → Y1(T2) = 1;
[0095] T3 (1.5 ns): External trigger signal din is high → Y1(T3) = 1;
[0096] T4 (2.0 ns): External trigger signal din is high → Y1(T4) = 1;
[0097] T5 (2.5 ns): External trigger signal din is high → Y1(T5) = 1;
[0098] T6 (3.0 ns): The external trigger signal din transitions to a low level (assuming the falling edge occurs between 2.5 and 3.0 ns) → Y1(T6) = 0;
[0099] T7 (3.5 ns): External trigger signal din is low → Y1(T7) = 0;
[0100] Three-level synchronization (three beats):
[0101] To prevent metastability and ensure the sampled values are stable within the corresponding clock domain, each Y1(Tn) needs to pass through two levels of registers. For example, for Y1(T1) = 1 sampled at the T4 edge: at the next rising edge of clk-45° (i.e., the next T1 time), the first level is stored: Y2(T1) = 1; at the next rising edge of clk-45°, the second level is stored: Y3(T1) = 1; Y3(T1) is the final stable trigger state aligned to the T4 time. After all 8 edges have completed this process, a set of stable time-coded values is obtained: Y3(T0), Y3(T1), ..., Y3(T7). Y3(T0) to Y3(T7) are arranged in chronological order (T0 earliest, T7 latest) to form an 8-bit binary sequence. Based on the above sampling results: Y3(T0)=0, Y3(T1)=1, Y3(T2)=1, Y3(T3)=1, Y3(T4)=1, Y3(T5)=1, Y3(T6)=0, Y3(T7)=0, the multi-path trigger state sequence is obtained as: [0 1 1 1 1 1 0 0]. It can be seen that the rising edge of the multi-path trigger state sequence occurs between T0 (0.0ns) and T1 (0.5ns), and the falling edge occurs between T5 (2.5ns) and T6 (3.0ns). The pulse width is approximately 2.5ns (estimated value from 0.25ns to 2.75ns).
[0102] 4. Analyze the multi-path trigger state sequence after synchronization.
[0103] Locate the trigger edge and sampling point, analyze the sequence, and find the transition from low level 0 to high level 1. Analyzing the sequence 01111100, it is found that the rising edge transition from level 0 to 1 occurs between the 1st and 2nd bits (i.e., Y3(T0) to Y3(T1)). This means that the rising edge transition of the external trigger signal din occurs within the time window of the multi-phase clock signal edge between T0 and T1. That is, after time T0 (0.0 ns) and before time T1 (0.5 ns). According to the timing mapping table, T0 corresponds to the time window of sampling point S1, and T1 corresponds to the time window of sampling point S2. According to the timing mapping table, only when the transition position is exactly on the edge can the mapped sampling point be directly found according to the timing mapping table. However, for the transition position in the above embodiment between the two edges T0 and T1, it is necessary to determine which sampling point it belongs to according to the set rules. For example, it can be judged by comparing the rising edge occurrence time with the edge occurrence time. If the rising edge occurrence time is closer to T1, it is determined to be aligned with S2. Alternatively, the trigger within the T0-T1 window can be classified as S2, and it is determined to be aligned with S2. Or, 0 sampled at T0 can be regarded as no trigger within the S1 time window, and 1 sampled at T1 can be regarded as a trigger within the S2 time window.
[0104] This embodiment provides a method to define the time window of each sampling point as starting from the multi-phase clock edge corresponding to the sampling point and ending at the next edge, that is, the time window of sampling point S1 is 0.0ns ~ 0.5ns (corresponding to T0 to T1); if the rising edge transition position is within a certain time window, it is aligned with the sampling point;
[0105] If the rising edge of the external trigger signal occurs between 0.0 and 0.5 ns, it falls within the window of sampling point S1. Therefore, the rising edge of the external trigger signal din is determined to be synchronized and precisely aligned to the ADC sampling point S1. After finding this sampling point S1, a sampling point index corresponding to S1 is generated, indicating that the current external trigger signal corresponds to the ADC sampling point S1. Subsequent data storage, waveform display, or trigger control logic will be based on this alignment result to ensure that the data segment starting from S1 is correctly captured and processed.
[0106] like Figure 2 As shown, the edges of the clock signal for each phase are numbered. The multi-channel trigger state sequence output after the input external trigger signal din is sampled by the four-phase clock signal is [01111100]. Its correspondence with the multi-phase clock signal is as follows:
[0107] T0: The first edge of clk-0° corresponds to the first sampled din state, and its value is 0 (low level);
[0108] T1: The first edge of clk-45° corresponds to the second sampling din state, and its value is 1 (high level);
[0109] T2: The first edge of clk-90° corresponds to the third sampling din state, and its value is 1 (high level);
[0110] T3: The fourth sampled DIN state at the first edge of clk-135°, with a value of 1 (high level);
[0111] T4: The fifth sampling din state at the second edge of clk-0°, with a value of 1 (high level);
[0112] T5: The sixth sampling din state of the second edge of clk-45°, its value is 1 (high level);
[0113] T6: The seventh sampling DIN state of the second edge of clk-90°, its value is 0 (low level);
[0114] T7: The eighth sampling DIN state of the second edge of clk-135°, its value is 0 (low level);
[0115] At this point, it can be seen from the obtained multi-channel trigger state sequence [01111100] that there is a rising edge between T0 and T1, indicating that a rising edge trigger signal has arrived and one cycle of acquisition is completed. Figure 3 As shown, this represents the data collected from S1 to S8. The edge of this rising bar corresponds to the sampling point. Using S1 as the trigger reference point, the starting position for storing data is determined based on the pre-trigger / post-trigger settings. For example, if the pre-trigger depth is set to 4, then data starting from the 4 points before S1 will be stored.
[0116] Example 2
[0117] This embodiment provides a multi-phase clock parallel data external trigger synchronization system, including:
[0118] The receiving module is used to receive external trigger signals, ADC sampling clock signals, and data from each sampling point of the ADC.
[0119] The multiphase clock generation module is used to generate multiphase clock signals within the FPGA based on the ADC sampled clock signal through a phase-locked loop.
[0120] The synchronous sampling module is used to synchronously sample the external trigger signal at each edge of the multi-phase clock signal to obtain the synchronized multi-path trigger state sequence.
[0121] Specifically, the synchronous sampling module includes:
[0122] The sampling unit is used to simultaneously sample the external trigger signal in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data.
[0123] The synchronization unit is used to synchronize multiple sampled data using a three-level D flip-flop chain to obtain multiple stable sampled values;
[0124] The encoding unit is used to arrange the multiple stable sampled values in order to obtain a multiple trigger state sequence.
[0125] The trigger parsing module is used to parse the synchronized multi-channel trigger state sequence, determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC.
[0126] Specifically, the trigger parsing module is also used for:
[0127] Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position;
[0128] Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.
[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for synchronizing the output of a plurality of parallel data signals from a plurality of clocked sources, comprising the steps of: Specifically, the following steps are included: Step 1: Receive the external trigger signal, the ADC sampling clock signal, and the data from each sampling point of the ADC; Step 2: Generate a multiphase clock signal within the FPGA using a phase-locked loop based on the ADC sampling clock signal; Step 3: Simultaneously sample the external trigger signal at each edge of the multiphase clock signal to obtain the synchronized multi-channel trigger state sequence; The specific process of obtaining the synchronized multi-path trigger state sequence is as follows: The external trigger signal is sampled in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data. A three-stage D flip-flop chain is used to synchronously process the multi-channel sampled data to obtain multiple stable sampled values; Arrange the multiple stable sampled values in order to obtain a multiple trigger state sequence; Step 4: Analyze the synchronized multi-channel trigger state sequence to determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC. The specific process of parsing the synchronized multi-path trigger state sequence is as follows: Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position; Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.
2. A method for the external synchronization of parallel data from multiple clock sources as recited in claim 1, wherein, In a multiphase clock signal, the phase difference between any two adjacent clock signals is equal, and the multiphase clock signal subdivides the clock period of the ADC sampling clock signal into multiple equally spaced time slices.
3. A method for externally triggered synchronization of parallel data from multiple clocks as recited in claim 1, wherein, The specific process of locating the level transition position is as follows: Set a sliding window with a size of 2 and a step value of 1. Use the sliding window to traverse the edges of the multi-path trigger state sequence. When the state of two adjacent edges within the sliding window changes, it is determined that a level jump has occurred. If the edge state change is from low level to high level, then determine that the level change is a rising edge change and record the rising edge change position in the multi-trigger state sequence at this time. If the edge state change is from high level to low level, then determine that the level change is a falling edge change and record the falling edge change position in the multi-trigger state sequence.
4. A method for externally triggered synchronization of parallel data from multiple clocks as recited in claim 3, wherein, The specific process of mapping the level transition position to the corresponding sampling point time window is as follows: Based on the rising edge transition position in the multi-trigger state sequence, locate the time window in which the rising edge transition occurs at the edge of the multi-phase clock signal; Based on the known timing relationship between the edges of the multiphase clock signal and the location of the ADC sampling points, the time window corresponding to the edges of the multiphase clock signal for each sampling point of the ADC is obtained. Based on the time window in which the rising edge transition occurs at the edge of the multiphase clock signal and the time window of the multiphase clock signal corresponding to each sampling point of the ADC, the position of the ADC sampling point corresponding to the rising edge transition degree is located.
5. A method for externally triggered synchronization of parallel data from multiple clocks as recited in claim 3, wherein, When the state of two adjacent edges within the sliding window changes, the following steps are also included: If the state of two adjacent edges in the current sliding window changes, move the sliding window. If the state of two adjacent edges in the next sliding window also changes, and the state changes of the edges in the current sliding window and the next sliding window are in opposite directions, then determine whether the state of several edges after the next sliding window remains unchanged relative to the last edge in the next sliding window. If so, then determine that the level in the next sliding window has changed.
6. A multi-phase clock parallel data external trigger synchronization system, characterized in that, include: The receiving module is used to receive external trigger signals, ADC sampling clock signals, and data from each sampling point of the ADC. The multiphase clock generation module is used to generate multiphase clock signals within the FPGA based on the ADC sampled clock signal through a phase-locked loop. The synchronous sampling module is used to synchronously sample the external trigger signal at each edge of the multi-phase clock signal to obtain the synchronized multi-path trigger state sequence. The synchronous sampling module includes: The sampling unit is used to simultaneously sample the external trigger signal in parallel at each edge of the multiphase clock signal to obtain multi-channel sampled data. The synchronization unit is used to synchronize multiple sampled data using a three-level D flip-flop chain to obtain multiple stable sampled values; The encoding unit is used to arrange the multiple stable sampled values in order to obtain a multiple trigger state sequence; The trigger parsing module is used to parse the synchronized multi-channel trigger state sequence, determine the ADC sampling point position corresponding to the edge of the external trigger signal, and realize the time alignment between the external trigger signal and the data of each sampling point of the ADC. The trigger parsing module is also used for: Analyze the multi-path trigger state sequence, detect the edges of the multi-path trigger state sequence, and locate the level transition position; Based on the known timing relationship between the edge of the multiphase clock signal and the position of the ADC sampling point, the level transition position is mapped to the corresponding sampling point time window, and the sampling point index of the ADC sampling point position corresponding to the edge of the external trigger signal is generated.