Data error correction simulation method, system, electronic device and product

Abstract

The application discloses a data error correction simulation method and system, electronic equipment and product, relates to the storage technical field, and is applied to a programmable logic chip. The method comprises the following steps: generating noise-added code word data based on a preset original bit error rate and a noise adding module; using a decoder to perform error correction decoding on the noise-added code word data generated through the noise adding module to obtain a decoding result; in the case that the decoding result does not satisfy a preset jump condition, returning to execute the step of using the decoder to perform error correction decoding on the noise-added code word data generated through the noise adding module to obtain the decoding result; and in the case that the decoding result satisfies the preset jump condition, executing the step of generating noise-added code word data based on a preset original bit error rate and a noise adding module based on a next preset original bit error rate until all preset original bit error rates are traversed. The parallel capability of the programmable logic chip can greatly improve the simulation speed.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data error correction simulation method, system, electronic device, and product. Background Technology

[0002] As flash memory storage density evolves from SLC (Single-Level Cell) to QLC (Quad-Level Cell), the error rate per data page increases significantly. To ensure data reliability, stronger error correction codes must be used. Low-density parity-check codes, especially QC-LDPC codes (Quasi-Cyclic Low Density Parity Check Codes) with quasi-cyclic structures, have become the mainstream solution due to their excellent error correction performance. However, their actual performance needs to be verified through extensive simulations of decoding erroneous bit data. Currently, simulation methods based on traditional CPUs (Central Processing Units) or GPUs require massive amounts of data (e.g., 10^64 bytes) to achieve statistical significance. 15 The extremely long processing time (of data points) makes verification impossible within a reasonable timeframe, which has become a key bottleneck restricting the development of high-reliability flash memory products.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a data error correction simulation method, system, electronic device and product, which aims to solve the technical problem of excessively long simulation time in related simulation schemes.

[0005] To achieve the above objectives, this application proposes a data error correction simulation method applied to a programmable logic chip, wherein the programmable logic chip includes at least one sub-simulation entity, and the sub-simulation entity includes at least one noise-adding module and at least one decoder.

[0006] The data error correction simulation method includes:

[0007] Based on the preset original bit error rate and the noise-adding module, noise-adding codeword data is generated.

[0008] The decoder is used to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result.

[0009] If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, wherein the noisy codeword data participating in the error correction decoding is different each time;

[0010] If the decoding result meets the preset jump condition, the step of generating noisy codeword data based on the preset original bit error rate and the noise-adding module is executed based on the next preset original bit error rate until each preset original bit error rate is traversed.

[0011] In one feasible implementation, the step of generating noisy codeword data based on a preset original bit error rate and the noisy module includes:

[0012] Read the target noise data from the random noise pool of the noise-adding module;

[0013] Determine the signal-to-noise ratio corresponding to the preset original bit error rate;

[0014] When the original correct codeword corresponding to the noisy codeword data is a fixed codeword, noisy codeword data is generated based on the target noise data and the signal-to-noise ratio.

[0015] In one feasible implementation, the noisy codeword data includes at least the confidence level of each bit in the noisy codeword;

[0016] The step of generating noisy codeword data based on the target noise data and the signal-to-noise ratio includes:

[0017] The noise standard deviation is determined by the signal-to-noise ratio.

[0018] Based on the transformation parameters related to the noise standard deviation, the target noise data is converted into the confidence level of the corresponding bit of the target noise data.

[0019] In one feasible implementation, after the step of determining the signal-to-noise ratio corresponding to the preset original bit error rate, the method further includes:

[0020] When the original correct codeword corresponding to the noise-added codeword data is a dynamic codeword, for any one of the noise bits to be added in the original correct codeword, the noise bit to be added is modulated to obtain a data signal;

[0021] A noise signal is generated based on the noise sample corresponding to the noise bit to be added in the target noise data and the signal-to-noise ratio;

[0022] The data signal and the noise signal are fused to obtain the noise-added signal of the bit to be noise-added;

[0023] The noise-added codeword data is generated based on the noise-added signals of each bit to be noise-added in the original correct codeword.

[0024] In one feasible implementation, the noise-adding module further includes a noise generator;

[0025] The data error correction simulation method further includes:

[0026] Noise samples are generated using the noise generator;

[0027] The noise sample is added to the random noise pool.

[0028] In one feasible implementation, the noise generator in the noise-adding module operates in the fast clock domain, and the decoder operates in the slow clock domain;

[0029] The data error correction simulation method further includes:

[0030] The minimum number of generators is determined based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder.

[0031] Configure the noise generation module with a noise generator number greater than or equal to the minimum number of generators.

[0032] In one feasible implementation, the step of determining the minimum number of generators based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder includes:

[0033] The bit throughput of the decoder is calculated using the second clock cycle and the length of the input codeword.

[0034] The noise contribution rate of a single noise generator is calculated using the first clock cycle and the decoding cycle.

[0035] The minimum number of generators is determined based on the ratio between the bit throughput and the noise contribution rate.

[0036] In one feasible implementation, the step of generating noise samples via the noise generator includes:

[0037] The random seed set configured for the noise generator is input to the noise generator, wherein the random seed set configured for the noise generator is different in different sub-simulation entities;

[0038] The noise generator performs random processing on the random seed group to continuously generate pairs of noise samples that meet a preset distribution. The random processing includes segmentation and recombination, function transformation, and polar coordinate transformation synthesis.

[0039] In one feasible implementation, the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result includes:

[0040] The target noisy codeword data is read from the decoder's buffer, wherein the noisy codeword data generated by the noise module is added to the decoder's buffer;

[0041] The target noisy codeword data is corrected and decoded based on the decoding parameters in the decoder to obtain the decoding result.

[0042] In one feasible implementation, after the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain a decoding result, the method includes:

[0043] When the cumulative number of decoding simulations corresponding to the decoding result reaches a preset number of simulations, or when the decoding result contains uncorrectable bits, the decoding result satisfies a preset jump condition.

[0044] If the cumulative number of decoding simulations corresponding to the decoding result has not reached the preset number of simulations, and the decoding result is a successful decoding, then the decoding result does not meet the preset jump condition.

[0045] In one feasible implementation, the step of determining the error correction performance of the decoding parameters in the decoder based on the decoding results at each preset original bit error rate includes:

[0046] Based on the decoding results under each preset original bit error rate, determine the uncorrectable bit rate corresponding to each preset original bit error rate;

[0047] By using the uncorrectable bit rate corresponding to each preset original bit error rate, the variation law of the uncorrectable bit rate with the preset original bit error rate is determined, wherein the variation law characterizes the error correction performance of the decoding parameters in the decoder.

[0048] In one feasible implementation, the step of determining the uncorrectable bit rate corresponding to each preset original bit error rate based on each decoding result under each preset original bit error rate includes:

[0049] For any one of the preset original bit error rates, based on each decoding result under the preset original bit error rate, count the number of uncorrectable frames under the preset original bit error rate and the total number of bits participating in the decoding simulation.

[0050] The uncorrectable bit rate of the preset original bit error rate is determined based on the ratio between the total number of uncorrectable frames and the total number of bits participating in the decoding simulation.

[0051] In one feasible implementation, the data error correction simulation method further includes:

[0052] Initialize decoding simulation information, wherein the decoding simulation information includes at least one of the following: an initial preset raw bit error rate, decoding parameters in the decoder, a preset jump condition, a random seed group of the noise generator, and a decoding decision mode.

[0053] In addition, to achieve the above objectives, this application also proposes a data error correction simulation system, wherein the data error correction simulation system is installed in a programmable logic chip, and the data error correction simulation system includes at least one sub-simulation entity in the programmable logic chip, wherein the sub-simulation entity includes at least one noise-adding module and at least one decoder.

[0054] The sub-simulation entity is used for:

[0055] Based on the preset original bit error rate and the noise-adding module, noise-adding codeword data is generated.

[0056] The decoder is used to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result.

[0057] If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, wherein the noisy codeword data participating in the error correction decoding is different each time;

[0058] If the decoding result meets the preset jump condition, the step of generating noisy codeword data based on the preset original bit error rate and the noise-adding module is executed based on the next preset original bit error rate.

[0059] In addition, to achieve the above objectives, this application also proposes an electronic device, which includes: a processor, a memory, and a data error correction simulation program stored in the memory and executable on the processor, wherein the data error correction simulation program, when executed, implements the steps of the data error correction simulation method as described above.

[0060] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data error correction simulation method described above.

[0061] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the data error correction simulation method described above.

[0062] One or more technical solutions proposed in this application have at least the following technical effects:

[0063] In this embodiment, the programmable logic chip includes at least one sub-emulation entity, which includes at least one noise-adding module and at least one decoder. The process involves generating noisy codeword data based on a preset raw bit error rate and the noise-adding module; using the decoder to perform error correction decoding on the noisy codeword data generated by the noise-adding module to obtain a decoding result; if the decoding result does not meet a preset jump condition, the process returns to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noise-adding module to obtain a decoding result; if the decoding result meets the preset jump condition, the process executes the step of generating noisy codeword data based on the preset raw bit error rate and the noise-adding module based on the next preset raw bit error rate, until all preset raw bit error rates are traversed. In other words, in this embodiment, a programmable logic chip is used for decoding simulation. A sub-emulation entity is set up in the programmable logic chip, and the noise-adding module in the sub-emulation entity generates noisy codeword data according to the raw bit error rate. Then, a decoder is used to decode the noisy codeword data generated by the noise-adding module to obtain a decoding result. If the decoding result meets the preset jump condition, the decoding simulation can proceed to the next preset raw bit error rate. Otherwise, if the condition is not met, the process continues based on the current preset raw bit error rate, iterating through each raw bit error rate and statistically analyzing the decoding results at each preset raw bit error rate to evaluate the error correction performance of the decoder's decoding parameters. It is understood that this embodiment uses a programmable logic chip to build a simulation pipeline architecture. By trading space for time, it achieves highly parallelized pipeline operations for generating and decoding noisy codeword data, improving decoding throughput and significantly increasing the simulation speed of the noise addition and decoding error correction processes. This shortens the simulation time and, consequently, the data error correction simulation time, breaking through the bottleneck in the development of high-reliability flash memory products. Attached Figure Description

[0064] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a schematic diagram of the first process of an embodiment of the data error correction simulation method of this application;

[0067] Figure 2 This is a schematic diagram of the second process in an embodiment of the data error correction simulation method of this application;

[0068] Figure 3 The intended scenario for generating random numbers by the noise generator in the data error correction simulation method of this application;

[0069] Figure 4 This is a schematic diagram of the connection structure of the random noise pool in the data error correction simulation method of this application.

[0070] Figure 5 This is a schematic diagram of a connected scenario of the random noise pool in the data error correction simulation method of this application.

[0071] Figure 6 This is a schematic diagram of the first framework of the data error correction simulation system of this application;

[0072] Figure 7 This is a schematic diagram of the second framework of the data error correction simulation system of this application;

[0073] Figure 8 This is a schematic diagram of the third framework of the data error correction simulation system of this application.

[0074] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0075] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0076] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0077] As flash memory storage density evolves from SLC to QLC, the error rate per data page increases significantly, necessitating stronger error correction codes to ensure data reliability. Low-density parity-check codes, especially QC-LDPC codes with quasi-cyclic structures, have become the mainstream solution due to their superior error correction performance. However, their actual performance needs to be verified through extensive simulations of decoding erroneous bit data. Currently, simulation methods based on traditional CPUs or GPUs require massive amounts of data (e.g., 10^64 bytes) to achieve statistical significance. 15 The extremely long processing time (of data points) makes verification impossible within a reasonable timeframe, which has become a key bottleneck restricting the development of high-reliability flash memory products.

[0078] The main solution of this application embodiment is as follows: Noise-added codeword data is generated based on a preset original bit error rate and a noise-adding module; a decoder is used to perform error correction decoding on the noise-added codeword data generated by the noise-adding module to obtain a decoding result; if the decoding result does not meet a preset jump condition, the process returns to the step of using a decoder to perform error correction decoding on the noise-added codeword data generated by the noise-adding module to obtain a decoding result, wherein the noise-added codeword data participating in the error correction decoding is different each time; if the decoding result meets the preset jump condition, the process of generating noise-added codeword data based on the preset original bit error rate and the noise-adding module is executed based on the next preset original bit error rate, until all preset original bit error rates are traversed.

[0079] In this embodiment, a programmable logic chip is used for decoding simulation. A sub-simulation entity is set up in the programmable logic chip. The noise-adding module in the sub-simulation entity generates noisy codeword data based on the original bit error rate. Then, a decoder decodes the noisy codeword data generated by the noise-adding module to obtain the decoding result. If the decoding result meets the preset jump condition, the decoding simulation can be performed by jumping to the next preset original bit error rate. Otherwise, if it does not meet the condition, the simulation continues based on the current preset original bit error rate, and so on, iterating through each original bit error rate. The decoding results under each preset original bit error rate are statistically analyzed to evaluate the error correction performance of the decoding parameters in the decoder. It can be understood that this embodiment builds a simulation pipeline architecture using a programmable logic chip. By trading space for time, it achieves a highly parallel pipeline operation for generating and decoding noisy codeword data, improving the decoding throughput. This significantly increases the simulation speed of the noise-adding and decoding error correction process, shortens the simulation time, and further shortens the data error correction simulation time, breaking the bottleneck in the development of high-reliability flash memory products.

[0080] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program execution functions, such as a programmable logic chip, storage device, computer, mobile phone, etc., or an electronic device capable of realizing the above functions.

[0081] Reference Figure 1 , Figure 1 This illustration shows a first flowchart of the data error correction simulation method provided in an embodiment of this application. In this embodiment, the data error correction simulation method is applied to a programmable logic chip. The programmable logic chip includes at least one sub-simulation entity, which includes at least one noise-adding module and at least one decoder. The data error correction simulation method includes steps S10 to S50:

[0082] Step S10: Generate noisy codeword data based on the preset original bit error rate and the noisy module;

[0083] It should be noted that the programmable logic chip mentioned above typically refers to an FPGA (Field Programmable Gate Array) chip. Compared to traditional solutions using CPUs or GPUs for decoding and simulation, using programmable logic chips for simulation can leverage their high-speed parallelism, thereby significantly reducing decoding and simulation time. Specifically, the programmable logic chip includes at least one sub-simulation entity, and each sub-simulation entity includes at least one noise-adding module and at least one decoder. Optionally, to fully utilize the hardware resources of the programmable chip, multiple simulation entities can be configured. Optionally, to meet the data throughput requirements of the decoder, multiple noise-adding modules can be configured for a single decoder.

[0084] For example, noisy codeword data is generated based on a preset raw bit error rate (RBER) and a noise-adding module. The preset raw bit error rate measures the number of erroneous bits in the codeword data being decoded by the decoder. The initial preset raw bit error rate can be set according to the needs of the actual simulation process, such as based on a rough evaluation of the decoding performance. The noise-adding module can generate random noise and apply this random noise to the original correct codewords according to the preset raw bit error rate, thereby generating noisy codeword data. It is understood that the noisy codeword data is generated after noise addition; therefore, some bits in the noisy codeword data are erroneous bits, and the number of erroneous bits is determined by the preset raw bit error rate.

[0085] Step S20: Use a decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result;

[0086] For example, the decoder can be configured with an internal or external buffer to store noisy codeword data generated by the noisy module, supporting a pipelined decoding operation. During decoding, the decoder can read the noisy codeword data from the buffer. Then, it decodes the read noisy codeword data using the decoding parameters configured in the decoder. These decoding parameters are the QC-LDPC matrix (i.e., the QC-LDPC code) used to verify the decoding performance. In practical applications, different decoding parameters can be configured in the decoder according to requirements.

[0087] In one feasible implementation, the step of using a decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result includes steps S21 to S22:

[0088] Step S21: Read the target noisy codeword data from the decoder's buffer, wherein the noisy codeword data generated by the noise module is added to the decoder's buffer;

[0089] Step S22: Based on the decoding parameters in the decoder, perform error correction decoding on the target noisy codeword data to obtain the decoding result.

[0090] For example, the decoder can be configured with a buffer, and the noisy codeword data generated by the noisy module will be added to the decoder's buffer. The target noisy codeword data is read from the decoder's buffer.

[0091] Optionally, the decoder can be configured with two independent buffers (e.g., Buffer A and Buffer B). When the noise-adding module writes a complete noisy codeword to Buffer A, the decoder core simultaneously reads the previous codeword from Buffer B for decoding. Once full, their roles are reversed; that is, the noisy codewords stored in the two independent buffers will take turns becoming the target noisy codewords.

[0092] Optionally, the decoder's buffer can also be a first-in, first-out (FIFO) queue. For example, a sufficiently deep buffer queue can be set up between the noise-adding module and the decoder core. Optionally, the noise-adding module can append its generated noise-adding codeword data to the tail of the buffer queue, while the decoder reads the target noise-adding codeword data from the head of the buffer queue.

[0093] Understandably, by setting up a cache, the generation, writing, and decoding of noisy codeword data are fully pipelined, eliminating waiting time and making the simulation decoding process highly parallel, thus reducing simulation time.

[0094] For example, internally, the decoder decodes the target noisy codeword data based on its configured decoding parameters. Optionally, if a QC-LDPC code structure is used, the decoder instantiates z parallel variable node processing units and z parallel parity node processing units according to the boost factor z of its parity check matrix. Each clock cycle, all units synchronously perform message passing. After several iterations, a hard decision is made on the posterior probability of the variable nodes, outputting the decoding result (corrected bits) and a "decoding success / failure" flag (e.g., passing CRC check). Optionally, this decoding result is also recorded for final decoding performance evaluation.

[0095] It is understood that in this embodiment, a simulation pipeline architecture is built using programmable logic chips. By trading space for time, the iterative algorithm is transformed into a deterministic pipeline operation, achieving high-speed decoding throughput for massive simulation scenarios.

[0096] In one feasible implementation, after the step of using a decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, the method includes steps S301 to S302:

[0097] Step S301: When the cumulative number of decoding simulations corresponding to the decoding result reaches the preset number of simulations, or when the decoding result contains uncorrectable bits, the decoding result satisfies the preset jump condition.

[0098] In step S302, if the cumulative number of decoding simulations corresponding to the decoding result has not reached the preset number of simulations, and the decoding result is a successful decoding, the decoding result does not meet the preset jump condition.

[0099] It should be noted that a judgment can be made on the decoding result obtained after each decoding simulation. That is, it can be judged whether it meets the preset jump condition, so as to jump to use a new preset raw bit error rate, such as jumping to use a new RBER for simulation again. Accordingly, the preset jump condition can be that the cumulative number of decoding simulations corresponding to the decoding result reaches the preset number of simulations, or the decoding result contains uncorrectable bits, that is, decoding failure.

[0100] Optionally, two thresholds can be set, including an upper limit for the number of simulation frames N_total (i.e., the preset number of simulations mentioned above) and an upper limit for the number of unacceptable error frames N_err_max. The number of error frames refers to the number of uncorrectable frames, such as the number of decoding failures. It should be noted that to improve simulation speed, the upper limit for the number of error frames N_err_max can be set to 1. Optionally, the total number of simulation frames frame_cnt and the number of uncorrectable error frames err_frame_cnt at the current RBER point can be continuously counted. If either frame_cnt >= N_total or err_frame_cnt >= N_err_max, the preset jump condition is considered met. N_err_max can be determined based on the simulation accuracy requirements. Conversely, if frame_cnt < N_total and err_frame_cnt < N_err_max, the jump condition is considered not met.

[0101] Step S30: If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result. The noisy codeword data participating in the error correction decoding is different each time.

[0102] For example, if the decoding result does not meet the preset jump condition, it indicates that the expected simulation depth has not been reached for the current preset original bit error rate, and the actual decoding performance cannot be verified. Therefore, the process returns to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result. It should be noted that the noisy codeword data participating in error correction decoding is different each time. Optionally, the noisy codeword data can be read from the first-in-first-out queue; alternatively, the noisy codeword data can be obtained through consumption for error correction decoding; alternatively, after performing error correction decoding on a noisy codeword data, the noisy codeword data can be discarded; so that the noisy codeword data participating in the noisy decoding is different each time.

[0103] Step S40: If the decoding result meets the preset jump condition, based on the next preset original bit error rate, execute the step of generating noisy codeword data based on the preset original bit error rate and the noisy module, until each preset original bit error rate is traversed.

[0104] For example, if the decoding result meets the preset jump condition, it indicates that the expected simulation depth has been achieved for the current preset raw bit error rate. Optionally, the next preset raw bit error rate can be determined according to the preset simulation order. Accordingly, based on the next preset raw bit error rate, the step of generating noisy codeword data based on the preset raw bit error rate and the noisy module is executed until each preset raw bit error rate is traversed, that is, the above steps are simulated for each preset raw bit error rate. Optionally, after traversing each preset raw bit error rate, the error correction performance of the decoding parameters in the decoder can be calculated based on the decoder results under each preset raw bit error rate, so as to output the performance evaluation result. For example, the total amount of simulation data (number of simulation frames or number of codewords) and the number of uncorrectable frames or uncorrectable codewords under each preset raw bit error rate are counted to calculate the uncorrectable bit error rate (UBER) under each preset raw bit error rate. The uncorrectable bit rates under each original bit error rate can be used to form or fit a curve characterizing the error correction performance of the decoding parameters in the decoder.

[0105] In this embodiment, the programmable logic chip includes at least one sub-emulation entity, which includes at least one noise-adding module and at least one decoder. The process involves generating noisy codeword data based on a preset raw bit error rate and the noise-adding module; using the decoder to perform error correction decoding on the noisy codeword data generated by the noise-adding module to obtain a decoding result; if the decoding result does not meet a preset jump condition, the process returns to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noise-adding module to obtain a decoding result; if the decoding result meets the preset jump condition, the process continues to the next preset raw bit error rate, executing the step of generating noisy codeword data based on the preset raw bit error rate and the noise-adding module, until all preset raw bit error rates are traversed. In other words, in this embodiment, a programmable logic chip is used for decoding simulation. A sub-emulation entity is set up in the programmable logic chip, and the noise-adding module in the sub-emulation entity generates noisy codeword data according to the raw bit error rate. Then, the decoder decodes the noisy codeword data generated by the noise-adding module to obtain a decoding result. If the decoding result meets the preset jump condition, the decoding simulation can proceed to the next preset raw bit error rate. Otherwise, if the condition is not met, the process continues based on the current preset raw bit error rate, iterating through each raw bit error rate and statistically analyzing the decoding results at each preset raw bit error rate to evaluate the error correction performance of the decoder's decoding parameters. It is understood that this embodiment uses a programmable logic chip to build a simulation pipeline architecture. By trading space for time, it achieves highly parallelized pipeline operations for generating and decoding noisy codeword data, improving decoding throughput and significantly increasing the simulation speed of the noise addition and decoding error correction processes. This shortens the simulation time and, consequently, the data error correction simulation time, breaking through the bottleneck in the development of high-reliability flash memory products.

[0106] In one feasible implementation, after the step of traversing each preset original bit error rate, the method includes steps S51 to S52:

[0107] Step S51: Based on the decoding results under each preset original bit error rate, determine the uncorrectable bit rate corresponding to each preset original bit error rate;

[0108] For example, the number of uncorrectable frames and the total number of simulations at each preset original bit error rate can be statistically analyzed using the decoding results at each preset original bit error rate. Then, the ratio of these two data points can be calculated to obtain the uncorrectable bit error rate of the preset original bit error rate.

[0109] In a feasible implementation, the step of determining the uncorrectable bit rate corresponding to each preset original bit error rate based on each decoding result under each preset original bit error rate includes steps S511 to S512:

[0110] Step S511: For any one of the preset original bit error rates, based on each decoding result under the preset original bit error rate, count the number of uncorrectable frames under the preset original bit error rate and the total number of bits participating in the decoding simulation.

[0111] Step S512: Determine the uncorrectable bit rate of the preset original bit error rate based on the ratio between the number of uncorrectable frames and the total number of bits participating in the decoding simulation.

[0112] It should be noted that since the process of determining the uncorrectable bit rate corresponding to each preset original bit error rate is similar, this embodiment will use one of them as an example for explanation.

[0113] For example, for any one of the preset raw bit error rates, the number of uncorrectable frames and the total number of bits participating in the decoding simulation are calculated based on the decoding results at that preset raw bit error rate.

[0114] For example, the uncorrectable bit rate of the preset original bit error rate can be obtained by calculating the ratio between the number of uncorrectable frames and the total number of bits participating in the decoding simulation. Optionally, the formula for calculating the uncorrectable bit rate can be as follows:

[0115] ;

[0116] In the formula, For uncorrectable frame rates, This represents the total number of bits involved in the decoding simulation.

[0117] Step S52: Determine the variation law of the uncorrectable bit rate with the preset original bit error rate by using the uncorrectable bit rate corresponding to each preset original bit error rate. The variation law characterizes the error correction performance of the decoding parameters in the decoder.

[0118] For example, after determining the uncorrectable bit rate corresponding to each preset raw bit error rate, a series of (RBER, UBER) data points can be obtained. This series of data points allows us to summarize the variation pattern of the uncorrectable bit rate with the preset raw bit error rate. Correspondingly, this variation pattern can characterize the error correction performance of the decoding parameters used in the decoder. Optionally, the variation pattern curve can be obtained through fitting, such as plotting the series of (RBER, UBER) data points obtained from the test on a log-log coordinate graph. A smooth UBER-RBER performance curve is obtained through curve fitting (such as piecewise linear fitting or polynomial fitting). This curve can be used to analyze whether an "error flattening" occurs (the curve becomes flat in the low UBER region).

[0119] In one feasible implementation, the data error correction simulation method further includes step S1:

[0120] Step S1: Initialize decoding simulation information, wherein the decoding simulation information includes at least one of the following: initial preset raw bit error rate, decoding parameters in the decoder, preset jump conditions, random seed group of noise generator, and decoding decision mode.

[0121] For example, in the initial stage of simulation, decoding simulation information is usually initialized first. This initial decoding simulation information can be pre-configured or configured in real-time. Optionally, in this embodiment, an input / output module can also be set in the programmable logic chip. Before simulation, the initial decoding simulation information can be input through the input / output module. Optionally, the decoding simulation information includes at least one of the following: an initial preset raw bit error rate, decoding parameters in the decoder, preset jump conditions, a random seed set of the noise generator, and a decoding decision mode. The initial preset raw bit error rate can be determined through low-data-volume CPU simulation, empirical estimation, multiple trials, etc. The decoding parameters in the decoder are the QC-LDPC code whose performance needs to be verified. The preset jump conditions can be a preset simulation count threshold. The random seed set of the noise generator is the seed for generating random noise in the noise generator of the noise addition module. The decoding decision mode can include hard decision and soft decision; compared to hard decision, the decision result of soft decision can also include the confidence level of the decided bits. After initializing the decoding simulation information, the simulation can officially begin.

[0122] Reference Figure 2 , Figure 2This illustration shows a second flowchart of the data error correction simulation method provided in this application embodiment. Contents identical or similar to those in the above embodiments can be referred to the above description and will not be repeated hereafter. The steps for generating noisy codeword data based on the preset original bit error rate and the noisy module include steps S11 to S13:

[0123] Step S11: Read the target noise data from the random noise pool of the noise-adding module;

[0124] Step S12: Determine the signal-to-noise ratio corresponding to the preset original bit error rate;

[0125] Step S13: When the original correct codeword corresponding to the noisy codeword data is a fixed codeword, generate noisy codeword data based on the target noise data and the signal-to-noise ratio.

[0126] It should be noted that, in this embodiment, to fully utilize the parallel capabilities of the programmable logic chip, a random noise pool, such as a FIFO (First-In, First-Out) queue, is also provided in the noise-adding module.

[0127] For example, the noise-adding module can read target noise data from a random noise pool. Optionally, the target noise data can be read randomly or in a first-in-first-out manner. Different preset raw bit error rates correspond to different signal-to-noise ratios (SNRs), and the SNR corresponding to the preset raw bit error rate can be determined through a pre-set mapping relationship.

[0128] For example, the aforementioned original correct codeword refers to the base codeword used to generate the noisy codeword data. To simplify the simulation process, the original correct codeword can be a fixed codeword. That is, the noisy codeword data is generated each time based on the same original correct codeword. Since the original correct codeword corresponding to the noisy codeword data is a fixed codeword, the noisy codeword data is generated each time based on the same original correct codeword. Therefore, in the actual generation process, to reduce computational complexity, only the target noise data and the signal-to-noise ratio (SNR) need to be considered. Optionally, after reading the target noise data from the random noise pool, the target noise data can be directly mapped to noisy codeword data based on the SNR.

[0129] It is understandable that, in this embodiment, by setting a fixed original correct codeword, the computational complexity in the simulation process can be further simplified, thereby speeding up the simulation.

[0130] In one feasible implementation, the noisy codeword data includes at least the confidence level of each bit in the noisy codeword; the step of generating the noisy codeword data based on the target noise data and the signal-to-noise ratio includes steps S131 to S132:

[0131] Step S131: Determine the noise standard deviation using the signal-to-noise ratio;

[0132] Step S132: Based on the transformation parameters related to the noise standard deviation, the target noise data is converted into the confidence level of the corresponding bit of the target noise data.

[0133] It should be noted that, in soft-decision mode, the noisy codeword data will include the confidence level of each bit in the noisy codeword. Optionally, the noisy codeword data can consist of each noisy bit (potentially erroneous bit) and its corresponding confidence level.

[0134] For example, the noise standard deviation can be determined by the signal-to-noise ratio. Alternatively, it can be calculated using a conversion formula, such as the following conversion formula:

[0135] ;

[0136] In the formula, For signal-to-noise ratio, The standard deviation of noise. It is the square root.

[0137] For example, based on transformation parameters related to the noise standard deviation, the target noise data is converted into the confidence level of the corresponding bit. It should be noted that the target noise data may include multiple noise samples, which can be random numbers, and the number of noise samples corresponds to the length of the original correct codeword (the number of bits in the codeword). For example, one bit in the original correct codeword can correspond to one noise sample. Optionally, the target noise data can be mapped to the confidence level of the corresponding bit using a mapping formula constructed from the transformation parameters related to the noise standard deviation. The mapping formula can be as follows:

[0138] ;

[0139] In the formula, and The transformation parameter is related to the noise standard deviation. For noise samples in the target noise data, Then it is The confidence level of the corresponding bit.

[0140] In one feasible implementation, after determining the signal-to-noise ratio corresponding to the preset original bit error rate, the method further includes steps S141 to S144:

[0141] Step S141: When the original correct codeword corresponding to the noise-added codeword data is a dynamic codeword, for any one of the noise bits to be added in the original correct codeword, the noise bit to be added is modulated to obtain the data signal.

[0142] Step S142: Generate a noise signal based on the noise sample corresponding to the noise bit to be added in the target noise data and the signal-to-noise ratio;

[0143] Step S143: The data signal and the noise signal are fused to obtain the noise-added signal of the bit to be added;

[0144] Step S144: Generate noisy codeword data based on the noise-adding signals of each noise-adding bit in the original correct codeword.

[0145] It should be noted that the original correct codeword corresponding to the noisy codeword data can also be a dynamic codeword, meaning that the original correct codeword used to generate the noisy codeword data is not fixed each time. Since the process of adding noise to the bits in the original correct codeword is roughly the same, this embodiment will use one bit as an example for explanation.

[0146] For example, when the original correct codeword is a dynamic codeword, for any one of the noise bits to be added in the original correct codeword, the noise bit to be added is modulated to obtain the data signal. Optionally, the correct data signal can be generated by BPSK (Binary Phase Shift Keying) modulation (e.g., "0" is mapped to +1, and "1" is mapped to -1).

[0147] For example, a noise signal is generated based on the noise sample corresponding to the bit to be noised in the target noise data and the signal-to-noise ratio. The noise signal can be obtained by multiplying the noise sample by the noise standard deviation σ corresponding to the signal-to-noise ratio. The data signal and the noise signal are then fused and superimposed to obtain the noise-added signal corresponding to the bit to be noised. Optionally, the signal fusion formula can be as follows:

[0148] ;

[0149] In the formula, For adding noise to the signal, For data signals, The standard deviation of noise. This is a noise signal.

[0150] For example, after determining the noise-adding signals of each noise-adding bit in the original correct codeword, hard decision or soft decision is performed on each noise-adding signal to obtain each noise-adding bit, or each noise-adding bit and its corresponding confidence level, which is the aforementioned noise-adding codeword data.

[0151] In one feasible implementation, the noise-adding module further includes a noise generator; the data error correction simulation method further includes steps S110 to S120:

[0152] Step S110: Generate noise samples using a noise generator;

[0153] It should be noted that, in this embodiment, a noise generator can also be included in the noise generation module. Optionally, the noise generator can be a Box-Muller generator. Accordingly, the noise generator can be used to generate noise values ​​that satisfy a preset distribution (which can be a standard Gaussian distribution), thereby obtaining a noise sample.

[0154] In one feasible implementation, the step of generating noise samples by a noise generator includes steps S111 to S112:

[0155] Step S111: Input the random seed group configured for the noise generator into the noise generator, wherein the random seed group configured for the noise generator is different in different sub-simulation entities.

[0156] Step S112: The random seed group is randomly processed by the noise generator to continuously generate pairs of noise samples that meet the preset distribution. The random processing includes segmentation and recombination, function transformation and polar coordinate transformation synthesis.

[0157] For example, during the simulation initialization phase, a random seed group can be configured for the noise generator. Different random seed groups will be configured for different simulation entities to avoid generating the same noise samples in different simulation entities. Optionally, the random seed group can be two 32-bit random numbers. The random seed group is input to the noise generator, which performs random processing on the random seed group to continuously generate paired noise values ​​that satisfy a preset distribution (such as a standard Gaussian distribution). This random processing includes segmentation and recombination, function transformation, and polar coordinate transformation synthesis.

[0158] Reference Figure 3 This is the intended scenario for a noise generator to generate random numbers. As shown in the figure, it takes two 32-bit seeds as input and continuously generates uniform random numbers a(32,0) and b(32,0) using a 32-bit uniform random number generator. Then, it takes the high 16 bits of b and concatenates them with a to form a 48-bit fraction u0(48,48), while taking the low 16 bits of b as a 16-bit fraction u1(16,16), which is sufficient segmentation. u0 is processed by a logarithmic lookup table to calculate e=-2ln(u0), resulting in a 31-bit value e(31,24). u1 is processed by sine / cosine lookup tables to obtain g0(16,15)=sin(2πu1) and g1(16,15)=cos(2πu1) respectively. e is then processed by a square root lookup table to calculate f= The output is a 20-bit f(20,16), which is the function transformation in the above steps. Finally, under the control of the output enable unit, f is multiplied by g0 and g1 respectively to generate two 18-bit normally distributed random numbers x0(18,13) and x1(18,13) in two's complement form, which is the polar coordinate transformation synthesis in the above steps. The random numbers x0 and x1 are the noise values ​​mentioned above. At the same time, the valid signal valid(1,0) indicates that the output is ready.

[0159] Step S120: Add the noise sample to the random noise pool.

[0160] For example, the noise samples generated by the noise generator are then added to a random noise pool. Optionally, the random noise pool can be an asynchronous FIFO.

[0161] Understandably, by building a random noise pool, support is provided for the noise generator to work in parallel throughout the simulation process, thereby making full use of the parallel performance of the programmable logic chip to reduce the simulation time.

[0162] In one feasible implementation, the noise generator in the noise-adding module operates in the fast clock domain, and the decoder operates in the slow clock domain; the data error correction simulation method further includes steps S01 to S02:

[0163] Step S01: Determine the minimum number of generators based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the length of the input codeword of the decoder, and the decoding cycle of the decoder.

[0164] Step S02: Configure the noise generator for the noise addition module to have a noise generator number greater than or equal to the minimum number of generators.

[0165] It should be noted that, in order to reduce the number of noise generators required and considering the computational complexity of both the noise generator and the decoder, in this embodiment, the noise generator is configured to operate in the fast clock domain, and the decoder is configured to operate in the slow clock domain.

[0166] For example, the minimum number of noise generators required is calculated using the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder. Then, a noise generator with a number greater than or less than this minimum number is configured for the noise-generating module. This ensures that the noise bandwidth is greater than or equal to the decoder's maximum bandwidth, preventing the decoder from waiting for input and guaranteeing decoding speed.

[0167] Reference Figure 4The figure shows a schematic diagram of the connection structure of the random noise pool in this embodiment. As shown, noise generation in the fast clock domain (e.g., clk_noise) includes multiple parallel generators (e.g., Box-Muller). Each generator is connected to a "k-beat serial-to-parallel" module to convert serial noise samples into parallel data. Subsequently, the multiple parallel data streams are integrated through a "bit-width merging" module, and then stably transmitted across clock domains via an asynchronous queue (e.g., FIFO, i.e., the aforementioned random noise pool), connecting the fast and slow clock domains. The confidence of the generated noise samples is mapped onto the slow clock domain (e.g., clk_main) to directly obtain the confidence of the corresponding bit. Further, refer to... Figure 5 This is a schematic diagram of a connection scenario for a random noise pool. As shown in the figure, the period of the fast clock domain can be 100MHz, while the period of the slow clock domain can be 20MHz. Generator n can be generator 7. The "k-beat serial-to-parallel conversion" can be "16-string serial-to-parallel conversion". The "confidence mapping" can be achieved using the mapping formula described in the above implementation: The mapping is then completed. For example, in the confidence mapping channel 255, the channel obtains the following mapped confidence level 255: In the formula, The noise level is 255.

[0168] In one feasible implementation, the step of determining the minimum number of generators based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder includes steps S010 to S030:

[0169] Step S010: Calculate the bit throughput of the decoder using the second clock cycle and the input codeword length;

[0170] Step S020: Calculate the noise contribution rate of a single noise generator using the first clock cycle and the decoding cycle.

[0171] Step S030: Determine the minimum number of generators based on the ratio between bit throughput and noise contribution rate.

[0172] For example, the bit throughput of the decoder can be calculated using the second clock cycle and the input codeword length. For instance, the decoder processes one codeword per clk_main cycle (i.e., the second clock cycle mentioned above). Let the clk_main frequency be F_main (Hz) and the codeword length be L (bits). Then the decoder's bit throughput R_decoder is: R_decoder = F_main L (bits per second).

[0173] For example, the noise contribution rate of a single noise generator is calculated based on the first clock cycle and the decoding cycle. The decoding cycle refers to the period during which the noisy codeword data is input into the decoder to obtain the decoding result. For instance, for a single Box-Muller noise generator operating at the clk_noise frequency (i.e., the first clock cycle mentioned above), it generates 2 noise samples per cycle. Let the clk_noise frequency be F_noise (Hz). Then the sample contribution rate of a single generator is R_gen_sample = 2. F_noise (samples / second). Each noise sample corresponds to one bit of noise addition. Considering that the decoder may have a decoding delay of D clk_main cycles, i.e., the aforementioned decoding cycles, the system allows the noise generation module to use this D-cycle time window to accumulate noise for a codeword. Therefore, within the time window T_window = D / F_main seconds, the number of noise samples that a single generator can contribute is N_contribution_per_window = R_gen_sample T_window = (2 F_noise) (D / F_main).

[0174] Step S030: Determine the minimum number of generators based on the ratio between bit throughput and noise contribution rate.

[0175] For example, after determining the bit throughput of the decoder and the noise contribution rate of a single noise generator, the ratio between the bit throughput and the noise contribution rate can be calculated to obtain the minimum number of generators mentioned above.

[0176] Understandably, calculating the minimum number of generators and using them to set the corresponding noise generators can ensure that the noise bandwidth is not lower than the decoder bandwidth, thus guaranteeing simulation speed.

[0177] This application provides a data error correction simulation system, referring to... Figure 6 This is a framework diagram of a data error correction simulation system. The data error correction simulation system is set in a programmable logic chip. In the programmable logic chip, the data error correction simulation system includes at least one sub-simulation entity 10. The sub-simulation entity 10 includes at least one noise-adding module 11 and at least one decoder 12.

[0178] Sub-simulation entity 10 is used for:

[0179] Based on the preset original bit error rate and the noise-adding module 11, noisy codeword data is generated; the decoder 12 is used to perform error correction decoding on the noisy codeword data generated by the noise-adding module 11 to obtain the decoding result.

[0180] If the decoding result does not meet the preset jump condition, return to the step of using decoder 12 to perform error correction decoding on the noisy codeword data generated by noisy module 11 to obtain the decoding result. The noisy codeword data participating in error correction decoding is different each time.

[0181] If the decoding result meets the preset jump condition, the step of generating noisy codeword data based on the preset original bit error rate and the noisy module is executed based on the next preset original bit error rate, until each preset original bit error rate is traversed.

[0182] Optionally, the sub-simulation entity 10 is also used for:

[0183] Read the target noise data from the random noise pool of the noise-adding module;

[0184] Determine the signal-to-noise ratio corresponding to the preset original bit error rate;

[0185] When the original correct codewords corresponding to the noisy codeword data are fixed codewords, noisy codeword data is generated based on the target noise data and the signal-to-noise ratio.

[0186] Optionally, the noisy codeword data includes at least the confidence level of each bit in the noisy codeword; the sub-simulation entity 10 is also used for:

[0187] Determine the noise standard deviation using the signal-to-noise ratio;

[0188] Based on the transformation parameters related to the noise standard deviation, the target noise data is converted into the confidence level of the corresponding bits of the target noise data.

[0189] Optionally, the sub-simulation entity 10 is also used for:

[0190] When the original correct codeword corresponding to the noisy codeword data is a dynamic codeword, for any one of the noise bits to be added in the original correct codeword, the noise bit to be added is modulated to obtain the data signal.

[0191] A noise signal is generated based on the noise samples corresponding to the noise bits to be added in the target noise data and the signal-to-noise ratio.

[0192] The data signal and the noise signal are fused to obtain the noise-added signal of the bits to be added;

[0193] Noise-added codeword data is generated based on the noise-adding signals of each bit to be noise-added in the original correct codeword.

[0194] Optionally, the noise-adding module also includes a noise generator; the sub-simulation entity 10 is also used for:

[0195] Noise samples are generated using a noise generator;

[0196] Add the noise samples to the random noise pool.

[0197] Optionally, the noise generator in the noise-adding module operates in the fast clock domain, and the decoder operates in the slow clock domain; see reference. Figure 7 The data error correction simulation system also includes a parameter configuration module 20, which is used for:

[0198] Determine the minimum number of generators based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the length of the input codeword of the decoder, and the decoding cycle of the decoder.

[0199] Configure the noise generator module with a noise generator number greater than or equal to the minimum number of generators.

[0200] Optionally, the parameter configuration module 20 is also used for:

[0201] The bit throughput of the decoder is calculated using the second clock cycle and the length of the input codeword.

[0202] The noise contribution rate of a single noise generator is calculated using the first clock cycle and the decoding cycle.

[0203] The minimum number of generators is determined based on the ratio between bit throughput and noise contribution rate.

[0204] Optionally, the parameter configuration module 20 is also used for:

[0205] The random seed set configured for the noise generator is input into the noise generator, wherein the random seed set configured for the noise generator is different in different sub-simulation entities;

[0206] The random seed group is randomly processed by a noise generator to continuously generate pairs of noise samples that meet a preset distribution. The random processing includes segmentation and recombination, function transformation, and polar coordinate transformation synthesis.

[0207] Optionally, the sub-simulation entity 10 is also used for:

[0208] Read the target noisy codeword data from the decoder's buffer, wherein the noisy codeword data generated by the noise module is added to the decoder's buffer;

[0209] The decoding result is obtained by performing error correction decoding on the target noisy codeword data based on the decoding parameters in the decoder.

[0210] Optionally, the sub-simulation entity 10 is also used for:

[0211] If the cumulative number of decoding simulations corresponding to the decoding result reaches the preset number of simulations, or if the decoding result contains uncorrectable bits, the decoding result satisfies the preset jump condition.

[0212] If the cumulative number of decoding simulations corresponding to the decoding result has not reached the preset number of simulations, and the decoding result is a successful decoding, the decoding result does not meet the preset jump condition.

[0213] Optionally, parameters Figure 8 The data error correction simulation system also includes a statistics module 30, which is used for:

[0214] Based on the decoding results under each preset original bit error rate, determine the uncorrectable bit rate corresponding to each preset original bit error rate;

[0215] By using the uncorrectable bit rate corresponding to each preset original bit error rate, the variation law of the uncorrectable bit rate with the preset original bit error rate is determined, where the variation law characterizes the error correction performance of the decoding parameters in the decoder.

[0216] Optionally, the statistics module 30 is also used for:

[0217] For any preset original bit error rate among the preset original bit error rates, based on each decoding result under the preset original bit error rate, count the number of uncorrectable frames under the preset original bit error rate, and the total number of bits participating in the decoding simulation.

[0218] The uncorrectable bit rate is determined based on the ratio between the number of uncorrectable frames and the total number of bits participating in the decoding simulation, which sets the preset original bit error rate.

[0219] Optionally, the parameter configuration module 20 is also used for:

[0220] Initialize the decoding simulation information, wherein the decoding simulation information includes at least one of the following: initial preset raw bit error rate, decoding parameters in the decoder, preset jump conditions, random seed group of noise generator, and decoding decision mode.

[0221] The data error correction simulation system provided in this application can solve the technical problem of excessively long simulation time in related simulation schemes. Compared with related technologies, the beneficial effects of the data error correction simulation system provided in this application are the same as those of the data error correction simulation method provided in the above embodiments, and will not be repeated here.

[0222] This application provides an electronic device, which includes: a processor, a memory, and a data error correction simulation program stored in the memory and executable on the processor. When the data error correction simulation program is executed, it implements the steps of the data error correction simulation method as described in the above embodiments.

[0223] The electronic device provided in this application can be a programmable logic chip, or other devices including a programmable logic chip. Furthermore, this electronic device can solve the technical problem of excessively long simulation time in related simulation schemes. Compared with related technologies, the beneficial effects of the electronic device provided in this application are the same as those of the data error correction simulation method provided in the above embodiments, and will not be repeated here.

[0224] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the data error correction simulation method in the above embodiments.

[0225] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0226] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0227] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the memory, cause the memory to:

[0228] Noise-added codeword data is generated based on the preset original bit error rate and the noise-adding module.

[0229] The decoder is used to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result.

[0230] If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result;

[0231] If the decoding result meets the preset jump condition, the step of generating noisy codeword data based on the preset original bit error rate and the noisy module is executed based on the next preset original bit error rate, until each preset original bit error rate is traversed.

[0232] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0233] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0234] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0235] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described data error correction simulation method, thereby solving the technical problem of excessively long simulation time in related simulation schemes. Compared with related technologies, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data error correction simulation method provided in the above embodiments, and will not be elaborated here.

[0236] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data error correction simulation method described above.

[0237] The computer program product provided in this application can solve the technical problem of excessively long simulation time in related simulation schemes. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as those of the data error correction simulation method provided in the above embodiments, and will not be repeated here.

[0238] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A data error correction simulation method, characterized in that, The application is to a programmable logic chip, wherein the programmable logic chip includes at least one sub-emulation entity, and the sub-emulation entity includes at least one noise-adding module and at least one decoder; The data error correction simulation method includes: Based on the preset original bit error rate and the noise-adding module, noise-adding codeword data is generated. The decoder is used to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result. If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, wherein the noisy codeword data participating in the error correction decoding is different each time; If the decoding result satisfies the preset jump condition, the step of generating noisy codeword data based on the preset original bit error rate and the noise module is executed based on the next preset original bit error rate until each preset original bit error rate is traversed. The noise-adding module also includes a noise generator and a random noise pool; The data error correction simulation method further includes: Noise samples are generated using the noise generator; The noise sample is added to the random noise pool; The noise generator in the noise-adding module operates in the fast clock domain, and the decoder operates in the slow clock domain. The data error correction simulation method further includes: The minimum number of generators is determined based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder. Configure the noise generation module with a noise generator number greater than or equal to the minimum number of generators.

2. The data error correction simulation method as described in claim 1, characterized in that, The step of generating noisy codeword data based on the preset original bit error rate and the noisy module includes: Read the target noise data from the random noise pool of the noise-adding module; Determine the signal-to-noise ratio corresponding to the preset original bit error rate; When the original correct codeword corresponding to the noisy codeword data is a fixed codeword, noisy codeword data is generated based on the target noise data and the signal-to-noise ratio.

3. The data error correction simulation method as described in claim 2, characterized in that, The noisy codeword data includes at least the confidence level of each bit in the noisy codeword; The step of generating noisy codeword data based on the target noise data and the signal-to-noise ratio includes: The noise standard deviation is determined by the signal-to-noise ratio. Based on the transformation parameters related to the noise standard deviation, the target noise data is converted into the confidence level of the corresponding bit of the target noise data.

4. The data error correction simulation method as described in claim 2, characterized in that, After the step of determining the signal-to-noise ratio corresponding to the preset original bit error rate, the method further includes: When the original correct codeword corresponding to the noise-added codeword data is a dynamic codeword, for any one of the noise bits to be added in the original correct codeword, the noise bit to be added is modulated to obtain a data signal; A noise signal is generated based on the noise sample corresponding to the noise bit to be added in the target noise data and the signal-to-noise ratio; The data signal and the noise signal are fused to obtain the noise-added signal of the bit to be noise-added; The noise-added codeword data is generated based on the noise-added signals of each bit to be noise-added in the original correct codeword.

5. The data error correction simulation method as described in claim 1, characterized in that, The step of determining the minimum number of generators based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder includes: The bit throughput of the decoder is calculated using the second clock cycle and the length of the input codeword. The noise contribution rate of a single noise generator is calculated using the first clock cycle and the decoding cycle. The minimum number of generators is determined based on the ratio between the bit throughput and the noise contribution rate.

6. The data error correction simulation method as described in claim 1, characterized in that, The step of generating noise samples using the noise generator includes: The random seed set configured for the noise generator is input to the noise generator, wherein the random seed set configured for the noise generator is different in different sub-simulation entities; The noise generator performs random processing on the random seed group to continuously generate pairs of noise samples that meet a preset distribution. The random processing includes segmentation and recombination, function transformation, and polar coordinate transformation synthesis.

7. The data error correction simulation method as described in claim 1, characterized in that, The steps of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result include: The target noisy codeword data is read from the decoder's buffer, wherein the noisy codeword data generated by the noise module is added to the decoder's buffer; The target noisy codeword data is corrected and decoded based on the decoding parameters in the decoder to obtain the decoding result.

8. The data error correction simulation method as described in claim 1, characterized in that, After the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, the method includes: When the cumulative number of decoding simulations corresponding to the decoding result reaches a preset number of simulations, or when the decoding result contains uncorrectable bits, the decoding result satisfies a preset jump condition. If the cumulative number of decoding simulations corresponding to the decoding result has not reached the preset number of simulations, and the decoding result is a successful decoding, then the decoding result does not meet the preset jump condition.

9. The data error correction simulation method as described in claim 1, characterized in that, After the step of traversing each preset raw bit error rate, the method includes: Based on the decoding results under each preset original bit error rate, determine the uncorrectable bit rate corresponding to each preset original bit error rate; By using the uncorrectable bit rate corresponding to each preset original bit error rate, the variation law of the uncorrectable bit rate with the preset original bit error rate is determined, wherein the variation law characterizes the error correction performance of the decoding parameters in the decoder.

10. The data error correction simulation method as described in claim 9, characterized in that, The step of determining the uncorrectable bit rate corresponding to each preset original bit error rate based on each decoding result under each preset original bit error rate includes: For any one of the preset original bit error rates, based on each decoding result under the preset original bit error rate, count the number of uncorrectable frames under the preset original bit error rate and the total number of bits participating in the decoding simulation. The uncorrectable bit rate of the preset original bit error rate is determined based on the ratio between the number of uncorrectable frames and the total number of bits participating in the decoding simulation.

11. The data error correction simulation method as described in claim 1, characterized in that, The data error correction simulation method further includes: Initialize decoding simulation information, wherein the decoding simulation information includes at least one of the following: an initial preset raw bit error rate, decoding parameters in the decoder, a preset jump condition, a random seed group of the noise generator, and a decoding decision mode.

12. A data error correction simulation system, characterized in that, The data error correction simulation system is installed in a programmable logic chip. The data error correction simulation system in the programmable logic chip includes at least one sub-simulation entity, and the sub-simulation entity includes at least one noise-adding module and at least one decoder. The sub-simulation entity is used for: Based on the preset original bit error rate and the noise-adding module, noise-adding codeword data is generated. The decoder is used to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result. If the decoding result does not meet the preset jump condition, return to the step of using the decoder to perform error correction decoding on the noisy codeword data generated by the noisy module to obtain the decoding result, wherein the noisy codeword data participating in the error correction decoding is different each time; If the decoding result meets the preset jump condition, then based on the next preset raw bit error rate, the step of generating noisy codeword data based on the preset raw bit error rate and the noisy module is executed until all preset raw bit error rates are traversed. The noise-adding module also includes a noise generator and a random noise pool; The sub-simulation entity is also used for: Noise samples are generated using the noise generator; The noise sample is added to the random noise pool; The noise generator in the noise-adding module operates in the fast clock domain, and the decoder operates in the slow clock domain. The noise generator in the noise generation module operates in the fast clock domain, and the decoder operates in the slow clock domain; the data error correction simulation system also includes a parameter configuration module, which is used for: The minimum number of generators is determined based on the first clock cycle of the fast clock domain, the second clock cycle of the slow clock domain, the input codeword length of the decoder, and the decoding cycle of the decoder. Configure the noise generation module with a noise generator number greater than or equal to the minimum number of generators.

13. An electronic device, characterized in that, The electronic device includes: a processor, a memory, and a data error correction simulation program stored in the memory and executable on the processor, wherein the data error correction simulation program, when executed, implements the steps of the data error correction simulation method as described in any one of claims 1-12.

14. A computer program product, characterized in that, The computer program product includes a data error correction simulation program, which, when executed by a processor, implements the steps of the data error correction simulation method as described in any one of claims 1-12.

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