Buck converter and operating method thereof

Abstract

The invention provides a buck converter and an operation method thereof. The buck converter includes a power stage, a feedback network, a control loop, a logic circuit, a driver circuit, and a bypass detector. The power stage comprises an input end and an output end. The feedback network is coupled to the power stage for generating a feedback voltage according to the output voltage. The control loop comprises an error amplifier and a comparator. The error amplifier is used for generating an error voltage by comparing a reference voltage with a feedback voltage, and the comparator is coupled to the error amplifier and is used for generating a comparator signal according to the error voltage. The logic circuit is used for generating a logic control signal according to a group of control signals to realize a control scheme. The driving circuit is used for driving the power stage according to the logic control signal. The bypass detector is used for comparing the input voltage with a preset threshold value and correspondingly generating a bypass mode signal.

Description

Technical Field

[0001] This invention relates to power management in electronic systems, particularly voltage regulation circuits and methods, especially buck converters designed for ultra-low power applications. Background Technology

[0002] Buck converters play a crucial role in modern electronic devices, especially in battery-powered systems where efficient voltage regulation is paramount. These converters are tasked with reducing voltage levels while maintaining high efficiency under a wide range of input and output conditions. As the demand for longer battery life and higher power efficiency continues to grow, the pressure to reduce the power consumption of buck converter designs is also increasing.

[0003] Traditional buck converters currently face challenges when the input voltage is close to or below the desired output voltage. To address this limitation, many designs incorporate a bypass mode, also known as a 100% duty cycle mode. This mode allows the converter to maintain regulation even when the input voltage is close to or below the target output voltage, thereby extending the effective operating range of the device.

[0004] In a typical design, a dedicated bypass detector continuously monitors the difference between the input and output voltages. When this difference falls below a preset threshold, bypass mode is activated to keep the high-side power transistor on. This effectively connects the input directly to the output, enabling the converter to operate under conditions where normal buck conversion would be impossible. Bypass mode typically remains enabled until the input-output voltage difference exceeds the preset threshold or until overcurrent protection circuitry is triggered.

[0005] While these existing buck converters with bypass modes offer improved versatility, they still have several significant limitations. One major issue is the high quiescent current consumed by the bypass detectors, which require continuous monitoring of voltage differences. This continuous power consumption poses a problem for low-power devices, especially those that rely on battery power, where even microampere current consumption can impact overall battery life.

[0006] Another limitation lies in the inefficiency of traditional protection mechanisms. Overcurrent protection circuits are crucial for safe operation, but they typically consume a lot of current, a characteristic that directly conflicts with the goal of achieving ultra-low quiescent current in modern designs. Furthermore, many existing designs fail to optimize power consumption during bypass mode operation, missing opportunities to further reduce quiescent current. Moreover, some designs do not transition smoothly enough between normal operation and bypass mode; these irregular transitions can lead to output voltage fluctuations, affecting the stability and reliability of the power supply.

[0007] Given these limitations, improvements to buck converter design are clearly urgently needed. An improved design should minimize quiescent current consumption, especially during bypass mode operation, to extend battery life in portable devices, and should implement more efficient protection mechanisms without compromising low-power operation, ensuring safety without sacrificing efficiency. Furthermore, an ideal design should provide a smooth transition between operating modes, maintaining a stable output voltage under all conditions. Finally, it should maintain high efficiency under a wide range of input and output voltage conditions, enhancing its versatility and applicability.

[0008] Addressing these challenges will result in a buck converter better suited for modern battery-powered devices where energy efficiency is paramount. Improved designs will lead to significant advancements in power management technology and its application in next-generation, long-lasting electronic devices. Summary of the Invention

[0009] An embodiment provides a buck converter including a power stage, a feedback network, a control loop, logic circuitry, a driver circuit, and a bypass detector. The power stage includes an input terminal and an output terminal. The input terminal receives an input voltage, and the output terminal transmits an output voltage. The feedback network is coupled to the power stage and generates a feedback voltage based on the output voltage. The control loop includes an error amplifier and a comparator. The error amplifier generates an error voltage by comparing a reference voltage with the feedback voltage, and the comparator is coupled to the error amplifier to generate a comparator signal based on the error voltage. The logic circuitry is coupled to the control loop and generates logic control signals based on a set of control signals to implement a control scheme. The driver circuitry is coupled between the logic circuitry and the power stage and drives the power stage based on the logic control signals. The bypass detector compares the input voltage with a predetermined threshold and generates a bypass mode signal accordingly, wherein the predetermined threshold is related to the output voltage.

[0010] An embodiment provides a method for operating a buck converter, the steps of which include operating the buck converter in a normal mode, wherein the normal mode includes alternately activating a high-side switch and a low-side switch to regulate the output voltage, monitoring the current in the output inductor of the buck converter by a zero-current detector, generating a bypass enable signal by the zero-current detector, activating a bypass detector according to the bypass enable signal, comparing the input voltage of the buck converter with a first predetermined threshold, the first predetermined threshold being related to the output voltage by the bypass detector, generating a bypass mode signal by the bypass detector when the input voltage drops below the first predetermined threshold, and switching the buck converter from the normal mode to a bypass mode according to the bypass mode signal, wherein the bypass mode includes activating the high-side switch and deactivating the low-side switch. Attached Figure Description

[0011] Figure 1 A schematic diagram depicting an embodiment of a buck converter.

[0012] Figure 2 yes Figure 1 The flowchart shows the operation method of switching the buck converter to bypass mode.

[0013] Figure 3A yes Figure 1 A flowchart of the operation method of the buck converter in bypass mode.

[0014] Figure 3B yes Figure 1 A flowchart of another operating method of the buck converter in bypass mode.

[0015] Figure 4 yes Figure 1 A flowchart of the method for operating a buck converter in sleep mode.

[0016] Figure 5 yes Figure 1 Timing diagram of the buck converter switching from continuous conduction mode to bypass mode.

[0017] Figure 6 yes Figure 1 This is a timing diagram of a buck converter switching from discontinuous conduction mode to bypass mode.

[0018] Figure 7 yes Figure 1 Timing diagram of a buck converter switching from bypass mode back to continuous conduction mode and a high current event occurring.

[0019] Figure 8 yes Figure 1 Timing diagram of a buck converter switching from bypass mode back to continuous conduction mode and an overcurrent event occurring.

[0020] [Symbol Explanation]

[0021] 100: Buck Converter

[0022] 110: Power stage

[0023] 120: Feedback Network

[0024] 130: Control loop

[0025] 140: Logic Circuits

[0026] 150: Drive circuit

[0027] 160: Bypass Detector

[0028] 170: Zero Current Detector

[0029] 180: On-time generator

[0030] 132: Error Amplifier

[0031] 134: Comparator

[0032] 162: Overcurrent Protection Circuit

[0033] 164: High Current Detection Circuit

[0034] VIN: Input voltage

[0035] VOUT: Output voltage

[0036] VFB: Feedback Voltage

[0037] VREF: Reference Voltage

[0038] VEAO: Output voltage of the error amplifier

[0039] VLX: Switching node voltage

[0040] VTH_IN: Input voltage threshold

[0041] VTH_OUT: Output voltage threshold

[0042] IL: Output inductor current

[0043] ILOAD: Load current

[0044] S1: First switch

[0045] S2: Second switch

[0046] LOUT: Output inductance

[0047] COUT: Output capacitor

[0048] SHYS: Hysteresis Switch

[0049] RBYP: Bypass resistor

[0050] RFB1, RFB2: Feedback resistors

[0051] CFF: Feedforward capacitor

[0052] REAO: Resistor

[0053] CEAO: Capacitor

[0054] RLOAD: Load resistance

[0055] dCOMP: Comparator output signal

[0056] LGC: Logic Control Signal

[0057] dBYP_IN: Bypass mode input signal; dBYP_OUT: Bypass mode output signal

[0058] dSLP: Sleep Pattern Signal

[0059] TON: Enable Time Signal

[0060] dOCP: Overcurrent protection signal

[0061] dLCD: High Current Detection Signal

[0062] EN_CMP: Comparator Enable signal; EN_BYP: Bypass Enable signal

[0063] 200, 300A, 300B: Methods S202~S214, S302~S314, S352~S360: Steps Detailed Implementation

[0064] This disclosure provides detailed descriptions of various embodiments. While specific implementation details are presented herein to facilitate a thorough understanding of this disclosure, those skilled in the art will understand that implementation of the invention is not limited to all of these details. In some cases, to avoid unnecessarily obscuring this disclosure, exhaustive descriptions of well-known methods, procedures, elements, and circuits have been omitted herein. As described herein, the technical features described in a single figure may be implemented individually or in combination with other features.

[0065] Figure 1 A schematic diagram of a buck converter 100 according to an embodiment is depicted. The buck converter 100 includes a power stage 110, a feedback network 120 coupled to the power stage 110, a control loop 130, logic circuitry 140, a drive circuitry 150, and a bypass detector 160. Logic circuitry 140 is coupled to the control loop 130, and drive circuitry 150 is coupled between logic circuitry 140 and power stage 110. The buck converter 100 may also include additional components, including a zero-current detector 170 and an on-time generator 180, both coupled to logic circuitry 140.

[0066] Power stage 110 includes an input terminal IN for receiving the input voltage VIN and an output terminal OUT for transmitting the output voltage VOUT. Feedback network 120 generates a feedback voltage VFB based on the output voltage VOUT. Control loop 130 includes an error amplifier 132 and a comparator 134. Error amplifier 132 generates an error voltage VEAO by comparing a reference voltage VREF with the feedback voltage VFB, while comparator 134 generates a comparison signal dCOMP based on the error voltage VEAO.

[0067] Power stage 110 also includes a first switch S1 (high-side switch) and a second switch S2 (low-side switch), which are connected in series and form a half-bridge configuration between the input terminal IN and the ground terminal. The output inductor LOUT can be coupled between the switching node of the first switch S1 and the second switch S2 and the output terminal OUT. The output capacitor COUT can be coupled between the output terminal OUT and the ground terminal. Furthermore, the first switch S1 may include a first terminal coupled to the input terminal IN, a second terminal coupled to the switching node, and a control terminal coupled to the drive circuit 150. Similarly, the second switch S2 may include a first terminal coupled to the switching node, a second terminal coupled to ground, and a control terminal coupled to the drive circuit 150.

[0068] Logic circuit 140 is the core of buck converter 100's operation, generating a logic control signal LGC based on various control signals to implement the control scheme of buck converter 100. Drive circuit 150 drives power stage 110 according to this logic control signal LGC. Additionally, bypass detector 160 provides logic circuit 140 with a control signal dBYP_IN for switching to bypass mode (explained in detail later). Furthermore, zero-current detector 170 generates a sleep mode signal dSLP associated with sleep mode activation, while on-time generator 180 generates a signal TON to control the duration of each switching cycle.

[0069] The bypass detector 160 is a dedicated component used to determine when the buck converter 100 should enter bypass mode, allowing efficient operation when the input voltage VIN is close to the desired output voltage VOUT. The bypass detector 160 compares the input voltage VIN with a reference voltage associated with the output voltage VOUT. When the input voltage VIN drops below a threshold, a bypass mode signal dBYP_IN is generated to initiate the bypass mode transition.

[0070] More specifically, the bypass detector 160 functions to monitor the relationship between the input voltage VIN and a reference voltage. The reference voltage VREF can be the actual output voltage of the buck converter or a predetermined threshold voltage. The bypass detector 160 continuously compares these voltages, and when the input voltage is equal to or lower than the reference voltage, it can trigger the buck converter 100 to switch to bypass mode by generating a bypass mode signal dBYP_IN. This mechanism allows the buck converter 100 to adapt to changing input conditions as the input voltage VIN approaches or drops below the desired output voltage VOUT.

[0071] The zero-current detector 170 is used to identify when the output current IL (flowing through the output inductor LOUT) reaches zero. When the output current IL is substantially zero, the zero-current detector 170 generates a sleep mode signal dSLP, indicating the zero-current condition.

[0072] The on-time generator 180 continuously monitors the input voltage VIN and the output voltage VOUT, and calculates the on-time of the first switch S1 required to maintain the desired output voltage. This calculation typically involves the following equation:

[0073] Ton = (VOUT × Ts) / VIN

[0074] Where Ts is the switching period.

[0075] Furthermore, the on-time generator 180 can dynamically adjust the on-time according to changes in the input voltage VIN or load conditions to maintain a constant output voltage VOUT.

[0076] In addition, the logic circuit 140 integrates the inputs of multiple protection mechanisms, receives the current protection signal dOCP from the overcurrent protection circuit 162, and this overcurrent protection circuit can be controlled by the high current signal dLCD sent by the high current detection circuit 164.

[0077] The overcurrent protection circuit 162 is a critical safety protection component that prevents circuit damage caused by excessive current draw. The overcurrent protection circuit 162 monitors the output current of the buck converter, typically using a sensing resistor or power transistor. The overcurrent protection circuit 162 compares the sensed current to a predetermined overcurrent threshold. If the threshold is exceeded, the overcurrent protection circuit 162 activates protective measures, such as shutting down the first switch S1 or switching the buck converter 100 to normal operating mode (i.e., alternately activating the first switch S1 and the second switch S2 to regulate the output voltage VOUT). It is worth noting that the overcurrent protection circuit 162 can be designed to be deactivated during bypass mode operation to save power and can be reactivated when the high current detection circuit 164 is enabled.

[0078] The high-current detection circuit 164 is a component designed to monitor potentially high currents during bypass mode operation while maintaining ultra-low quiescent current consumption. The high-current detection circuit 164 remains enabled in bypass mode, during which the overcurrent protection circuit 162 is disabled to save power. The high-current detection circuit 164 monitors the voltage difference between the input voltage VIN and the switching node voltage VLX. This voltage difference is proportional to the current flowing through the first switch S1. The measured voltage difference is compared to a preset threshold. This threshold is set to detect high-current events, where the current increases significantly but does not yet reach a level that triggers full overcurrent protection. When the voltage difference exceeds the threshold, the high-current detection circuit 164 generates a high-current signal dLCD to the overcurrent protection circuit 162.

[0079] Feedback network 120 includes a hysteresis switch SHYS and a bypass resistor RBYP, both coupled to the output terminal OUT. Additionally, a resistor divider in feedback network 120 can be coupled between the bypass resistor RBYP and ground. Feedback network 120 also includes a feedforward capacitor CFF, coupled to the output terminal OUT, the resistor divider, and the error amplifier 132. The resistor divider may include two resistors RFB1 and RFB2 connected in series. The feedback voltage VFB is sensed at the junction of these two resistors RFB1 and RFB2.

[0080] The control loop 130 includes additional components to enhance its functionality and implement the control scheme. An RC (Resistor-Capacitor) circuit can be coupled between the error amplifier 132 and ground to provide the necessary compensation and stability, and the RC circuit can consist of a resistor REAO and a capacitor CEAO coupled in series.

[0081] Error amplifier 132 may have a non-inverting input that receives reference voltage VREF, an inverting input coupled to feedback network 120, a first output that outputs voltage EA VEAO, and a second output that is coupled to logic circuit 140.

[0082] Comparator 134 has a non-inverting input connected to the first output of error amplifier 132, an inverting input receiving the voltage VRAMP, an output coupled to logic circuit 140, and a signal input coupled to logic circuit 140. Comparator 134 can generate a comparison signal dCOMP, while allowing logic circuit 140 to control its power state. It should be noted that the signal EN_CMP is used to control the enable state of comparator 134.

[0083] The load RLOAD represents the electrical load connected to the output terminal OUT of the buck converter 100. The load current ILOAD is drawn, and the magnitude of the load current ILOAD is a key parameter in the control scheme that determines the operating mode of the buck converter 100.

[0084] Figure 2 This is a flowchart of an operation method 200 for switching the buck converter 100 to bypass mode. Bypass mode, also known as 100% duty cycle mode, is an operating state of the buck converter in this embodiment, used to handle situations where the input voltage VIN is close to or lower than the desired output voltage VOUT. This mode extends the converter's operating range and improves efficiency under these specific conditions. Method 200 includes the following steps:

[0085] S202: Operating buck converter 100 in normal mode;

[0086] S206: Generate bypass enable signal EN_BYP;

[0087] S208: Enable bypass detector 160;

[0088] S210: The bypass detector 160 of the buck converter compares the input voltage VIN with a predetermined threshold related to the output voltage VOUT;

[0089] S211: Has the input voltage dropped below a predetermined threshold? If yes, proceed to S212; if no, return to S210.

[0090] S212: Generates the bypass mode signal dBYP_IN;

[0091] S214: Switch the buck converter 100 from normal mode to bypass mode.

[0092] In bypass mode, bypass detector 160, overcurrent protection circuit 162, and comparator 134 can be disabled to reduce power consumption. However, high current detection circuit 164 can be enabled to perform the aforementioned detection function. Furthermore, in bypass mode, first switch S1 is enabled, while second switch S2 and hysteresis switch SHYS are disabled.

[0093] Figure 3A This is a flowchart of method 300A for operating the buck converter 100 in bypass mode. Method 300A includes the following steps:

[0094] S302: When operating in bypass mode, disable the overcurrent protection circuit 162 and enable the high current detection circuit 164.

[0095] S304: High current detection circuit 164 monitors the voltage difference between the input voltage VIN and the switching node voltage VLX;

[0096] S306: Does the voltage difference exceed the predetermined threshold? If yes, proceed to S308; if no, return to S304.

[0097] S308: The high current detection circuit 164 generates a high current signal dLCD to enable the overcurrent protection circuit 162.

[0098] S310: Overcurrent protection circuit 162 compares the output current IL with the overcurrent threshold.

[0099] S312: Does the output current IL exceed the overcurrent threshold? If yes, proceed to S314; if no, proceed to S313.

[0100] S313: Disable overcurrent protection circuit 162; Return to S304;

[0101] S314: Switches the buck converter 100 from bypass mode to normal mode.

[0102] During bypass mode operation, the buck converter 100 uses a high-current sensing mechanism, rather than traditional overcurrent protection, to monitor changes in output current. This significantly reduces power consumption while maintaining basic protection functions.

[0103] The high-current detection circuit 164 operates by continuously monitoring the voltage difference between the input voltage VIN and the switching node voltage VLX. The switching node is the connection point between the first switch S1 and the second switch S2. This voltage difference is proportional to the output current and follows the relationship:

[0104] VIN-VLX=IL×RS1

[0105] RS1 is the on-resistance of the first switch S1.

[0106] The high-current detection circuit 164 compares this voltage difference with a preset threshold. If the difference exceeds this threshold, it indicates that a high-current event is occurring, which may be caused by a sudden increase in load demand or a potential fault.

[0107] Upon detecting a high-current event, the circuit triggers a wake-up signal to activate the full overcurrent protection system. This phased approach allows the converter to maintain ultra-low quiescent current during bypass mode operation while still providing robust protection when needed. This high-current sensing mechanism demonstrates the design efficiency of the buck converter in balancing ultra-low power consumption with comprehensive protection features.

[0108] Figure 3B This is a flowchart of method 300B for operating the buck converter 100 in bypass mode. Method 300B includes the following steps:

[0109] S352: When operating in bypass mode, disable the overcurrent protection circuit 162 and enable the high current detection circuit 164.

[0110] S354: Monitors output voltage VOUT and reference voltage VREF;

[0111] S356: Does the output voltage VOUT exceed the reference voltage VREF? If yes, proceed to S358; if no, return to S354.

[0112] S358: Enable bypass exit signal dBYP_OUT;

[0113] S360: Switches the buck converter 100 from bypass mode to normal mode.

[0114] The steps described above illustrate an alternative process for managing bypass mode operation and exiting, allowing for smooth transitions between modes and enhancing overall system stability. Furthermore, continuous monitoring and conditional exit ensure the converter operates in the most suitable mode under current conditions. Therefore, this approach effectively balances the power efficiency requirements of bypass mode with the requirements of appropriate voltage regulation and protection, making it suitable for battery-powered devices.

[0115] Figure 4 This is a flowchart of a method 400 for operating a buck converter 100 in sleep mode. Method 400 includes the following steps:

[0116] S402: When operating in sleep mode, disable the overcurrent protection circuit 162, bypass detector 160 and comparator 134;

[0117] S404: The error amplifier 132 compares the feedback voltage VFB with the reference voltage VREF;

[0118] S406: Is the feedback voltage VFB lower than the reference voltage VREF? If yes, proceed to S408; if no, return to S404.

[0119] S408: Is the sleep mode signal low? If yes, proceed to S410; if no, return to S404.

[0120] S410: Switches the buck converter 100 from sleep mode to normal mode.

[0121] The buck converter 100 primarily operates in two modes: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In continuous conduction mode, the output current IL typically does not drop to zero during the switching cycle; this mode is suitable for medium to heavy load applications. The inductor current waveform in continuous conduction mode resembles a triangular wave with DC bias and oscillates above zero. Continuous conduction mode offers several advantages, including lower peak current, reduced conduction losses and electromagnetic interference, and better voltage regulation and faster transient response due to the continuously stored energy in the inductor. However, continuous conduction mode can result in higher switching losses at light loads due to the continuous switching of the power transistors.

[0122] Discontinuous conduction mode presents a different scenario. In this mode, the inductor current drops to zero for a period during each switching cycle. This typically occurs in two situations: when the load is light and when the converter design uses a relatively small inductor. In discontinuous conduction mode, the inductor current exhibits a unique waveform characteristic. In each cycle, the current rises rapidly from zero, reaches a peak, and then quickly drops back to zero. Subsequently, the current remains at zero for a period before the start of a new cycle. This mode forms a series of intermittent triangular pulses, each separated by a period of zero current, often referred to as a sleep mode. Discontinuous conduction mode can improve efficiency at light loads by reducing switching losses because the low-side transistor can turn on at zero current, reducing turn-on losses and allowing the use of a smaller inductor, which is beneficial for miniaturization. However, compared to continuous conduction mode, discontinuous conduction mode generally results in higher peak current and larger output voltage ripple.

[0123] The switching between continuous and discontinuous conduction modes in a buck converter is a dynamic process, primarily influenced by load current, input voltage, and the converter's design parameters. Buck converters, especially ultra-low quiescent current buck converters like those in this embodiment, typically employ complex control strategies to ensure a smooth transition between these two modes, maintaining optimal efficiency under varying operating conditions. The zero-current detector 170 plays a crucial role in this process. It accurately identifies the transition point between continuous and discontinuous conduction modes, allowing the controller to flexibly adjust the switching strategy. Specifically, under light loads, the converter tends to operate in discontinuous conduction mode to improve energy efficiency; while under heavier loads, it switches to continuous conduction mode for more precise voltage regulation and reduced conduction losses. Furthermore, this embodiment introduces a bypass mode specifically for handling extremely light loads or situations where the input voltage is close to the output voltage. This multi-mode adaptive approach enables the buck converter to maintain high efficiency throughout its entire operating range. This design is particularly suitable for battery-powered devices. In such applications, every bit of power is critical, and the converter's high efficiency maximizes battery life.

[0124] Figure 5 This is a timing diagram of the buck converter 100 switching from continuous conduction mode to bypass mode. Between times t0 and t1, the buck converter 100 operates in continuous conduction mode. The input voltage VIN is higher than the output voltage VOUT but begins to decrease. The feedback voltage VFB oscillates around the reference voltage VREF, indicating normal regulation. The error amplifier 132, comparator 134, bypass detector 170, and overcurrent protection circuit 162 are all enabled. The high current detection circuit 164 is disabled.

[0125] At time t1, the input voltage VIN drops to the voltage threshold VTH_IN, which initiates the transition to bypass mode. The bypass mode signal dBYP_IN goes high, causing the buck converter 100 to enter bypass mode. The bypass detector 170, comparator 134, and overcurrent protection circuit 162 are disabled to reduce power consumption. The high current detection circuit 164 is enabled to perform its function.

[0126] During the time interval t1 to t2, the buck converter 100 operates in bypass mode. At this time, the output voltage VOUT decreases synchronously with the input voltage VIN. Because the hysteresis switch SHYS is closed, the feedback voltage VFB drops below the reference voltage VREF, resulting in a hysteresis effect. In this mode, precise voltage regulation is temporarily suspended, but the error amplifier 132 continuously monitors the output voltage VOUT.

[0127] When time reaches t2, the input voltage VIN bottoms out and rebounds, beginning an upward trend. Simultaneously, the load current ILOAD also increases. Between t2 and t3, the input voltage VIN continues to rise, while other signal parameters remain stable.

[0128] At time t3, the output voltage VOUT reaches the preset threshold VTH_OUT, triggering the buck converter 100 to exit bypass mode. The error amplifier 132 generates a pulse signal dBYP_OUT, marking the end of bypass mode. At this time, the buck converter 100 restarts the bypass detector 170, comparator 134, and overcurrent protection circuit 162, while disabling the high-current detection circuit 164 that previously operated in bypass mode. This series of coordinated actions prepares the buck converter 100 to resume continuous conduction mode operation. After time t3, the converter fully returns to continuous conduction mode and resumes normal switching operation.

[0129] The buck converter 100 utilizes an error amplifier 132 as the core component for exiting bypass mode. In bypass mode, the output voltage VOUT closely follows the input voltage, and the first switch S1 is effectively connected directly to the input IN and the output OUT. Throughout the process, the error amplifier 132 continuously compares the feedback voltage VFB with the reference voltage VREF.

[0130] The reference voltage VREF represents the ideal output voltage or a preset threshold. The error amplifier 132 accurately calculates the difference between the actual output and the reference voltage, continuously monitoring whether the system has reached the conditions for resuming normal operation.

[0131] In certain situations, when the error amplifier 132 detects that the output voltage VOUT is equal to or exceeds the reference voltage VREF, it triggers bypass mode exit. This typically occurs when the input voltage VIN is sufficient for normal buck operation. Once the appropriate voltage relationship is detected, the error amplifier 132 generates the signal dBYP_OUT, initiating the process of switching back from bypass mode to normal mode. This design ensures that the system can flexibly respond to different voltage conditions, maintaining high efficiency while timely resuming normal buck functionality.

[0132] The disclosed procedure offers several advantages. First, it achieves smooth switching using the error amplifier 132 (the core component of the control loop), allowing for a seamless return to normal operation without the introduction of additional switches or potential instabilities. By using the reference voltage VREF, the procedure precisely controls when the converter exits bypass mode, ensuring optimal output voltage regulation. This design also provides significant flexibility, allowing designers to adjust the reference voltage VREF to fine-tune the bypass mode exit point for different applications or operating conditions. In terms of energy efficiency, the procedure maintains ultra-low quiescent current characteristics by eliminating the need for additional high-power components during bypass mode. Finally, the procedure introduces an adaptive operating mechanism, enabling the system to dynamically respond to input voltage changes and smoothly switch between different modes to maintain optimal efficiency and regulation performance.

[0133] Figure 6 This is a timing diagram of the buck converter 100 switching from discontinuous conduction mode to bypass mode. During the initial time period t0 to t1, the buck converter 100 operates in discontinuous conduction mode. During this time, although the input voltage VIN shows a decreasing trend, it remains higher than the output voltage VOUT, while the feedback voltage VFB oscillates continuously around the reference voltage VREF. The operating mode of the buck converter 100 affects the operating state of various components. In normal mode, the error amplifier 132, comparator 134, bypass detector 170, and overcurrent protection circuit 162 are all enabled, comprehensively monitoring and regulating system operation. However, when the converter enters sleep mode, to optimize power consumption, all of the above components except for the error amplifier 132 are disabled. Simultaneously, the high current detection circuit 164 is enabled to handle potential high current situations and ensure system safety.

[0134] At time t1, the input voltage VIN drops to the voltage threshold VTH_IN, triggering the bypass mode switching mechanism. At this time, the buck converter 100 is in sleep mode. In order to enter bypass mode, the converter needs to wake up from sleep mode first.

[0135] During the time interval from t1 to t2, the buck converter 100 begins its wake-up process. Comparator 134, bypass detector 160, and overcurrent protection circuit 162 are activated successively, indicating that the buck converter 100 is exiting sleep mode. Simultaneously, the input voltage VIN continuously decreases, gradually approaching the level of the output voltage VOUT.

[0136] At time t2, the bypass mode signal dBYP_IN goes high, at which point the buck converter 100 officially enters bypass mode. Subsequently, the comparator 134, bypass detector 160, and overcurrent protection circuit 162 are deactivated to save energy, while the high current detection circuit 164 is activated to monitor for possible high current situations.

[0137] Between time t2 and t3, the buck converter 100 remains in bypass mode. The input voltage VIN reaches its lowest point and begins to rise, the output voltage VOUT follows the input voltage VIN, and the high current detection circuit 164 is enabled, performing current monitoring in bypass mode.

[0138] When time t3 is reached, the output voltage VOUT rises to the threshold voltage VTH_OUT, causing the buck converter 100 to exit bypass mode. At this time, the error amplifier 132 generates a pulse signal dBYP_OUT to end the bypass mode. Subsequently, the system restarts the bypass detector 170, comparator 134, and overcurrent protection circuit 162. Simultaneously, the high current detection circuit 164 is turned off. This series of reconfiguration actions prepares the buck converter 100 to re-enter discontinuous conduction mode. After time t3, the buck converter 100 returns to discontinuous conduction mode.

[0139] Figure 7 This is a timing diagram of the buck converter 100 switching from bypass mode back to continuous conduction mode and the occurrence of a high-current event. Between time t0 and t1, the buck converter 100 operates in continuous conduction mode. During this time, although the input voltage VIN is higher than the output voltage VOUT, it shows a decreasing trend. The feedback voltage VFB oscillates around the reference voltage VREF, indicating that the system is in normal regulation. The error amplifier 132, comparator 134, bypass detector 170, and overcurrent protection circuit 162 are all active, while the high-current detection circuit 164 is deactivated.

[0140] At time t1, when the input voltage VIN drops to the voltage threshold VTH_IN, the system begins to switch to bypass mode. The bypass mode signal dBYP_IN rises, causing the buck converter 100 to enter bypass mode. To save power, the bypass detector 170, comparator 134, and overcurrent protection circuit 162 are all disabled, while the high current detection circuit 164 is enabled.

[0141] Between time t1 and t2, buck converter 100 operates in bypass mode. The output voltage VOUT follows the continuously decreasing input voltage VIN. Due to the hysteresis effect caused by the hysteresis switch SHYS being turned off, the feedback voltage VFB drops below the reference voltage VREF. At this point, precise voltage regulation is no longer maintained, but error amplifier 132 continues to monitor the output voltage VOUT.

[0142] At time t2, the input voltage VIN reaches its lowest point and begins to rise, while a high current event occurs, with the load current ILOAD exceeding the high current threshold. This causes the high current detector 164 to trigger the high current signal dLCD, thereby activating the overcurrent protection circuit 162.

[0143] Between time t2 and t3, despite the occurrence of a high-current event, the buck converter 100 remains in bypass mode because the load current ILOAD has not yet reached the overcurrent protection threshold. The output voltage VOUT continues to closely follow the input voltage VIN. The high-current detection circuit 164 and the overcurrent protection circuit 162 remain enabled, continuously monitoring the operation in bypass mode.

[0144] At time t3, when the output voltage VOUT rises to the voltage threshold VTH_OUT, the system begins to exit bypass mode. Error amplifier 132 generates a pulse signal dBYP_OUT to end the bypass mode. The system re-enables bypass detector 170, comparator 134, and overcurrent protection circuit 162, while disabling high current detection circuit 164. After this reconfiguration, buck converter 100 can fully recover to continuous conduction mode operation.

[0145] Figure 8 This is a timing diagram of the buck converter 100 switching from bypass mode back to continuous conduction mode and the occurrence of an overcurrent event. Between time t0 and t1, the buck converter 100 operates in continuous conduction mode. At this time, although the input voltage VIN is higher than the output voltage VOUT, it begins to show a decreasing trend. The feedback voltage VFB oscillates around the reference voltage VREF, indicating that the system is in normal regulation. During this stage, the error amplifier 132, comparator 134, bypass detector 170, and overcurrent protection circuit 162 are all active, while the high current detection circuit 164 is deactivated.

[0146] At time t1, when the input voltage VIN drops to the voltage threshold VTH_IN, the system begins to switch to bypass mode. The bypass mode signal dBYP_IN goes high, triggering the buck converter 100 to enter bypass mode. To reduce power consumption, the bypass detector 170, comparator 134, and overcurrent protection circuit 162 are disabled. Simultaneously, the high current detection circuit 164 is enabled to perform its monitoring function.

[0147] Between time t1 and t2, buck converter 100 is in full bypass mode. The output voltage VOUT closely follows the input voltage VIN, both continuing to decrease. Due to the hysteresis effect caused by the hysteresis switch SHYS being turned off, the feedback voltage VFB drops below the reference voltage VREF. At this point, the system no longer maintains precise voltage regulation. However, error amplifier 132 remains on, continuously monitoring the output voltage VOUT.

[0148] At time t2, the input voltage VIN reaches its minimum value and begins to rise. Simultaneously, the system experiences an overcurrent event; the load current ILOAD suddenly rises above the overcurrent protection threshold, causing the high-current detector 164 to trigger the high-current signal dLCD, thereby activating the overcurrent protection circuit 162. This event signifies the beginning of the system's transition from bypass mode back to continuous conduction mode.

[0149] At time t3, the load current ILOAD exceeds the overcurrent protection threshold, triggering the overcurrent protection circuit 162. The bypass detector 160 deactivates the bypass mode signal dBYP_IN, indicating that the buck converter 100 begins to transition from bypass mode back to normal operation mode. The bypass detector 170, comparator 134, and overcurrent protection circuit 162 are reactivated, while the high current detection circuit 164 is deactivated. After time t3, the buck converter 100 fully recovers to continuous conduction mode. It is noteworthy that in this specific case, the pulse signal dBYP_OUT, which normally indicates the end of bypass mode, may not be generated. This is because exiting bypass mode is directly triggered by the overcurrent protection mechanism, rather than through a standard bypass mode exit procedure. This unconventional exit method highlights the system's flexibility and rapid response to abnormal situations. This transition process demonstrates the buck converter 100's high adaptability in maintaining system safety and stability. By rapidly responding to overcurrent events and smoothly switching back to normal operation mode, the system ensures continuous and effective operation while avoiding potential damage risks.

[0150] The core advantage of the buck converter design disclosed herein lies in its superior low-power performance. By cleverly selectively disabling specific components (such as the on-time generator 180, comparator 134, and overcurrent protection circuit 162) in bypass mode, this design achieves a significant reduction in power consumption. This characteristic is crucial for extending the battery life of portable devices, where standby power consumption is often a decisive factor. Compared to conventional buck converters, the ultra-low quiescent current characteristic described herein exhibits superior performance advantages in microampere current applications.

[0151] Another key advantage of this design is its ability to maintain efficient operation over a wider input voltage range. Its advanced bypass mode implementation enables smooth transitions between Continuous On-Mode (CCM), Discontinuous On-Mode (DCM), Sleep Mode, and Bypass Mode. This flexibility allows the buck converter to handle input voltages close to or even below the target output voltage, extending battery life and improving overall system reliability in environments with varying power supply conditions. This ability to adapt to a wide input voltage range makes the buck converter suitable for battery-powered devices that need to maintain efficient operation even as battery voltage gradually decreases.

[0152] This buck converter design also integrates sophisticated protection mechanisms, maintaining high power efficiency while ensuring safety. Among these, a high-current sensing circuit provides a low-power method to monitor potential problems in bypass mode, while retaining the ability to quickly activate comprehensive overcurrent protection when necessary, effectively preventing various fault conditions. This method ensures safe system operation without sacrificing ultra-low quiescent current performance. Furthermore, the design achieves smooth transitions between various operating modes, minimizing output voltage fluctuations and ensuring the stability of the load power supply. Introducing hysteresis during mode transitions further enhances system stability and efficiency, effectively avoiding frequent mode switching.

[0153] By dynamically adjusting the operating mode based on input voltage and load conditions, the buck converter disclosed herein maintains high efficiency under various operating conditions. This adaptability is particularly suitable for applications with variable load demands, ensuring optimal energy utilization whether the device is operating at full power or in standby mode. The combination of ultra-low quiescent current, a wide input voltage range, and optimized efficiency directly translates to longer battery life for portable electronic devices. This not only significantly improves the user experience but also reduces the frequency of charging or battery replacement, a core requirement in the design of modern mobile and IoT devices.

[0154] Finally, the superior input / output adaptability of the buck converter disclosed herein simplifies overall system design. It reduces reliance on additional voltage regulation stages or complex power management schemes, thereby effectively reducing system cost and complexity. This not only enables a more optimized design and a more streamlined component configuration but also significantly improves the overall reliability of the final product. These advantages make the buck converter design of this disclosure suitable for modern battery-powered devices, IoT applications, and any system where power efficiency, adaptability, and long-term operating capability are primary considerations.

[0155] In this specification and claims, the terminology used is for the purpose of describing specific embodiments of the invention only and should not be construed as limiting the scope of the invention. Unless the context clearly indicates otherwise, the singular forms "a," "the," etc., used in this specification and claims should be understood to include their plural forms as well.

[0156] As used herein, the term “and / or” should be interpreted as encompassing any single item or any combination of the listed items. Specifically, when expressions such as “A and / or B” are used, they should be understood to include: (1) only A; (2) only B; and (3) both A and B.

[0157] Furthermore, when the terms "comprising," "including," or "having" are used herein, they should be understood as indicating the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. In other words, these terms should be interpreted as introducing an open-ended enumeration, not a closed-ended enumeration.

[0158] In this document, the terms “coupled,” “connected,” and “electrically connected” are used interchangeably and should be broadly understood to indicate the state of electrical and / or electronic connection. These terms should not be interpreted restrictively but should include all forms of electrical or electronic connection. Furthermore, the term “communication” as used in this invention should be understood as a broad concept. Specifically, when describing “communication” between a first entity and a second entity, this means that the first entity is sending and / or receiving signals to and / or from the second entity electrically (via wired or wireless media). These signals may include, but are not limited to, voice information, image information, control information, or any combination thereof. It is worth noting that the above definition of “communication” is not limited by signal type and can apply to both analog and digital signals. In other words, as long as there is transmission or reception of electrical messages, regardless of their specific form, it should be considered within the scope of “communication” as described in this invention.

[0159] The illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithm steps described in the various embodiments of the present invention can be implemented by electronic hardware, firmware, software, or any combination thereof. The functional interchangeability of hardware, firmware, and software has been generally described in the various illustrative elements, modules, and circuits described above. The choice of a specific implementation will depend on the constraints of the particular application and the overall system design.

[0160] The hardware and data processing apparatus used to implement the various illustrative elements, logic, logic blocks, modules, and circuits described herein may include, but are not limited to: general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware elements, or any combination thereof. This hardware and apparatus shall be configured to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration. In some embodiments, specific functions may be performed by dedicated circuitry to optimize performance.

[0161] As previously described, certain aspects of the present invention can be implemented in software. For example, the various functions of the elements, or the various blocks or steps of the methods, operations, programs, or algorithms, can be implemented as non-transitory processor-executable instructions or computer-executable instructions in one or more computer program modules. These instructions can be encoded on one or more processor-readable or computer-readable storage media for execution by or control of the operation of a data processing apparatus (including the apparatus elements described herein). The aforementioned storage media may include, but are not limited to: random-access memory (RAM), read-only memory (ROM), electrically-erasable programmable read-only memory (EEPROM), hard disk storage, optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other medium capable of storing program code in the form of instructions or data structures. Any combination of these storage media should also be considered within the scope of protection of the present invention.

[0162] In the description of the embodiments, the various illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithm steps can be implemented using electronic hardware, firmware, software, or a combination thereof. The functional interchangeability of hardware, firmware, and software has been generally illustrated in the various illustrative elements, modules, circuits, and steps described above. Whether such functionality is implemented via hardware, firmware, or software depends on the specific application and the constraints of the overall system design.

[0163] Some embodiments may include additional features not specifically described herein, while other embodiments may not include undisclosed elements. In other words, undisclosed elements may be selectively omitted. It should be emphasized that the omission of undisclosed elements should be considered as one possible implementation of the invention, rather than a limitation. This allows the invention to be adapted to different application scenarios and technical requirements.

[0164] Although the various features described in this invention may be described within the context of a single embodiment, it should be understood that these features can be combined or separated in various ways to constitute different implementations. Features described in a single embodiment may be integrated into a comprehensive embodiment, implemented separately in multiple independent embodiments, or implemented in any suitable sub-combination. Therefore, the scope of the claims of this invention may include combinations of all features, sub-combinations after removing one or more features, and variations or modifications of these sub-combinations. This flexible structure is intended to provide comprehensive protection and allow for technological development, enabling the invention to adapt to different application needs and technical conditions. The scope of protection of this invention should include, but is not limited to, the explicitly described embodiments, but should also cover all variations, modifications, and sub-combinations consistent with the basic principles of this invention.

[0165] The order of operations described in the various embodiments of the present invention, as illustrated in the accompanying drawings, should not be construed as a restrictive order of execution. The order of these operations can be adjusted according to specific implementations to achieve the desired result without performing all illustrated operations. The scope of the invention also includes inserting additional operations (not illustrated) between the illustrated operations. For example, one or more additional operations may be performed before, after, or simultaneously with any illustrated operation.

[0166] In some implementations, multiplexing or parallel processing techniques may be employed to improve efficiency. Furthermore, the separation of the various system components described in this specification should not be construed as requiring such a division in all implementations. Instead, the described program components and systems may be integrated into a single software suite or multiple software suites depending on specific needs.

[0167] It should be specifically noted that the various schematic diagrams (including but not limited to component diagrams) discussed herein are provided for illustrative purposes only and are not drawn to scale. These diagrams are intended to aid in understanding various aspects of the invention and should not be construed as limiting the scope of the invention.

[0168] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A buck converter, comprising: Power stage, including: The input terminal is used to receive the input voltage; and The output terminal is used to output the output voltage; A feedback network, coupled to the power stage, is used to generate a feedback voltage based on the output voltage; The control loop includes: An error amplifier is used to generate an error voltage by comparing a reference voltage with the feedback voltage; and A comparator, coupled to the error amplifier, is used to generate a comparator signal based on the error voltage; A logic circuit, coupled to the control loop, is used to generate logic control signals based on a set of control signals to implement the control scheme. A driving circuit, coupled between the logic circuit and the power stage, is used to drive the power stage according to the logic control signal; and A bypass detector is used to compare the input voltage with a predetermined threshold and generate a bypass mode signal accordingly, wherein the predetermined threshold is related to the output voltage.

2. The buck converter as described in claim 1, further comprising: An on-time generator, coupled to the logic circuit, is used to generate the first control signal in the group of control signals; as well as A zero-current detector, coupled to the logic circuit, is used to generate a second control signal and a bypass enable signal from the set of control signals and send them to the bypass detector.

3. The buck converter as described in claim 2, further comprising: The overcurrent protection circuit is used to generate the overcurrent protection signal in this set of control signals; as well as A high-current detection circuit is used to detect the output current.

4. The buck converter of claim 1, wherein the power stage further comprises: A first switch and a second switch are connected in series to form a half-bridge configuration between the input terminal and the ground terminal; The output inductor is coupled between the switching nodes of the first switch and the second switch and the output terminal; as well as The output capacitor is coupled between the output terminal and the ground terminal.

5. The buck converter as described in claim 4, wherein: The first switch includes: The first terminal is coupled to this input terminal; The second end is coupled to the switch node; and The control terminal is coupled to the drive circuit; and The second switch includes: The first end is coupled to the switch node; The second end is coupled to the grounding end; and The control terminal is coupled to the drive circuit.

6. The buck converter of claim 1, wherein the feedback network comprises: A hysteresis switch is coupled to the output and controlled by the bypass mode signal; A bypass resistor is connected to this output terminal; A resistor divider is coupled between the hysteresis switch and the ground terminal; as well as A feedforward capacitor is coupled to the output, the resistor divider, and the error amplifier.

7. The buck converter as claimed in claim 1, wherein the control loop further comprises: An RC (resistor-capacitor) circuit is coupled between the error amplifier and ground.

8. The buck converter of claim 7, wherein the error amplifier comprises: The non-inverting input is used to receive the reference voltage; The inverting input is coupled to the feedback network; First output terminal; as well as The second output terminal is coupled to this logic circuit.

9. The buck converter of claim 8, wherein the comparator comprises: The non-inverting input is coupled to the first output terminal of the error amplifier; Inverting input; The signal terminal is coupled to the logic circuit. as well as The output terminal is coupled to this logic circuit.

10. The buck converter of claim 1, further comprising a load coupled between the output terminal and the ground terminal.

11. A method of operating a buck converter, comprising: The buck converter is operated in normal mode, which includes alternating activation of the high-side switch and the low-side switch to regulate the output voltage. The current in the output inductor of the buck converter is monitored by a zero-current detector; The bypass enable signal is generated by the zero-current detector; The bypass detector is activated based on the bypass activation signal; The input voltage of the buck converter is compared with a first predetermined threshold value, which is related to the output voltage, by a bypass detector; When the input voltage drops below the first predetermined threshold, the bypass detector generates a bypass mode signal; and Based on the bypass mode signal, the buck converter is switched from the normal mode to the bypass mode, wherein the bypass mode includes enabling the high-side switch and disabling the low-side switch.

12. The method of claim 11, further comprising: When operating in this bypass mode: Disable the bypass detector and the comparator of the buck converter; as well as The error amplifier of the buck converter monitors the difference between the feedback voltage and the reference voltage.

13. The method of claim 12, further comprising: The error amplifier determines whether the output voltage has risen above the reference voltage by a predetermined margin. as well as If the output voltage has risen above the reference voltage by a predetermined margin: The error amplifier generates a bypass exit signal; and Enable the comparator of this buck converter.

14. The method of claim 13, further comprising: Based on the bypass exit signal, the buck converter is switched back from the bypass mode to the normal mode.

15. The method of claim 11, further comprising: When operating in this bypass mode: Disable the overcurrent protection circuit of the buck converter; as well as Enable the high current detection circuit of the buck converter.

16. The method of claim 15, further comprising: The high-current detection circuit monitors the voltage difference between the input voltage and the switching node voltage of the buck converter.

17. The method of claim 16, further comprising: The high-current detection circuit determines whether the voltage difference exceeds a second predetermined threshold. as well as If the voltage difference exceeds the second predetermined threshold: The high-current detection circuit generates a high-current signal; as well as Enable the overcurrent protection circuit.

18. The method of claim 17, further comprising: The overcurrent protection circuit compares the output current with the overcurrent threshold. as well as If the output current exceeds the overcurrent threshold, the buck converter will be switched back from the bypass mode to the normal mode.

19. The method of claim 18, further comprising: If the output current does not exceed the overcurrent threshold, the buck converter remains in bypass mode and the overcurrent protection circuit is disabled.

20. The method of claim 11, further comprising: Before operating the buck converter in the normal mode, the buck converter is operated in a sleep mode, wherein the sleep mode includes: Deactivate the high-side switch and the low-side switch; and Disable the bypass detector and the comparator of the buck converter.

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