Low noise amplifier and wireless receiving system

Abstract

The invention discloses a low noise amplifier and a wireless receiving system. The low-noise amplifier comprises an input matching circuit used for receiving a to-be-amplified signal output by a signal input end and matching impedance between the signal input end and an input end of a first amplifying circuit; the first amplification circuit is used for performing first-stage amplification processing on the signal to be amplified; the inter-stage matching circuit is used for matching the output impedance of the amplifying circuit with the input impedance of a second amplifying circuit; the second amplification circuit is used for performing second-stage amplification on the output signal of the inter-stage matching circuit; the output matching circuit is used for matching the output impedance of the second amplifying circuit with the impedance between a signal output end and outputting an amplified signal through the signal output end; and the bias adjusting circuit is used for adjusting the bias voltage of at least one of the first amplifying circuit and the second amplifying circuit. By adopting the scheme, the dynamic range of the low-noise amplifier can be improved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to a low-noise amplifier and a wireless receiving system. Background Technology

[0002] A low-noise amplifier (LNO) is the first-stage active circuit in a wireless receiving system. Its core function is to amplify the weak signal received from the antenna while introducing as little additional noise as possible. The performance of the LNO directly determines the sensitivity, dynamic range, and signal-to-noise ratio of the entire receiving system.

[0003] For low-noise amplifiers (LNOA), since they need to receive weak signals across the entire operating frequency band and provide sufficient signal-to-noise ratio for subsequent signal processing, they must possess sufficient gain across the entire operating frequency band to suppress noise in subsequent circuits. Simultaneously, LNOA is often affected by out-of-band blocking or strong in-band interference. Particularly in radar applications, strong near-end reflections can easily lead to saturation risks. Therefore, LNOA must also possess high linearity and a large dynamic range to ensure the system's receiving sensitivity and signal integrity in complex electromagnetic environments.

[0004] However, the performance of existing low-noise amplifiers is difficult to adjust flexibly according to application requirements. Summary of the Invention

[0005] The problem this invention aims to solve is: how to flexibly adjust a low-noise amplifier to meet application requirements.

[0006] To address the above problems, embodiments of the present invention provide a low-noise amplifier, the low-noise amplifier comprising:

[0007] An input matching circuit, connected to the signal input terminal, is used to receive the signal to be amplified output from the signal input terminal and to match the impedance between the signal input terminal and the input terminal of the first amplifier circuit.

[0008] The first amplification circuit is connected to the input matching circuit and is used to perform a first-stage amplification of the signal to be amplified.

[0009] An interstage matching circuit, connected to the first amplifier circuit, matches the output impedance of the amplifier circuit with the input impedance of the second amplifier circuit.

[0010] The second amplification circuit is connected to the interstage matching circuit and is used to amplify the output signal of the interstage matching circuit in the second stage.

[0011] An output matching circuit is used to match the output impedance of the second amplifier circuit with the impedance between the signal output terminal, and to output the amplified signal through the signal output terminal.

[0012] And a bias adjustment circuit for adjusting the bias voltage of at least one of the first amplifier circuit and the second amplifier circuit.

[0013] In one possible embodiment, the first amplifier circuit includes: a first MOSFET and a second MOSFET; wherein:

[0014] The gate of the first MOS transistor is connected to the first output terminal of the input matching circuit, and the drain is connected to the first input terminal of the interstage matching circuit.

[0015] The gate of the second MOS transistor is connected to the second output terminal of the input matching circuit, and the drain is connected to the second input terminal of the interstage matching circuit.

[0016] The sources of both the first and second MOSFETs are grounded.

[0017] In one possible embodiment, the input matching circuit includes: a transformer balun; the same-name terminal of the secondary coil of the transformer balun serves as the first output terminal of the input matching circuit, and the opposite-name terminal of the secondary coil of the transformer balun serves as the second output terminal of the input matching circuit.

[0018] In one possible embodiment, the bias adjustment circuit includes: a first bias adjustment unit, the first bias adjustment unit comprising:

[0019] The first resistor is connected to the center tap of the balun secondary coil of the transformer.

[0020] And a first bias adjustment sub-circuit, connected to the first resistor, for adjusting the gate voltage of the first MOSFET and the second MOSFET through the first resistor, so that the first MOSFET and the second MOSFET are biased near the optimal noise level.

[0021] In one possible embodiment, the first bias adjustment sub-circuit includes:

[0022] The first reference branch is formed by the first reference current source;

[0023] Several first mirror current branches formed by the first switching transistor;

[0024] And a first bias controller and a first output resistor, wherein the first output resistor is connected to the output terminal of the plurality of first mirror current branches;

[0025] The first mirror current branch is used to replicate and amplify the current of the first reference branch; the first bias controller is connected to the first switching transistor of the plurality of first mirror current branches and is used to control whether the first mirror current branch is connected to the first reference branch, so as to change the magnitude of the current flowing through the first output resistor.

[0026] In one possible embodiment, the low-noise amplifier further includes:

[0027] The first capacitor neutralization unit is connected to the first amplifier circuit and is used to neutralize the parasitic capacitance of the first amplifier circuit.

[0028] In one possible embodiment, the first capacitor neutralization unit includes:

[0029] The first capacitor has one end connected to the gate of the first MOS transistor and the other end connected to the drain of the second MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the first MOS transistor.

[0030] The second capacitor has one end connected to the gate of the second MOSFET and the other end connected to the drain of the first MOSFET, and is used to neutralize the gate-drain parasitic capacitance of the second MOSFET.

[0031] In one possible embodiment, the gate width of the first MOS transistor and the second MOS transistor is in the range of [60μm, 90μm].

[0032] In one possible embodiment, the second amplifier circuit includes: a third MOSFET and a fourth MOSFET, wherein:

[0033] The gate of the third MOS transistor is connected to the first output terminal of the interstage matching circuit, and the drain is connected to the first input terminal of the output matching circuit.

[0034] The gate of the fourth MOS transistor is connected to the second output terminal of the interstage matching circuit, and the drain is connected to the second input terminal of the output matching circuit.

[0035] The sources of both the third and fourth MOS transistors are grounded.

[0036] In one possible embodiment, the interstage matching circuit includes: a first transformer, wherein the same-name terminal of the secondary coil of the first transformer serves as the first output terminal of the interstage matching circuit, and the opposite-name terminal of the secondary coil of the first transformer serves as the second output terminal of the interstage matching circuit.

[0037] In one possible embodiment, the bias adjustment circuit includes: a second bias adjustment unit, the second bias adjustment unit comprising:

[0038] The second resistor is connected to the center tap of the secondary coil of the first transformer.

[0039] And a second bias adjustment sub-circuit, connected to the second resistor, for adjusting the gate voltage of the third MOS transistor and the fourth MOS transistor through the second resistor, so that the third MOS transistor and the fourth MOS transistor are biased near the zero point of the third transconductance.

[0040] In one possible embodiment, the second bias adjustment sub-circuit includes:

[0041] Several second mirror current branches formed by the second switching transistor;

[0042] And a second bias controller and a second output resistor, wherein the second output resistor is connected to the output terminal of the plurality of second mirror current branches;

[0043] The second mirror current branch is used to replicate and amplify the current of the first reference branch; the second bias controller is connected to the second switching transistor of the plurality of second mirror current branches and is used to control whether the second mirror current branch is connected to the first reference branch, so as to change the magnitude of the current flowing through the second output resistor.

[0044] In one possible embodiment, the low-noise amplifier further includes:

[0045] The second capacitor neutralization unit is connected to the second amplifier circuit and is used to neutralize the parasitic capacitance of the second amplifier circuit.

[0046] In one possible embodiment, the second capacitor neutralization unit includes:

[0047] The third capacitor has one end connected to the gate of the third MOS transistor and the other end connected to the drain of the fourth MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the third MOS transistor.

[0048] The fourth capacitor has one end connected to the gate of the fourth MOS transistor and the other end connected to the drain of the third MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the fourth MOS transistor.

[0049] In one possible embodiment, the gate width of the third MOS transistor and the fourth MOS transistor is in the range of [60μm, 90μm].

[0050] In one possible embodiment, the output matching circuit includes a fifth capacitor and a second transformer connected to the fifth capacitor.

[0051] This invention also provides a wireless receiving system, which includes any of the low-noise amplifiers described above.

[0052] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0053] By applying the solution of this invention, a bias adjustment circuit is provided, which can adjust the bias voltage of at least one of the first amplifier circuit and the second amplifier circuit. By adjusting the bias voltage of the first amplifier circuit, the noise figure of the low-noise amplifier can be changed, and by adjusting the bias voltage of the second amplifier circuit, the gain of the second amplifier circuit can be changed, thereby changing the gain of the low-noise amplifier. Thus, the performance of the low-noise amplifier can be flexibly adjusted according to actual application requirements to better meet application needs. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the structure of a low-noise amplifier according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of another low-noise amplifier in an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the structure of a first bias adjustment sub-circuit in an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of another low-noise amplifier in an embodiment of the present invention;

[0058] Figure 5 This is a schematic diagram showing the variation of the noise figure NF of the low-noise amplifier in the operating frequency band in an embodiment of the present invention.

[0059] Figure 6 This is a schematic diagram showing the curve variation of the input reflection coefficient S11 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram showing the curve change of the gain S21 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram showing the curve variation of the reverse isolation S12 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention.

[0062] Figure 9 This is a schematic diagram showing the curve variation of the input 1dB compression point IP1dB of the low-noise amplifier in the operating frequency band in an embodiment of the present invention.

[0063] Figure 10 This is a schematic diagram showing the curve variation of the input third-order intermodulation point IIP3 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Detailed Implementation

[0064] The gain of existing low-noise amplifiers is usually fixed. As a result, when receiving weak signals, the low-noise amplifier will have insufficient sensitivity due to insufficient gain, and when receiving strong signals, the gain will be too high, which will cause saturation or distortion of subsequent circuits, produce nonlinear effects (such as harmonics, blocking), and even damage devices. In other words, the dynamic range of low-noise amplifiers is limited and cannot adapt to the wide range of signal strength changes in actual communication. Therefore, it is difficult to ensure the receiving sensitivity and signal integrity of the system in complex electromagnetic environments.

[0065] To address this problem, the present invention provides a bias adjustment circuit. Since the bias adjustment circuit can adjust the bias voltage of at least one of the first amplifier circuit and the second amplifier circuit, the performance of the low-noise amplifier can be flexibly adjusted to better meet application requirements.

[0066] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0067] Reference Figure 1 This invention provides a low-noise amplifier, which may include: an input matching circuit 11, a first amplification circuit 12, an interstage matching circuit 13, a second amplification circuit 14, an output matching circuit 15, and a bias adjustment circuit. Wherein:

[0068] The input matching circuit 11 is connected to the signal input terminal and is used to receive the signal to be amplified RFin output by the signal input terminal and match the impedance between the signal input terminal and the input terminal of the first amplification circuit 12.

[0069] The first amplifier circuit 12 is connected to the input matching circuit 11 and is used to perform a first-stage amplification of the signal to be amplified, RFin.

[0070] The interstage matching circuit 13 is connected to the first amplifier circuit 112 and matches the output impedance of the amplifier circuit 12 with the input impedance of the second amplifier circuit 14.

[0071] The second amplifier circuit 14 is connected to the interstage matching circuit 13 and is used to amplify the output signal of the interstage matching circuit 13 in the second stage.

[0072] The output matching circuit 15 is used to match the output impedance of the second amplifier circuit 14 with the impedance between the signal output terminal, and to output the amplified signal through the signal output terminal.

[0073] The bias adjustment circuit 16 is used to adjust the bias voltage of at least one of the first amplifier circuit 12 and the second amplifier circuit 14.

[0074] In specific implementations, the bias adjustment circuit 16 can be used solely to adjust the bias voltage of the first amplifier circuit 12, solely to adjust the bias voltage of the second amplifier circuit 14, or simultaneously to adjust the bias voltages of both the first amplifier circuit 12 and the second amplifier circuit 14. By adjusting the bias voltage of the first amplifier circuit 12, the noise figure of the low-noise amplifier can be changed. By adjusting the bias voltage of the second amplifier circuit 14, the gain of the second amplifier circuit 14 can be changed, thereby changing the gain of the low-noise amplifier.

[0075] In practical implementation, the bias adjustment circuit 16 can increase the bias voltage of the first amplifier circuit 12 or the second amplifier circuit 14 to reduce the noise of the low-noise amplifier and increase its gain. The bias adjustment circuit 16 can also decrease the bias voltage of the first amplifier circuit 12 or the second amplifier circuit 14 to decrease the bias voltage of the low-noise amplifier and reduce its gain, thus preventing signal distortion due to excessive gain and ensuring signal integrity.

[0076] In practical implementation, a low-noise amplifier can convert a single-ended signal RFin into a differential signal pair output. The differential signal pair includes a first output signal RFoutp and a second output signal RFoutn, which have the same amplitude but opposite phase. To achieve the conversion of the port signal from single-ended to differential, transformers can be used to implement the various matching circuits.

[0077] Figure 2 This is a schematic diagram of the circuit structure of a low-noise amplifier according to an embodiment of the present invention. (Refer to...) Figure 2 In a specific implementation, the input matching circuit 11 may include: a transformer balun T1; the same-name terminal of the secondary coil of the transformer balun T1 serves as the first output terminal of the input matching circuit 11, and the opposite-name terminal of the secondary coil of the transformer balun T1 serves as the second output terminal of the input matching circuit 11.

[0078] Specifically, transformer balun T1 is a single-ended to differential converter formed by a transformer. The primary winding of transformer balun T1 has its same-name terminal connected to the signal input terminal to receive the signal RFin to be amplified, while its opposite-name terminal is grounded. The same-name terminal of the secondary winding of transformer balun T1 serves as the first output terminal of transformer balun T1 and is connected to one input terminal of the first amplifier circuit 12. The opposite-name terminal of the secondary winding of transformer balun T1 serves as the second output terminal of transformer balun T1 and is connected to the other input terminal of the first amplifier circuit 12. Thus, the single-ended signal RFin to be amplified is converted into a differential signal output after passing through transformer balun T1.

[0079] In specific implementation, the primary coil of the transformer balun T1 can be wound with metal M7, with one turn and a regular octagonal shape. The secondary coil of the transformer balun T1 can be wound with metal M8, with two turns and also a regular octagonal shape. Since the thickness of metal M8 is greater than that of metal M7, the overall Q value of the transformer balun T1 is improved, thereby reducing noise.

[0080] In a specific implementation, the interstage matching circuit 13 may include a first transformer T2. The same-name terminal of the secondary coil of the first transformer T2 serves as the first output terminal of the interstage matching circuit 13, and the opposite-name terminal of the secondary coil of the first transformer T2 serves as the second output terminal of the interstage matching circuit 13. The center tap of the primary coil of the first transformer T2 is connected to the power supply voltage VDD, thereby powering the first amplifier circuit 12.

[0081] In practical implementation, the primary coil of the first transformer T2 can be wound with a thicker metal M8, with one turn and a regular octagonal shape. The secondary coil of the first transformer T2 can be wound with a thinner metal M7, with one turn and also a regular octagonal shape. Because the thickness of metal M8 is greater than that of metal M7, the Q values ​​on both sides of the first transformer T2 are better matched, thereby reducing the complexity of the interstage matching circuit 13 while achieving impedance matching on both sides of the first transformer T2.

[0082] In specific implementation, refer to Figure 2 The output matching circuit 15 may include a fifth capacitor C5 and a second transformer T3 connected to the fifth capacitor C5. The fifth capacitor C5 is connected in parallel to the primary coil port of the second transformer T3 to balance the capacitance on both sides of the second transformer T3, thereby completing impedance matching. The center tap of the primary coil of the second transformer T3 is connected to the power supply voltage VDD, thereby providing power to the second amplifier circuit 14.

[0083] In practical implementation, the primary coil of the second transformer T3 is wound with a thicker metal M8, with one turn and a regular octagonal shape. The secondary coil of the second transformer T3 can be wound with a thinner metal M7, with one turn and also a regular octagonal shape. Because the thickness of metal M8 is greater than that of metal M7, the corresponding parasitic resistance is smaller, resulting in a smaller IR voltage drop at the drain.

[0084] In practical implementation, ground rings can be uniformly added around transformer balun T1, first transformer T2, and second transformer T3 for isolation, thereby reducing coupling between transformers. These ground rings can include multiple layers, each of which is not closed, thus reducing eddy currents. Furthermore, transformer balun T1, first transformer T2, and second transformer T3 can all adopt a centrally symmetrical and vertically coupled structure, and use metal M8 and metal M7 to obtain a higher inductance quality factor.

[0085] By using transformers to implement each matching circuit, the impedance matching circuit in this embodiment of the invention can be made more compact, which helps to reduce the area of ​​the low-noise amplifier. Furthermore, it can greatly simplify the structure of the bias adjustment circuit 16 and the power supply circuit.

[0086] In specific implementations, the first amplifier circuit 12 and the second amplifier circuit 14 can be implemented using various circuit structures, and no restrictions are imposed here. The structures of the first amplifier circuit 12 and the second amplifier circuit 14 can be the same or different.

[0087] To simplify circuit complexity, in embodiments of the present invention, the first amplifier circuit 12 and the second amplifier circuit 14 can be configured to have identical structures, both implemented using common-source amplifier circuits formed by MOS transistors. Specifically:

[0088] In one embodiment, reference is made to Figure 2 The first amplifier circuit 12 may include: a first MOSFET M1 and a second MOSFET M2; wherein:

[0089] The gate of the first MOS transistor M1 is connected to the first output terminal of the input matching circuit 11, and the drain is connected to the first input terminal of the interstage matching circuit 13.

[0090] The gate of the second MOS transistor M2 is connected to the second output terminal of the input matching circuit 11, and the drain is connected to the second input terminal of the interstage matching circuit 13.

[0091] The sources of both the first MOSFET M1 and the second MOSFET M2 are grounded.

[0092] In a practical implementation, the first MOSFET M1 and the second MOSFET M2 form a common-source amplifier circuit. The input impedance of this common-source amplifier circuit can be simplified and equivalent to the series connection of the gate resistance Rg and the gate-to-ground capacitance Cg of the two MOSFETs.

[0093] The second amplifier circuit 14 may include: a third MOSFET M3 and a fourth MOSFET M4, wherein:

[0094] The gate of the third MOS transistor M3 is connected to the first output terminal of the interstage matching circuit 13, and the drain is connected to the first input terminal of the output matching circuit 15.

[0095] The gate of the fourth MOS transistor M4 is connected to the second output terminal of the interstage matching circuit 13, and the drain is connected to the second input terminal of the output matching circuit 15.

[0096] The sources of the third MOS transistor M3 and the fourth MOS transistor M4 are both grounded.

[0097] In practical implementation, the third MOSFET M3 and the fourth MOSFET M4 form a common-source amplifier circuit. The input impedance of this common-source amplifier circuit can be simplified and equivalent to the series connection of the gate resistance Rg and the gate-to-ground capacitance Cg of the two MOSFETs.

[0098] In practical implementation, the gain and noise figure of the low-noise amplifier are closely related to the gate width of the MOSFETs in the first amplifier circuit 12 and the second amplifier circuit 14. As the gate width of the MOSFET increases, its gate parasitic resistance first decreases and then increases (U-shaped), while the parasitic capacitance increases with the gate width. Therefore, after the gate width of the MOSFET reaches a certain size, its transconductance tends to stabilize, while the noise figure first decreases and then increases with the gate width. On the other hand, as the bias voltage of the MOSFET increases, its power gain gradually increases, but at the same time, the noise figure and linearity are also affected. Therefore, when selecting the gate width of the MOSFET, various factors need to be considered comprehensively.

[0099] In one embodiment of the present invention, a first MOS transistor M1 and a second MOS transistor M2 with a large gate width can be used to balance the gain, linearity and noise of the low-noise amplifier.

[0100] In one embodiment of the present invention, a third MOS transistor M3 and a fourth MOS transistor M4 with a large gate width can be used to balance the gain, linearity and noise of the low-noise amplifier.

[0101] Specifically, the gate width of the first MOS transistor M1 to the fourth MOS transistor M4 can be between [60μm, 90μm].

[0102] Preferably, the gate width of the first MOSFET M1 and the second MOSFET M2 can be 80µm. The gate width of the third MOSFET M3 and the fourth MOSFET M4 can also be 80µm. In this case, reducing the quality factor of the input impedance reduces the difficulty of input matching and the size of the inductor used, resulting in smaller parasitic resistances of the transformer balun T1 and the first transformer T1, thus introducing less noise. This allows for a balance between input impedance and noise matching.

[0103] In specific implementations, the bias adjustment circuit 16 may only include a first bias adjustment unit, which adjusts the bias voltage of the first amplifier circuit 12 based on noise requirements. Alternatively, the bias adjustment circuit 16 may only include a second bias adjustment unit, which adjusts the bias voltage of the second amplifier circuit 14 based on the signal strength of the signal to be amplified, RFin. The bias adjustment circuit 16 may also include both a first and a second bias adjustment unit simultaneously, thereby simultaneously meeting the application requirements for noise and gain by adjusting the bias voltages of the first amplifier circuit 12 and the second amplifier circuit 14.

[0104] In one embodiment, the first bias adjustment unit may include a first resistor R1 and a first bias adjustment sub-circuit 161. The first resistor R1 is connected to the center tap of the secondary winding of the transformer balun T1. The first bias adjustment sub-circuit 161 is connected to the first resistor R1 and is used to adjust the gate voltages of the first MOSFET M1 and the second MOSFET M2 through the first resistor R1, so that the first MOSFET M1 and the second MOSFET M2 are biased near the optimal noise level.

[0105] The first bias adjustment sub-circuit 161 adjusts the gate voltages of the first MOSFET M1 and the second MOSFET M2 through the first resistor R1. The first resistor R1 can make the real part of the common-mode input impedance greater than zero, thereby improving the stability of the low-noise amplifier.

[0106] In one embodiment, reference is made to Figure 3 The first bias adjustment sub-circuit 161 may include: a first reference branch 1611, a plurality of first mirror current branches (such as first mirror current branches 16121 to 16126), a first bias controller 1613, and a first output resistor Rout1. Wherein:

[0107] The first reference branch 1611 is formed by the first reference current source Iin. The first mirror current branch is formed by the first switching transistor. The first output resistor Rout1 is connected to the output terminals of the plurality of first mirror current branches.

[0108] The first mirror current branch is used to replicate and amplify the current of the reference branch 1611. The first bias controller 1613 is connected to the first switching transistor of the plurality of first mirror current branches and is used to control whether the first mirror current branch is connected to the first reference branch 1611 to change the magnitude of the current flowing through the first output resistor Rout1. The bias voltage range near the optimal noise is typically 0.6V to 0.65V.

[0109] In a specific implementation, the first reference branch 1611 consists of a fifth MOSFET M5 and a first reference current source Iin. The drain of the fifth MOSFET M5 is connected to the first reference current source Iin, and the gate is connected to the first bias controller 1613.

[0110] Each first current mirror branch consists of a first switching transistor and a source resistor connected in series. For example, the first current mirror branch 16121 consists of the first switching transistor Q1 and the source resistor RL1, the first current mirror branch 16126 consists of the first switching transistor Q2 and the source resistor RL2, and so on, with the first current mirror branch 16126 consisting of the first switching transistor Q6 and the source resistor RL6. The source resistor is used to resist PVT fluctuations. PVT fluctuations refer to performance fluctuations caused by changes in three key factors—process, voltage, and temperature—during electronic systems or manufacturing processes.

[0111] The first bias controller 1613 is connected to the gate of the first switching transistor in each first mirror current branch, thereby controlling the amplification ratio of the drain current of the first switching transistor in the branch by controlling the on or off of the first switching transistor.

[0112] In a specific implementation, the first bias controller 1613 can output a switch control signal under the control of an external control signal. The switch control signal can include multiple control bits, each of which can turn on or off the first switch in a first mirror current branch. Therefore, by controlling the first switch in different first mirror current branches, the magnitude of the current flowing through the first output resistor Rout1 can be changed, thereby changing the bias voltage VG and achieving precise adjustment of the gate voltage of the MOS transistor in the first amplifier circuit 12.

[0113] In a specific implementation, the first bias adjustment sub-circuit 161 can be configured to include six first mirror current branches, thereby enabling precise adjustment of the gate voltage of the MOS transistor in the first amplifier circuit 12 in 20mV increments, achieving flexible control of the gain of the low-noise amplifier.

[0114] In one embodiment, the second bias adjustment unit may include a second resistor R2 and a second bias adjustment sub-circuit 162. The second resistor R2 is connected to the center tap of the secondary coil of the first transformer T2; the second bias adjustment sub-circuit, connected to the second resistor R2, is used to adjust the gate voltages of the third MOSFET M3 and the fourth MOSFET M4 through the second resistor R2.

[0115] The second bias adjustment sub-circuit 162 adjusts the gate voltages of the third MOSFET M3 and the fourth MOSFET M4 through the second resistor R2. By setting the second resistor R, the stability of the low-noise amplifier can be improved while completing the bias of the second amplifier circuit 14.

[0116] In a specific implementation, the second bias adjustment sub-circuit 162 may include: a plurality of second mirror current branches formed by the second switching transistor, a second bias controller and a second output resistor, wherein the second output resistor is connected to the output terminals of the plurality of second mirror current branches.

[0117] The second mirror current branch is used to replicate and amplify the current of the first reference branch 1611; the second bias controller is connected to the second switching transistor of the plurality of second mirror current branches and is used to control whether the second mirror current branch is connected to the first reference branch, so as to change the magnitude of the current flowing through the second output resistor.

[0118] In some embodiments, the second bias adjustment sub-circuit 162 can adjust the gate voltages of the third MOSFET M3 and the fourth MOSFET M4, so that the third MOSFET M3 and the fourth MOSFET M4 are biased near the zero of the third transconductance, thereby improving the overall linearity of the low-noise amplifier.

[0119] The bias voltage range near the zero of the third transconductance is typically 0.5V to 0.55V. Ideally, the third MOSFET M3 and the fourth MOSFET M4 in the second amplifier circuit 14 can be biased at the zero of the third transconductance gm3, thereby minimizing the impact of the third MOSFET M3 and the fourth MOSFET M4 on the linearity of the low-noise amplifier.

[0120] The second bias adjustment sub-circuit 162 can be implemented with reference to the above description of the first bias adjustment sub-circuit 161, and will not be repeated here.

[0121] In practical applications, the inventors discovered that the gate-drain capacitance of the MOSFET in a common-source amplifier circuit has a certain impact on the circuit's performance, especially in high-frequency applications. The gate-drain parasitic capacitance of a single MOSFET in a common-source amplifier circuit can reach tens of femtofarads (fF), which reduces the gain and stability of the low-noise amplifier.

[0122] Therefore, in one embodiment of the present invention, the low-noise amplifier may further include at least one of a first capacitor neutralization unit and a second capacitor neutralization unit. Wherein:

[0123] The first capacitor neutralization unit is connected to the first amplifier circuit 12 and is used to neutralize the parasitic capacitance of the first amplifier circuit 12.

[0124] The second capacitor neutralization unit is connected to the second amplifier circuit 14 and is used to neutralize the parasitic capacitance of the second amplifier circuit 14.

[0125] In specific implementations, the structures of the first capacitor neutralization unit and the second capacitor neutralization unit may be the same or different, and no restrictions are imposed here.

[0126] In one embodiment, reference is made to Figure 4 The first capacitor neutralization unit may include: a first capacitor C1 and a second capacitor C2. Wherein:

[0127] The first capacitor C1 has one end connected to the gate of the first MOS transistor M1 and the other end connected to the drain of the second MOS transistor M2, and is used to neutralize the gate-drain parasitic capacitance of the first MOS transistor M1.

[0128] The second capacitor C2 has one end connected to the gate of the second MOS transistor M2 and the other end connected to the drain of the first MOS transistor M1, and is used to neutralize the gate-drain parasitic capacitance of the second MOS transistor M2.

[0129] The second capacitor neutralization unit may include: a third capacitor C3 and a fourth capacitor C4. Wherein:

[0130] The third capacitor C3 has one end connected to the gate of the third MOS transistor M3 and the other end connected to the drain of the fourth MOS transistor M4, and is used to neutralize the gate-drain parasitic capacitance of the third MOS transistor M3.

[0131] The fourth capacitor C4 is connected at one end to the gate of the fourth MOS transistor M4 and at the other end to the drain of the third MOS transistor M3, and is used to neutralize the gate-drain parasitic capacitance of the fourth MOS transistor M4.

[0132] In specific implementation, the first capacitor C1 and the second capacitor C2 are cross-coupled across the two ends of the first amplifier circuit 12. Taking a positive signal input to the gate of the first MOSFET M1 and a negative signal input to the gate of the second MOSFET M2 as an example, the positive signal input to the gate of the first MOSFET M1 is coupled to the drain of the first MOSFET M1 through the gate-drain parasitic capacitance of the first MOSFET M1, while the negative signal input to the gate of the second MOSFET M2 is also coupled to the drain of the first MOSFET M1 through the second capacitor C2. When the capacitance value of the second capacitor C2 is equal to that of the gate-drain parasitic capacitance of the first MOSFET M1, the two will cancel each other out. This can reduce the negative impact of the Miller effect of the gate-drain parasitic capacitance of the first MOSFET M1 and the second MOSFET M2 in the first amplifier circuit 12, and improve the circuit gain, stability and reverse isolation.

[0133] In specific implementation, the third capacitor C3 and the fourth capacitor C4 are cross-coupled across the two ends of the second amplifier circuit 14. Similar to the function of the first capacitor C1 and the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 can also reduce the negative impact of the Miller effect of the gate-drain parasitic capacitance of the third MOS transistor M3 and the fourth MOS transistor M4 in the second amplifier circuit 14, and improve the circuit gain, stability and reverse isolation.

[0134] In practical implementation, the low-noise amplifier can be applied to the millimeter-wave radar receiving channel, operating in the V-band, i.e., 58 GHz ~ 64 GHz, and can balance gain and linearity, as well as input impedance matching and noise matching in the V-band.

[0135] Figure 5 This is a schematic diagram showing the variation of the noise figure NF of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Figure 6 This is a schematic diagram showing the curve variation of the input reflection coefficient S11 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Figure 7 This is a schematic diagram showing the curve change of the gain S21 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Figure 8 This is a schematic diagram showing the curve variation of the reverse isolation S12 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Figure 9 This is a schematic diagram showing the curve change of the input 1dB compression point IP1dB of the low-noise amplifier in the operating frequency band in an embodiment of the present invention. Figure 10 This is a schematic diagram showing the curve variation of the input third-order intermodulation point IIP3 of the low-noise amplifier in the operating frequency band in an embodiment of the present invention.

[0136] from Figure 5 As can be seen, within the operating frequency band, the noise figure NF of the low-noise amplifier in this embodiment of the invention is as low as 4.5dB, that is, the noise of the low-noise amplifier is very small, thereby improving the sensitivity of the low-noise amplifier in receiving signals.

[0137] from Figure 6 As can be seen, within the operating frequency band, the input reflection coefficient S11 of the low-noise amplifier in this embodiment of the invention is less than -15dB, indicating that the low-noise amplifier in this embodiment of the invention has excellent input return loss and possesses wide bandwidth, low reflection, and high stability input matching performance.

[0138] from Figure 7 As can be seen, within the operating frequency band, the gain of the low-noise amplifier in this embodiment of the invention can reach up to 19dB, which is high gain and relatively flat, thus indicating that the low-noise amplifier has wide bandwidth, high gain and high stability amplification performance.

[0139] from Figure 8 As can be seen, within the operating frequency band, the reverse isolation of the low-noise amplifier in this embodiment of the invention is below -45 dB throughout (down to about -55 dB), indicating that the low-noise amplifier in this embodiment of the invention has excellent performance in terms of high isolation, high stability, and resistance to load pull.

[0140] from Figure 9 As can be seen, within the operating frequency band, the input 1dB compression point IP1dB of the low-noise amplifier in this embodiment of the invention fluctuates between -9.8dBm and -10.9dBm across the entire frequency band, with small fluctuation amplitude and good linearity. The input 1dB compression point IP1dB is used to quantify the critical value at which the amplifier transitions from "linear" to "compressed." Exceeding this critical value, the low-noise amplifier begins to exhibit significant compression distortion, serving as an upper limit benchmark for the linear dynamic range of large signals.

[0141] from Figure 10 As can be seen, within the operating frequency band, the low-noise amplifier in this embodiment of the invention exhibits a full-band IIP3 ≥ +1.4 dBm and a peak value of +2 dBm, demonstrating good linearity. The third-order intermodulation point IIP3 is used to quantify the amplifier's resistance to third-order intermodulation distortion (IMD3) caused by strong two-tone / multi-tone interference.

[0142] As can be seen from the above, the low-noise amplifier in the embodiments of the present invention can not only flexibly control the gain, but also take into account noise, linearity, input impedance matching and noise matching.

[0143] This invention also provides a wireless receiving system, which includes the low-noise amplifier described above.

[0144] In some embodiments, the wireless receiving system may further include a signal strength detection device that can detect signal strength and feed the detection result back to the bias adjustment circuit of the low noise amplifier, so that the bias adjustment circuit can automatically adjust the gain of the low noise amplifier based on the signal strength.

[0145] In specific implementations, the wireless receiving system includes, but is not limited to, a radar system.

[0146] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A low-noise amplifier, characterized in that, include: An input matching circuit, connected to the signal input terminal, is used to receive the signal to be amplified output from the signal input terminal and to match the impedance between the signal input terminal and the input terminal of the first amplifier circuit. The first amplification circuit is connected to the input matching circuit and is used to perform a first-stage amplification of the signal to be amplified. An interstage matching circuit, connected to the first amplifier circuit, matches the output impedance of the amplifier circuit with the input impedance of the second amplifier circuit. The second amplification circuit is connected to the interstage matching circuit and is used to amplify the output signal of the interstage matching circuit in the second stage. An output matching circuit is used to match the output impedance of the second amplifier circuit with the impedance between the signal output terminal, and to output the amplified signal through the signal output terminal. And a bias adjustment circuit for adjusting the bias voltage of at least one of the first amplifier circuit and the second amplifier circuit.

2. The low-noise amplifier as described in claim 1, characterized in that, The first amplifier circuit includes: a first MOSFET and a second MOSFET; wherein: The gate of the first MOS transistor is connected to the first output terminal of the input matching circuit, and the drain is connected to the first input terminal of the interstage matching circuit. The gate of the second MOS transistor is connected to the second output terminal of the input matching circuit, and the drain is connected to the second input terminal of the interstage matching circuit. The sources of both the first and second MOSFETs are grounded.

3. The low-noise amplifier as described in claim 2, characterized in that, The input matching circuit includes a transformer balun; the same-name terminal of the secondary coil of the transformer balun serves as the first output terminal of the input matching circuit, and the opposite-name terminal of the secondary coil of the transformer balun serves as the second output terminal of the input matching circuit.

4. The low-noise amplifier as described in claim 3, characterized in that, The bias adjustment circuit includes: a first bias adjustment unit, the first bias adjustment unit comprising: The first resistor is connected to the center tap of the balun secondary coil of the transformer. And a first bias adjustment sub-circuit, connected to the first resistor, for adjusting the gate voltage of the first MOSFET and the second MOSFET through the first resistor, so that the first MOSFET and the second MOSFET are biased near the optimal noise level.

5. The low-noise amplifier as described in claim 4, characterized in that, The first bias adjustment sub-circuit includes: The first reference branch is formed by the first reference current source; Several first mirror current branches formed by the first switching transistor; And a first bias controller and a first output resistor, wherein the first output resistor is connected to the output terminal of the plurality of first mirror current branches; The first mirror current branch is used to replicate and amplify the current of the first reference branch; the first bias controller is connected to the first switching transistor of the plurality of first mirror current branches and is used to control whether the first mirror current branch is connected to the first reference branch, so as to change the magnitude of the current flowing through the first output resistor.

6. The low-noise amplifier as described in claim 2, characterized in that, Also includes: The first capacitor neutralization unit is connected to the first amplifier circuit and is used to neutralize the parasitic capacitance of the first amplifier circuit.

7. The low-noise amplifier as described in claim 6, characterized in that, The first capacitor neutralization unit includes: The first capacitor has one end connected to the gate of the first MOS transistor and the other end connected to the drain of the second MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the first MOS transistor. The second capacitor has one end connected to the gate of the second MOSFET and the other end connected to the drain of the first MOSFET, and is used to neutralize the gate-drain parasitic capacitance of the second MOSFET.

8. The low-noise amplifier as described in claim 2, characterized in that, The gate width of the first MOS transistor and the second MOS transistor is between [60μm, 90μm].

9. The low-noise amplifier as claimed in claim 1, characterized in that, The second amplifier circuit includes: a third MOSFET and a fourth MOSFET, wherein: The gate of the third MOS transistor is connected to the first output terminal of the interstage matching circuit, and the drain is connected to the first input terminal of the output matching circuit. The gate of the fourth MOS transistor is connected to the second output terminal of the interstage matching circuit, and the drain is connected to the second input terminal of the output matching circuit. The sources of both the third and fourth MOS transistors are grounded.

10. The low-noise amplifier as claimed in claim 9, characterized in that, The interstage matching circuit includes: a first transformer, wherein the same-name terminal of the secondary coil of the first transformer serves as the first output terminal of the interstage matching circuit, and the opposite-name terminal of the secondary coil of the first transformer serves as the second output terminal of the interstage matching circuit.

11. The low-noise amplifier as claimed in claim 10, characterized in that, The bias adjustment circuit includes: a second bias adjustment unit, the second bias adjustment unit comprising: The second resistor is connected to the center tap of the secondary coil of the first transformer. And a second bias adjustment sub-circuit, connected to the second resistor, for adjusting the gate voltage of the third MOS transistor and the fourth MOS transistor through the second resistor, so that the third MOS transistor and the fourth MOS transistor are biased near the zero point of the third transconductance.

12. The low-noise amplifier as claimed in claim 11, characterized in that, The second bias adjustment sub-circuit includes: Several second mirror current branches formed by the second switching transistor; And a second bias controller and a second output resistor, wherein the second output resistor is connected to the output terminal of the plurality of second mirror current branches; The second mirror current branch is used to replicate and amplify the current of the first reference branch; the second bias controller is connected to the second switching transistor of the plurality of second mirror current branches and is used to control whether the second mirror current branch is connected to the first reference branch, so as to change the magnitude of the current flowing through the second output resistor.

13. The low-noise amplifier as claimed in claim 9, characterized in that, Also includes: The second capacitor neutralization unit is connected to the second amplifier circuit and is used to neutralize the parasitic capacitance of the second amplifier circuit.

14. The low-noise amplifier as claimed in claim 13, characterized in that, The second capacitor neutralization unit includes: The third capacitor has one end connected to the gate of the third MOS transistor and the other end connected to the drain of the fourth MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the third MOS transistor. The fourth capacitor has one end connected to the gate of the fourth MOS transistor and the other end connected to the drain of the third MOS transistor, and is used to neutralize the gate-drain parasitic capacitance of the fourth MOS transistor.

15. The low-noise amplifier as claimed in claim 9, characterized in that, The gate width of the third MOS transistor and the fourth MOS transistor is between [60μm, 90μm].

16. The low-noise amplifier as claimed in claim 1, characterized in that, The output matching circuit includes a fifth capacitor and a second transformer connected to the fifth capacitor.

17. A wireless receiving system, characterized in that, Includes the low-noise amplifier as described in any one of claims 1 to 16.

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