Dual-channel synchronization method, system, device, equipment, medium and program product

Abstract

The invention discloses a dual-channel synchronization method, system, device and equipment, a medium and a program product, applied to a first channel in dual channels, the method comprises the following steps: controlling to output a first signal and detecting a second signal to carry out handshake interaction with a second channel in the dual channels; the second signal is output by the second channel; in response to the detection that the second signal is at the low level, calculating a first time difference between the first starting timestamp and the first ending timestamp; the first starting timestamp is used for representing a starting moment of a current control period of the first channel, and the first ending timestamp is used for representing a moment when the first channel detects that the second signal is at a low level; receiving a second time difference sent by a second channel; and determining the starting time of the next control period of the first channel based on the first time difference and the second time difference. By adopting the method, high-precision, high-reliability and easy-to-integrate dual-channel synchronization can be realized.

Description

Technical Field

[0001] This application relates to the field of safety control, and more particularly to a dual-channel synchronization method, system, device, equipment, medium, and program product. Background Technology

[0002] In fields with high functional safety requirements, such as elevator electronics and automotive electronics, a dual-channel control architecture is typically used. This architecture includes two independent but functionally identical control channels that operate synchronously to achieve state comparison and fault-tolerant control, thereby meeting relevant safety standards.

[0003] Precise synchronization between the two channels is fundamental to ensuring system security, and the complexity and reliability of the synchronization scheme directly affect the system's construction cost and security. Related technologies for achieving dual-channel synchronization mainly include: hard-wired synchronization relying on external independent hardware, software synchronization relying on communication messages, and hybrid schemes combining both. However, the above schemes cannot simultaneously achieve synchronization accuracy, system integrability, and system reliability. Therefore, a dual-channel synchronization scheme that offers high synchronization accuracy, ease of integration, and high reliability is needed. Summary of the Invention

[0004] This application provides a dual-channel synchronization method, apparatus, electronic device, and computer storage medium, which can balance dual-channel synchronization accuracy, system integrability, and system reliability. The above technical solution is as follows: In a first aspect, embodiments of this application provide a dual-channel synchronization method applied to the first channel of a dual-channel system. The method includes: The system interacts with the second channel of the dual-channel system by controlling the output of the first signal and detecting the second signal; the second signal is output by the second channel. In response to detecting that the second signal is low, a first time difference between a first start timestamp and a first end timestamp is calculated; the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low. The second time difference is received from the second channel. The second time difference is calculated by the second channel based on the second start timestamp and the second end timestamp. The second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level. Based on the first time difference and the second time difference, the start time of the next control cycle of the first channel is determined.

[0005] In one possible implementation, a handshake interaction is performed with the second channel in the dual-channel configuration by controlling the output of a first signal and detecting a second signal, including: The control output first signal is set to a high level, so that the second channel controls the output second signal to a high level in response to detecting that the first signal is high. In response to detecting that the second signal is high, the first signal is controlled to switch to low, so that the second channel controls the second signal to switch to low in response to detecting that the first signal is low.

[0006] In one possible implementation, the start time of the next control cycle of the first channel is determined based on a first time difference and a second time difference, including: The first overload value is calculated based on the first time difference and the second time difference; Based on the first overload value and the current control cycle of the first channel, determine the start time of the next control cycle of the first channel.

[0007] In one possible implementation, after the control output first signal is high, the method further includes: If the waiting time for the second signal to be high exceeds the first preset time, the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected. After controlling the output of the first signal and detecting the second signal to perform a handshake interaction with the second channel in the dual-channel setup, the method further includes: If the waiting time for the second signal to be low exceeds the second preset time, the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected. In response to detecting that the second signal is low, after calculating the first time difference between the first start timestamp and the first end timestamp, the method further includes: If the waiting time for the second channel to send the second time difference exceeds the third preset time, then the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected.

[0008] In one possible implementation, after calculating the first time difference between the first start timestamp and the first end timestamp in response to detecting that the second signal is low, the method further includes: The first time difference is sent to the second channel so that the second channel can determine the start time of the next control cycle based on the first time difference and the second time difference.

[0009] Secondly, embodiments of this application provide a dual-channel synchronization method applied to the second channel in a dual-channel configuration. The method includes: By detecting the first signal and controlling the output of the second signal, a handshake interaction is performed with the first channel in the dual-channel system; the first signal is output by the first channel. In response to the detection that the first signal is low, a second time difference between the second start timestamp and the second end timestamp is calculated; the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to low level; The first time difference is received by the first channel; the first time difference is calculated by the first channel based on the first start timestamp and the first end timestamp, the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low level; Based on the first time difference and the second time difference, the start time of the next control cycle of the second channel is determined.

[0010] In one possible implementation, a handshake interaction is performed with the first channel in the dual-channel configuration by detecting a first signal and controlling the output of a second signal, including: In response to detecting that the first signal is high, the second signal is controlled to be output as high. In response to detecting that the first signal is low, the control signal switches to low level.

[0011] In one possible implementation, the start time of the next control cycle of the second channel is determined based on the first time difference and the second time difference, including: The second overload value is calculated based on the first time difference and the second time difference; Based on the second overload value and the current control cycle of the second channel, determine the start time of the next control cycle of the second channel.

[0012] In one possible implementation, the method also includes: If the waiting time for the first signal to be high exceeds the fourth preset time, then the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected. In response to detecting that the first signal is high, and controlling the output of the second signal to be high, the method further includes: If the waiting time for the first signal to be low exceeds the fifth preset time, then the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected. In response to detecting that the first signal is low, after calculating the second time difference between the second start timestamp and the second end timestamp, the method further includes: If the waiting time for the first channel to send the first time difference exceeds the sixth preset time, then the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected.

[0013] In one possible implementation, after calculating the second time difference between the second start timestamp and the second end timestamp in response to detecting that the first signal is low, the method further includes: The second time difference is sent to the first channel so that the first channel can determine the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

[0014] Thirdly, embodiments of this application provide a dual-channel synchronization system, which includes: a first channel and a second channel; wherein, The first channel is used to execute the method steps provided in the first aspect of the embodiments of this application; The second channel is used to execute the method steps provided in the second aspect of the embodiments of this application.

[0015] Fourthly, embodiments of this application provide a dual-channel synchronization device applied to the first channel of a dual-channel system. The device includes: The first input / output module is used to perform a handshake interaction with the second channel in the dual-channel configuration by controlling the output of a first signal and detecting a second signal; the second signal is output by the second channel. The first calculation module is used to calculate a first time difference between a first start timestamp and a first end timestamp in response to detecting that the second signal is low; the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low. The first communication module is used to receive the second time difference sent by the second channel. The second time difference is calculated by the second channel based on the second start timestamp and the second end timestamp. The second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level. The second calculation module is used to determine the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

[0016] Fifthly, embodiments of this application provide a dual-channel synchronization device applied to the second channel of a dual-channel system. The device includes: The second input / output module is used to detect a first signal and control the output of a second signal to perform a handshake interaction with the first channel in the dual channels; the first signal is output by the first channel. The third calculation module is used to calculate the second time difference between the second start timestamp and the second end timestamp in response to the detection that the first signal is low; the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to low level; The second communication module is used to receive the first time difference sent by the first channel; the first time difference is calculated by the first channel based on the first start timestamp and the first end timestamp, the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low level; The fourth calculation module is used to determine the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

[0017] In a sixth aspect, embodiments of this application provide an electronic device, including: a processor and a memory; wherein the memory stores a computer program, the computer program being adapted to be loaded by the processor and to execute the method steps provided in the first or second aspect of embodiments of this application.

[0018] In a seventh aspect, embodiments of this application provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the method steps provided in the first or second aspect of embodiments of this application.

[0019] The aforementioned dual-channel synchronization method, system, device, equipment, medium, and program products achieve handshake through direct signal interaction during the handshake interaction phase. This not only reduces system complexity but also avoids the risk of single-point failures that may arise from external hardware, improving the system's ease of integration and reliability. During the local calculation phase, the first channel, acting as the detection end, calculates the first time difference between the start time of its current control cycle and the time it detects the falling edge of the second signal. The second channel, acting as the control end, calculates the second time difference between the start time of its current control cycle and the time it detects the falling edge of the second signal. This quantifies the offset of the same event relative to the respective cycle start points of both channels, providing high-precision time difference data for subsequent synchronization compensation. During the data exchange phase, the two channels achieve bidirectional data sharing by exchanging the time differences they have calculated, which helps improve the reliability of dual-channel synchronization. During the cycle adjustment phase, each channel can adjust the start time of its next control cycle based on the time difference data from both sides, thereby transforming the event alignment relationship of the handshake interaction phase into precise time control of the future cycle start time, improving the accuracy of dual-channel synchronization. The aforementioned dual-channel synchronization method achieves high-precision, high-reliability, and easily integrated dual-channel synchronization through handshake interaction, local computation, data exchange, and periodic adjustment, without the need for independent external hardware. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of the architecture of a dual-channel synchronization system provided for an exemplary embodiment of this application; Figure 2 A flowchart illustrating a dual-channel synchronization method provided for an exemplary embodiment of this application; Figure 3 A flowchart illustrating another dual-channel synchronization method provided for an exemplary embodiment of this application; Figure 4 A schematic diagram of a dual-channel synchronization device provided for an exemplary embodiment of this application; Figure 5 A schematic diagram of another dual-channel synchronization device provided as an exemplary embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0024] First, let's introduce the application scenario applicable to the embodiments of this application: Elevator main controllers generally adopt a dual-channel redundant architecture to ensure the absolute safety of elevator operation. This architecture includes two functionally identical control channels that operate in parallel, monitoring key parameters such as elevator speed, position, and door lock status in real time, and executing safety algorithms. The calculation results of the two channels must be compared periodically in real time. Once an inconsistency is found, the elevator main controller will immediately determine a fault and trigger safety protection measures such as emergency braking. To ensure the effectiveness of the dual-channel status comparison and the coordination of control outputs, precise synchronization of the two channels is required.

[0025] Please see Figure 1 This is a schematic diagram of the architecture of a dual-channel synchronization system provided in an embodiment of this application. The dual-channel synchronization system includes a first channel and a second channel that are functionally identical and redundant. The first channel 10 includes: a first processor 101, a first timer 102, a first input / output module 103, and a first communication module 104. The second channel 20 includes: a second processor 201, a second timer 202, a second input / output module 203, and a second communication module 204.

[0026] The processor (including the first processor 101 and the second processor 201) is the control core of each channel, used to coordinate the timers, input / output modules, and communication modules of each channel to perform dual-channel synchronous operation. The timers (including the first timer 102 and the second timer 202) are high-precision timing units used to generate periodic interrupts in response to the configuration of each channel processor to define the control cycle and record precise timestamps to mark the occurrence of events. The input / output modules (including the first input / output module 103 and the second input / output module 203) are digital signal interfaces used to convert internal logic instructions into external physical level outputs under the control of the processor, and to convert external physical level states into internal digital signals for the processor to read. The communication modules (including the first communication module 104 and the second communication module 204) are data exchange interfaces used to realize bidirectional data communication under the control of the processor.

[0027] Specifically, the first processor 101 is configured to: acquire the current control period and record timestamp of the first timer 102; set the first overload value of the first timer 102; perform input reading and output control of the first input / output module 103; transmit the first time difference to the first communication module 104; and read the second time difference acquired by the first communication module 104. The first timer 102 is configured to: implement timing according to the period set by the first processor 101. The first input / output module 103 is configured to: output the first signal IO_1 according to the command of the first processor 101 and detect the second signal IO_2 output by the second input / output module 203; and trigger the first timer 102 to record the timestamp. The first communication module 104 is configured to: communicate with the second communication module 204 of the second channel 20 via the Bus bus according to the command of the first processor 101.

[0028] The second processor 201 is configured to: acquire the current control period and record timestamp of the second timer 202; set the second overload value of the second timer 202; control the input reading and output of the second input / output module 203; transmit the second time difference to the second communication module 204; and read the first time difference acquired by the second communication module 204. The second timer 202 is configured to: implement timing according to the period set by the second processor 201. The second input / output module 203 is configured to: output the second signal IO_2 according to the command of the second processor 201 and detect the first signal IO_1 output by the first input / output module 103; and trigger the second timer 202 to record the timestamp. The second communication module 204 is configured to: communicate with the first communication module 104 of the first channel 10 via the Bus bus according to the command of the second processor 201.

[0029] It should be understood that a processor and timer are essential for a dual-channel system to achieve periodic safety control. Therefore, the aforementioned dual-channel synchronization system only requires adding input / output modules and communication modules (such as UART / SPI) to an existing dual-channel system to achieve dual-channel synchronization. On the one hand, it improves the system's ease of integration while ensuring synchronization accuracy; on the other hand, it does not introduce additional safety-related failure rates beyond the failure rates of the input / output and communication modules, thus improving the system's reliability.

[0030] In one possible implementation, the dual-channel synchronization process executed by the aforementioned dual-channel synchronization system can be divided into: cycle initiation phase, handshake interaction phase, local calculation phase, data exchange phase, and cycle adjustment phase.

[0031] At the beginning of the cycle, the first channel 10 controls the first timer 102 via the first processor 101 to record the first start timestamp corresponding to the start time of its current control cycle. The second channel 20 controls the second timer 202 via the second processor 102 to record the second start timestamp corresponding to the start time of its current control cycle.

[0032] During the handshake interaction phase, the first channel 10 controls the first input / output module 103 to output a first signal at a high level via the first processor 101. After the second input / output module 203 of the second channel 20 detects the first signal as high, it sets the corresponding input status register. The second processor 201 of the second channel 20 reads this status register, determines that the first signal has become high, and controls the second input / output module 203 to output a second signal as high. After the first input / output module 103 of the first channel 10 detects the second signal as high, it sets the corresponding input status register. The first processor 101 of the first channel 10 reads this status register, determines that the second signal has become high, and controls the first input / output module 103 to switch the first signal to a low level. After the second input / output module 203 of the second channel 20 detects the first signal as low, it sets the corresponding input status register. The second processor 201 of the second channel 20 reads this status register, determines that the first signal has become low, controls the second input / output module 203 to switch the second signal to a low level, and simultaneously controls the second timer 202 to record the second termination timestamp corresponding to that moment. After the first input / output module 103 of the first channel 10 detects that the second signal is low, it sets the corresponding input status register. The first processor 101 of the first channel 10 reads the status register to know that the second signal has become low, and controls the first timer 102 to record the first termination timestamp corresponding to that moment.

[0033] During the local calculation phase, the first channel 10 calculates the first time difference between the first start timestamp and the first end timestamp using the first processor 101; the first start timestamp represents the start time of the current control cycle of the first channel 10, and the first end timestamp represents the moment when the first channel 10 detects that the second signal is at a low level. The second channel 20 calculates the second time difference between the second start timestamp and the second end timestamp using the second processor 201; the second start timestamp represents the start time of the current control cycle of the second channel 20, and the second end timestamp represents the moment when the second channel 20 controls the second signal to switch to a low level.

[0034] During the data exchange phase, the first channel 10 sends a first time difference to the second communication module 204 of the second channel 20 via the first communication module 104. The second channel 20 sends a second time difference to the first communication module 104 of the first channel 10 via the second communication module 204. The first channel 10 receives the second time difference sent by the second communication module 204 via the first communication module 104. The second channel 20 receives the first time difference sent by the first communication module 104 via the second communication module 204.

[0035] During the periodic adjustment phase, the first channel 10 calculates a first overload value based on a first time difference and a second time difference using the first processor 101, and writes the first overload value into the first timer 102. The first timer 102 of the first channel 10 determines the start time of the next control cycle of the first channel based on the first overload value and the current control cycle of the first channel. The second channel 20 calculates a second overload value based on the first time difference and the second time difference using the second processing module 201, and writes the second overload value into the second timer 202. The second timer 202 of the second channel 20 determines the start time of the next control cycle of the second channel 20 based on the second overload value and the current control cycle of the second channel 20.

[0036] The entire dual-channel synchronization process, through the aforementioned dual-channel synchronization system, completes cycle start timestamp recording, handshake interaction, local calculation, data exchange, and cycle adjustment. It achieves high-precision, high-reliability, and easy-to-integrate dual-channel synchronization without the need for independent external hardware.

[0037] In one embodiment, such as Figure 2 As shown, a dual-channel synchronization method is provided, which can be applied to... Figure 1 The following steps are illustrated using the first channel 10 and the second channel 20 as examples: S201: The first channel 10 interacts with the second channel 20 in the dual channels by controlling the output of the first signal and detecting the second signal.

[0038] The second signal is output from the second channel 20.

[0039] Optionally, at the start of the current control cycle, the first channel 10 and the second channel 20 respectively record the current values ​​of their local timers (i.e., the first timer 102 and the second timer 202 mentioned above) as the first start timestamp of their respective cycles. Second start timestamp Subsequently, the first channel 10 controls its output to set the first signal IO_1 to a high level. After detecting the high level of the first signal, the second channel 20 controls its output to set the second signal IO_2 to a high level. After detecting the high level of the second signal IO_2, the first channel 10 controls its output to set the first signal IO_1 to a low level, at which point the first signal IO_1 generates a falling edge. After detecting the falling edge of the first signal IO_1, the second channel 20 immediately sets the second signal IO_2 to a low level, at which point the second signal IO_2 generates a falling edge. The second channel 20 records the current value of its second timer 202 as the second termination timestamp. After detecting the falling edge of the second signal IO_2, the first channel 10 immediately records the current value of its first timer 102 as the first termination timestamp. .

[0040] Specifically, at the beginning of the current control cycle, the first channel 10 controls the first timer 102 through the first processor 101 to record the first start timestamp corresponding to the start time of its current control cycle. The second channel 20 controls the second timer 202 via the second processor 102 to record the second start timestamp corresponding to the start time of its current control cycle. Subsequently, the first channel 10 controls the first input / output module 103 to output the first signal IO_1 as high. After detecting the high level of the first signal, the second channel 20 controls the second input / output module 203 to output the second signal IO_2 as high. After detecting the high level of the second signal IO_2 through the first input / output module 103, the first channel 10 controls the first input / output module 103 to output the first signal IO_1 as low, at which point the first signal IO_1 generates a falling edge. After detecting the falling edge of the first signal IO_1 through the second input / output module 203, the second channel 20 immediately controls the second input / output module 203 to output the second signal IO_2 as low, at which point the second signal IO_2 generates a falling edge. The second channel 20 records the current value of its second timer 202 as the second termination timestamp. After the first channel 10 detects the falling edge of the second signal IO_2 through the first input / output module, it immediately records the current value of its first timer 102 as the first termination timestamp. .

[0041] S202: In response to detecting that the first signal is low, the second channel 20 calculates the second time difference between the second start timestamp and the second end timestamp.

[0042] The second start timestamp is used to characterize the start time of the current control cycle of the second channel 20, and the second end timestamp is used to characterize the moment when the second channel 20 controls the second signal to switch to a low level.

[0043] Optionally, after the second channel 20 controls the second signal to switch to a low level, the second processor 102 will send the second termination timestamp. With the second start timestamp Subtracting them gives us the second starting timestamp. Second End Timestamp The second time difference between .

[0044] S203: In response to detecting that the second signal is low, the first channel 10 calculates the first time difference between the first start timestamp and the first end timestamp.

[0045] The first start timestamp is used to characterize the start time of the current control cycle of the first channel 10, and the first end timestamp is used to characterize the moment when the first channel 10 detects that the second signal is low. It can be understood that the moment when the first channel 10 detects that the second signal is low is also the moment when the first channel 10 detects the falling edge of the second signal.

[0046] Optionally, after detecting that the second signal is low, the first channel 10 transmits the first termination timestamp through the first processor 101. With the first start timestamp Subtracting them gives us the second starting timestamp. Second End Timestamp The first time difference between .

[0047] S204: The second channel 20 sends the second time difference to the first channel 10.

[0048] Optionally, the second channel 20 transmits the second time difference through the second communication module 204. Send to the first communication module 104 of the first channel 10.

[0049] S205: The first channel 10 receives the second time difference sent by the second channel 20.

[0050] Optionally, the first channel 10 receives the second time difference sent by the second channel 20 through the first communication module 104.

[0051] S206: The first channel 10 determines the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

[0052] Optionally, the first channel 10 is transmitted via the first processor 101 based on a first time difference. Second time difference Calculate the first overload value , the first overload value Write to the first timer 102, and the first timer 102 is based on the first reload value. and the current control cycle of the first channel 10 This determines the start time of the next control cycle for the first channel.

[0053] Specifically, the first channel 10 can calculate the first overload value through the first processor 101 in the following two ways: Method 1: Based on the current control cycle of the second channel 20 Calculate the first overload value using the reference value. In this method, the second channel 20 does not need to adjust the start time of its next control cycle, that is, it does not need to execute steps S207~S209 below. The specific formula is as follows: (1) Method 2: Calculate the first overload value using a preset reference value. In this mode, the second channel 20 also needs to execute steps S207~S209 as described below, and adjust the start time of its next control cycle based on the preset reference value. The specific formula is as follows: (2) It is worth noting that in equation (2) (That is, the preset reference value) can be set according to the ideal control cycle length. For example, in scenarios with high real-time requirements, it can be... Set to 2ms, etc.; in scenarios with less stringent real-time requirements, you can... The embodiment of this application sets it to 10ms, etc. The specific setting value is not limited.

[0054] S207: The first channel 10 sends the first time difference to the second channel 20.

[0055] Optionally, the first channel 10 transmits the first time difference through the first communication module 104. Send to the second communication module 204 of the second channel 20.

[0056] S208: The second channel 20 receives the first time difference transmitted by the first channel 10.

[0057] Optionally, the second channel 20 receives the first time difference sent by the first channel 10 through the second communication module 204.

[0058] S209: The second channel 20 determines the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

[0059] Optionally, the second channel 10 is based on the first time difference via the second processor 201. Second time difference Calculate the second overload value , the second overload value Write to the second timer 202, and the second timer 202 is based on the second overload value. Current control cycle of the second channel 20 This determines the start time of the next control cycle for the second channel 20.

[0060] Specifically, the second channel 20 calculates the second overload value through the second processor 201. The following two methods can be used: Method 1: Based on the current control cycle of the first channel 10 Calculate the second overload value using the reference value. In this method, the first channel 20 does not need to adjust the start time of its next control cycle, that is, it does not need to execute the above process steps S204~S206 again. The specific formula is as follows: (3) Method 2: Calculate the second overload value using a preset reference value. In this method, the first channel 10 also needs to execute the above-mentioned process steps S204~S206, and based on the preset reference value. Adjust the start time of its next control cycle. The specific formula is as follows: (4) It is worth noting that in equation (4) This refers to a preset reference value, which can be set according to the ideal control cycle length. For example, in scenarios with high real-time requirements, it can be... Set to 2ms, etc.; in scenarios with less stringent real-time requirements, you can... The embodiment of this application sets it to 10ms, etc. The specific setting value is not limited.

[0061] The aforementioned dual-channel synchronization method achieves handshake through direct signal interaction during the handshake phase, eliminating the need for independent external hardware. This reduces system complexity, avoids single-point-of-failure risks associated with external hardware, and improves system integrability and reliability. During the local calculation phase, the first channel, acting as the detection end, calculates the first time difference between the start of its current control cycle and the moment it detects the falling edge of the second signal. The second channel, acting as the control end, calculates the second time difference between the start of its current control cycle and the moment it detects the falling edge of the second signal. This quantifies the offset of the same event relative to the respective cycle start points of both channels, providing high-precision time difference data for subsequent synchronization compensation. During the data exchange phase, the two channels share bidirectional data by exchanging their calculated time differences, enhancing the reliability of dual-channel synchronization. In the cycle adjustment phase, each channel can adjust the start time of its next control cycle based on the time difference data from both sides, transforming the event alignment relationship from the handshake phase into precise time control of future cycle start times, thus improving the accuracy of dual-channel synchronization. The aforementioned dual-channel synchronization method achieves high-precision, high-reliability, and easily integrated dual-channel synchronization through handshake interaction, local computation, data exchange, and periodic adjustment, without the need for independent external hardware.

[0062] In one embodiment, such as Figure 3 As shown, another dual-channel synchronization method is provided, which can be applied to... Figure 1 The following steps are illustrated using the first channel 10 and the second channel 20 as examples: S301: The first channel 10 records the first start timestamp through the first timer.

[0063] Optionally, at the start of its current control cycle, the first channel 10 controls the first timer 102 via the first processor 101 to record the first start timestamp corresponding to the start of its current control cycle. Understandably, at the beginning of its current control cycle, the first channel 10 controls the first input / output module 103 to output a first signal at a low level (e.g., 0V) through the first processor 101.

[0064] S302: The second channel 20 records the second start timestamp through the second timer.

[0065] Optionally, at the start of its current control cycle, the second channel 20 controls the second timer 202 via the second processor 201 to record the second start timestamp corresponding to the start of its current control cycle. Understandably, at the beginning of its current control cycle, the second channel 20 controls the second input / output module 203 to output a second signal at a low level (e.g., 0V) through the second processor 201.

[0066] S303: The first signal of the first channel 10 control output is high level.

[0067] Optionally, the first channel 10 controls the first input / output module 103 to output a first signal at a high level (e.g., 3.3V) through the first processor 101.

[0068] S304: The second channel 20 determines whether the duration of waiting for the first signal to be high exceeds the fourth preset duration. If yes, then execute S327; otherwise, execute S305.

[0069] Optionally, while waiting for the first signal to be high, the second channel 20, through the second processor 201, determines whether the duration of waiting for the first signal to be high exceeds a fourth preset duration. If the duration exceeds the fourth preset duration, the second channel 20 stops waiting for the first signal to be high and directly determines the start time of its next control cycle according to the second preset overload value and the current control cycle of the second channel, and collects the corresponding timeout error information. If the duration does not exceed the fourth preset duration, the second channel 20 continues to determine whether the first signal is high.

[0070] S305: Second channel 20 determines whether the first signal is high. If yes, execute S306; if no, execute S304 again.

[0071] Optionally, if the time for the second channel 20 to wait for the first signal to be high does not exceed a fourth preset time, the second channel 20 determines whether the first signal is high through the second processor 201 and the second input / output module 203. If the second channel 20 determines through the second processor 201 that the first signal detected by the second input / output module 203 is high, it controls the second input / output module 203 to output the second signal as high. If the second channel 20 determines through the second processor 201 that the first signal detected by the second input / output module 203 is not high, it continues to wait and determines whether the time for waiting for the first signal to be high exceeds the fourth preset time.

[0072] S306: The second signal of the second channel 20 control output is high level.

[0073] Optionally, in response to detecting that the first signal is high, the second channel 20 controls the second input / output module 203 to output a second signal at a high level (e.g., 3.3V) via the second processor 201.

[0074] S307: The first channel 10 determines whether the duration of waiting for the second signal to be high exceeds the first preset duration. If yes, then execute S328; otherwise, execute S308.

[0075] Optionally, while waiting for the second signal to go high, the first channel 10 determines, through the first processor 101, whether the duration of waiting for the second signal to go high exceeds a first preset duration. If the duration exceeds the first preset duration, the first channel 10 stops waiting for the second signal to go high and directly determines the start time of its next control cycle according to the first preset overload value and the current control cycle of the first channel, and collects the corresponding timeout error information. If the duration does not exceed the first preset duration, the first channel 10 continues to determine whether the second signal is high.

[0076] S308: Channel 10 determines whether the second signal is high. If yes, execute S309; ​​otherwise, execute S307.

[0077] Optionally, if the time for the first channel 10 to wait for the second signal to be high does not exceed a first preset time, the first channel 10 determines whether the second signal is high through the first processor 101 and the first input / output module 103. If the first channel 10 determines through the first processor 101 that the second signal detected by the first input / output module 103 is high, it controls the first input / output module 103 to switch the second signal to low. If the first channel 10 determines through the first processor 101 that the second signal detected by the first input / output module 103 is not high, it continues to wait and determines whether the time for waiting for the second signal to be high exceeds the first preset time.

[0078] S309: The first channel 10 controls the first signal to switch to a low level.

[0079] Optionally, in response to detecting that the second signal is high, the first channel 10 controls the first input / output module 103 to switch the first signal to low level through the first processor 101.

[0080] S310: The second channel 20 determines whether the duration of waiting for the first signal to be low exceeds the fifth preset duration. If yes, then execute S327; otherwise, execute S311.

[0081] Optionally, while waiting for the first signal to be low, the second channel 20, through the second processor 201, determines whether the duration of waiting for the first signal to be low exceeds a fifth preset duration. If the duration exceeds the fifth preset duration, the second channel 20 stops waiting for the first signal to be low and directly determines the start time of its next control cycle according to the second preset overload value and the current control cycle of the second channel, and collects the corresponding timeout error information. If the duration does not exceed the fifth preset duration, the second channel 20 continues to determine whether the first signal is low.

[0082] S311: Second channel 20 determines whether the first signal is low. If yes, execute S312; otherwise, execute S310.

[0083] Optionally, if the time for the second channel 20 to wait for the first signal to be low does not exceed a fifth preset time, the second channel 20 determines whether the first signal is low through the second processor 201 and the second input / output module 203. If the second channel 20 determines through the second processor 201 that the first signal detected by the second input / output module 203 is low, it controls the second input / output module 203 to output a second signal that is low. If the second channel 20 determines through the second processor 201 that the first signal detected by the second input / output module 203 is not low, it continues to wait and determines whether the time for waiting for the first signal to be low exceeds the fifth preset time.

[0084] S312: The second channel 20 controls the second signal to switch to a low level.

[0085] Optionally, in response to detecting that the first signal is low, the second channel 20 controls the second input / output module 203 to output the second signal as low (e.g., 0V) through the second processor 201.

[0086] S313: The second channel 20 records the second termination timestamp corresponding to the moment when its control second signal switches to a low level.

[0087] Optionally, the second channel 20 controls the second timer 202 via the second processor 201 to record the second termination timestamp corresponding to the moment when the control second signal switches to a low level. .

[0088] S314: The second channel 20 calculates the second time difference between the second start timestamp and the second end timestamp.

[0089] Understandably, the second start timestamp is used to characterize the start time of the current control cycle of the second channel 20, and the second end timestamp is used to characterize the moment when the second channel 20 controls the second signal to switch to a low level.

[0090] Optionally, after the second channel 20 controls the second signal to switch to a low level, the second processor 102 will send the second termination timestamp. With the second start timestamp Subtracting them gives us the second starting timestamp. Second End Timestamp The second time difference between .

[0091] S315: The first channel 10 determines whether the duration of waiting for the second signal to be low exceeds the second preset duration. If yes, then execute S328; otherwise, execute S316.

[0092] Optionally, while waiting for the second signal to be low, the first channel 10 determines, through the first processor 101, whether the duration of waiting for the second signal to be low exceeds a second preset duration. If the duration exceeds the second preset duration, the first channel 10 stops waiting for the second signal to be low and directly determines the start time of its next control cycle according to the first preset overload value and the current control cycle of the first channel, and collects the corresponding timeout error information. If the duration does not exceed the first preset duration, the first channel 10 continues to determine whether the second signal is low.

[0093] S316: Channel 10 determines whether the second signal is low. If yes, execute S317; otherwise, execute S315.

[0094] Optionally, if the time for the first channel 10 to wait for the second signal to be low does not exceed a second preset time, the first channel 10 determines whether the second signal is low through the first processor 101 and the first input / output module 103. If the first channel 10 determines through the first processor 101 that the second signal detected by the first input / output module 103 is low, it controls the first input / output module 103 to switch the second signal to low. If the first channel 10 determines through the first processor 101 that the second signal detected by the first input / output module 103 is not low, it continues to wait and determines whether the time for waiting for the second signal to be low exceeds the second preset time.

[0095] S317: The first channel 10 records the first termination timestamp corresponding to the moment when it detects that the second signal is low.

[0096] Optionally, the first channel 10 controls the first timer 102 via the first processor 101 to record the first termination timestamp corresponding to the moment when it detects that the second signal is low. .

[0097] S318: The first channel 10 calculates the first time difference between the first start timestamp and the first end timestamp.

[0098] The first start timestamp is used to characterize the start time of the current control cycle of the first channel 10, and the first end timestamp is used to characterize the moment when the first channel 10 detects that the second signal is low. It can be understood that the moment when the first channel 10 detects that the second signal is low is also the moment when the first channel 10 detects the falling edge of the second signal.

[0099] Optionally, after detecting that the second signal is low, the first channel 10 transmits the first termination timestamp through the first processor 101. With the first start timestamp Subtracting them gives us the second starting timestamp. Second End Timestamp The first time difference between .

[0100] S319: The first channel 10 sends the first time difference to the second channel 20.

[0101] Optionally, the first channel 10 transmits the first time difference through the first communication module 104. Send to the second communication module 204 of the second channel 20.

[0102] S320: The second channel 20 determines whether the waiting time for receiving the first time difference exceeds the sixth preset time. If yes, then execute S327; if no, then execute S321.

[0103] Optionally, the second channel 20 waits to receive the first time difference. During the process, the second processor 201 determines the waiting time difference for receiving the first time difference. Does the duration exceed the sixth preset duration? If waiting to receive the first time difference... If the duration exceeds the sixth preset duration, the second channel 20 will no longer wait to receive the first time difference. Directly according to the second preset overload value and the current control cycle of the second channel. This determines the start time of the next control cycle and collects the corresponding timeout error information. If waiting to receive the first time difference... If the duration does not exceed the sixth preset duration, the second channel 20 will continue to determine whether the first time difference has been received.

[0104] S321: Second channel 20 determines whether the first time difference has been received. If yes, execute S322; otherwise, execute S320.

[0105] Optionally, wait to receive the first time difference in the second channel 20. If the duration does not exceed the sixth preset duration, the second channel 20 determines whether the first time difference has been received through the second processor 201 and the second communication module 204. If the second channel 20 determines that it has received the first time difference Based on the first time difference Second time difference This determines the start time of its next control cycle. If the second channel 20 determines that it has not received the first time difference... Then continue to wait and determine whether the first time difference has been received. .

[0106] S322: The second channel 20 determines the start time of its next control cycle based on the first time difference and the second time difference.

[0107] Optionally, the second channel 10 is based on the first time difference via the second processor 201. Second time difference Calculate the second overload value , the second overload value Write to the second timer 202, and the second timer 202 is based on the second overload value. Current control cycle of the second channel 20 This determines the start time of the next control cycle for the second channel 20.

[0108] Specifically, the second channel 20 calculates the second overload value through the second processor 201. The following two methods can be used: Method 1: Based on the current control cycle of the first channel 10 Calculate the second overload value using the reference value. In this way, the first channel 20 does not need to adjust the start time of its next control cycle, that is, it does not need to execute the process steps S323~S326 below. The specific formula can be found in the above formula (3).

[0109] Method 2: Using preset reference values (Can be set to 2ms, 10ms, etc.) Calculate the second overload value In this mode, the first channel 10 also needs to execute the following process steps S323~S326, based on the preset reference value. Adjust the start time of its next control cycle. The specific formula can be found in equation (4) above.

[0110] S323: The second channel 20 sends the second time difference to the first channel 10.

[0111] Optionally, the second channel 20 transmits the second time difference through the second communication module 204. Send to the first communication module 104 of the first channel 10.

[0112] S324: The first channel 10 determines whether the waiting time for receiving the second time difference exceeds the third preset time. If yes, then execute S328; if no, then execute S325.

[0113] Optionally, the first channel 10 waits to receive the second time difference. During the process, the first processor 101 determines the time difference to wait for receiving the second time difference. Does the duration exceed the third preset duration? If waiting to receive the second time difference... If the duration exceeds the third preset duration, then the first channel 10 will no longer wait to receive the second time difference. Directly according to the first preset overload value and the current control cycle of the first channel. It determines the start time of its next control cycle and collects the corresponding timeout error information. If waiting to receive the second time difference... If the duration does not exceed the third preset duration, then the first channel 20 continues to determine whether the second time difference has been received. .

[0114] S325: Channel 10 determines whether the second time difference has been received. If yes, proceed to S326; otherwise, proceed to the next step.

[0115] Optionally, wait to receive the second time difference in the first channel 10. If the duration does not exceed the third preset duration, the first channel 10 determines whether the second time difference has been received through the first processor 101 and the first communication module 104. If the first channel 10 determines that the second time difference has been received... Based on the first time difference Second time difference This determines the start time of the next control cycle. If the first channel 10 determines that it has not received the second time difference... Then continue to wait and determine whether the second time difference has been received. .

[0116] S326: The first channel 10 determines the start time of its next control cycle based on the first time difference and the second time difference.

[0117] Optionally, the first channel 10 is transmitted via the first processor 101 based on a first time difference. Second time difference Calculate the first overload value , the first overload value Write to the first timer 102, and the first timer 102 is based on the first reload value. and the current control cycle of the first channel 10 This determines the start time of the next control cycle for the first channel.

[0118] Specifically, the first channel 10 can calculate the first overload value through the first processor 101 in the following two ways: Method 1: Based on the current control cycle of the second channel 20 Calculate the first overload value using the reference value. In this way, the second channel 20 does not need to adjust the start time of its next control cycle, that is, it does not need to execute the steps S319~S322 above. The specific formula can be found in the above formula (1).

[0119] Method 2: Using preset reference values (Can be set to 2ms, 10ms, etc.) Calculate the first overload value In this manner, the second channel 20 also needs to perform the steps S319~S322 described above, and based on the preset reference value. Adjust the start time of its next control cycle. The specific formula can be found in equation (2) above.

[0120] S327: The second channel 20 determines the start time of its next control cycle according to the second preset overload value and the current control cycle of the second channel, and collects the corresponding timeout error information.

[0121] Optionally, if the second channel 20 determines a timeout during any of the steps S304, S310, and S320 described above, it will reset the second preset reload value through the second processor 201. Write to the second timer 202, and the second timer 202 reloads according to the second timeout value. Current control cycle of the second channel 20 The second channel 20 determines the start time of the next control cycle. Simultaneously, the second channel 20 collects corresponding timeout error information through the second processor 201, and reports the corresponding timeout error information to the system fault handling module after the current control cycle ends, ensuring system safety and integrity.

[0122] S328: The first channel 10 determines the start time of its next control cycle according to the first preset overload value and the current control cycle of the first channel, and collects the corresponding timeout error information.

[0123] Optionally, if the first channel 10 determines that a timeout has occurred during any of the steps S307, S315, and S324 described above, it will reset the first preset reload value through the first processor 101. Write to the first timer 102, and the first timer 102 is based on the first preset reload value. and the current control cycle of the first channel 20 The system determines the start time of the next control cycle for the first channel. Simultaneously, the first channel 20 collects corresponding timeout error information through the first processor 101, and reports the corresponding timeout error information to the system fault handling module after the current control cycle ends, ensuring system safety and integrity.

[0124] It is worth noting that if any step in the current control cycle of the first channel 10 or the second channel 20 times out, the next control cycle of the dual channels can be handed over to the system fault handling module to take over, or the same dual-channel synchronization process as the current control cycle can be executed, depending on the actual situation. This application embodiment does not limit this.

[0125] In this embodiment, when a timeout error occurs in the dual-channel synchronization process, on the one hand, the start time of the next cycle is set according to the preset reload value to improve system availability; on the other hand, the corresponding timeout error information is reported to the system fault handling module to ensure system safety and integrity. Subsequently, the dual channels can respond to the instructions sent by the system fault handling module to execute the safety control task of that cycle, or execute the same dual-channel synchronization process as the current control cycle, which effectively improves the reliability of dual-channel synchronization.

[0126] The aforementioned dual-channel synchronization method achieves handshake through direct signal interaction during the handshake phase, eliminating the need for independent external hardware. This reduces system complexity, avoids single-point-of-failure risks associated with external hardware, and improves system integrability and reliability. During the local calculation phase, the first channel, acting as the detection end, calculates the first time difference between the start of its current control cycle and the moment it detects the falling edge of the second signal. The second channel, acting as the control end, calculates the second time difference between the start of its current control cycle and the moment it detects the falling edge of the second signal. This quantifies the offset of the same event relative to the respective cycle start points of both channels, providing high-precision time difference data for subsequent synchronization compensation. During the data exchange phase, the two channels share bidirectional data by exchanging their calculated time differences, enhancing the reliability of dual-channel synchronization. In the cycle adjustment phase, each channel can adjust the start time of its next control cycle based on the time difference data from both sides, transforming the event alignment relationship from the handshake phase into precise time control of future cycle start times, thus improving the accuracy of dual-channel synchronization. The aforementioned dual-channel synchronization method achieves high-precision, high-reliability, and easily integrated dual-channel synchronization through handshake interaction, local computation, data exchange, and periodic adjustment, without the need for independent external hardware.

[0127] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0128] Based on the above-mentioned dual-channel synchronization method, such as Figure 4 As shown, this application embodiment also provides a dual-channel synchronization device 400 for implementing the dual-channel synchronization method applied to the first channel in a dual-channel configuration as described above. The dual-channel synchronization device 400 includes: The first input / output module 401 is used to perform a handshake interaction with the second channel in the dual channels by controlling the output of a first signal and detecting a second signal; the second signal is output by the second channel. The first calculation module 402 is used to calculate a first time difference between a first start timestamp and a first end timestamp in response to detecting that the second signal is low; the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low. The first communication module 403 is used to receive the second time difference sent by the second channel; the second time difference is calculated by the second channel based on the second start timestamp and the second end timestamp, the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level; The second calculation module 404 is used to determine the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

[0129] In one embodiment, the first input / output module 401 is specifically configured to: control the output of a first signal to be at a high level, so that the second channel controls the output of a second signal to be at a high level in response to detecting that the first signal is at a high level; and control the first signal to switch to a low level in response to detecting that the second signal is at a high level, so that the second channel controls the second signal to switch to a low level in response to detecting that the first signal is at a low level.

[0130] In one embodiment, the second calculation module 404 is specifically used to: calculate a first overload value based on a first time difference and a second time difference; and determine the start time of the next control cycle of the first channel according to the first overload value and the current control cycle of the first channel.

[0131] In one embodiment, the dual-channel synchronization device 400 further includes a first timeout processing module, configured to: after the control output first signal is high, if the waiting time for the second signal to be high exceeds a first preset time, determine the start time of the next control cycle of the first channel according to a first preset reload value and the current control cycle of the first channel, and collect corresponding timeout error information; after handshaking with the second channel in the dual channels by controlling the output of the first signal and detecting the second signal, if the waiting time for the second signal to be low exceeds a second preset time, determine the start time of the next control cycle of the first channel according to the first preset reload value and the current control cycle of the first channel, and collect corresponding timeout error information; after calculating the first time difference between the first start timestamp and the first end timestamp in response to detecting the second signal to be low, if the waiting time for the second channel to send the second time difference exceeds a third preset time, determine the start time of the next control cycle of the first channel according to the first preset reload value and the current control cycle of the first channel, and collect corresponding timeout error information.

[0132] In one embodiment, the first communication module 403 is further configured to send a first time difference to the second channel so that the second channel determines the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

[0133] Based on the above-mentioned dual-channel synchronization method, such as Figure 5 As shown, this application embodiment also provides a dual-channel synchronization device 500 for implementing the dual-channel synchronization method applied to the second channel in a dual-channel configuration as described above. The dual-channel synchronization device 500 includes: The second input / output module 501 is used to detect a first signal and control the output of a second signal to perform a handshake interaction with the first channel in the dual channels; the first signal is output by the first channel. The third calculation module 502 is used to calculate the second time difference between the second start timestamp and the second end timestamp in response to the detection that the first signal is low; the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to low level; The second communication module 503 is used to receive the first time difference sent by the first channel; the first time difference is calculated by the first channel based on the first start timestamp and the first end timestamp, the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low level; The fourth calculation module 504 is used to determine the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

[0134] In one embodiment, the second input / output module 501 is specifically configured to: control the output of a second signal to be high level in response to detecting that the first signal is high level; and control the second signal to switch to low level in response to detecting that the first signal is low level.

[0135] In one embodiment, the fourth calculation module 504 is specifically used to: calculate a second overload value based on a first time difference and a second time difference; and determine the start time of the next control cycle of the second channel based on the second overload value and the current control cycle of the second channel.

[0136] In one embodiment, the dual-channel synchronization device 500 further includes a second timeout processing module, configured to: if the duration of waiting for the first signal to be high exceeds a fourth preset duration, determine the start time of the next control cycle of the second channel according to a second preset reload value and the current control cycle of the second channel, and collect corresponding timeout error information; after controlling the output of the second signal to be high in response to detecting the first signal to be high, if the duration of waiting for the first signal to be low exceeds a fifth preset duration, determine the start time of the next control cycle of the second channel according to the second preset reload value and the current control cycle of the second channel, and collect corresponding timeout error information; after calculating the second time difference between the second start timestamp and the second end timestamp in response to detecting the first signal to be low, if the duration of waiting for the first channel to send the first time difference exceeds a sixth preset duration, determine the start time of the next control cycle of the second channel according to the second preset reload value and the current control cycle of the second channel, and collect corresponding timeout error information.

[0137] In one embodiment, the second communication module 503 is further configured to: send a second time difference to the first channel so that the first channel determines the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

[0138] This application also provides an electronic device, the internal structure of which can be shown in the following figure. Figure 6 As shown. The electronic device includes: a main controller 601, a network interface 602, a user input device 603, a memory 604, and a communication bus 605. Wherein: The main controller 601 employs a dual-channel architecture to ensure system operational safety. The dual channels include a first channel and a second channel with identical functions and redundancy. The first channel includes a first processor, a first timer, a first input / output module, and a first communication module. Specifically, the first processor, acting as the control core of the first channel, coordinates the first timer, the first input / output module, and the first communication module within the first channel to perform dual-channel synchronous operation. The first timer is a high-precision timing unit used to generate periodic interrupts in response to the configuration of the first processor to define the control cycle and record precise timestamps to mark the occurrence of events. The first input / output module is a digital signal interface used, under the control of the first processor, to convert internal logic instructions into external physical level outputs and to convert external physical level states into internal digital signals for the processor to read. The first communication module is a data exchange interface used to implement bidirectional data communication under the control of the first processor. The second channel includes a second processor, a second timer, a second input / output module, and a second communication module. Specifically, the second processor, acting as the control core of the second channel, coordinates the second timer, the second input / output module, and the second communication module within the second channel to perform dual-channel synchronous operation. The second timer is a high-precision timing unit used to generate periodic interrupts in response to the configuration of the second processor to define the control cycle and record precise timestamps to mark the occurrence of events. The second input / output module is a digital signal interface used, under the control of the second processor, to convert internal logic instructions into external physical level outputs and to convert external physical level states into internal digital signals for the processor to read. The second communication module is a data exchange interface used to implement bidirectional data communication under the control of the second processor.

[0139] The network interface 602 may include a Bluetooth module, a Near Field Communication (NFC) module, a Wireless Fidelity (Wi-Fi) module, etc.

[0140] The user input device 603 can be a touch layer covering the display screen, or a button, trackball, or touchpad set on the casing of the printing device, or an external keyboard, touchpad, or mouse, etc.

[0141] Memory 604 may include random access memory (RAM) or read-only memory (ROM). Optionally, memory 604 may also include a non-transitory computer-readable medium. Memory 604 can be used to store instructions, programs, code, code sets, or instruction sets. Memory 604 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a data acquisition function), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data involved in the various method embodiments described above, etc. Memory 604 may also be at least one storage device located remotely from the aforementioned main control 601. Figure 6 As shown, the memory 604, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a dual-channel synchronization program.

[0142] The communication bus 605 can be used to realize the connection and communication of the main controller 601, network interface 602, user input device 603, and memory 604.

[0143] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0144] This application also provides a computer storage medium storing instructions that, when executed on a computer or processor, cause the computer or processor to perform one or more steps in the above embodiments. If the constituent modules of the above-described electronic device are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer storage medium.

[0145] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0146] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this specification are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Versatile Discs (DVDs)), or semiconductor media (e.g., Solid State Disks (SSDs)).

[0147] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks. Unless otherwise specified, the technical features of this embodiment and its implementation can be combined arbitrarily.

[0148] The embodiments described above are merely preferred embodiments of this specification and are not intended to limit the scope of this specification. Any modifications and improvements made by those skilled in the art to the technical solutions of this specification without departing from the spirit of this specification should fall within the protection scope defined by the claims.

[0149] It should be noted that the information, data and signals involved in the embodiments of this specification are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0150] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

Claims

1. A dual-channel synchronization method, characterized in that, The method, applied to the first channel of the dual channels, includes: The system interacts with the second channel of the dual-channel system by controlling the output of a first signal and detecting a second signal; the second signal is output by the second channel. In response to detecting that the second signal is low, a first time difference between a first start timestamp and a first end timestamp is calculated; the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low; The second time difference is received from the second channel; the second time difference is calculated by the second channel based on the second start timestamp and the second end timestamp, the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level; Based on the first time difference and the second time difference, the start time of the next control cycle of the first channel is determined.

2. The method as described in claim 1, characterized in that, The step of controlling the output of a first signal and detecting a second signal to perform a handshake interaction with the second channel in the dual channels includes: The control output first signal is set to a high level, so that the second channel controls the output second signal to a high level in response to detecting that the first signal is high. In response to detecting that the second signal is high, the first signal is controlled to switch to low, so that the second channel controls the second signal to switch to low in response to detecting that the first signal is low.

3. The method as described in claim 1, characterized in that, Determining the start time of the next control cycle of the first channel based on the first time difference and the second time difference includes: Calculate the first overload value based on the first time difference and the second time difference; Based on the first overload value and the current control cycle of the first channel, determine the start time of the next control cycle of the first channel.

4. The method as described in claim 2, characterized in that, After the control output first signal is high, the method further includes: If the time for waiting for the second signal to be high exceeds the first preset time, the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected. After controlling the output of the first signal and detecting the second signal to perform a handshake interaction with the second channel of the dual channels, the method further includes: If the duration of waiting for the second signal to be low exceeds the second preset duration, then the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected. After responding to the detection that the second signal is low and calculating the first time difference between the first start timestamp and the first end timestamp, the method further includes: If the waiting time for the second channel to send the second time difference exceeds the third preset time, then the start time of the next control cycle of the first channel is determined according to the first preset overload value and the current control cycle of the first channel, and the corresponding timeout error information is collected.

5. The method as described in claim 1, characterized in that, After responding to the detection that the second signal is low and calculating the first time difference between the first start timestamp and the first end timestamp, the method further includes: The first time difference is sent to the second channel so that the second channel determines the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

6. A dual-channel synchronization method, characterized in that, The method, applied to the second channel of the dual channels, includes: By detecting a first signal and controlling the output of a second signal, a handshake interaction is performed with the first channel of the dual channels; the first signal is output by the first channel. In response to detecting that the first signal is low, a second time difference between a second start timestamp and a second end timestamp is calculated; the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to low level; The first time difference is received by the first channel; the first time difference is calculated by the first channel based on the first start timestamp and the first end timestamp, the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low. Based on the first time difference and the second time difference, the start time of the next control cycle of the second channel is determined.

7. The method as described in claim 6, characterized in that, The step of detecting a first signal and controlling the output of a second signal to perform a handshake interaction with the first channel of the dual channels includes: In response to detecting that the first signal is high, the second signal is controlled to be output as high. In response to detecting that the first signal is low, the second signal is controlled to switch to low level.

8. The method as described in claim 6, characterized in that, Determining the start time of the next control cycle of the second channel based on the first time difference and the second time difference includes: Calculate the second overload value based on the first time difference and the second time difference; Based on the second overload value and the current control cycle of the second channel, determine the start time of the next control cycle of the second channel.

9. The method as described in claim 7, characterized in that, The method further includes: If the duration of waiting for the first signal to be high exceeds the fourth preset duration, the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected. After detecting that the first signal is high, the method further includes controlling the output of the second signal to be high. If the duration of waiting for the first signal to be low exceeds the fifth preset duration, then the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected. After responding to the detection that the first signal is low and calculating the second time difference between the second start timestamp and the second end timestamp, the method further includes: If the waiting time for the first channel to send the first time difference exceeds the sixth preset time, then the start time of the next control cycle of the second channel is determined according to the second preset overload value and the current control cycle of the second channel, and the corresponding timeout error information is collected.

10. The method of claim 6, wherein after calculating the second time difference between the second start timestamp and the second end timestamp in response to detecting that the first signal is low, the method further comprises: The second time difference is sent to the first channel so that the first channel determines the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

11. A dual-channel synchronization system, characterized in that, The dual-channel synchronization system includes: a first channel and a second channel; wherein... The first channel is used to perform the method steps as described in any one of claims 1-5; The second channel is used to perform the method steps as claimed in any one of claims 6-10.

12. A dual-channel synchronization device, characterized in that, The device, applied to the first channel of the dual channels, comprises: The first input / output module is used to perform a handshake interaction with the second channel of the dual channels by controlling the output of a first signal and detecting a second signal; the second signal is output by the second channel. A first calculation module is configured to calculate a first time difference between a first start timestamp and a first end timestamp in response to detecting that the second signal is low; the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low; The first communication module is used to receive the second time difference sent by the second channel; the second time difference is calculated by the second channel based on the second start timestamp and the second end timestamp, the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level; The second calculation module is used to determine the start time of the next control cycle of the first channel based on the first time difference and the second time difference.

13. A dual-channel synchronization device, characterized in that, The device, applied to the second channel of the dual channels, comprises: The second input / output module is used to detect a first signal and control the output of a second signal to perform a handshake interaction with the first channel of the dual channels; the first signal is output by the first channel. The third calculation module is used to calculate a second time difference between a second start timestamp and a second end timestamp in response to detecting that the first signal is low; the second start timestamp is used to characterize the start time of the current control cycle of the second channel, and the second end timestamp is used to characterize the moment when the second channel controls the second signal to switch to a low level; The second communication module is used to receive the first time difference sent by the first channel; the first time difference is calculated by the first channel based on the first start timestamp and the first end timestamp, the first start timestamp is used to characterize the start time of the current control cycle of the first channel, and the first end timestamp is used to characterize the moment when the first channel detects that the second signal is low level; The fourth calculation module is used to determine the start time of the next control cycle of the second channel based on the first time difference and the second time difference.

14. An electronic device, characterized in that, include: A processor and a memory; the memory stores a computer program, and the processor executes the computer program to implement the method steps of any one of claims 1-10.

15. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions adapted for loading by a processor and executing the method steps as claimed in any one of claims 1-10.

16. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1-10.

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