Energy storage component

Abstract

An energy storage component is provided. A method of manufacturing an integrated electrical device comprising an energy storage component comprises: providing a support comprising a porous region (103); forming an insulating layer (104), the insulating layer (104) having an opening (OP) defining a portion of the porous region; forming a bottom electrode layer (105); etching the bottom electrode layer such that the bottom electrode layer is removed on the insulating layer and on the top surface of the portion of the porous region such that the bottom electrode layer remains inside the pores of the portion of the porous region; forming an intermediate layer (106) comprising a dielectric layer or an ion conductor; a top electrode layer (107) is formed on the intermediate layer.

Description

Technical Field

[0001] This invention relates to the field of integration, and more specifically, to electronic products including energy storage components such as capacitors or ion capacitors and methods for manufacturing the same, and also to energy storage components including capacitors or ion capacitors having discontinuous bottom electrode layers. Background Technology

[0002] Various techniques have been developed for integrating passive components (such as energy storage components, capacitive devices, etc.) into / on a substrate (such as a silicon wafer).

[0003] It is generally desirable to construct integrated energy storage components that provide high energy density. Various approaches have been explored in this regard. In the case of capacitive devices, conventional methods for increasing capacitance include reducing the thickness of the dielectric layer (constrained by the need to avoid dielectric breakdown when an operating voltage is applied) and selecting a material with a high dielectric constant as the dielectric layer material.

[0004] Recently, a scheme has been proposed to conformally form the conductive and dielectric layers of integrated energy storage components on the contoured surface (i.e., to form conductive and dielectric layers such that their shapes conform to the shape of the underlying surface) instead of using planar layers. This type of energy storage component can be referred to as a "three-dimensional" component (to distinguish it from planar devices). As an example, the PICS technology proposed by Murata Integrated Passive Solutions employs three-dimensional capacitive components and enables the integration of high-density capacitive components into a silicon substrate.

[0005] Recently, three-dimensional capacitive components have been fabricated by embedding metal-insulator-metal (MIM) structures in porous anodized materials such as porous anodized aluminum oxide (PAA). This technique provides highly integrated capacitors that can be used in a wide range of applications. The technique achieves capacitor stacking (e.g., MIM stacking) in a porous structure formed over a substrate such as a silicon wafer. This porous structure can be produced by anodizing a thin layer of aluminum deposited over the substrate (e.g., deposited on the substrate or deposited on one or more layers formed on the substrate itself). The anodizing process converts Al into porous aluminum oxide (PAA). A mask can optionally be formed on the aluminum layer prior to anodizing, allowing the anodizing process to form islands of porous material. These components using dielectrics in the MIM stack are referred to as capacitors in this specification.

[0006] There are also devices that use an ionic conductor (referred to as an ionic conductor in this application) with electronic insulating properties between the electrodes, called ionic capacitors, where the ionic conductor is a solid electrolyte such as LiPON. These ionic capacitors can also be housed in porous anodic alumina structures.

[0007] In particular, planar capacitance densities of approximately 200 to 500 nF / mm² have been reported using solid-state electrolytes. In such ionic capacitors, energy is stored by accumulating mobile charges (such as Li+, Na+, etc.) at the electrolyte / electrode interface through electrostatic and / or redox processes.

[0008] Furthermore, these ionic capacitors can also be housed inside the pores of a 3D structure to increase capacitance density.

[0009] Forming (non-ionic) or ionic capacitors within the pores of anodic porous oxides or within other types of 3D structures remains difficult.

[0010] Typically, a conductive layer (usually aluminum) is deposited on the top electrode of an ionic or non-ionic capacitor formed above a support (e.g., a porous anodic oxide support). This conductive layer is typically defined by etching, usually to define the edge outside the 3D support (if a 3D support is used). This etching is usually selective and is configured to stop after etching the top electrode layer on which the conductive layer has been deposited. Ideally, the etching process has no effect on the underlying dielectric or ionic conductor layer.

[0011] It has been observed that, particularly when using solid electrolytes such as LiPON, the SF6 used to etch the top electrode (typically TiN) can react with lithium within the LiPON layer, potentially resulting in an irregular surface with a grassy appearance. Figure 1 This is a SEM image of such a damaged LiPON layer. Furthermore, these structures have been observed to be based on LiF. This means that SF6 etching has almost no selectivity and is not suitable for thin layers with a thickness on the order of 20 nm (a thickness suitable for anodic porous oxide devices).

[0012] When the intermediate layer (such as including the LiPON layer) is damaged, the top and bottom electrode layers may short-circuit together, and other undesirable characteristics may be acquired.

[0013] In particular, when using thin dielectric or thin ionic conductor layers (less than 20 nanometers), a solution is needed to prevent these undesirable effects from occurring.

[0014] The present invention was made in view of the above-mentioned problems. Summary of the Invention

[0015] This invention provides a method for manufacturing an integrated electrical device including an energy storage component, the method comprising:

[0016] A support is provided that includes a porous region (e.g., an anodic porous oxide region), the porous region comprising a plurality of substantially straight holes extending from the top surface of the porous region toward the bottom of the porous region;

[0017] An insulating layer is formed, the insulating layer having an opening that defines a portion of the porous region;

[0018] A bottom electrode layer (continuous layer) is conformally formed inside the pores of the portion of the porous region, on the top surface of the portion of the porous region, and on the insulating layer.

[0019] Etch the bottom electrode layer so that:

[0020] The bottom electrode layer is removed on at least a portion of the insulating layer including the opening and on the top surface of the portion of the porous oxide (the top surface including the top portion of the hole), such that the bottom electrode layer is retained inside the hole of the portion of the porous region (the bottom electrode layer is discontinuous after this etching).

[0021] An intermediate layer (continuous layer) comprising a dielectric layer or an ionic conductor (e.g., a solid electrolyte) is formed on the bottom electrode layer (inside the hole), on the top surface of the portion of the porous region, and on the insulating layer (the intermediate layer extends conformally on the bottom electrode layer and extends beyond the opening so as to also extend on the insulating layer).

[0022] A top electrode layer (continuous layer) is formed on the intermediate layer (the intermediate layer extends conformally on the intermediate layer and on the intermediate layer below which the bottom electrode layer has been etched outside the opening).

[0023] A photolithographic mask can be used to define the portion of the insulating layer that includes the opening, so that only the portion of the bottom electrode layer on the insulating layer outside the opening is removed. "Including the opening" means that there is a continuous portion of insulating layer surrounding the opening and has an edge that coincides with the edge of the porous region.

[0024] Alternatively, the portion of the insulating layer including the opening is not defined by a photomask, and the entire bottom electrode layer on the insulating layer is removed.

[0025] The term "conformal" means that the layer follows the contour of the support on which it is formed, rather than being divided into separate parts. For example, prior to the etching step, the bottom electrode layer follows the contour of the holes in the porous region and extends on the walls, bottom, and top portions of the holes.

[0026] The bottom electrode layer extends over an insulating layer that is planar outside its openings. Therefore, the bottom electrode layer above (or at least above a portion of) the insulating layer exhibits a surface that is etched at a faster rate than the bottom electrode layer inside the openings in the porous region. This also applies to the top surface of the portion of the porous region where the bottom electrode layer is removed.

[0027] For example, etching can be performed using plasma-assisted dry etching to form reactive classes from the etchant gas, ultimately providing heavy ions that contribute mechanically to the etching. However, plasma cannot form reactive classes inside the hole, so etching does not occur inside the hole.

[0028] For example, and alternatively, wet etching can also be used. The type of etchant can be selected to allow for limited diffusion / renewal within the hole, which limits the etching rate inside the hole.

[0029] Generally, etchant particles typically have low diffusion rates inside the holes covered by the bottom electrode layer, resulting in low etch rates. Therefore, the bottom electrode layer on top of the insulating layer and the top portion of the hole can be removed in a single etch step, for example, without using a photolithography mask (or ultimately by using a mask that defines the opening above the insulating layer), while keeping the bottom electrode layer inside the opening.

[0030] The initially continuous bottom electrode layer is discontinuous after this etching and is divided into multiple parts, each existing inside its own hole. However, these parts are electrically connected together by a conductive anodization barrier layer.

[0031] The energy storage component is a capacitor or ion capacitor, comprising a bottom electrode layer (divided into multiple electrically connected parts), a middle layer, and a top electrode layer.

[0032] In the obtained structure, the bottom electrode layer is patterned in an etching step that can be maskless. The top electrode layer extends further than the bottom electrode layer (because the top electrode layer is a continuous layer on the intermediate layer), and during the additional patterning of the top electrode layer and the intermediate layer, the risk of short-circuiting the top electrode layer to the bottom electrode layer through a damaged intermediate layer is avoided.

[0033] According to a particular implementation, the method includes forming a conductive layer on a top electrode layer.

[0034] This conductive layer can be a current collector for the component. For example, it may consist of aluminum.

[0035] According to a particular embodiment, the method includes etching to define a conductive region of a conductive layer above and above the top electrode layer, the perimeter of the conductive region including the perimeter of said portion of the porous region.

[0036] Etching stops when it reaches the insulating layer.

[0037] Therefore, in this particular embodiment, this additional etching can etch through the conductive region and the intermediate layer. The distance between the edge of the conductive region formed by this etching and the edge of the opening in the insulating layer ensures that no electrical short circuit occurs between the top electrode and the bottom electrode.

[0038] For example, this additional etching can define a conductive region such that its perimeter is contained within the perimeter of the portion of the removed bottom electrode layer above the portion of the insulating layer (when using a mask). Preferably, these two perimeters are spaced apart to avoid an electrical short circuit between the top and bottom electrodes.

[0039] According to a specific implementation, etching to define the conductive areas of the conductive layer is non-selective etching.

[0040] This particular implementation facilitates the definition of the conductive area and the top electrode layer.

[0041] According to a particular implementation, etching is performed to define the conductive regions of the conductive layer and / or to etch the bottom electrode layer, including ion beam etching.

[0042] Ion beam etching has been observed to be particularly suitable for removing the bottom electrode layer on a planar surface, while having a low etching rate inside the hole.

[0043] According to a particular implementation, etching to define the conductive regions of the conductive layer and / or etching the bottom electrode layer includes a single etching step.

[0044] According to a particular implementation, the entire bottom electrode layer is exposed during the etching of the bottom electrode layer.

[0045] In other words, no photomask is used when etching the bottom electrode layer and exposing the entire bottom electrode layer to the etchant.

[0046] The present invention is not limited to this embodiment, and a mask may be used to define the portion of the bottom electrode layer to be removed above the insulating layer.

[0047] The present invention also provides an integrated electrical device including an energy storage component, comprising:

[0048] A support member including a porous region comprising a plurality of substantially straight holes extending from the top surface of the porous region toward the bottom of the porous region;

[0049] An insulating layer having openings that define a portion of a porous region;

[0050] A bottom electrode layer is conformally disposed inside the pores of said portion of the porous region, the bottom electrode layer of the pore having an edge consistent with the top surface of said portion of the porous region (the bottom electrode layer is discontinuous, not present in the top portion of the pore, and not present on the insulating layer or on at least a portion of the insulating layer including the opening).

[0051] An intermediate layer, comprising a dielectric layer or an ionic conductor, is disposed on the bottom electrode layer, the top surface of the portion of the porous region, and the insulating layer (since it is not covered by the bottom electrode layer).

[0052] The top electrode layer is arranged on the intermediate layer.

[0053] This integrated electrical device can be obtained through any implementation of the method defined above.

[0054] According to a particular embodiment, the device also includes a conductive region on the top electrode layer, the edge of which (e.g., the lateral edge when the device is viewed from the top) is spaced from the bottom electrode layer by a distance equal to at least the thickness of the conductive region.

[0055] In this particular embodiment, the edge of the conductive region is always spaced apart from the bottom electrode layer (when viewed from above). For example, this may result in the edge of the conductive region being spaced apart from the edge of an opening in the insulating layer by the stated distance. Furthermore, if a portion of the bottom electrode layer remains on the insulating layer, that portion is also spaced apart from the edge of the conductive layer. This avoids an electrical short circuit between the top and bottom electrodes. Attached Figure Description

[0056] Further features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of illustration only and not limitation, in the accompanying drawings:

[0057] - Figure 1 (It has been described) as an image of a damaged LiPON layer.

[0058] - Figure 2 This is a schematic diagram of a support component with a bottom electrode layer.

[0059] - Figure 3 It shows Figure 2 The etched structure

[0060] - Figure 4 It shows the formation in Figure 3 The conductive layer on the device,

[0061] - Figure 5The sidewalls formed to obtain the conductive region are shown, and

[0062] - Figure 6 It shows the formation in Figure 5 Additional conductive regions on the device. Detailed Implementation

[0063] We will now describe energy storage components (e.g., capacitors and ion capacitors) and the methods and steps for obtaining these capacitors and ion capacitors. In particular, we will describe the use of a buffer layer disposed on the bottom electrode layer. However, the invention is not limited to this configuration and is also applicable to the use of a buffer layer disposed on an intermediate layer.

[0064] Figure 2 This is an exemplary device including a substrate 100. The substrate may include semiconductor regions (typically silicon), or it may also include glass or other materials. In particular, the substrate 100 may include a conductive layer configured to function as a current collector at a level on its top surface.

[0065] In this specification, the porous region is formed by the anodization of a metal, i.e., the porous region is an anodic porous oxide region. This invention is also applicable to other types of porous regions.

[0066] exist Figure 2 An anodization barrier layer 101 (e.g., tungsten) has been deposited on the substrate.

[0067] A metal layer 102, typically comprising aluminum, has been deposited on the anodized barrier layer. The material of this layer should be selected such that straight holes extending from the top surface of the metal layer to the anodized barrier layer can be formed.

[0068] Here, a portion of the metal layer has been anodized to obtain straight-hole PORs within the anodic porous oxide region 103, which extend vertically in the figure to reach the anodic oxide barrier layer (as disclosed in document WO 2015 / 063420). Alternatively, the entire metal layer may be anodized, and only a subset of the pores will be used to accommodate the stack of layers described later.

[0069] An insulating layer 104 has been formed over the metal layer 102. This insulating layer can be formed on the metal layer 102 or on the anodic porous oxide region (especially where the metal layer has been completely converted to anodic porous oxide), or over a hard mask used as an anodizing mask to define a portion of the metal layer to be anodized. When deposited over an anodizing mask, the insulating layer 104 can be similar to the second hard mask described in document EP 3567645.

[0070] An opening OP has been formed in the insulating layer 104, which opens onto a portion of the anolyte porous oxide (or onto the entire anolyte porous oxide region). The opening has a diameter L1 (its maximum horizontal width).

[0071] On top of this structure, a bottom electrode layer 105 has been deposited conformally, for example, by ALD. This layer may include TiN or other conductive materials. At this stage, the bottom electrode layer is continuous, covering the walls of the hole, the top portion of the hole, the bottom of the hole (where it contacts the anodic oxide barrier layer 101), and the insulating layer 104.

[0072] Figure 3 It shows Figure 2 The structure after the etching of the bottom electrode layer has been performed is indicated by the arrow marked ETC.

[0073] For example, the etching is a non-selective etching such as ion beam etching, and is performed without the use of a photomask.

[0074] The etching is configured such that the etchant will have a low diffusion rate inside the hole covered by the bottom electrode layer. However, the etchant will readily diffuse to the planar surface above the insulating layer outside the opening and to the top portion of the hole (i.e., the top surface of a portion of the anodic porous oxide region), where the bottom electrode layer is removed.

[0075] In an alternative embodiment not shown, a mask is used to define a portion of the bottom electrode layer to be removed above the insulating layer. This mask defines a portion of the insulating layer. For example, the mask could be a photoresist mask with an opening that includes an opening in the insulating layer (when viewed from above).

[0076] Figure 4 It shows Figure 3 The structure has undergone multiple conformal depositions. The intermediate layer 106 (here, a dielectric layer or an ion-conducting layer) has been deposited conformally (e.g., by ALD). For example, this layer may comprise at least one material selected from the group consisting of Si. x O yAl x O y Hf x O y Zr x O y Ti x O y Li x P y O z N x1 Li x Si y P z O x1 N y1 N x M′ y M″ z (P x1 O y1 ) z Where M′ and M″ are metals selected from the group consisting of Al, Ti, and Fe, and N is an element selected from the group consisting of Li, Na, and K. Combinations of these materials may also be considered for use in the intermediate layer.

[0077] The intermediate layer is deposited directly on the bottom electrode layer inside the pore (on the walls and at the bottom), directly on the anolyte porous oxide at the level of the top surface of the portion of the anolyte porous oxide region, and deposited on the insulating layer.

[0078] A top electrode layer 107 has been deposited conformally on the intermediate layer. This top electrode layer can be similar to the bottom electrode layer, and it can also contain TiN.

[0079] The stack formed by the bottom electrode layer, the intermediate layer, and the top electrode layer constitutes an energy storage component, such as a capacitor or an ion capacitor (depending on the material of the intermediate layer). All bottom electrode layer portions of each hole are electrically connected together by a conductive anodic oxide barrier layer 101.

[0080] It should be noted that there is no bottom electrode layer at the top level of the hole, which avoids the electric field being concentrated in the geometrically narrow intermediate layer.

[0081] A conductive layer 108, which may include aluminum, has been deposited above the top electrode layer.

[0082] Figure 5 It shows Figure 4The conductive layer 108 has been patterned by etching to define the structure of the conductive regions of the conductive layer 108. The etching stops at the insulating layer 104 and thus etches through the top electrode layer and the intermediate layer. Here, the conductive regions have a perimeter (e.g., viewed from above) that includes the perimeter of the portion of the anodic porous oxide region (coinciding with the opening). In other words, the conductive regions completely cover the opening, and the conductive regions have a diameter L2 greater than L1.

[0083] The etching steps shown in the figure define the edge EDG of the conductive region, intermediate layer, and top electrode layer. A distance L3 is chosen between the edge EDG and the edge of the opening OP to prevent electrical short circuits in the top and bottom electrode layers should the intermediate layer be damaged at the level of the edge EDG during the etching steps shown in the figure. For example, L3 is at least the thickness of the conductive region.

[0084] It should be noted that this etching can be similar to the reference. Figure 3 The etching described can also be ion beam etching. In particular, this etching is advantageous because it is non-selective.

[0085] Subsequently, as Figure 6 As shown above, an insulating region 110 can be formed to define an electrical contact portion, which is filled with an additional conductive region 111 (typically aluminum) located above and in contact with the conductive region 108. Furthermore, the insulating region may have additional openings filled with additional conductive regions 112 to contact the metal region 102 and the bottom electrode layer through the barrier layer 101. Thus, an electrical contact is formed between the bottom electrode layer, the anodized barrier layer, the metal region, and the additional conductive region 112.

[0086] In an alternative embodiment not shown, the metal layer 102 has been fully anodized, and the bottom electrode layer is connected to the additional conductive region 112 via a further porous region serving as a through-hole, also via a barrier layer 101, the through-hole comprising a conductive material extending from the bottom to the top of the hole in the further porous region.

[0087] Additional variants

[0088] Although the invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited to the specificities of these embodiments. Various changes, modifications, and developments can be made to the embodiments described above within the scope of the appended claims.

Claims

1. A method for manufacturing an integrated electrical device including an energy storage component, comprising: A support member is provided that includes a porous region (103) comprising a plurality of substantially straight holes (PORs) extending from the top surface of the porous region toward the bottom of the porous region. An insulating layer (104) is formed, the insulating layer (104) having an opening (OP) that defines a portion of the porous region; A bottom electrode layer (105) is conformally formed inside the holes of the portion of the porous region, on the top surface of the portion of the porous region, and on the insulating layer. The bottom electrode layer is etched such that the bottom electrode layer is removed on at least a portion of the insulating layer including the opening and on the top surface of the portion of the porous region, such that the bottom electrode layer is retained inside the holes of the portion of the porous region. An intermediate layer (106) comprising a dielectric layer or an ion conductor is formed on the top surface of the portion of the porous region, on the bottom electrode layer, and on the insulating layer. A top electrode layer (107) is formed on the intermediate layer.

2. The method according to claim 1, further comprising: A conductive layer (108) is formed on the top electrode layer.

3. The method according to claim 2, further comprising: Etching is performed to define a conductive region of the conductive layer above and above the top electrode layer, the perimeter of which includes the perimeter of the portion of the porous region. The etching stops when it reaches the insulating layer.

4. The method according to claim 3, wherein, Etching to define the conductive regions of the conductive layer is non-selective etching.

5. The method according to claim 4, wherein, Etching to define the conductive regions of the conductive layer and / or etching the bottom electrode layer includes ion beam etching.

6. The method according to claim 1, wherein, Etching to define the conductive regions of the conductive layer and / or etching the bottom electrode layer comprises a single etching step.

7. The method according to claim 1, wherein, During the etching of the bottom electrode layer, the entire bottom electrode layer is exposed.

8. An integrated electrical device including an energy storage component, comprising: A support member including a porous region (103) comprising a plurality of substantially straight holes (PORs) extending from the top surface of the porous region toward the bottom of the porous region. An insulating layer (104) having an opening (OP) that defines a portion of the porous region; A bottom electrode layer (105) is conformally disposed inside the pores of the portion of the porous region, the bottom electrode layer of the pores having an edge that coincides with the top surface of the portion of the porous region; An intermediate layer (106), comprising a dielectric layer or an ion conductor, is disposed on the bottom electrode layer, on the top surface of the portion of the porous region, and on the insulating layer; A top electrode layer (107) is arranged on the intermediate layer.

9. The integrated electrical device of claim 8, further comprising a conductive region on the top electrode layer, the edge of the conductive region being spaced from the bottom electrode layer by a distance at least the thickness of the conductive region.

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