Semiconductor structure and forming method thereof
By combining VFET technology with back-side power rail technology to form a bottom source/drain and back-side metal interconnect structure, the problem of insufficient integration of VFET devices is solved, and the requirements of sub-5nm process and chip performance improvement are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INTPROP OPERATION MANAGEMENT CO LTD
- Filing Date
- 2024-10-09
- Publication Date
- 2026-04-14
AI Technical Summary
In existing VFET processes, device integration is limited and cannot meet the process requirements below 5nm.
By combining VFET technology with back-side power rail technology, the integration density of the device is improved by forming a lower source/drain and a back-side metal interconnect structure on the back side of the semiconductor substrate.
It improves the device integration of VFET, meets the requirements of sub-5nm process, increases wiring resources and reduces the area of standard cells, and improves chip performance.
Smart Images
Figure CN121865645A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] The increased integration density of integrated circuits is due to the miniaturization of the underlying field-effect transistors (FETs). However, in recent years, with the evolution of process nodes, lateral fin field-effect transistors (FinFETs) can no longer meet the process requirements below 5nm. The new generation of vertical field-effect transistors (VFETs) overcomes the limitations of lateral gate spacing and can meet the requirements of sub-5nm processes, making them an ideal replacement for lateral FinFETs.
[0003] VFET is a novel type of field-effect transistor device. Its channel is perpendicular to the wafer surface, with the source and drain terminals located on the top and bottom sides of the channel. The gate surrounds the channel. When the VFET is turned on, current flows through the channel from top to bottom or bottom to top, perpendicular to the wafer surface. This structure of the VFET is not limited by the gate spacing in FinFET and is considered a potential replacement for FinFET in the future.
[0004] Back power rails are an emerging interconnect technology. In traditional processes, devices are located on the wafer surface, and all interconnects are laid out on top of the devices. Back power rail technology, however, places some of the traces that would otherwise be on top of the devices on the back of the chip. Back power rails can increase trace resources, reduce the area of standard cells, and improve chip performance.
[0005] Current VFET technology limits device integration. Therefore, it is necessary to provide a more efficient and reliable technical solution that combines VFET technology with back-side power rail technology to improve VFET device integration. Summary of the Invention
[0006] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET.
[0007] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including opposing front and back sides, the front side of the semiconductor substrate having a plurality of fin structures and a hard mask layer located on the top surface of the fin structures, and isolation structures further forming in the semiconductor substrate on both sides of the fin structures; sequentially forming an etch stop layer and a bottom spacer layer on the front side of the semiconductor substrate on both sides of the fin structures; removing the semiconductor substrate to form an opening exposing the etch stop layer and the bottom surface of the fin structures; forming a lower source drain in the opening, the back side of the lower source drain being not lower than the back side of the isolation structure; forming a back dielectric layer and a back metal interconnect structure electrically connecting the lower source drain in the back dielectric layer and the back side of the isolation structure.
[0008] In some embodiments of this application, a method for sequentially forming an etch stop layer and a bottom spacer layer on the semiconductor substrate surfaces on both sides of the fin structure includes: sequentially forming an etch stop layer and a bottom spacer layer on the front side of the semiconductor substrate, the sidewall of the fin structure, the top surface and sidewall of the hard mask layer; forming a fill layer on the surface of the bottom spacer layer, wherein the top surface of the fill layer is lower than the top surface of the fin structure; etching away portions of the etch stop layer and the bottom spacer layer located on the top surface and sidewall of the hard mask layer and the sidewall of the fin structure; and removing the fill layer.
[0009] In some embodiments of this application, after forming an etch stop layer and a bottom spacer layer sequentially on the semiconductor substrate surfaces on both sides of the fin structure, the method further includes: forming a gate structure and an interfin dielectric layer on the surface of the bottom spacer layer, the sidewall of the fin structure, and the sidewall of the hard mask layer; etching the gate structure and the hard mask layer so that the top surface of the gate structure is lower than the top surface of the fin structure and removing the hard mask layer; forming a top spacer layer on a portion of the fin structure sidewall and the top surface of the gate structure; forming an upper source drain on the top surface of the fin structure and the top spacer layer; forming a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain in the front dielectric layer on the surface of the upper source drain and the interfin dielectric layer.
[0010] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the fin structure, and the sidewall of the hard mask layer.
[0011] In some embodiments of this application, the method of removing the opening formed by the semiconductor substrate to expose the etch stop layer and the bottom surface of the fin structure includes: thinning the back side of the semiconductor substrate to expose the bottom surface of the isolation structure; and etching the back side of the semiconductor substrate to expose the etch stop layer and the bottom surface of the fin structure.
[0012] In some embodiments of this application, the bottom surface of the fin structure is not lower than the bottom surface of the etching stop layer.
[0013] Another aspect of this application provides a semiconductor structure, including: a lower source drain, wherein a plurality of fin structures are formed on the front side of the lower source drain, and isolation structures for isolating adjacent lower source drains are formed on both sides of the fin structures, and the back side of the lower source drain is not lower than the back side of the isolation structures; an etch stop layer and a bottom spacer layer are sequentially formed on the front side of the lower source drain and the isolation structures on both sides of the fin structures; a back dielectric layer and a back metal interconnect structure electrically connected to the lower source drain are formed on the back side of the lower source drain and the isolation structures.
[0014] In some embodiments of this application, a gate structure is further formed on the surface of the bottom spacer layer and part of the sidewalls of the fin structure, the top surface of the gate structure being lower than the top surface of the fin structure; a top spacer layer is further formed on part of the sidewalls of the fin structure and the top surface of the gate structure; an interfinite dielectric layer is formed on the surface of the gate structure, the top surface of the interfinite dielectric layer being higher than the top surface of the fin structure; an upper source drain is formed on the top surface of the fin structure and the top spacer layer; a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain are formed on the surface of the upper source drain and the interfinite dielectric layer.
[0015] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the fin structure, and the sidewall of the hard mask layer.
[0016] In some embodiments of this application, the bottom surface of the fin structure is not lower than the bottom surface of the etching stop layer.
[0017] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET. Attached Figure Description
[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0019] in:
[0020] Figures 1 to 12 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0023] Figures 1 to 12 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0024] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a front side and a back side opposite to each other, a plurality of fin structures 110 and a hard mask layer 111 located on the top surface of the fin structures 110 are formed on the front side of the semiconductor substrate 100, and isolation structures 120 are also formed in the semiconductor substrate 100 on both sides of the fin structures 110.
[0025] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0026] It should be noted that the terms "front side," "back side," "top surface," and "bottom surface" used in the embodiments of this application refer to the accompanying drawings of the embodiments of this application. Specifically, "front side" and "top surface" refer to the upward direction in the drawings, that is, the surface on the semiconductor substrate 100 in the direction in which the fin structure 110 is formed; conversely, "back side" and "bottom surface" refer to the downward direction in the drawings, that is, the surface on the semiconductor substrate 100 in the direction opposite to the fin structure 110.
[0027] In some embodiments of this application, the fin structure 110 can be formed by etching the semiconductor substrate 100. Alternatively, the fin structure 110 can be formed by epitaxial growth of an epitaxial layer on the surface of the semiconductor substrate 100 followed by etching the epitaxial layer. The hard mask layer 111 serves as a mask during the etching process of the fin structure 110. There can be multiple fin structures 110; for simplicity, only one fin structure 110 is shown here as an example.
[0028] In some embodiments of this application, the material of the isolation structure 120 includes insulating materials such as silicon oxide or silicon nitride. The isolation structure 120 is used to isolate adjacent active regions.
[0029] refer to Figures 2 to 5 As shown, an etch stop layer 130 and a bottom spacer layer 140 are sequentially formed on the surface of the semiconductor substrate 100 on both sides of the fin structure 110.
[0030] refer to Figure 2 As shown, an etch stop layer 130 and a bottom spacer layer 140 are sequentially formed on the front side of the semiconductor substrate 100, the sidewall of the fin structure 110, the top surface of the hard mask layer 111, and the sidewall.
[0031] In some embodiments of this application, the etch stop layer 130 and the bottom spacer layer 140 need to have a uniform thickness, and therefore can be prepared using an ALD atomic layer deposition process.
[0032] In some embodiments of this application, the etch stop layer 130 is required to be a dielectric material having a high etch selectivity (e.g., greater than 10) between the semiconductor substrate 100 and the isolation structure 120, such as a carbon-containing silicon oxide (carbon-containing silicon oxide) or a carbon-containing silicide (silicon carbide).
[0033] In some embodiments of this application, the bottom spacer layer 140 is made of a dielectric material, such as SiN, SiO, SiON, etc.
[0034] In some embodiments of this application, the etching stop layer 130 and the bottom spacer layer 140 can be made of the same material and will be prepared simultaneously without being distinguished as two separate layers.
[0035] refer to Figure 3 As shown, a filling layer 131 is formed on the surface of the bottom spacer layer 140, and the top surface of the filling layer 131 is lower than the top surface of the fin structure 110.
[0036] In some embodiments of this application, the material of the filler layer 131 is etch-selective with the materials of the bottom spacer layer 140 and the etch stop layer 130, for example, silicon oxide.
[0037] refer to Figure 4As shown, etching removes portions of the etch stop layer 130 and the bottom spacer layer 140 located on the top surface and sidewalls of the hard mask layer 111 and the sidewalls of the fin structure 110. Because the material of the filler layer 131 is etch-selective with the materials of the bottom spacer layer 140 and the etch stop layer 130, the filler layer 131 acts as a barrier to protect the bottom spacer layer 140 and the etch stop layer 130 located below it during etching. The etching is an anisotropic etching process.
[0038] refer to Figure 5 As shown, the filling layer 131 is removed.
[0039] In some embodiments of this application, the top surfaces of the etch stop layer 130 and the bottom spacer layer 140 may be slightly higher or slightly lower or flush with the bottom surface of the filler layer 131.
[0040] refer to Figure 6 As shown, a gate structure 150 and an interfin dielectric layer 160 are formed on the surface of the bottom spacer layer 140, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111.
[0041] In some embodiments of this application, the gate structure 150 includes conventional gate structure layers such as a gate dielectric layer, a work function layer, and a gate metal layer, sequentially located on the surface of the bottom spacer layer 140, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111. The gate dielectric layer is composed of multiple layers of high-dielectric-constant dielectric materials such as silicon oxide and hafnium oxide. The work function layer is made of materials such as titanium nitride. The gate metal layer is made of materials such as titanium.
[0042] In some embodiments of this application, the material of the interfin dielectric layer 160 includes insulating materials such as silicon oxide or silicon nitride.
[0043] refer to Figure 7 As shown, the gate structure 150 and the hard mask layer 111 are etched so that the top surface of the gate structure 150 is lower than the top surface of the fin structure 110, and the hard mask layer 111 is removed. The height difference between the top surfaces of the gate structure 150 and the fin structure 110 defines the height of the subsequently formed top spacer layer. This height difference can be set according to specific needs.
[0044] refer to Figure 8 As shown, a top spacer layer 141 is formed on the sidewalls of a portion of the fin structure 110 and on the top surface of the gate structure 150. The top surface of the top spacer layer 141 is flush with the top surface of the fin structure 110. The material of the top spacer layer 141 can be the same as the material of the bottom spacer layer 140.
[0045] refer to Figure 9 As shown, an upper source drain 171 is formed on the top surface of the fin structure 110 and the top spacer layer 141. The top surface of the upper source drain 171 may be higher than, lower than or flush with, the top surface of the interfin dielectric layer 160.
[0046] In some embodiments of this application, the upper source drain 171 is formed using an in-situ doping epitaxial growth process on the fin structure 110 as a substrate. The doping type of the upper source drain 171 is set according to device requirements and can be P-type or N-type.
[0047] The method for forming the semiconductor structure described in this application further includes: forming a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain in the front dielectric layer on the surface of the upper source drain 171 and the interfin dielectric layer 160. For the sake of brevity, the front dielectric layer and the front metal interconnect structure are omitted here.
[0048] In some embodiments of this application, the surface of the upper source drain 171 may be formed with metal silicide for electrically connecting the front metal interconnect structure.
[0049] refer to Figure 10 As shown, removing the semiconductor substrate 100 from the back side of the semiconductor substrate forms an opening 181 that exposes the etch stop layer 130 and the bottom surface of the fin structure 110.
[0050] In some embodiments of this application, the method of removing the opening 181 formed by the semiconductor substrate 100 to expose the etch stop layer 130 and the bottom surface of the fin structure 110 includes: thinning the back side of the semiconductor substrate 100 to expose the bottom surface of the isolation structure 120; etching the back side of the semiconductor substrate 100 to expose the etch stop layer 130 and the bottom surface of the fin structure 110 (i.e., using the etch stop layer 130 as an etch stop signal).
[0051] In some embodiments of this application, the bottom surface of the fin structure 110 is not lower than (higher than or flush with) the bottom surface of the etch stop layer 130.
[0052] refer to Figure 11 As shown, a lower source drain 170 is formed in the opening 181, and the back side of the lower source drain 170 is not lower than the back side of the isolation structure 120.
[0053] In some embodiments of this application, the lower source / drain 170 is formed using an in-situ doped epitaxial growth process on the fin structure 110 as a substrate. The doping type of the lower source / drain 170 is set according to device requirements and can be P-type or N-type.
[0054] refer to Figure 12As shown, a back dielectric layer 190 and a back metal interconnect structure 191 electrically connected to the lower source drain 170 are formed on the back side of the lower source drain 170 and the isolation structure 120.
[0055] In some embodiments of this application, the material of the back dielectric layer 190 includes silicon oxide or a low-k dielectric material, etc.
[0056] In some embodiments of this application, the material of the back metal interconnect structure 191 includes copper or tungsten, etc.
[0057] In some embodiments of this application, the surface of the lower source drain 170 may be formed with metal silicide for electrically connecting the back metal interconnect structure 191.
[0058] This application provides a method for forming a semiconductor structure that combines VFET process with back-side power rail technology, thereby improving the device integration density of VFET.
[0059] Embodiments of this application also provide a semiconductor structure, referencing Figure 12 As shown, it includes: a lower source drain 170, the front side of which has a plurality of fin structures 110 formed, and isolation structures 120 formed on both sides of the fin structures 110 to isolate adjacent lower source drains 170, the back side of which is not lower than the back side of the isolation structures 120; an etch stop layer 130 and a bottom spacer layer 140 are sequentially formed on the front sides of the lower source drains 170 and the isolation structures 120 on both sides of the fin structures 110; a back dielectric layer 190 and a back metal interconnect structure 191 electrically connected to the lower source drains 170 are formed on the back side of the lower source drains 170 and the isolation structures 180.
[0060] It should be noted that the terms "front side," "back side," "top side," and "bottom side" used in the embodiments of this application refer to the accompanying drawings of the embodiments of this application. Specifically, "front side" and "top side" refer to the upward direction in the drawings, that is, the surface on the lower source drain 170 in the direction in which the fin structure 110 is formed; conversely, "back side" and "bottom side" refer to the downward direction in the drawings, that is, the surface on the lower source drain 170 in the direction opposite to the fin structure 110.
[0061] In some embodiments of this application, the number of fin structures 110 may be multiple. For the sake of brevity, only one fin structure 110 is shown here as an example.
[0062] In some embodiments of this application, the material of the isolation structure 120 includes insulating materials such as silicon oxide or silicon nitride. The isolation structure 120 is used to isolate adjacent lower source drains 170.
[0063] In some embodiments of this application, the material of the etch stop layer 130 is, for example, a carbon-containing silicon oxide (carbon-containing silicon dioxide) or a carbon-containing silicide (silicon carbide).
[0064] In some embodiments of this application, the bottom spacer layer 140 is made of a dielectric material, such as SiN, SiO, SiON, etc.
[0065] In some embodiments of this application, the etching stop layer 130 and the bottom spacer layer 140 can be made of the same material and will be prepared simultaneously without being distinguished as two separate layers.
[0066] Continue to refer to Figure 12 As shown, a gate structure 150 is also formed on the surface of the bottom spacer layer 140 and part of the sidewall of the fin structure 110, and the top surface of the gate structure 150 is lower than the top surface of the fin structure 110.
[0067] In some embodiments of this application, the gate structure 150 includes conventional gate structure layers such as a gate dielectric layer, a work function layer, and a gate metal layer, sequentially located on the surface of the bottom spacer layer 140, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111. The gate dielectric layer is made of high- or low-dielectric-constant dielectric materials such as silicon oxide or hafnium oxide. The work function layer is made of materials such as titanium nitride. The gate metal layer is made of materials such as titanium.
[0068] Continue to refer to Figure 12 As shown, a top spacer layer 141 is also formed on the sidewall of part of the fin structure 110 and the top surface of the gate structure 150.
[0069] In some embodiments of this application, the top surface of the top spacer layer 141 is flush with the top surface of the fin structure 110. The material of the top spacer layer 141 may be the same as the material of the bottom spacer layer 140.
[0070] Continue to refer to Figure 12 As shown, an interfin dielectric layer 160 is formed on the surface of the gate structure 150, and the top surface of the interfin dielectric layer 160 is higher than the top surface of the fin structure 110.
[0071] In some embodiments of this application, the material of the interfin dielectric layer 160 includes insulating materials such as silicon oxide or silicon nitride.
[0072] Continue to refer to Figure 12 As shown, an upper source drain 171 is formed on the top surface of the fin structure 110 and the top spacer layer 141.
[0073] In some embodiments of this application, the top surface of the upper source drain 171 may be higher than, lower than or flush with the top surface of the interfin dielectric layer 160.
[0074] In some embodiments of this application, the upper source drain 171 is formed using an in-situ doping epitaxial growth process on the fin structure 110 as a substrate. The doping type of the upper source drain 171 is set according to device requirements and can be P-type or N-type.
[0075] In embodiments of this application, a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain 171 are further formed on the surfaces of the upper source drain 171 and the interfin dielectric layer 160. For the sake of brevity, the front dielectric layer and the front metal interconnect structure are omitted here.
[0076] In some embodiments of this application, the surface of the upper source drain 171 may be formed with metal silicide for electrically connecting the front metal interconnect structure.
[0077] In some embodiments of this application, the bottom surface of the fin structure 110 is not lower than (higher than or flush with) the bottom surface of the etch stop layer 130.
[0078] In some embodiments of this application, the lower source / drain 170 is formed using an in-situ doped epitaxial growth process on the fin structure 110 as a substrate. The doping type of the lower source / drain 170 is set according to device requirements and can be P-type or N-type.
[0079] Continue to refer to Figure 12 As shown, a back dielectric layer 190 and a back metal interconnect structure 191 electrically connected to the lower source drain 170 are formed on the back side of the lower source drain 170 and the isolation structure 120.
[0080] In some embodiments of this application, the material of the back dielectric layer 190 includes silicon oxide or silicon nitride, etc.
[0081] In some embodiments of this application, the material of the back metal interconnect structure 191 includes copper or tungsten, etc.
[0082] In some embodiments of this application, the surface of the lower source drain 170 may be formed with metal silicide for electrically connecting the back metal interconnect structure 191.
[0083] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET.
[0084] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0085] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0086] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0087] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0088] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a front side and a back side opposite to each other, a plurality of fin structures are formed on the front side of the semiconductor substrate, and isolation structures are also formed in the semiconductor substrate on both sides of the fin structures; An etch stop layer and a bottom spacer layer are sequentially formed on the front side of the semiconductor substrate on both sides of the fin structure; The semiconductor substrate is removed from the back side to form an opening that exposes the etch stop layer and the bottom surface of the fin structure; A lower source drain is formed in the opening; A back dielectric layer and a back metal interconnect structure electrically connecting the lower source drain are formed on the back side of the lower source drain and the isolation structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for sequentially forming an etch stop layer and a bottom spacer layer on the semiconductor substrate surfaces on both sides of the fin structure includes: An etch stop layer and a bottom spacer layer are sequentially formed on the front side of the semiconductor substrate, the top surface of the fin structure, and the sidewalls. A filling layer is formed on the surface of the bottom spacer layer, the top surface of the filling layer being lower than the top surface of the fin structure; Etching removes a portion of the etching stop layer and bottom spacer layer located on the top surface and sidewalls of the fin structure; Remove the filler layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming an etch stop layer and a bottom spacer layer sequentially on the semiconductor substrate surfaces on both sides of the fin structure, the method further includes: A gate structure and an interfin dielectric layer are formed on the surface of the bottom spacer layer and on the sidewall of the fin structure. The gate structure is etched so that the top surface of the gate structure is lower than the top surface of the fin structure; A top spacer layer is formed on the sidewalls of some fin structures and on the top surface of the gate structure; An upper source drain is formed on the top surface of the fin structure and the top spacer layer; A front dielectric layer and a front metal interconnect structure electrically connecting the upper source drain are formed on the surface of the upper source drain and the interfin dielectric layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer and the sidewall of the fin structure.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for removing the opening in the semiconductor substrate that exposes the etch stop layer and the bottom surface of the fin structure includes: Thin the back side of the semiconductor substrate to expose the bottom surface of the isolation structure; The back side of the semiconductor substrate is etched to expose the etch stop layer and the bottom surface of the fin structure.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The bottom surface of the fin structure is not lower than the bottom surface of the etching stop layer.
7. A semiconductor structure, characterized in that, include: The lower source drain has a plurality of fin structures formed on its front side, and isolation structures that isolate adjacent lower source drains are formed on both sides of the fin structures. The back side of the lower source drain is not lower than the back side of the isolation structures. The lower source drain and the front side of the isolation structure on both sides of the fin structure are sequentially formed with an etching stop layer and a bottom spacer layer. The lower source drain and isolation structure have a back dielectric layer formed on the back side and a back metal interconnect structure electrically connected to the lower source drain in the back dielectric layer.
8. The semiconductor structure as described in claim 7, characterized in that, A gate structure is also formed on the surface of the bottom spacer layer and part of the sidewalls of the fin structure, with the top surface of the gate structure being lower than the top surface of the fin structure; a top spacer layer is also formed on part of the sidewalls of the fin structure and the top surface of the gate structure; an interfinite dielectric layer is formed on the surface of the gate structure, with the top surface of the interfinite dielectric layer being higher than the top surface of the fin structure; an upper source drain is formed on the top surface of the fin structure and the top spacer layer; a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain are formed on the surface of the upper source drain and the interfinite dielectric layer.
9. The semiconductor structure as described in claim 8, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer and the sidewall of the fin structure.
10. The semiconductor structure as claimed in claim 7, characterized in that, The bottom surface of the fin structure is not lower than the bottom surface of the etching stop layer.