Ge on Si PIN photoelectric detector with shielding ring and preparation method thereof

Abstract

The invention discloses a Ge on Si PIN photoelectric detector with a shielding ring and a preparation method, and relates to the technical field of semiconductor photoelectric devices, and the detector is provided with a P-type shielding ring formed through ion implantation of boron elements on the surface layer of an N-type Si substrate and surrounding the periphery of an active region of a Ge mesa. According to the invention, the shielding ring at a specific position is introduced into the substrate, the electric field distribution at the edge of the mesa is effectively modulated under the reverse bias voltage, the high electric field is pushed away from the Ge etching side wall region with dense defects, and the side wall leakage current is obviously inhibited from the physical source, so that the dark current of the device is greatly reduced. The structure has excellent low-noise performance while ensuring high responsivity and high bandwidth tunability, the preparation process of the structure is completely compatible with a silicon-based CMOS (complementary metal oxide semiconductor) technology, and the structure is suitable for high-performance short-wave infrared light communication, sensing and imaging systems.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a Ge on Si PIN photodetector with a shielding ring and its fabrication method. Background Technology

[0002] Near-infrared photodetectors are crucial in optical communication, sensing, and imaging. Currently, the mainstream high-performance detectors in this field primarily use indium gallium arsenide (InGaAs), which exhibits high responsivity and sensitivity in the 1550 nm communication band. However, InGaAs detectors are expensive to fabricate, require complex heteroepitaxial growth techniques, and are incompatible with mainstream silicon-based CMOS processes, limiting their widespread application in low-cost, large-scale integrated systems.

[0003] In recent years, colloidal quantum dot (such as PbS quantum dot) detectors have attracted attention due to their advantages such as solution-handleability and low cost. However, they suffer from problems such as poor stability, low carrier mobility, and difficulty in integration with silicon processes, and their performance and reliability are still insufficient to meet commercial requirements. In contrast, germanium (Ge), as a traditional semiconductor material, has excellent light absorption characteristics in the near-infrared band (especially up to 1550 nm), and its fabrication process is highly compatible with silicon-based CMOS processes, making it an ideal candidate material for achieving low-cost, high-performance on-chip optoelectronic integration.

[0004] However, traditional Ge-based photodetectors also face challenges. Many structures use bulk germanium to fabricate PIN photodetectors, and mesa etching is performed on the Ge layer region. However, during the dry etching process, some defects are introduced into the Ge sidewalls, which increases the leakage current of the sidewalls. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a Ge on SiPIN photodetector with a shielding ring and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a Ge on Si PIN photodetector with a shielding ring, comprising: N-type Si substrate; A shielding ring is located on the surface of the N-type Si substrate and surrounds the active region of the device. The shielding ring is a P-type region formed by ion implantation. An intrinsic Ge epitaxial layer is located on the upper surface of the N-type Si substrate and part of the shielding ring; A P-doped Ge layer is located on the upper surface of the intrinsic Ge epitaxial layer, and the intrinsic Ge epitaxial layer and the P-doped Ge layer form a mesa structure; The first metal electrode is located on the upper surface of the P-doped Ge layer and forms an ohmic contact with the P-doped Ge layer; The second metal electrode is located on the surface of the N-type Si substrate and forms an ohmic contact with the N-type Si substrate; A passivation layer is disposed on the sidewall of the mesa structure, the uncovered upper surface of the P-doped Ge layer and the shielding ring, and the upper surface of the N-type Si substrate.

[0006] In one embodiment of the present invention, the inner boundary of the shielding ring is located within the side wall projection of the platform structure, the outer boundary is located outside the side wall projection of the platform structure, and the horizontal distance between the inner boundary and the side wall projection of the platform structure is greater than 0.5 μm. The overlapping portion of the shielding ring and the projection of the platform structure does not exceed 30% of the projected area of ​​the platform structure.

[0007] In one embodiment of the present invention, the doping concentration of the shielding ring is 1×10⁻⁶. 18 -5×10 19 cm -3 The ion implantation element is B, and the ion implantation depth is 50-300 nm.

[0008] In one embodiment of the present invention, the resistivity of the N-type Si substrate is no more than 0.005 Ω·cm and the thickness is 300 μm-500 μm.

[0009] In one embodiment of the present invention, the thickness of the intrinsic Ge epitaxial layer is 0.1-2 μm.

[0010] In one embodiment of the present invention, the doping concentration of the P-doped Ge layer is 5 × 10⁻⁶. 18 -5×10 19 cm -3 The thickness is 10-200nm.

[0011] In one embodiment of the present invention, the width of the tabletop structure does not exceed 2 mm.

[0012] In one embodiment of the present invention, the material of the passivation layer is at least one of Al2O3, SiO2, and SiN, and the thickness is 1-500 nm.

[0013] In one embodiment of the present invention, the second metal electrode is an electrode located on the lower surface of the N-type Si substrate; or, the second metal electrode is an annular electrode located on the upper surface of the N-type Si substrate, the annular electrode being disposed around the mesa structure.

[0014] This invention provides a method for fabricating a Ge on Si PIN photodetector with a shielding ring, applicable to the Ge on Si PIN photodetector with a shielding ring described in any of the above embodiments. The fabrication method includes: Step 1: Select an N-type Si substrate; Step 2: Perform photolithography on the surface of the N-type Si substrate to define a shielding ring pattern area, wherein the shielding ring pattern area is a closed loop surrounding a preset mesa area; Step 3: Perform ion implantation on the patterned area of ​​the shielding ring, with the implanted element being B, to form a shielding ring with a depth of 50-300 nm; Step 4: Intrinsic Ge epitaxial layer and P-doped Ge layer are sequentially grown on the N-type Si substrate and part of the shielding ring; Step 5: Pattern the intrinsic Ge epitaxial layer and the P-doped Ge layer into a mesa structure using photolithography and etching processes; wherein the sidewall projection of the mesa structure is located between the inner and outer boundaries of the shielding ring, and the horizontal distance between the sidewall projection of the mesa structure and the inner boundary of the shielding ring is greater than 0.5 μm; Step 6: Deposit a passivation layer on the device surface; Step 7: Define and etch contact windows on the passivation layer to expose part of the P-doped Ge layer and part of the N-type Si substrate; Step 8: Form a metal electrode within the contact window to form ohmic contacts with the P-doped Ge layer and the N-type Si substrate, respectively.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The Ge-on-Si PIN photodetector with a shielding ring of the present invention creatively forms a local electric field modulation region in the substrate region below the Ge mesa sidewall by introducing a P-type shielding ring surrounding the active region in an N-type Si substrate. Under reverse bias, the depletion region of the main PN junction (P-type Ge / i-Ge / N-Si) expands laterally. Due to the P-type doping of the shielding ring, it modulates the distribution of the edge electric field in the depletion region, causing the electric field peak to shift from the defective Ge sidewall region to the interior of the shielding ring, effectively shielding the direct effect of the high electric field on the Ge sidewall defects. This structural electric field redistribution fundamentally reduces the carrier tunneling and generation-recombination probability through the Ge sidewall defects, thereby significantly suppressing the sidewall leakage current caused by etching damage at the source.

[0016] 2. The Ge on Si PIN photodetector with a shielding ring of the present invention is formed based on standard photolithography and ion implantation processes, fully compatible with mainstream silicon-based CMOS process flows. The entire device fabrication process (epitaxy, etching, deposition, and metallization) utilizes mature technologies in semiconductor manufacturing, eliminating the need for special or expensive process modules. This facilitates large-scale, low-cost manufacturing on existing production lines and allows for monolithic integration with readout circuits, reducing system complexity.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a Ge on Si PIN photodetector with a shielding ring provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another Ge on Si PIN photodetector with a shielding ring provided in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating a method for fabricating a Ge on Si PIN photodetector with a shielding ring, as provided in an embodiment of the present invention.

[0019] Icons: 1- N-type Si substrate; 2- Intrinsic Ge epitaxial layer; 3- P-doped Ge layer; 4- First metal electrode; 5- Second metal electrode; 6- Shielding ring; 7- Passivation layer. Detailed Implementation

[0020] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a Ge on Si PIN photodetector with a shielding ring and its preparation method based on the present invention.

[0021] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0022] In a first aspect, embodiments of the present invention provide a Ge on Si PIN photodetector with a shielding ring. By introducing a P-type shielding ring in the N-type Si substrate surrounding the active region, the electric field distribution at the edge of the mesa is effectively modulated. By enhancing the bulk electric field and reducing the sidewall electric field, the sidewall leakage current is reduced.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of a Ge on Si PIN photodetector with a shielding ring provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the Ge on Si PIN photodetector with a shielding ring in this embodiment includes: an N-type Si substrate 1, an intrinsic Ge epitaxial layer 2, a P-doped Ge layer 3, a first metal electrode 4, a second metal electrode 5, a shielding ring 6, and a passivation layer 7. The shielding ring 6 is located on the surface of the N-type Si substrate 1 and surrounds the active region of the device; the shielding ring 6 is a P-type region formed by ion implantation. The intrinsic Ge epitaxial layer 2 is located on the upper surface of the N-type Si substrate 1 and part of the upper surface of the shielding ring 6. The P-doped Ge layer 3 is located on the upper surface of the intrinsic Ge epitaxial layer 2, and the intrinsic Ge epitaxial layer 2 and the P-doped Ge layer 3 form a mesa structure. The first metal electrode 4 is located on the upper surface of the P-doped Ge layer 3 and forms an ohmic contact with it. The second metal electrode 5 is located on the lower surface of the N-type Si substrate 1 and forms an ohmic contact with it. The passivation layer 7 is disposed on the sidewall of the mesa structure, the uncovered upper surface of the P-doped Ge layer 3 and the shielding ring 6, and the upper surface of the N-type Si substrate 1.

[0024] Please see Figure 2 , Figure 2 This is a schematic diagram of another Ge on Si PIN photodetector with a shielding ring provided in an embodiment of the present invention. Figure 2 Another arrangement of metal electrodes is shown, in which the second metal electrode 5 is a ring electrode located on the upper surface of the N-type Si substrate 1. The ring electrode is arranged around the mesa structure and is connected to the substrate through a contact window to form an ohmic contact.

[0025] This embodiment features a Ge on Si PIN photodetector with a shielding ring. The shielding ring, a locally p-doped annular region, is embedded in an N-type substrate, and the Ge mesa sidewalls are designed to fall at the center of the ring width. Under reverse bias, in a structure without a shielding ring, the depletion region of the central PIN junction expands outwards. Due to the large etching defects on the Ge mesa sidewalls, a high sidewall electric field leads to a large dark current. However, in this application, the introduction of the shielding ring reduces the longitudinal electric field at the p-Si (shielding ring) / n-Si junction, thereby decreasing the sidewall electric field of Ge. By injecting the shielding ring into the etched interface to form a PIP structure, the effective electric field applied to the Ge sidewall defects is significantly weakened compared to a bulk PIN structure. The tunneling current of charge carriers through defect states and the generation current generated by defects as generation centers are thus strongly suppressed, directly leading to a significant decrease in dark current.

[0026] In an optional embodiment, the inner boundary of the shielding ring 6 is located within the side wall projection of the platform structure, and the outer boundary is located outside the side wall projection of the platform structure. The horizontal distance between the inner boundary and the side wall projection of the platform structure is greater than 0.5 μm. In this embodiment, the width of the shielding ring is related to the diameter of the platform structure, and the overlapping part of the shielding ring and the projection of the platform structure does not exceed 30% of the projected area of ​​the platform structure.

[0027] In this embodiment, the inner boundary of the shielding ring is maintained at a distance greater than 0.5 μm from the sidewall projection of the mesa structure. This safe distance takes into account lithographic alignment errors and the width of the lateral expansion of the depletion region. It ensures that the shielding ring is completely outside the photoelectric conversion active region (i.e., the central region directly below the mesa). Therefore, the process by which photons incident on the central region of the mesa are absorbed by the intrinsic Ge epitaxial layer 2 and generate electron-hole pairs remains completely unaffected. The drift and collection paths of photogenerated carriers under the built-in electric field are also undisturbed, thus ensuring that the core photoelectric parameters of the device, such as quantum efficiency and responsivity, are essentially consistent with those of an ideal mesa device without a shielding ring.

[0028] Optionally, the doping concentration of shielding ring 6 is 1×10⁻⁶. 18 -5×10 19 cm -3 The ion implantation element is boron, and the ion implantation depth is 50-300 nm. This concentration range is sufficient to effectively modulate local conductivity and electric field, but it avoids forming another easily broken sharp PN junction with the N-type Si substrate due to excessive concentration. The depth range ensures that it can participate in depletion region modulation in the vertical direction.

[0029] In an optional embodiment, the resistivity of the N-type Si substrate 1 is no more than 0.005 Ω·cm, for example, it can be 0.0002 Ω·cm or 0.004 Ω·cm. The thickness is 300 μm-500 μm, for example, it can be 300 μm, 400 μm or 500 μm.

[0030] In this embodiment, a high-quality intrinsic (i-type) germanium layer can be grown on the upper surface of the N-type Si substrate 1 by epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) to form an intrinsic Ge layer 2.

[0031] Optionally, the thickness of the intrinsic Ge epitaxial layer 2 is 0.1-2 μm. For example, it can be 100 nm, 200 nm, 1.5 μm, or 2 μm. The intrinsic Ge epitaxial layer 2 is used to absorb near-infrared light and generate photogenerated carriers.

[0032] It is understandable that when a photodetector pursues a large bandwidth, in order to reduce the carrier transit time, the thickness of the intrinsic Ge epitaxial layer 2 needs to be reduced, and its thickness can be controlled at around 100-500nm; while when a photodetector pursues high absorption efficiency, the thickness of the intrinsic Ge epitaxial layer 2 needs to be increased to improve the detector's responsivity.

[0033] For example, when the thickness of the intrinsic Ge epitaxial layer 2 is 200 nm, this thickness can ensure a certain initial light absorption at a communication wavelength of 1550 nm, while the core objective is to minimize the transit time of photogenerated carriers. Although the intrinsic Ge epitaxial layer is very thin, the conduction band shift at the N-Si / i-Ge heterojunction interface can still effectively suppress the reverse injection of electrons from N-Si to the i-Ge region. This heterojunction barrier enables the device in this embodiment to achieve high-speed performance while its dark current is still much lower than that of a homojunction Ge photodiode.

[0034] For example, when the thickness of the intrinsic Ge epitaxial layer 2 is 1.5 μm, this thickness is slightly greater than the absorption depth of Ge at a wavelength of 1550 nm, aiming to ensure that incident photons are fully absorbed. A thicker intrinsic Ge epitaxial layer does not linearly increase the dark current because the depletion region width is mainly determined by the bias voltage and doping concentration. Thanks to the barrier effect of the N-Si / i-Ge heterojunction and the lower defect density of the intrinsic Ge epitaxial layer compared to bulk Ge, the photodetector of this embodiment achieves high responsivity while maintaining a low dark current, thus ensuring excellent signal-to-noise ratio in low-light environments.

[0035] In this embodiment, the doping concentration of the P-doped Ge layer 3 is 5 × 10⁻⁶. 18 -5×10 19 cm -3Optionally, the P-doped Ge layer 3 can also be formed by epitaxial growth, with a thickness of 10-200 nm. The P-doped Ge layer 3, together with the underlying intrinsic Ge epitaxial layer 2 and the N-type Si substrate 1, constitutes a PIN junction.

[0036] In other alternative embodiments, the P-doped Ge layer 3 can also be achieved by ion implantation into the intrinsic Ge epitaxial layer 2, with an ion implantation depth of 100-200 nm. Exemplarily, boron (B) ions are implanted into the upper surface region of the intrinsic Ge epitaxial layer 2 to form a doping concentration of 5 × 10⁻⁶ nm. 19 cm -3 A P-type Ge region with a junction depth of 150 nm is used as the P-doped Ge layer 3. It should be noted that rapid thermal annealing (RTA) is required after ion implantation to activate the dopant and repair lattice damage.

[0037] In this embodiment, the intrinsic Ge epitaxial layer 2 and the P-doped Ge layer 3 are patterned into a mesa structure by an etching process. The width of the mesa structure is no more than 2 mm, and its sidewalls are perpendicular to the substrate surface. For example, the intrinsic Ge epitaxial layer 2 and the P-doped Ge layer 3 can be patterned into a cylindrical mesa structure with a diameter of 100 μm by an etching process.

[0038] It is understandable that if the P-doped Ge layer 3 is achieved by ion implantation into the intrinsic Ge epitaxial layer 2, the implantation pattern of the P-type Ge region will not exceed the mesa area of ​​the intrinsic Ge epitaxial layer 2.

[0039] In this embodiment, the materials of the first metal electrode 4 and the second metal electrode 5 are gold, silver, or aluminum. Exemplarily, a Ti / Au multilayer metal can be deposited on the upper surface of the P-doped Ge layer 3 using electron beam evaporation or thermal evaporation processes to form an ohmic contact with the P-doped Ge layer 3. An Ti / Au multilayer metal is deposited on the lower surface of the N-type Si substrate 1 to form an ohmic contact.

[0040] In this embodiment, the passivation layer 7 is made of at least one of Al2O3, SiO2, and SiN, and has a thickness of 1-500 nm. The passivation layer 7 can be formed by plasma-enhanced chemical vapor deposition (PECVD) to reduce the surface state density and suppress surface leakage current.

[0041] This embodiment of the Ge on Si PIN photodetector with a shielding ring addresses the physical root cause of sidewall leakage from the perspective of bulk electric field distribution, while the passivation layer covering the sidewalls chemically saturates surface dangling bonds, reducing interface state density. The synergistic effect of these two elements provides dual protection. Even with minor defects or incomplete passivation, the electric field shielding effect of the shielding ring effectively suppresses leakage; conversely, good passivation also reduces the initial surface state density that the shielding ring needs to address. This synergistic effect significantly improves the long-term stability and reliability of the device, making it particularly suitable for applications in harsh environments or requiring long lifespans.

[0042] Secondly, embodiments of the present invention provide a method for fabricating a Ge on Si PIN photodetector with a shielding ring, applicable to the Ge on Si PIN photodetector with a shielding ring provided in the first aspect. Please refer to... Figure 3 , Figure 3 This is a schematic diagram illustrating a method for fabricating a Ge on Si PIN photodetector with a shielding ring according to an embodiment of the present invention. Figure 3 As shown, the fabrication method of the Ge on Si PIN photodetector with a shielding ring in this embodiment includes the following steps: Step 1: Select an N-type Si substrate.

[0043] In this embodiment, the resistivity of the N-type Si substrate does not exceed 0.005 Ω·cm. This low-resistivity substrate facilitates the formation of low-resistivity ohmic contacts with the metal electrodes, reducing the series resistance of the device. Optionally, the thickness of the N-type Si substrate is 300-500 μm to provide sufficient mechanical support strength for subsequent processing. The use of a highly doped N-type substrate provides an ideal electron collection terminal for the device, and its low-resistivity characteristics are fundamental to achieving efficient charge extraction and low-power operation.

[0044] After selecting an N-type Si substrate, the silicon wafer is cleaned using a standard RCA cleaning process to remove surface organic matter, metal particles, and the natural oxide layer, resulting in a clean, hydrophilic surface.

[0045] Step 2: Perform photolithography on the surface of the N-type Si substrate to define the shielding ring pattern area, which is a closed loop surrounding the preset mesa area.

[0046] In this embodiment, the width of the ring and the position of its inner boundary are determined according to the design distance, such as the inner boundary being >0.5μm from the edge of the preset platform.

[0047] Step 3: Perform ion implantation in the shielding ring pattern area, with the implanted element being B, to form a shielding ring with a depth of 50-300 nm; In this embodiment, boron (B) ion implantation is performed using photoresist as a mask to form a doping concentration of 1×10⁻⁶ ions at a depth of 50-300 nm on the substrate surface. 18 -5×10 19 cm -3 A P-type shielding ring was used. After implantation, the photoresist was removed and rapid thermal annealing was performed to activate the doping.

[0048] Step 4: Intrinsic Ge epitaxial layer and P-doped Ge layer are sequentially grown on N-type Si substrate and part of the shielding ring.

[0049] Alternatively, an intrinsic Ge epitaxial layer and a P-doped Ge layer can be sequentially epitaxially grown on a substrate containing a shielding ring using chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) processes.

[0050] For example, an intrinsic Ge epitaxial layer with a thickness of 0.1-2 μm can be epitaxially grown on an N-type Si substrate under appropriate temperature and pressure conditions. Subsequently, a boron (B) precursor is introduced, and in-situ doping epitaxy is continued to form a layer with a thickness of 10-200 nm and a doping concentration of approximately 5 × 10⁻⁶. 18 -5×10 19 cm -3 P-doped Ge layer.

[0051] Step 5: Pattern the intrinsic Ge epitaxial layer and the P-doped Ge layer into a mesa structure using photolithography and etching processes; wherein, the sidewall projection of the mesa structure is located between the inner and outer boundaries of the shielding ring, and the horizontal distance between the sidewall projection of the mesa structure and the inner boundary of the shielding ring is greater than 0.5 μm.

[0052] Alternatively, the Ge layer can be etched to expose the Si substrate using reactive ion etching (RIE) to form Ge mesa. It should be noted that photolithographic alignment is crucial in this step, ensuring that the projection of the sidewall of the finally etched mesa falls between the inner and outer boundaries of the shielding ring, and that the distance from the inner boundary is greater than 0.5 μm.

[0053] Step 6: Deposit a passivation layer on the device surface.

[0054] In this embodiment, a SiO2, Al2O3, or SiN layer of no more than 500 nm is deposited as a passivation layer on the entire device surface (including the mesa sidewalls, top, and exposed substrate area) using methods such as plasma-enhanced chemical vapor deposition (PECVD).

[0055] Step 7: Define and etch contact windows on the passivation layer to expose part of the P-doped Ge layer and part of the N-type Si substrate.

[0056] In this embodiment, photoresist is spin-coated again onto the passivation layer surface, and the first electrode contact window (located at the center of the top of the mesa) and the second electrode contact window (located at the edge region of the front side of the substrate) are defined by photolithography. The SiO2 passivation layer in the window region is etched away using buffered oxide etching (BOE) solution or dry etching process, exposing the surface of the underlying P-type heavily doped Ge layer and the surface of the N-type Si substrate.

[0057] Step 8: Form a metal electrode within the contact window to form ohmic contacts with the P-doped Ge layer and the N-type Si substrate, respectively.

[0058] Specifically, a metal (such as Ti / Au) is deposited using an evaporation or sputtering process, and a first metal electrode and a second metal electrode are formed by a lift-off or etching process. Alloying annealing can be performed to optimize the ohmic contact.

[0059] In other alternative embodiments, the second electrode may also be deposited and patterned separately on the back side of the N-type Si substrate.

[0060] The present invention discloses a method for fabricating a Ge on Si PIN photodetector with a shielding ring. The formation of the shielding ring is based on standard photolithography and ion implantation processes, fully compatible with mainstream silicon-based CMOS process flows. The entire device fabrication process (epitaxy, etching, deposition, and metallization) utilizes mature technologies in semiconductor manufacturing, eliminating the need for special or expensive process modules. This facilitates large-scale, low-cost manufacturing on existing production lines and allows for monolithic integration with readout circuits, reducing system complexity.

[0061] For details regarding the fabrication method of the Ge on Si PIN photodetector with shielding ring and its corresponding beneficial effects, please refer to the relevant content on the Ge on Si PIN photodetector with shielding ring provided in the first aspect, which will not be repeated here.

[0062] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0063] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0064] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A Ge on Si PIN photodetector with a shielding ring, characterized in that, include: N-type Si substrate (1); A shielding ring (6) is located on the surface of the N-type Si substrate (1) and surrounds the active region of the device. The shielding ring (6) is a P-type region formed by ion implantation. The intrinsic Ge epitaxial layer (2) is located on the upper surface of the N-type Si substrate (1) and part of the shielding ring (6); A P-doped Ge layer (3) is located on the upper surface of the intrinsic Ge epitaxial layer (2), and the intrinsic Ge epitaxial layer (2) and the P-doped Ge layer (3) form a mesa structure; The first metal electrode (4) is located on the upper surface of the P-doped Ge layer (3) and forms an ohmic contact with the P-doped Ge layer (3); The second metal electrode (5) is located on the surface of the N-type Si substrate (1) and forms an ohmic contact with the N-type Si substrate (1); A passivation layer (7) is disposed on the sidewall of the mesa structure, the upper surface of the uncovered P-doped Ge layer (3) and the shielding ring (6), and the upper surface of the N-type Si substrate (1).

2. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The inner boundary of the shielding ring (6) is located within the side wall projection of the platform structure, and the outer boundary is located outside the side wall projection of the platform structure. The horizontal distance between the inner boundary and the side wall projection of the platform structure is greater than 0.5 μm, and the overlapping part of the shielding ring and the projection of the platform structure does not exceed 30% of the projected area of ​​the platform structure.

3. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The doping concentration of the shielding ring (6) is 1×10⁻⁶. 18 -5×10 19 cm -3 The ion implantation element is B, and the ion implantation depth is 50-300 nm.

4. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The resistivity of the N-type Si substrate (1) is no more than 0.005 Ω·cm and the thickness is 300 μm-500 μm.

5. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The thickness of the intrinsic Ge epitaxial layer (2) is 0.1-2 μm.

6. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The doping concentration of the P-doped Ge layer (3) is 5 × 10⁻⁶. 18 -5×10 19 cm -3 The thickness is 10-200nm.

7. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The width of the tabletop structure does not exceed 2mm.

8. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The passivation layer (7) is made of at least one of Al2O3, SiO2, and SiN, and has a thickness of 1-500 nm.

9. The Ge on Si PIN photodetector with a shielding ring according to claim 1, characterized in that, The second metal electrode (5) is an electrode located on the lower surface of the N-type Si substrate (1); or, the second metal electrode (5) is an annular electrode located on the upper surface of the N-type Si substrate (1), the annular electrode being arranged around the mesa structure.

10. A method for fabricating a Ge on Si PIN photodetector with a shielding ring, characterized in that, The method for fabricating a Ge on Si PIN photodetector with a shielding ring according to any one of claims 1-9 comprises: Step 1: Select an N-type Si substrate; Step 2: Perform photolithography on the surface of the N-type Si substrate to define a shielding ring pattern area, wherein the shielding ring pattern area is a closed loop surrounding a preset mesa area; Step 3: Perform ion implantation on the patterned area of ​​the shielding ring, with the implanted element being B, to form a shielding ring with a depth of 50-300 nm; Step 4: Intrinsic Ge epitaxial layer and P-doped Ge layer are sequentially grown on the N-type Si substrate and part of the shielding ring; Step 5: Pattern the intrinsic Ge epitaxial layer and the P-doped Ge layer into a mesa structure using photolithography and etching processes; wherein the sidewall projection of the mesa structure is located between the inner and outer boundaries of the shielding ring, and the horizontal distance between the sidewall projection of the mesa structure and the inner boundary of the shielding ring is greater than 0.5 μm; Step 6: Deposit a passivation layer on the device surface; Step 7: Define and etch contact windows on the passivation layer to expose part of the P-doped Ge layer and part of the N-type Si substrate; Step 8: Form a metal electrode within the contact window to form ohmic contacts with the P-doped Ge layer and the N-type Si substrate, respectively.

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