Preparation method of vertical structure Micro-LED chip integrated with Ag reflector

Abstract

The invention discloses a preparation method of a vertical-structure Micro-LED chip integrated with an Ag reflector, and the method comprises the following steps: providing an LED epitaxial wafer which comprises a substrate and a GaN-based epitaxial layer; preparing an MgO array on the GaN-based epitaxial layer; the GaN-based epitaxial layer is etched, so that a Micro-LED pixel array can be formed; preparing a passivation layer; preparing a filling layer on the passivation layer; carrying out planarization processing on the filling layer and the passivation layer until the MgO array is exposed; the MgO array is removed; preparing an Ag reflector; preparing a first bonding metal, wherein the first bonding metal completely coats the Ag reflector; providing a driving chip, and preparing second bonding metal; bonding the first bonding metal and the second bonding metal; removing the substrate to expose the first semiconductor layer; and preparing an N electrode on the first semiconductor layer. According to the method, the high etching selection ratio between MgO and GaN is fully utilized, and MgO is used as a mask for etching the GaN-based epitaxial layer, so that the process can be effectively simplified. In addition, the introduction of MgO does not cause the risk of electric leakage, and the method has the advantages of low cost and easy wet removal.

Description

Technical Field

[0001] This application relates to the field of semiconductor display devices, specifically to a method for fabricating a vertical structure Micro-LED chip with an integrated Ag mirror. Background Technology

[0002] Micro-LED chip structures mainly include three types: upright, flip-chip, and vertical. Among them, the vertical structure has significant advantages in terms of current uniformity, light extraction efficiency, heat dissipation performance, miniaturization potential, and system integration due to its design with electrodes placed at the top and bottom ends.

[0003] Metal mirrors are a key technology for improving the light extraction efficiency of LED chips. Silver (Ag) is the preferred mirror material due to its reflectivity of over 95% in the visible light band. However, during chip fabrication, Ag is prone to spheroidization, oxidation, and migration, leading to a decrease in reflectivity and even device failure. This problem becomes more severe as chip size decreases, making it difficult to effectively integrate Ag mirrors into vertical structure Micro-LEDs.

[0004] Chinese invention patent CN202510926032.2 discloses a Micro-LED microdisplay chip containing an Ag reflector and its fabrication method, proposing an integration scheme based on a sacrificial metal layer. The technical solution is as follows: First, a sacrificial metal layer is prepared on an epitaxial layer, and the epitaxial layer is etched to form Micro-LED pixel array units; then, a passivation layer is prepared, making its upper surface flush with the upper surface of the sacrificial metal layer, and a groove is formed after removing the sacrificial metal layer; finally, an Ag reflector is prepared within the groove, and the surface of the Ag reflector is fully covered by a first bonding metal layer, so that the Ag reflector is completely encapsulated, effectively suppressing Ag metal migration, oxidation, and spheroidization, significantly improving the brightness of the Micro-LED microdisplay chip while enhancing its reliability.

[0005] However, the above solutions still have obvious limitations: First, when etching the epitaxial layer to form Micro-LED pixel array units, a mask material prepared by photolithography is needed to cover the sacrificial metal layer, which increases the complexity of the process, reduces production efficiency, and may also damage the sacrificial metal layer during the etching process, causing metal to sputter onto the sidewall of the Micro-LED pixel array unit and causing leakage. Second, the N electrode and P electrode in the fabricated chip are located on the same side, which is not a strictly vertical structure, and there is a problem of current spread. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector, thereby simplifying the process and avoiding the risk of leakage.

[0007] The objective of this invention is achieved as follows: A method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector, comprising the following steps: S1. Provide an LED epitaxial wafer, the LED epitaxial wafer comprising a substrate and a GaN-based epitaxial layer, the GaN-based epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially stacked on the substrate; S2. Fabricate an MgO array on the second semiconductor layer; S3. Using an MgO array as a mask, etch the GaN-based epitaxial layer to form a Micro-LED pixel array; S4. Prepare a passivation layer that covers the entire surface of the LED epitaxial wafer; S5. Prepare a filling layer on the passivation layer. The filling layer fills the gaps in the Micro-LED pixel array and completely covers the Micro-LED pixel array. S6. Planarize the filling layer and passivation layer until the MgO array is exposed; S7. Remove the MgO array and form a groove in the original position of the MgO array; S8. Fabricate an Ag mirror on the second semiconductor layer exposed in the groove; S9. Prepare the first bonding metal, which completely covers the Ag mirror; S10. Provide a driver chip and fabricate a second bonding metal on the driver chip; S11, bonding the first bonding metal and the second bonding metal; S12. Remove the substrate to expose the first semiconductor layer; S13. An N electrode is prepared on the first semiconductor layer.

[0008] The present invention provides a method for fabricating a vertical structure Micro-LED chip with an integrated Ag mirror. This method uses an MgO array instead of a sacrificial metal layer, directly utilizing the MgO array as a mask during the etching of the GaN-based epitaxial layer, thus saving a photolithography step. Furthermore, MgO and GaN exhibit a high etching selectivity, enabling complete etching of the GaN-based epitaxial layer, which is beneficial for fabricating vertical structures. In addition, MgO is an inorganic insulating material, which, compared to a sacrificial metal layer, does not pose a risk of leakage current and has the advantages of low cost and easy wet removal.

[0009] As an alternative to the preparation method of the present invention, the method for preparing the MgO array is a lift-off photolithography process, and the thickness of the MgO array unit is 100nm-400nm.

[0010] As an optional embodiment of the preparation method of the present invention, the etching selectivity ratio of the MgO array to the GaN-based epitaxial layer in step S3 is greater than 10.

[0011] As an optional embodiment of the preparation method of the present invention, the etching method in step S3 is ICP etching, and the etching gas is Cl2 and BCl3, wherein the proportion of Cl2 is 60%-90%.

[0012] As an optional embodiment of the preparation method of the present invention, the Ag reflector is a periodic structure formed by Ni / Ag stack, Pt / Ag stack, or a combination of the two; the total thickness of the Ag reflector is 100nm-300nm, wherein the thickness of a single Ni layer is 2Å-10Å, and the thickness of a single Pt layer is 2Å-10Å.

[0013] As a preferred option among the above-mentioned alternatives, the Ag mirror is a Ni / Ag / Ni / Ag stack; the total thickness of the Ag mirror is 200 nm, wherein the thickness of a single Ni layer is 2 Å-10 Å.

[0014] As an optional method of the preparation method of the present invention, the method for removing the MgO array in step S7 is wet etching, and the etching solution is acetic acid or hydrochloric acid solution.

[0015] As an optional embodiment of the preparation method of the present invention, the N electrode is composed of a full-surface ITO electrode and an independent metal electrode; the material of the independent metal electrode is one or more of Al, Ti, Au, and Cr; the independent metal electrode exists in the form of a grid on the ITO electrode.

[0016] As an optional embodiment of the preparation method of the present invention, the material of the passivation layer is SiN. x One or more combinations of SiO2 and Al2O3; the filling layer material is one or more combinations of polyoxysilane spin-coating material, SU-8, polyimide, and benzocyclobutene.

[0017] As an optional embodiment of the preparation method of the present invention, the method for planarizing the filling layer and passivation layer in step S6 is chemical mechanical polishing.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, some of which will become clear as the description proceeds, and others will be learned by practicing the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below.

[0020] Figure 1 This is a cross-sectional schematic diagram of the LED epitaxial wafer in an embodiment of this application.

[0021] Figure 2 This is a schematic cross-sectional view of the MgO array after preparation in the embodiments of this application.

[0022] Figure 3 This is a cross-sectional schematic diagram of the Micro-LED pixel array formed by etching in an embodiment of this application.

[0023] Figure 4 This is a cross-sectional schematic diagram of the passivation layer after it has been prepared in an embodiment of this application.

[0024] Figure 5 This is a cross-sectional schematic diagram of the filling layer after preparation in an embodiment of this application.

[0025] Figure 6 This is a cross-sectional schematic diagram after removing the filling layer and passivation layer above MgO in the embodiments of this application.

[0026] Figure 7 This is a cross-sectional schematic diagram of the process after removing MgO and preparing the Ag reflector in the embodiments of this application.

[0027] Figure 8 This is a cross-sectional view of the first bonding metal prepared in the embodiments of this application.

[0028] Figure 9 This is a cross-sectional schematic diagram of the driver chip after the second bonding metal is fabricated in an embodiment of this application.

[0029] Figure 10 This is a cross-sectional schematic diagram of the first bonding metal and the second bonding metal after bonding in an embodiment of this application.

[0030] Figure 11 This is a cross-sectional schematic diagram of the ITO electrode after it has been fabricated in an embodiment of this application.

[0031] Figure 12 This is a cross-sectional schematic diagram of the N electrode after its fabrication in an embodiment of this application.

[0032] In the figure: 101-substrate, 102-first semiconductor layer, 103-light-emitting layer, 104-second semiconductor layer, 105-MgO array, 106-Micro-LED pixel array, 107-passivation layer, 108-filling layer, 109-Ag reflector, 110-first bonding metal, 111-ITO electrode, 112-independent metal electrode, 201-driver chip, 202-second bonding metal. Detailed Implementation

[0033] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0034] A method for fabricating a vertically structured Micro-LED chip with an integrated Ag mirror, such as... Figure 1-12 As shown, it includes the following steps: S1. Provide an LED epitaxial wafer, the LED epitaxial wafer includes a substrate 101 and a GaN-based epitaxial layer, the GaN-based epitaxial layer includes a first semiconductor layer 102, a light-emitting layer 103 and a second semiconductor layer 104 sequentially stacked on the substrate 101; S2. Prepare an MgO array 105 on the second semiconductor layer 104; S3. Using MgO array 105 as a mask, etch the GaN-based epitaxial layer to form Micro-LED pixel array 106; S4. Prepare passivation layer 107, which covers the entire surface of the LED epitaxial wafer; S5. A filling layer 108 is prepared on the passivation layer 107. The filling layer 108 fills the gaps of the Micro-LED pixel array 106 and completely covers the Micro-LED pixel array 106. S6. Planarize the filling layer 108 and the passivation layer 107 until the MgO array 105 is exposed. S7. Remove the MgO array 105 and form a groove at the original position of the MgO array 105. S8. An Ag reflector 109 is fabricated on the second semiconductor layer 104 exposed in the groove; S9. Prepare the first bonding metal 110, which completely covers the Ag mirror 109; S10. Provide a driver chip 201 and fabricate a second bonding metal 202 on the driver chip 201; S11, bonding the first bonding metal 110 and the second bonding metal 202; S12. Remove substrate 101 to expose first semiconductor layer 102; S13. An N electrode is prepared on the first semiconductor layer 102.

[0035] In some embodiments, the MgO array 105 is fabricated using a lift-off photolithography process, and the thickness of the MgO array units is 100 nm-400 nm. MgO is an inorganic non-metallic material that is low in cost and easily removed by wet methods. If the MgO thickness is too thin, it is impossible to etch GaN down to the Si substrate; if it is too thick, it increases the cost.

[0036] In some embodiments, the etching selectivity ratio between the MgO array 105 and the GaN-based epitaxial layer in step S3 is greater than 10. The MgO array can be directly used as a mask when etching the GaN-based epitaxial layer, saving a photolithography step and simplifying the process. It eliminates the need to prepare an excessively thick MgO mask to etch GaN up to the Si substrate, which is beneficial for fabricating vertical structures.

[0037] In some embodiments, the etching method in step S3 is ICP etching, and the etching gases are Cl2 and BCl3, wherein Cl2 accounts for 60%-90%. Cl2 achieves efficient etching of GaN through chemical reaction, while BCl3 is used to remove non-volatile etching products. Chemical action dominates the etching of GaN. The etching gases do not react chemically with MgO, and the etching rate of MgO is low.

[0038] In some embodiments, the Ag reflector 109 is a periodic structure formed by Ni / Ag stacks, Pt / Ag stacks, or a combination of both; the total thickness of the Ag reflector 109 is 100nm-300nm, wherein the thickness of a single Ni layer is 2Å-10Å, and the thickness of a single Pt layer is 2Å-10Å. Ni / Ag and Pt / Ag have high reflectivity in the visible light band and can form good ohmic contacts. If the Ag reflector is too thin, light can pass through, and its full potential cannot be realized; if the reflector is too thick, it will increase costs. Ni and Pt can solve the problem of poor adhesion between Ag and GaN. Ni and Pt have poor light transmittance, and excessive thickness will reduce the amount of light reaching the Ag reflector.

[0039] In some embodiments, the Ag reflector 109 is a Ni / Ag / Ni / Ag stack; the total thickness of the Ag reflector 109 is 200 nm, wherein the thickness of a single Ni layer is 2 Å-10 Å. The Ni / Ag / Ni / Ag stack provides dual protection, preventing Ag reflector failure due to Ni / Ag oxidation. When the Ni / Ag far from GaN oxidizes and fails, the Ni / Ag closer to GaN can still perform its reflective function.

[0040] In some embodiments, the method for removing the MgO array 105 in step S7 is wet etching, using an acetic acid or hydrochloric acid solution as the etching solution. MgO reacts with acetic acid or hydrochloric acid solution, allowing for rapid removal at low cost without damaging the chip.

[0041] In some embodiments, the N-electrode consists of a full-surface ITO electrode 111 and a separate metal electrode 112; the material of the separate metal electrode 112 is one or more of Al, Ti, Au, and Cr; the separate metal electrode 112 exists in a grid form on the ITO electrode 111. The ITO electrode 111 has both high transparency and moderate conductivity, while the separate metal electrode 112 has high conductivity but low transparency. The two work together to ensure both light transmission and conductivity.

[0042] In some embodiments, the passivation layer 107 is made of SiN. x The filler layer 108 is made of one or more of the following: SiO2, Al2O3, SiN. xAll three materials—SiO2, Al2O3, and MgO—are insulating, capable of passivating sidewall defects and simultaneously encapsulating the luminescent layer to prevent leakage. The filler layer must be higher than the MgO layer by a certain height to ensure that after polishing, the passivation layer and filler layer always completely encapsulate the luminescent layer, preventing leakage.

[0043] In some embodiments, the method for planarizing the filling layer 108 and the passivation layer 107 in step S6 is chemical mechanical polishing (CMP). CMP combines physical and chemical methods to achieve surface planarization. The planarized surface is crucial for subsequent photolithography processes, and the precision of the photolithography process directly affects the manufacturing quality and performance of the chip.

[0044] The following are some embodiments of this application. Example 1

[0045] This embodiment provides a method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector, including the following steps: Step S1: Provide an LED epitaxial wafer. The LED epitaxial wafer includes a substrate 101 and a GaN-based epitaxial layer. The GaN-based epitaxial layer includes a first semiconductor layer 102, a light-emitting layer 103, and a second semiconductor layer 104 sequentially stacked on the substrate 101, such as... Figure 1 As shown. The substrate 101 is a silicon substrate, the first semiconductor layer 102 is an N-type GaN layer, the light-emitting layer 103 is an InGaN / GaN multiple quantum well layer, and the second semiconductor layer 104 is a P-type GaN layer.

[0046] First, clean the LED epitaxial wafer: immerse it in acetone and alcohol in sequence and sonicate for 5 minutes, then rinse it with deionized water for 6 minutes and spin dry for later use.

[0047] Step S2: Prepare an MgO array 105 on the second semiconductor layer 104 by a stripping method, such as... Figure 2 As shown.

[0048] Specifically, an array pattern is defined on the second semiconductor layer 104 using photolithography. Then, a 300 nm thick MgO film is prepared on the surface of the second semiconductor layer 104 using electron beam evaporation. Finally, the MgO on the photoresist is removed by a stripping method to form an MgO array 105.

[0049] Step S3: Using an inductively coupled plasma etching (ICP) machine with the MgO array 105 as a mask, the GaN-based epitaxial layer (second semiconductor layer 104, light-emitting layer 103, and first semiconductor layer 102) in the areas not protected by the MgO array is removed to form a Micro-LED pixel array 106, as shown below. Figure 3As shown. The specific etching process is as follows: chamber pressure 4 mTorr / etching gas 100 sccm Cl2 and 20 sccm BCl3 / upper electrode power 330 W / lower electrode power 180 W.

[0050] Step S4: Prepare passivation layer 107, which covers the entire surface of the LED epitaxial wafer, such as... Figure 4 As shown.

[0051] Specifically, ALD (atomic layer deposition) is first used to deposit 50nm of Al2O3 on the entire surface of the LED epitaxial wafer, and then PECVD is used to deposit 150nm of SiO2 on the Al2O3.

[0052] Step S5: A filling layer 108 is prepared on the passivation layer 107. The filling layer 108 fills the gaps in the Micro-LED pixel array 106 and completely covers the Micro-LED pixel array 106, forming a planarized surface, such as... Figure 5 As shown.

[0053] Specifically, a layer of polyoxysilane spin-coating material (SOG) is spin-coated at 6000 rpm. The SOG fills the gaps in the Micro-LED pixel array 106 and completely covers the Micro-LED pixel array 106, forming a planarized surface. Then, it is pre-baked at 150°C for 60 seconds, followed by 60 seconds of exposure, and finally cured at 180°C for 1 hour to complete the preparation of the filling layer 108.

[0054] Step S6: Planarize the filler layer 108 and passivation layer 107 using chemical mechanical polishing (CMP) until the MgO array 105 is exposed, as shown. Figure 6 As shown.

[0055] Step S7: Use a solution of hydrochloric acid and water in a volume ratio of 1:1 to corrode and remove the MgO array 105, forming a groove at the original position of the MgO array 105.

[0056] Step S8: An Ag reflector 109 is fabricated on the exposed second semiconductor layer 104 within the groove using a lift-off method, such as... Figure 7 As shown, the Ag reflector 109 is composed of four metal layers: Ni / Ag / Ni / Ag, with thicknesses of 2 Å / 1000 Å / 7 Å / 1000 Å, respectively. The function of the Ag reflector 109 is to reflect the light emitted from the light-emitting layer 103 toward the second semiconductor layer 104 back and out through the first semiconductor layer 102.

[0057] Step S9: Prepare the first bonding metal 110. The size of the first bonding metal 110 is larger than the size of the Ag reflector 109, so that the first bonding metal 110 completely covers the Ag reflector 109. Figure 8 As shown. The first bonding metal 110 is made of Cr / Pt / Au. The first bonding metal 110 prevents the Ag reflector 109 from contacting the outside world, avoiding oxidation of the Ag reflector 109 and inhibiting Ag migration and spheroidization. Furthermore, oxygen plasma cannot be used to treat the surface during the preparation of the first bonding metal 110.

[0058] Step S10: Provide a driver chip 201, and fabricate a second bonding metal 202 on the driver chip 201, such as... Figure 9 As shown, the second bonding layer metal 202 is Cr / Pt / Au.

[0059] Step S11: Using a bonding machine, hot-press bonding of the first bonding metal 110 and the second bonding metal 202 is performed to achieve bonding between the driver chip 201 and the LED epitaxial wafer, as follows. Figure 10 As shown. The bonding pressure is 400 kg, the bonding temperature is 300 °C, and the time is 1800 s.

[0060] Step S12: First, use mechanical grinding to thin the substrate 101 to less than 100um, and then use deep silicon to dry etch away the remaining substrate to expose the first semiconductor layer 102.

[0061] Step S13: First, deposit an ITO electrode 111 on the surface of the first semiconductor 102, such as... Figure 11 As shown. Then, an independent metal electrode 112 is fabricated on the ITO electrode 111. The ITO electrode 111 and the independent metal electrode 112 constitute the N-electrode. The ITO electrode has a visible light transmittance exceeding 80% and low sheet resistance, enabling uniform current diffusion across the LED emitting surface. The independent metal electrode 112 is made of Ti / Au and exists in a grid form on the ITO electrode 111, further dispersing the current on the ITO surface to the LED chip emitting area, avoiding excessively high local current density. The ITO electrode 111 combines high transparency with moderate conductivity, while the independent metal electrode 112 has high conductivity but low transparency. Their synergistic effect ensures both light transmittance and conductivity.

[0062] It should be noted that the embodiments of this application do not specifically limit the order of steps in the fabrication method of Micro-LED chips. The embodiments of the fabrication method in this application only describe the fabrication process or steps. Device structures, shapes, and materials not described can be referred to the above embodiments of Micro-LED chips, and will not be repeated here. The obtained Micro-LED chips can be further used in electronic devices, including but not limited to: augmented reality (AR) display devices, virtual reality (VR) display devices, near-eye displays (NEDs), and head-up displays (HUDs).

[0063] The present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a vertically structured Micro-LED chip with an integrated Ag mirror, characterized in that, Includes the following steps: S1. Provide an LED epitaxial wafer, the LED epitaxial wafer comprising a substrate and a GaN-based epitaxial layer, the GaN-based epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially stacked on the substrate; S2. Fabricate an MgO array on the second semiconductor layer; S3. Using an MgO array as a mask, etch the GaN-based epitaxial layer to form a Micro-LED pixel array; S4. Prepare a passivation layer, wherein the passivation layer covers the entire surface of the LED epitaxial wafer; S5. A filling layer is prepared on the passivation layer, the filling layer filling the gaps of the Micro-LED pixel array and completely covering the Micro-LED pixel array; S6. Planarize the filling layer and passivation layer until the MgO array is exposed; S7. Remove the MgO array and form a groove in the original position of the MgO array; S8. Fabricate an Ag mirror on the second semiconductor layer exposed in the groove; S9. Prepare a first bonding metal, which completely covers the Ag mirror; S10. Provide a driver chip and fabricate a second bonding metal on the driver chip; S11, bonding the first bonding metal and the second bonding metal; S12. Remove the substrate to expose the first semiconductor layer; S13. An N electrode is prepared on the first semiconductor layer.

2. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The MgO array is prepared by a lift-off photolithography process, and the thickness of the MgO array unit is 100nm-400nm.

3. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: In step S3, the etching selectivity ratio between the MgO array and the GaN-based epitaxial layer is greater than 10.

4. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 3, characterized in that: In step S3, the etching equipment is ICP etching, and the etching gases are Cl2 and BCl3, with Cl2 accounting for 60%-90%.

5. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The Ag reflector is a periodic structure formed by Ni / Ag stacks, Pt / Ag stacks, or a combination of both; the total thickness of the Ag reflector is 100nm-300nm, wherein the thickness of a single Ni layer is 2Å-10Å, and the thickness of a single Pt layer is 2Å-10Å.

6. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 5, characterized in that: The Ag reflector is a Ni / Ag / Ni / Ag stack; the total thickness of the Ag reflector is 200 nm, wherein the thickness of a single Ni layer is 2 Å-10 Å.

7. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The method for removing the MgO array in step S7 is wet etching, and the etching solution is acetic acid or hydrochloric acid solution.

8. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The N electrode consists of a full-surface ITO electrode and independent metal electrodes; the independent metal electrodes are made of one or more of Al, Ti, Au, and Cr; the independent metal electrodes exist in a grid form on the ITO electrode.

9. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The passivation layer is made of SiN. x The filling layer is made of one or more of the following: SiO2, Al2O3; the filling layer is made of one or more of the following: polyoxysilane spin-coating material, SU-8, polyimide, benzocyclobutene.

10. The method for fabricating a vertical structure Micro-LED chip with an integrated Ag reflector according to claim 1, characterized in that: The method for planarizing the filling layer and passivation layer in step S6 is chemical mechanical polishing.

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