Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package may include a first semiconductor chip having a device region and a dummy region surrounding the device region in a plan view; a second semiconductor chip on an upper surface of the device region of the first semiconductor chip; and a molding layer covering the second semiconductor chip on the first semiconductor chip, in which the first semiconductor chip includes: a first semiconductor substrate; a first lower pad disposed on a lower surface of the first semiconductor substrate; a first upper insulating layer including a first insulating layer and a second insulating layer, and disposed on an upper portion of the first semiconductor substrate; and a first upper pad and a trench region disposed within the second insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0138024, filed on October 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package comprising stacked semiconductor chips. Background Technology

[0004] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, in a semiconductor package, after the semiconductor chip is mounted on a printed circuit board, it is electrically connected using bonding leads or bumps. With the development of the electronics industry, there is a growing need for semiconductor packages to implement high-capacity characteristics. Furthermore, as electronic products become smaller, the demand for smaller semiconductor packages is increasing. Summary of the Invention

[0005] The present invention provides a semiconductor package with improved reliability.

[0006] Furthermore, the technical spirit of the present invention is not limited to the problems mentioned herein, and those skilled in the art will clearly understand from the description herein other problems not mentioned.

[0007] According to some aspects, a semiconductor package is provided, the semiconductor package may include: a first semiconductor chip that may have a device region and a pseudo-region surrounding the device region in a plan view; one or more second semiconductor chips located on an upper surface of the device region of the first semiconductor chip; and a molding layer that covers at least a portion of the one or more second semiconductor chips on the first semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor substrate; and a first lower pad disposed on the lower surface of the first semiconductor substrate;

[0008] A first upper insulating layer, comprising a first insulating layer and a second insulating layer and disposed on the upper portion of a first semiconductor substrate; and a first upper pad and trench region disposed within the second insulating layer.

[0009] According to some aspects, a semiconductor package is provided, the semiconductor package including: a first semiconductor chip; a second semiconductor chip located on an upper surface of the first semiconductor chip; and a molding layer covering at least a portion of the second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor substrate; a first upper insulating layer including a first insulating layer and a second insulating layer disposed on the upper surface of the first semiconductor substrate; a first upper pad disposed within the second insulating layer; a first lower pad disposed on a lower surface of the first semiconductor substrate; and a trench region disposed within the second insulating layer, wherein each of the second semiconductor chips includes: a second semiconductor substrate; a second lower pad disposed on the lower surface of the second semiconductor substrate; and a second upper pad disposed on an upper portion of the second semiconductor substrate, and wherein the width of the second semiconductor chip in the horizontal direction is less than the longest width of the trench region in the horizontal direction.

[0010] According to some aspects, a semiconductor package is provided, which may include a first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip, a molding layer covering one or more sidewalls of the second semiconductor chip on the first semiconductor chip, and a lower bump disposed on a lower surface of the first semiconductor chip and electrically connected to a first lower pad. The first semiconductor chip includes: a first semiconductor substrate; a first upper insulating layer including a first insulating layer and a second insulating layer and disposed on the upper surface of the first semiconductor substrate; a first via penetrating the first semiconductor substrate; a first wiring pattern electrically connected to the first via and disposed within the first insulating layer; a first upper pad disposed within the second insulating layer and electrically connected to the first wiring pattern; a trench region disposed within the second insulating layer; and a first lower pad. The second semiconductor chip comprises: a second semiconductor substrate; a second upper insulating layer disposed on the upper surface of the second semiconductor substrate; a second lower insulating layer disposed on the lower surface of the second semiconductor substrate; a second upper pad disposed within the second upper insulating layer; and a second lower pad disposed within the second lower insulating layer. In a plan view, when the area of ​​the trench region overlapping with the second semiconductor chip is referred to as the first region and the area of ​​the trench region not overlapping with the second semiconductor chip is referred to as the second region, the trench region has a stepped structure in which the vertical dimensions of the first region and the second region are different from each other, and wherein the vertical length of the second region is 1 μm, and the vertical length of the first region is less than half the vertical length of the second region.

[0011] According to some aspects, a method for manufacturing a semiconductor package is provided, the method comprising: the step of disposed of one or more second semiconductor chips on a first semiconductor chip; and the step of bonding the first semiconductor chip and the lowermost of the one or more second semiconductor chips, wherein the first semiconductor chip may include: a first semiconductor substrate; a first upper insulating layer disposed on an upper surface of the first semiconductor substrate; a first upper pad disposed within the first upper insulating layer; a first lower pad disposed on a lower surface of the first semiconductor substrate; and a trench region disposed within the first upper insulating layer.

[0012] In some embodiments, the trench region may have a first portion and a second portion, the first portion being laterally located inside the periphery of the second semiconductor chip, and the second portion being laterally located outside the periphery of the second semiconductor chip. The first portion of the trench region may have a first depth, and the second portion of the trench region may have a second depth, wherein the first depth is less than the second depth.

[0013] In some embodiments, the trench region may have a variable depth that increases laterally as it moves laterally from the inner edge of the trench region toward the outer edge of the trench region, and wherein the trench region is positioned to laterally overlap with the periphery of the second semiconductor chip.

[0014] In some embodiments, each of one or more second semiconductor chips may include: a second semiconductor substrate; a second lower pad disposed on a lower surface of the second semiconductor substrate; and a second upper pad disposed on an upper portion of the second semiconductor substrate. In some embodiments, bonding may include a hybrid bonding process.

[0015] In some embodiments, the method may further include providing a molding layer that covers at least a portion of one or more second semiconductor chips on a first semiconductor chip. Attached Figure Description

[0016] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 This is a plan view showing a semiconductor package according to an embodiment;

[0018] Figure 2 It is according to the embodiment along Figure 1 A cross-sectional view taken from line I-I';

[0019] Figure 3 This illustrates an embodiment. Figure 2 A magnified view of region II;

[0020] Figure 4This illustrates an embodiment. Figure 2 A magnified view of region II;

[0021] Figure 5 This illustrates an embodiment. Figure 2 Another enlarged view of region II;

[0022] Figure 6 This illustrates an embodiment. Figure 2 A magnified view of region III;

[0023] Figure 7 This illustrates an embodiment. Figure 3 A magnified view of region A;

[0024] Figures 8 to 10 This illustrates an embodiment. Figure 3 A magnified view of region A;

[0025] Figure 11 This is a plan view illustrating a trench region included in a semiconductor package according to an embodiment;

[0026] Figures 12 to 15 This is a plan view showing the trench region according to an embodiment; and

[0027] Figure 16 This is a cross-sectional view showing a semiconductor package according to an embodiment. Detailed Implementation

[0028] The inventive concept can be modified in various forms and can have various embodiments. In this regard, the inventive concept will now be described in detail with respect to embodiments illustrated in the accompanying drawings. However, this is not intended to limit this embodiment to a particular form of disclosure. Embodiments of the inventive concept are capable of various modifications and can be embodied in many different forms.

[0029] All examples or example terms are simply used to explain the technical scope of this disclosure in detail, and therefore the scope of this disclosure is not limited by examples or example terms, provided that they are not defined by the claims.

[0030] Unless otherwise specifically stated, in this specification, the vertical direction is defined as Z.

[0031] The direction, and the first horizontal direction and the second horizontal direction can be defined as horizontal directions perpendicular to the Z direction, respectively. The first horizontal direction can be referred to as the X direction, and the second horizontal direction can be referred to as the Y direction. Vertical horizontal can refer to the height level in the vertical direction (e.g., the Z direction). The horizontal width in the first horizontal direction can refer to the length in the horizontal direction (e.g., the X direction and / or the Y direction), and the vertical length can refer to the length in the vertical direction (e.g., the Z direction).

[0032] As described herein, a semiconductor package with improved reliability is provided. In some cases, one or more semiconductor chips in a semiconductor package may be affected by warping due to biasing of metal components therein. As an example, warping of metal wiring may occur during an annealing process. Such warping can affect the bonding process, resulting in undesirable defects including cracks. The inventors have recognized that such undesirable effects can be prevented by incorporating one or more trench regions into the semiconductor package. By utilizing one or more trenches formed therein, the semiconductor package can have improved reliability because bonding defects and / or crack defects caused by warping can be mitigated.

[0033] Figure 1 This is a plan view showing the semiconductor package 10 according to an embodiment. Figure 2 It is according to the embodiment along Figure 1 The cross-sectional view taken from line I-I'.

[0034] Reference Figure 1 and Figure 2 The semiconductor package 10 may include a memory package such as a high-bandwidth memory (HBM) package. The semiconductor package 10 may include a chip stack package. The semiconductor package 10 may include a first semiconductor chip 100, a second semiconductor chip 200, a molding layer 400, and a lower bump 500.

[0035] The first semiconductor chip 100 may be a lower semiconductor chip. The first semiconductor chip 100 may be a logic chip or a buffer chip. The first semiconductor chip 100 may include a first semiconductor substrate 110, a first lower pad 150, a first lower insulating layer 121, a first wiring pattern 123, a first via 170, a first upper insulating layer 130, and a first upper pad 160. A first horizontal direction (e.g., the X direction) may be parallel to the lower surface of the first semiconductor substrate 110. A second horizontal direction (e.g., the Y direction) may be parallel to the lower surface of the first semiconductor substrate 110 and intersect the first horizontal direction (e.g., the X direction). For example, the second horizontal direction (e.g., the Y direction) may be perpendicular to the first horizontal direction (e.g., the X direction). For example, a third direction (e.g., the Z direction) may be perpendicular to the lower surface of the first semiconductor substrate 110. A third direction (e.g., the Z direction) may be a vertical direction.

[0036] The first semiconductor chip 100 may have a thickness ranging from approximately 30 μm to approximately 80 μm. Because the thickness of the first semiconductor chip 100 is 80 μm or less, the semiconductor package 10 can be miniaturized. Because the thickness of the first semiconductor chip 100 is 30 μm or greater, damage to the first semiconductor chip 100 can be prevented during the manufacturing process of the semiconductor package 10. The thickness of the first semiconductor chip 100 may correspond to the gap between the lower and upper surfaces of the first semiconductor chip 100.

[0037] Multiple second semiconductor chips 200 may be disposed on a first semiconductor chip 100. The multiple second semiconductor chips 200 may be stacked vertically on the upper surface of the first semiconductor chip 100. In this specification, unless otherwise stated, "vertically" may mean parallel to the vertical direction (e.g., the Z direction). The multiple second semiconductor chips 200 may be upper semiconductor chips. The multiple second semiconductor chips 200 may be identical semiconductor chips. Each of the second semiconductor chips 200 may be a memory chip or memory core chip, such as a DRAM chip. For example, each of the second semiconductor chips 200 may be a high-bandwidth memory (HBM) chip. The storage capacity of each of the second semiconductor chips 200 may be the same as each other. The second semiconductor chips 200 may have the same dimensions as each other. For example, each of the second semiconductor chips 200 may have substantially the same width as each other. The sidewalls of the second semiconductor chips 200 may be vertically aligned with each other. However, the thickness of the uppermost second semiconductor chip 200 may be greater than the thickness of the remaining second semiconductor chips 200. The thickness of the remaining second semiconductor chips 200 may be substantially the same as each other.

[0038] The width of a component can be measured in a first horizontal direction (e.g., the X direction). The thickness of a component can be measured in a vertical direction (e.g., the Z direction). The fact that the width, thickness, dimensions, and horizontality of a particular component are the same indicates that the range of errors that may occur during the process is the same. The second semiconductor chip 200 can be a semiconductor chip of a different type from the first semiconductor chip 100. The width of the first semiconductor chip 100 can be greater than the width of the second semiconductor chip 200.

[0039] The number of the second semiconductor chip 200 can be varied, and is not limited to... Figure 2 The illustration is shown below. For example, the semiconductor package 10 may include a single second semiconductor chip 200 or four or more second semiconductor chips 200. For example, the semiconductor package 10 may include eight, twelve, or sixteen second semiconductor chips 200.

[0040] The components of the first semiconductor chip 100 will be described below.

[0041] The first semiconductor substrate 110 may be a first substrate. The first semiconductor substrate 110 may have a chip region CR and a pseudo-region DR in a plan view. The chip region CR may correspond to a component region. The chip region CR may be a device region. The chip region CR of the first semiconductor substrate 110 may be the central region of the first semiconductor substrate 110. The pseudo-region DR of the first semiconductor substrate 110 may be an edge region of the first semiconductor substrate 110. The pseudo-region DR of the first semiconductor substrate 110 may surround the chip region CR in a plan view. For example, the pseudo-region DR of the first semiconductor substrate 110 may be disposed between the chip region CR and the outer wall of the first semiconductor substrate 110. The first semiconductor substrate 110 may include a semiconductor material, such as silicon, germanium, or silicon-germanium. The first semiconductor substrate 110 may include a crystalline semiconductor material. The first semiconductor chip 100 may include, for example, Figure 6 The first integrated circuit 115 shown is illustrated. (Refer to...) Figure 8 The first integrated circuit 115 is described in detail.

[0042] The outer wall of the first semiconductor chip 100 may include a first outer wall 110a, a second outer wall 110b, a third outer wall, and a fourth outer wall. The second outer wall 110b may be adjacent to the first outer wall 110a. The third outer wall may be opposite to the first outer wall 110a and adjacent to the second outer wall 110b. The fourth outer wall may be opposite to the second outer wall 110b and adjacent to the first outer wall 110a and the third outer wall.

[0043] The first semiconductor chip 100 may include a first lower pad 150 disposed on the lower surface of the first semiconductor substrate 110. A first lower insulating layer 121 is located on the lower surface of the first semiconductor substrate 110 and may cover the first lower pad 150. The first lower insulating layer 121 may include a silicon-based insulating material. The silicon-based insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbonitride. The first lower insulating layer 121 may include multiple stacked layers.

[0044] The first wiring pattern 123 may be disposed within the first upper insulating layer 130. The first upper insulating layer 130 may include multiple layers. In some embodiments, the first upper insulating layer 130 may include a first insulating layer 131 and a second insulating layer 132. However, this is only for some embodiments, and the first upper insulating layer 130 may include three or more layers. More specifically, the first wiring pattern 123 may be disposed within the first insulating layer 131. The first wiring pattern 123 may be electrically connected to the first integrated circuit 115 (e.g., see...). Figure 6 At least one of the first through hole 170 and the first through hole 170.

[0045] The first wiring pattern 123 may include a first aluminum wiring pattern 124 located on its upper portion. The first aluminum wiring pattern 124 may include aluminum and a material different from the first wiring pattern 123. A component electrically connected to a semiconductor chip may mean that the component is electrically connected to at least one of the through-holes of the semiconductor chip and an integrated circuit. In this specification, electrical connection / connection means direct connection / contact or indirect connection / contact through another conductive component.

[0046] The first lower pad 150 can be disposed on the lower surface of the first semiconductor chip 100. For example, the first lower pad 150 can be disposed on the lower surface of the first lower insulating layer 121. The vertical level of the upper surface of the first lower insulating layer 121 can be higher than or the same as the vertical level of the upper surface of the first lower pad 150. That is, the first lower pad 150 can be covered by the first lower insulating layer 121.

[0047] In an example embodiment, the first lower insulating layer 121 may comprise an inorganic insulating material subjected to compressive stress. In an example embodiment, the first lower insulating layer 121 may be formed to have compressive stress using a plasma-enhanced chemical vapor deposition (PECVD) process. For example, the first lower insulating layer 121 may comprise at least one of oxides and nitrides. For example, the first lower insulating layer 121 may comprise at least one of silicon oxide and silicon nitride. To adjust the compressive stress of the first lower insulating layer 121, the process conditions of the PECVD process used to form the first lower insulating layer 121 and / or the thickness of the first lower insulating layer 121 may be controlled.

[0048] The first lower pad 150 may be electrically connected to the first via 170. The upper surface of the first lower pad 150 may be in physical contact with the first via 170. The first lower pad 150 may include, for example, aluminum or copper. The lower surface of the first semiconductor chip 100 may include the lower surface of the first lower pad 150 and the lower surface of the first lower insulating layer 121.

[0049] The lower bump 500 may be disposed on the lower surface of the first semiconductor chip 100. For example, the lower bump 500 may be disposed on the lower surface of the first lower pad 150 and may be electrically connected to the first lower pad 150. Therefore, the lower bump 500 may be electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200 through the first lower pad 150. The lower bump 500 may include a conductive post 501 and a solder ball 503. The conductive post 501 may be disposed between the first lower pad 150 and the solder ball 503 and may be electrically connected to the first lower pad 150 and the solder ball 503. The conductive post 501 may include a material different from the material of the first lower pad 150 and the solder ball 503. For example, the conductive post 501 may include copper and / or a copper alloy. The solder ball 503 may include a solder material. The solder material may include tin (Sn), silver (Ag), zinc (Zn), and / or alloys thereof.

[0050] The first semiconductor chip 100 may further include a guide ring 127. The guide ring 127 may be disposed within the first upper insulating layer 130. The guide ring 127 may have a closed loop in a plan view. The guide ring 127 may be disposed in a plan view between the dummy region DR of the first semiconductor substrate 110 and the first wiring pattern 123. The guide ring 127 may protect the first wiring pattern 123 or the first integrated circuit 115 (e.g., see...). Figure 6 It is protected from external contamination or external stress. The first guide ring 127 may include, but is not limited to, a metallic material.

[0051] The first via 170 may be disposed within the first semiconductor substrate 110 and may penetrate and / or pass through the first semiconductor substrate 110. The first via 170 may also penetrate at least a portion of the first lower insulating layer 121. The first via 170 may be electrically connected to the first wiring pattern 123. The first via 170 may be electrically connected to the first integrated circuit 115 (e.g., see [link to integrated circuit]) via the first wiring pattern 123. Figure 6 The first through-hole 170 may include a metal, such as copper, tungsten, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0052] The first upper insulating layer 130 can be disposed on the upper surface of the first semiconductor substrate 110. The upper surface of the first semiconductor substrate 110 can face the lower surface of the first insulating layer 131. The upper surface of the first semiconductor substrate 110 can be a back surface. The first via 170 can also be disposed within the first upper insulating layer 130. The first upper insulating layer 130 can cover the upper sidewall of the first via 170.

[0053] The first upper insulating layer 130 may include a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 may cover the upper surface of the first semiconductor substrate 110. The first insulating layer 131 may be multilayer or single-layer. The first insulating layer 131 may include a silicon-based insulating material. The first wiring pattern 123 may be disposed within the first insulating layer 131.

[0054] The second insulating layer 132 may be disposed on the first insulating layer 131. The second insulating layer 132 may include a material different from the first insulating layer 131. As an example, the second insulating layer 132 may include a silicon-based insulating material. As another example, the second insulating layer 132 may include an insulating polymer such as polyimide. The upper surface of the second insulating layer 132 may be the upper surface of the first semiconductor chip 100.

[0055] A first upper pad 160 may be disposed on the upper surface of the first semiconductor substrate 110. The first upper pad 160 may be disposed above the first via 170 and electrically connected to the first via 170. In this specification, the horizontal of a component may refer to vertical horizontality. The first upper pad 160 may be disposed within the first upper insulating layer 130. More specifically, the first upper pad 160 may be disposed within the second insulating layer 132. A portion of the lower surface and side surface of the first upper pad 160 may be covered by the first upper insulating layer 130. The upper surface of the first upper pad 160 may not be covered by the first upper insulating layer 130. The first upper pad 160 may include a metal such as copper. The upper surface of the first semiconductor chip 100 may include the upper surface of the first upper insulating layer 130 and the upper surface of the first upper pad 160.

[0056] A change in temperature applied to the first semiconductor chip 100 may cause warping of the first semiconductor chip 100. For example, while the first semiconductor chip 100 is heated from a first temperature to a second temperature, the first semiconductor chip 100 may deform into an upward bulge due to the rapid thermal expansion of the metal wiring pattern of the first wiring pattern 123. Furthermore, the second semiconductor chip 200 may also deform into an upward bulge or a downward recess. To prevent cracking due to warping of the first semiconductor chip 100 or the second semiconductor chip 200, the first semiconductor chip 100 may include a trench region 300. The trench region 300 may be disposed within the second insulating layer 132. Figure 2 The trench region 300 is depicted as being located only within the second insulating layer 132. However, if the depth of the trench region 300 increases, it may be located not only within the second insulating layer 132 but also within the first insulating layer 131. At least a portion of the trench region 300 may overlap with the second semiconductor chip 200. The remaining portion of the trench region 300 may overlap with the molding layer 400. In some embodiments, the trench region may overlap with the entire periphery or a portion of the periphery of the second semiconductor chip. From a plan view, the trench region 300 can be divided into a first region and a second region. In some embodiments, the region of the trench region 300 that overlaps with the second semiconductor chip 200 may be referred to as the first region. In some embodiments, the region of the trench region 300 that does not overlap with the second semiconductor chip 200 may be referred to as the second region. The second region may overlap with the molding layer 400. The first and second regions may have different vertical levels. In some embodiments, when the vertical levels of each of the first and second regions are different, the trench region 300 may have a stepped structure. That is, a trench region 300, including a first region and a second region, can be formed with a double-step difference.

[0057] In the accompanying drawings, trench region 300 and molding layer 400 are shown as distinct, but trench region 300 and molding layer 400 may be filled with the same material. In some embodiments, trench region 300 and molding layer 400 may be filled with resin, epoxy molding compound (EMC), or any combination thereof. In some embodiments, a first region that overlaps only with the second semiconductor chip 200 may be filled with resin. In some embodiments, a second region that does not overlap with the second semiconductor chip 200 may be filled with EMC. In some embodiments, both the first and second regions may be filled with the same material, and the same material may represent a mixture of resin and EMC.

[0058] The bonding strength can be improved by filling the gaps at the edges or corners of the areas where the first semiconductor chip 100 and the second semiconductor chip 200 contact each other while filling the trench area 300 with resin or EMC.

[0059] By forming the trench region 300, when multiple second semiconductor chips 200 are stacked on the upper surface of the first semiconductor chip 100, which can serve as the core chip, the direct impact between the first upper insulating layer 130 and the second semiconductor chip 200 can be mitigated, thereby improving one or more defects caused by cracks.

[0060] The molding layer 400 may cover the first upper insulating layer 130. Unlike the figures, the upper surface of the first semiconductor substrate 110 may be the front surface, and the back surface of the first semiconductor substrate 110 may be the front surface.

[0061] In this case, the first integrated circuit 115 and the first wiring pattern 123 can be arranged on the back surface of the first semiconductor substrate 110. The components of the second semiconductor chip 200 will be described below.

[0062] like Figure 2 As shown, the second semiconductor chip 200 can be disposed on the first semiconductor chip 100.

[0063] For example, a second semiconductor chip 200 may be disposed on a chip region CR of a first semiconductor substrate 110. Each of the second semiconductor chips 200 may include a second semiconductor substrate 210, a second integrated circuit, a second lower insulating layer 221, a second lower pad 250, a second wiring pattern 223, a second via 270, a second upper pad 260, and a second upper insulating layer 230. Unless otherwise stated, the materials and electrical connections of the second semiconductor substrate 210, the second integrated circuit, the second lower insulating layer 221, the second lower pad 250, the second wiring pattern 223, and the second via 270 may be substantially the same as those of the first semiconductor substrate 110, the first integrated circuit 115, the first lower insulating layer 121, the first lower pad 150, the first wiring pattern 123, and the first via 170. The second semiconductor substrate 210 may be a second substrate.

[0064] The second integrated circuit may be disposed on the lower surface of the second semiconductor substrate 210. The lower surface of the second semiconductor substrate 210 may be the front surface. The second integrated circuit may be associated with the first integrated circuit 115 (e.g., see [reference]). Figure 6 Different types of circuits. The second integrated circuit can be a memory circuit. The second semiconductor substrate 210 can include semiconductor material. The second lower insulating layer 221 can be disposed on the lower surface of the second semiconductor substrate 210 and can cover the second integrated circuit.

[0065] The second lower insulating layer 221 may include multiple layers to form a multilayer. The second lower insulating layer 221 may include a silicon-based insulating material. More specifically, the second lower insulating layer 221 may include an inorganic insulating material subjected to compressive stress. In an example embodiment, the second lower insulating layer 221 may be formed to have compressive stress using a plasma-enhanced chemical vapor deposition (PECVD) process. For example, the second lower insulating layer 221 may include at least one of oxides and nitrides. For example, the second lower insulating layer 221 may include at least one of silicon oxide and silicon nitride. To control the compressive stress of the second lower insulating layer 221, the process conditions of the PECVD process used to form the second lower insulating layer 221 and / or the thickness of the second lower insulating layer 221 may be controlled. The second lower pad 250 may be disposed on the lower surface of the second semiconductor chip 200.

[0066] For example, the second lower pad 250 may be disposed on the lower surface of the second lower insulating layer 221. The lower surface of the second semiconductor chip 200 may include the lower surface of the second lower pad 250 and the lower surface of the second lower insulating layer 221. The second lower pad 250 may include, for example, copper. The second via 270 may be disposed in the second semiconductor substrate 210 and may penetrate the second semiconductor substrate 210.

[0067] The second via 270 can be electrically connected to the second wiring pattern 223. The second via 270 may include metal. Therefore, the second lower pad 250 and the second wiring pattern 223 can be electrically connected through the second via 270. The second upper insulating layer 230 may be disposed on the upper surface of the second semiconductor substrate 210.

[0068] The upper surface of the second semiconductor substrate 210 may be a back-side surface. The second upper insulating layer 230 may include multiple layers to form a multilayer. For example, the second upper insulating layer 230 may include a silicon-based insulating material. A second wiring pattern 223 may be disposed within the second upper insulating layer 230. The second wiring pattern 223 may include a metal. The second wiring pattern 223 may include a second aluminum wiring pattern 224 thereon. The second aluminum wiring pattern 224 may include aluminum and a material different from the second wiring pattern 223. A second upper pad 260 may be electrically connected to a second integrated circuit and / or a second via 270 through the second wiring pattern 223. The second upper pad 260 may be disposed within the second upper insulating layer 230. The upper surface of the second upper pad 260 may not be covered by the second upper insulating layer 230. For example, the second upper pad 260 may include a metal such as copper.

[0069] A change in temperature applied to the second semiconductor chip 200 may cause warping of the second semiconductor chip 200. For example, while the second semiconductor chip 200 is heated from a first temperature to a second temperature, the second semiconductor chip 200 may deform upward or downward due to the rapid thermal expansion of the metal wiring pattern of the second wiring pattern 223. To prevent cracks caused by such warping, a trench region 300 may be arranged, and the description of the trench region 300 is the same as that described elsewhere herein and is therefore omitted. The uppermost second semiconductor chip 200 may include a second semiconductor substrate 210, a second integrated circuit, a second lower insulating layer 221, and a second lower pad 250, but may not include the second via 270, the second upper pad 260, the second wiring pattern 223, and the second upper insulating layer 230.

[0070] The thickness of the second semiconductor substrate 210 of the uppermost second semiconductor chip 200 may be greater than the thickness of the second semiconductor substrate 210 of each of the other second semiconductor chips 200. The uppermost second semiconductor chip 200 may be referred to as the third semiconductor chip. A molding layer 400 may be disposed on the upper surface of the first semiconductor chip 100 to cover one or more sidewalls of the second semiconductor chip 200. The molding layer may cover at least a portion of (one or more) the second semiconductor chip(s).

[0071] The upper surface of the molding layer 400 may expose the upper surface of the uppermost second semiconductor chip 200. For example, the upper surface of the molding layer 400 may be positioned at substantially the same level as the upper surface of the uppermost second semiconductor chip 200. Alternatively, the molding layer 400 may also cover the upper surface of the uppermost second semiconductor chip 200. The molding layer 400 may include an insulating polymer such as EMC. The lowermost second semiconductor chip 200 may be directly bonded to the first semiconductor chip 100.

[0072] Each of the first semiconductor chip 100 and the second semiconductor chip 200 included in the semiconductor package 10 can be directly bonded. Direct bonding can be formed using a hybrid bonding process. The second lower pad 250 of the lowest second semiconductor chip 200 can be directly bonded to the first upper pad 160. For example, the second lower pad 250 of the lowest second semiconductor chip 200 is directly disposed on and in direct physical contact with the first upper pad 160. The second lower pad 250 of the lowest second semiconductor chip 200 may include the same metal as the first upper pad 160 (e.g., copper). The interface between the second lower pad 250 of the lowest second semiconductor chip 200 and the first upper pad 160 may be inconspicuous, but is not limited thereto. The second lower insulating layer 221 of the lowest second semiconductor chip 200 can be directly bonded to the first upper insulating layer 130.

[0073] For example, chemical bonds can be formed between the second lower insulating layer 221 of the bottommost second semiconductor chip 200 and the first upper insulating layer 130. In some embodiments, the bumps and the insulating film surrounding the bumps arranged between the first semiconductor chip 100 and the second semiconductor chip 200 used in the case of thermocompression bonding (TCB) can be omitted. By direct bonding, the thickness of the semiconductor package in the vertical direction can be relatively reduced. By direct bonding, the second lower insulating layer 221 of the bottommost second semiconductor chip 200 can be firmly bonded to the first upper insulating layer 130. The second lower insulating layer 221 of the bottommost second semiconductor chip 200 may include, but is not limited to, the same insulating material as the first upper insulating layer 130. For example, the interface between the second lower insulating layer 221 of the bottommost second semiconductor chip 200 and the first upper insulating layer 130 may not be distinguished. The second semiconductor chips 200 can be directly bonded to each other.

[0074] For example, the second upper pad 260 and the second lower pad 250, which face each other, can be in direct contact with each other and can be directly bonded to each other. The interface between the directly bonded second upper pad 260 and the second lower pad 250 can be indistinguishable. The interface between the directly bonded second upper pad 260 and the second lower pad 250 can be a virtual interface. The second lower pad 250 can include the same metal (e.g., copper) as the second upper pad 260 directly bonded to the second lower pad 250. The second lower insulating layer 221 can be directly bonded to the second upper insulating layer 230, and the second lower insulating layer 221 and the second upper insulating layer 230 can face each other.

[0075] For example, the second lower insulating layer 221 may be in direct contact with the second upper insulating layer 230, and the second lower insulating layer 221 and the second upper insulating layer 230 may face each other. Chemical bonds may be formed between the second lower insulating layer 221 and the second upper insulating layer 230, which are directly bonded to each other. Therefore, strong bonds may be formed between the second lower insulating layer 221 and the second upper insulating layer 230, which are directly bonded to each other. The second lower insulating layer 221 may include, but is not limited to, the same material as the second upper insulating layer 230, which is directly bonded to the second lower insulating layer 221. For example, the interface between the second lower insulating layer 221 and the second upper insulating layer 230, which are directly bonded to each other, may not be distinguished.

[0076] Figure 3 This illustrates an embodiment. Figure 2 A magnified view of region II. Figure 3 and Figure 1 and Figure 2 They were used as a reference together.

[0077] The trench region 300 can be arranged at both ends of the center of the second semiconductor chip 200. Figure 3The accompanying drawings depict two trench regions 300 disposed within the second insulating layer 132; however, when viewed from above, two or more trench regions 300 may be present disposed within the second insulating layer 132. In some embodiments, four trench regions 300 may be disposed at each vertex of the second semiconductor chip 200. In some embodiments, the trench regions 300 may be divided into a first region and a second region as described herein. Figure 3 As shown, portion 302 of trench region 300 can be considered a first portion or may also be referred to herein as a first region. Portion 304 of trench region 300 can be considered a second portion or may also be referred to herein as a second region. The first portion may be laterally located inside the periphery of the second semiconductor chip, and the second portion may be laterally located outside the periphery of the second semiconductor chip. The combination of the first and second portions of the trench region can form a stepped structure or stepped shape. Portion 302 (first portion) may have a first depth smaller than the second depth of portion 304 (second portion). The first portion (portion 302) may have an inner edge in a first horizontal direction (e.g., the X direction), and the second portion (portion 304) may have an outer edge in the first horizontal direction (e.g., the X direction). As shown, the depth of trench region 300 can vary from the inner edge to the outer edge. The trench region may have a variable depth that increases as it moves laterally from the inner edge of the trench region toward the outer edge of the trench region.

[0078] The widths at both ends of the first region can be defined as W1. The widths at both ends of the second region can be defined as W2. In some embodiments, W1 may correspond to the longest width of the first region in the horizontal direction. Furthermore, W1 may correspond to the width of the second semiconductor chip 200 in the horizontal direction. In some embodiments, W2 may correspond to the longest width of the second region in the horizontal direction. Figure 3 In the diagram, the longest width of the first region in the first horizontal direction (e.g., the X direction) is shown as W1, but the longest width in the second horizontal direction (e.g., the Y direction) orthogonal to the first horizontal direction (e.g., the X direction) can also be defined as W1.

[0079] Furthermore, the longest width of the second region in the first horizontal direction (e.g., the X direction) is shown as W2, but the longest width in the second horizontal direction (e.g., the Y direction) orthogonal to the first horizontal direction (e.g., the X direction) can also be defined as W2. This does not mean that the trench region 300 exists for all regions within the widths of W1 and W2, and the trench region 300 can be formed discontinuously.

[0080] That is, W1 and W2 can be calculated as the length connecting the outermost points of each region. For some regions on the lower surface of the second semiconductor chip 200, trench regions 300 may not be formed. In some embodiments, in Figure 3 In this case, the second insulating layer 132 can physically contact the lower surface of the second semiconductor chip 200 without forming the trench region 300. The longest width W1 of the first region can be smaller than the longest width W2 of the second region.

[0081] Figure 4 This illustrates an embodiment. Figure 2 A magnified view of region II. This will mainly concern... Figure 3 Different references Figures 1 to 3 To describe Figure 4 .

[0082] From the plan view, the trench regions 300_1 can be continuously connected to each other. The trench regions 300_1 can have the following characteristics: Figure 3 The first and second regions shown have different vertical and horizontal dimensions, but Figure 4 The first regions within the trench regions 300_1 can be continuously connected to each other. In some embodiments, in the region where the second insulating layer 132 contacts the second semiconductor chip 200, the trench regions 300_1 can be formed along the outer surface of the second semiconductor chip 200. Figure 4 In the plan view, the trench region 300_1 is formed by completely removing the upper surface of the second insulating layer 132, and the upper surface of the second insulating layer 132 does not contact the lower surface of the second semiconductor chip 200. However, when viewed from above, the central region of the area of ​​the second insulating layer 132 where the trench region 300_1 is not formed can physically contact the second semiconductor chip 200.

[0083] This will refer to Figure 15 Provide a detailed description. Figure 4 In the case of a trench region of 300_1, the longest width W1 of the first region can be less than the longest width W2 of the second region.

[0084] The trench region 300_1 is formed continuously, and even in the case of the trench region 300_1, only the first region can overlap with the second semiconductor chip 200. Furthermore, even in the case of the trench region 300_1, the second region that does not overlap with the second semiconductor chip 200 can overlap with the molding layer 400.

[0085] Figure 5 This illustrates an embodiment. Figure 2 A magnified view of region II. Figure 5 and Figures 1 to 4 They are referenced together, and the main description is related to Figure 4 The difference.

[0086] As seen in the plan view, the trench regions 300_2 can be arranged at intervals (e.g., discontinuous in the plane of the insulation layer).

[0087] In some embodiments, the trench region 300_2 may be disposed at or adjacent to each corner of the second semiconductor chip 200, or disposed at or adjacent to each vertex or edge of the second semiconductor chip 200. In this document... Figure 5 In the description, a corner may refer to a corner of the second semiconductor chip 200, and a vertex may refer to a vertex of the second semiconductor chip 200. A trench region 300_2 disposed at a corner may not be continuous with a trench region 300_2 disposed at a vertex. A trench region 300_2 disposed at a corner may not be continuous with a trench region 300_2 disposed at another corner. At both ends of the trench region 300_2 disposed at the corner, a trench region 300_2 disposed at the vertex may be disposed. A second insulating layer 132 may be disposed between the trench region 300_2 disposed at the corner and the trench region 300_2 disposed at the vertex. This refers to... Figure 13 and Figure 14 Provide a detailed description. Figure 5 In the case of a trench area of ​​300_2, the longest width W1 of the first area can be less than the longest width W2 of the second area.

[0088] Furthermore, the groove region 300_2 formed at the corner can correspond to the first region. That is, in Figure 5 In the diagram, the trench region 300_2 formed at the corner is shown as being formed at the center of the lower surface of the second semiconductor chip 200. The depth of the trench region 300_2 formed at the corner in the vertical direction may be less than the depth of the second region in the vertical direction.

[0089] The vertical depth of the trench region 300_2 formed at the corner can be the same as the vertical depth of the first region. That is, the first region of the trench region 300_2 formed at the corner and the trench region 300_2 formed at the apex can be formed by the same process. From a plan view, the trench region 300_2 formed at the corner can completely overlap with the second semiconductor chip 200. However, when viewed together... Figure 13 and Figure 14 When viewed from above, they may not completely overlap. In the case of the trench region 300_2 formed at the apex, the trench region 300_2 may overlap with the second semiconductor chip 200 only for the first region.

[0090] Furthermore, in the case of trench region 300_2, the second region that does not overlap with the second semiconductor chip 200 can overlap with the molding layer 400.

[0091] Figure 6 This illustrates an embodiment. Figure 2 A magnified view of region III.

[0092] Reference Figure 6 The first integrated circuit 115 can be arranged on the upper part of the chip region CR of the first semiconductor substrate 110.

[0093] The lower surface of the first semiconductor substrate 110 may be the front surface. The first integrated circuit 115 may not be disposed on the dummy region DR of the first semiconductor substrate 110. The first integrated circuit 115 may include transistors. The first integrated circuit 115 may include logic circuits. The first insulating layer 131 may be disposed on the upper part of the first semiconductor substrate 110 and may cover the first integrated circuit 115.

[0094] Figure 7 This illustrates an embodiment. Figure 3 A magnified view of region A.

[0095] Reference Figure 7 The trench area 300 can be arranged within the second insulating layer 132.

[0096] The trench region 300 can be divided into a first region and a second region. In some embodiments, the length of the first region in the vertical direction (e.g., the Z direction) is defined as H1. In some embodiments, the length of the second region in the vertical direction (e.g., the Z direction) is defined as H2. The length H2 of the second region in the vertical direction (e.g., the Z direction) of the trench region 300 can be greater than the length H1 of the first region in the vertical direction (e.g., the Z direction). In some embodiments, the length H2 of the second region in the vertical direction (e.g., the Z direction) of the trench region 300 can be less than 1 μm.

[0097] In some embodiments, the length H1 of the first region in the trench region 300 in the vertical direction (e.g., the Z direction) may be less than or equal to half the length H2. That is, the length H1 may be less than half the length H2. The first region and the second region may have different steps, and therefore they may be distinguishable step shapes. That is, the trench region 300 including the first region and the second region may not have a slope.

[0098] Figures 8 to 10 This illustrates an embodiment. Figure 3 A magnified view of region A.

[0099] Reference Figure 8 as well as Figure 1 and Figure 2 The trench region 300a can be arranged within the second insulating layer 132.

[0100] From a plan view, in some embodiments, trench region 300a may have a vertical (e.g., Z-direction) length that increases toward the edge of the first semiconductor chip 100. Trench region 300a may have a triangle with a constant slope. Although trench region 300a is not divided into a first region and a second region as described herein, the depth of the portion corresponding to the second region in the vertical direction (e.g., Z-direction) may be greater than the depth of the portion corresponding to the first region in the vertical direction (e.g., Z-direction).

[0101] The trench region 300a is shown only for region A, but the tilt angle can be reversed if the trench region 300a is located on the opposite side of the center of the second semiconductor chip 200. (Refer to...) Figure 9 as well as Figure 1 and Figure 2 The trench region 300b can be arranged within the second insulating layer 132.

[0102] In a plan view, the trench region 300b may have a vertical length that increases toward the edge of the first semiconductor chip 100. In some embodiments, the trench region 300b may have a gentle curvature or a gradually changing curvature. In some embodiments, the trench region 300b may have a convex shape that protrudes toward the upper surface of the first semiconductor chip 100. That is, the second insulating layer 132 in which the trench region 300b is formed may have a concave shape that is recessed toward the lower surface of the second semiconductor chip 200. Figure 9 The trench region 300b shown is not divided into a first region and a second region as described herein, but the depth of the portion corresponding to the second region in the vertical direction (e.g., the Z direction) may be greater than the depth of the portion corresponding to the first region in the vertical direction (e.g., the Z direction).

[0103] The trench region 300b is shown only for region A, but when the trench region 300b is located on the opposite side relative to the center of the second semiconductor chip 200, the angle forming the gentle (or gradual) curvature can be opposite.

[0104] Reference Figure 10 as well as Figure 1 and Figure 2 The trench area 300c can be arranged within the second insulating layer 132.

[0105] From a plan view, the trench region 300c may have a vertical length that increases as it moves toward the edge of the first semiconductor chip 100. In some embodiments, the trench region 300c may have a gentle curvature or a gradually changing curvature. In some embodiments, the trench region 300c may have a concave shape toward the upper surface of the first semiconductor chip 100. That is, the second insulating layer 132 in which the trench region 300c is formed may have a convex shape that protrudes toward the lower surface of the second semiconductor chip 200. Figure 10 The trench region 300c shown is not divided into a first region and a second region as described herein, but the depth of the portion corresponding to the second region in the vertical direction (e.g., the Z direction) may be greater than the depth of the portion corresponding to the first region in the vertical direction (e.g., the Z direction).

[0106] The trench region 300c is shown only for region A, but when the trench region 300c is located on the opposite side of the center of the second semiconductor chip 200, the angle forming the gentle curvature or the gradual curvature can be opposite.

[0107] Figure 11 This is a plan view illustrating a trench region included in a semiconductor package according to an embodiment. Figures 12 to 15 This is a plan view showing the trench region according to an embodiment. Figures 11 to 15 In the description, the corners are simply described as the corners of the second semiconductor chip 200, and the vertices are simply described as the vertices of the second semiconductor chip 200. Figure 11 and Figure 1 and Figure 2 They were used as a reference together.

[0108] When viewed from above, the trench region 300 can be arranged within the second insulating layer 132. The trench region assembly can have, for example, Figure 11 The diagram shows multiple trench regions. For example, four trench regions 300 may exist. In some embodiments, the trench regions 300 may be arranged at each vertex of the second semiconductor chip 200 and may be spaced apart from each other. At least a portion of the trench regions 300 may overlap with the second semiconductor chip 200. In some embodiments, the area of ​​the trench region 300 that overlaps with the second semiconductor chip 200 may be a first region. In some embodiments, the remaining area of ​​the trench region 300 that does not overlap with the second semiconductor chip 200 may be a second region. As described above, the description of the longest widths W1 and W2 of each region of the trench region 300 is omitted. When viewed from above, the trench region 300 may have a square shape.

[0109] In the accompanying drawings, the trench region 300 is depicted as a square shape with each side having the same length, but is not limited to this, and may have a rectangular shape with each side having a different length. Each vertex of the second semiconductor chip 200 is depicted corresponding to the horizontal center of the trench region 300, but the vertices of the second semiconductor chip 200 do not necessarily need to correspond to the center of the trench region 300. Figure 11 In the text, the depths of the first and second regions are depicted as constant, but as... Figure 7 As depicted, the depths of the first and second regions can differ from each other. Furthermore, the trench region 300 can be formed not only as... Figure 7 The staircase shape depicted in the text has two steps, and it can be formed as follows: Figures 8 to 10 The triangles, concave shapes, and convex shapes depicted in the image. This can also be applied in the same way. Figures 12 to 15 The trench area 300 is depicted in the diagram. Viewed from a plan view (e.g., the plan of the insulation layer), Figure 11 Can be with Figure 3 correspond. Figure 12 and Figure 1 and Figure 2 They were used as a reference together.

[0110] When viewed from above, the trench region 300 can be arranged within the second insulating layer 132. The trench region assembly can have, for example, Figure 12 The diagram shows multiple trench regions. For example, four trench regions 300 may exist. In some embodiments, the trench regions 300 may be arranged at each vertex of the second semiconductor chip 200 and may be spaced apart from each other. At least a portion of the trench regions 300 may overlap with the second semiconductor chip 200. In some embodiments, the area of ​​the trench region 300 that overlaps with the second semiconductor chip 200 may be a first region. In some embodiments, the remaining area of ​​the trench region 300 that does not overlap with the second semiconductor chip 200 may be a second region. When viewed from above, the trench regions 300 may have a right-angled triangular shape (e.g., a right triangle).

[0111] More specifically, the trench region 300 may have a right-angled triangular shape in which at least a portion of the hypotenuse overlaps with the second semiconductor chip 200. In the figures, the trench region 300 is depicted as an isosceles triangle with each side having the same length except for the hypotenuse, but is not limited thereto, and may be a right-angled triangle with each side having a different length. Furthermore, at least some of the hypotenuse may overlap with the second semiconductor chip 200, but the angles of the non-overlapping sides may not be right angles. In some embodiments, the trench region 300 may be an obtuse triangle or an acute triangle. In the plan view, Figure 12 Can be with Figure 3 correspond. Figure 13 and Figure 1 and Figure 2 They were used as a reference together.

[0112] When viewed from above, the trench region 300 can be arranged within the second insulating layer 132. The trench region assembly can have, for example, Figure 13 The diagram shows multiple trench regions. For example, eight trench regions 300 may exist. In some embodiments, the trench regions 300 may be arranged at each vertex and each corner of the second semiconductor chip 200 and may be spaced apart from each other. At least a portion of the trench regions 300 may overlap with the second semiconductor chip 200. In some embodiments, the area of ​​the trench regions 300 that overlaps with the second semiconductor chip 200 may be a first region. In some embodiments, the remaining area of ​​the trench regions 300 that does not overlap with the second semiconductor chip 200 may be a second region. When viewed from above, the trench regions 300 may have a square shape.

[0113] In the accompanying drawings, trench regions 300 located at the corners of the second semiconductor chip 200 are depicted as square shapes with each side having the same length, and trench regions 300 located at the corners of the second semiconductor chip 200 are depicted as rectangular shapes, but this is not a limitation. In some embodiments, a trench region 300 at the corner of the second semiconductor chip 200 may be a rectangular shape with each side having a different length. In some embodiments, a trench region 300 at the corner of the second semiconductor chip 200 may be a square shape with each side having the same length. Although each corner of the second semiconductor chip 200 is depicted as corresponding to the center of the trench region 300 in the horizontal direction, the corner of the second semiconductor chip 200 does not necessarily have to correspond to the center of the trench region 300. The trench regions 300 located at one corner of the second semiconductor chip 200 and the trench regions 300 located at the other corner may be positioned separately from each other.

[0114] The second insulating layer 132 can be disposed between the trench region 300 disposed at the corner and the trench region 300 disposed at the vertex. In the plan view, Figure 13 Can be with Figure 5 correspond. Figure 14 and Figure 1 and Figure 2 They were used as a reference together.

[0115] When viewed from above, the trench region 300 can be arranged within the second insulating layer 132. The trench region assembly can have, for example, Figure 14The diagram shows multiple trench regions. For example, eight trench regions 300 may exist. In some embodiments, the trench regions 300 may be arranged at each vertex and each corner of the second semiconductor chip 200 and may be spaced apart from each other. At least a portion of the trench regions 300 may overlap with the second semiconductor chip 200. In some embodiments, the area of ​​the trench regions 300 that overlaps with the second semiconductor chip 200 may be a first region. In some embodiments, the remaining area of ​​the trench regions 300 that does not overlap with the second semiconductor chip 200 may be a second region. When viewed from above, the trench regions 300 may be in the shape of a right-angled triangle or a square.

[0116] In the case of a right-angled triangle, more specifically, the trench region 300 may be a right-angled triangle whose hypotenuse overlaps with the second semiconductor chip 200. In the figures, the trench region 300 is depicted as a right-angled triangle at the vertices of the second semiconductor chip 200, and also as a rectangle at the corners of the second semiconductor chip 200, but is not limited thereto. In some embodiments, the trench region 300 is depicted as an isosceles triangle with each side having the same length except for the hypotenuse, but it may be a right-angled triangle with each side having a different length. Furthermore, at least some of the hypotenuses may overlap with the second semiconductor chip 200, but the angles of the non-overlapping sides may be non-right angles within the triangle. In some embodiments, the trench region 300 may be an obtuse or acute triangle. The trench region 300 at the vertices may have a rectangular shape with each side having a different length.

[0117] In some embodiments, the trench regions 300 disposed at the corners of the second semiconductor chip 200 may be square shapes with each side having the same length. Although each vertex of the second semiconductor chip 200 is depicted corresponding to the horizontal center of the trench region 300, the vertices of the second semiconductor chip 200 do not necessarily need to correspond to the center of the trench region 300. The trench regions 300 disposed at the corners of the second semiconductor chip 200 and the trench regions 300 disposed at the vertices may be disposed separately from each other.

[0118] The second insulating layer 132 can be disposed between the trench region 300 disposed at the corner and the trench region 300 disposed at the apex. From the plan view, Figure 14 Can be with Figure 5 correspond. Figure 15 and Figure 1 and Figure 2 They were used as a reference together.

[0119] Viewed from above, trench region 300 may be disposed within second insulating layer 132. Trench region 300 may be formed as a continuous single structure. Viewed from above, second insulating layer 132 may be formed on both the outer and inner surfaces of trench region 300. That is, trench region 300 may be disposed continuously (e.g., adjacent to ground) along the outer surface of second semiconductor chip 200. In some embodiments, trench region 300 is formed along the outer surface of second semiconductor chip 200, but has an outer surface that is further outward than the outer surface of second semiconductor chip 200. In some embodiments, trench region 300 is formed along the outer surface of second semiconductor chip 200, but has an inner surface that is further inward than the outer surface of second semiconductor chip 200. At least a portion of trench region 300 may overlap with second semiconductor chip 200. In some embodiments, the region of trench region 300 that overlaps with second semiconductor chip 200 may be a first region. In some embodiments, the remaining region of trench region 300 that does not overlap with second semiconductor chip 200 may be a second region. In a plan view, Figure 15 Can be with Figure 4 correspond. Figure 16 This is a cross-sectional view showing the semiconductor package 1 according to an embodiment.

[0120] Reference Figure 16 The semiconductor package 1 may include solder balls 825, package substrate 820, insert solder balls 815, insert substrate 800, semiconductor device 20, and chip stack package 10'.

[0121] For example, a printed circuit board can be used as a package substrate 820.

[0122] The package substrate 820 may include substrate wiring 823. Substrate wiring 823 may be disposed within the package substrate 820. Electrical connection to the package substrate 820 may mean electrical connection to at least one of the substrate wirings 823. Substrate wiring 823 may include a metal such as copper, aluminum, tungsten, and / or titanium. Solder balls 825 may be disposed on the lower surface of the package substrate 820 and may be electrically connected to the substrate wiring 823.

[0123] External electrical signals can be transmitted to solder balls 825. Solder balls 825 may include solder material. An insert substrate 800 may be disposed on the package substrate 820.

[0124] The insert substrate 800 may include an upper insert pad 811 and insert wiring 813. The upper insert pad 811 may be disposed on the upper surface of the insert substrate 800. The upper insert pad 811 may include metal. The insert wiring 813 may be disposed within the insert substrate 800 and may be electrically connected to the upper insert pad 811. Electrical connection to the insert substrate 800 may mean electrical connection to at least one of the insert wirings 813. The insert wiring 813 may include metals such as copper, aluminum, tungsten, and / or titanium. Insert solder balls 815 may be disposed between the package substrate 820 and the insert substrate 800 to electrically connect the package substrate 820 to the insert substrate 800.

[0125] The pitch of the insert solder ball 815 can be smaller than the pitch of the solder ball 825. The insert solder ball 815 may include solder material. The chip stack package 10' may be disposed on the upper surface of the insert substrate 800.

[0126] In reference Figure 2 The semiconductor package 10 described in the illustrated embodiments can be used as a chip stack package 10'. For example, the chip stack package 10' may include a first semiconductor chip 100, a second semiconductor chip 200, a molding layer 400, and a lower bump 500. The lower bump 500 may be disposed on and electrically connected to the upper insert pad 811. The lower bump 500 may be located between the insert substrate and the first semiconductor chip.

[0127] For example, the lower bump 500 can be engaged with the upper surface of the corresponding upper insert pad 811. The pitch of the lower bump 500 can be smaller than the pitch of the insert solder ball 815. The semiconductor device 20 can be disposed on the insert substrate 800 and can be laterally spaced from the chip stack package 10'.

[0128] Semiconductor device 20 may include a graphics processing unit (GPU) or a central processing unit (CPU). Semiconductor device 20 may be a semiconductor chip of a different type than the first semiconductor chip 100 and the second semiconductor chip 200. Semiconductor device 20 may perform functions different from those of the first semiconductor chip 100 and the second semiconductor chip 200. Semiconductor device 20 may include integrated circuits and chip pads. Integrated circuits may be disposed within semiconductor device 20. Chip pads may be disposed on the lower surface of semiconductor device 20 and may be electrically connected to the integrated circuit of semiconductor device 20. Conductive bumps 570 may be disposed between insert substrate 800 and semiconductor device 20.

[0129] For example, conductive bumps 570 can be electrically connected to the chip pads and corresponding upper through-hole pads 811 of the semiconductor device 20. Conductive bumps 570 can include solder material. The pitch of conductive bumps 570 can be smaller than the pitch of the through-hole solder balls 815. The semiconductor device 20 can be electrically connected to the chip stack package 10' via the through-hole substrate 800. The semiconductor device 20 can be electrically connected to the package substrate 820 and solder balls 825 via the through-hole substrate 800. A molding pattern 480 can be disposed on the upper surface of the through-hole substrate 800 to cover the sidewalls of the chip stack package 10' and the semiconductor device 20.

[0130] For example, molding pattern 480 may cover the outer wall of the first semiconductor chip 100 and the outer wall of the molding layer 400. Molding pattern 480 may include a polymer, such as an epoxy molding compound. Molding pattern 480 may have insulating properties. Unlike what is shown, semiconductor package 1 may include two or more chip stack packages 10'. In this case, semiconductor device 20 may be located between chip stack packages 10'.

[0131] According to several aspects, a method for manufacturing a semiconductor package is provided. The semiconductor manufacturing method can produce one or more semiconductor packages according to the techniques described herein.

[0132] In some embodiments, a semiconductor package manufacturing method may include the steps of disposed of one or more second semiconductor chips on a first semiconductor chip and bonding the first semiconductor chip and the lowest of the one or more second semiconductor chips, wherein the first semiconductor chip may include: a first semiconductor substrate; a first upper insulating layer disposed on an upper surface of the first semiconductor substrate; a first upper pad disposed within the first upper insulating layer; a first lower pad disposed on a lower surface of the first semiconductor substrate; and a trench region disposed within the first upper insulating layer.

[0133] In some embodiments, the trench region may have a first portion and a second portion, the first portion being laterally located inside the periphery of the second semiconductor chip, and the second portion being laterally located outside the periphery of the second semiconductor chip. The first portion of the trench region may have a first depth, and the second portion of the trench region may have a second depth, wherein the first depth is less than the second depth.

[0134] In some embodiments, the trench region may have a variable depth that increases laterally as it moves laterally from the inner edge of the trench region toward the outer edge of the trench region, and wherein the trench region is positioned to laterally overlap with the periphery of the second semiconductor chip.

[0135] In some embodiments, each of one or more second semiconductor chips may include: a second semiconductor substrate; a second lower pad disposed on a lower surface of the second semiconductor substrate; and a second upper pad disposed on an upper portion of the second semiconductor substrate. In some embodiments, bonding may include a hybrid bonding process.

[0136] In some embodiments, the method may further include providing a molding layer that covers at least a portion of one or more second semiconductor chips on a first semiconductor chip.

[0137] According to some aspects, a chip stack package is provided, the chip stack package comprising: a first semiconductor chip having an insulating layer; and a second semiconductor chip located on the insulating layer of the first semiconductor chip and having a periphery, wherein the first semiconductor chip includes a trench region located in the insulating layer, the trench region having a first portion and a second portion, the first portion being laterally located inside the periphery of the second semiconductor chip, and the second portion being laterally located outside the periphery of the second semiconductor chip, and wherein the first portion of the trench region has a first depth, and the second portion of the trench region has a second depth, wherein the first depth is less than the second depth.

[0138] In some embodiments, the first and second portions of the trench region combine to form a stepped structure. In some embodiments, the trench region overlaps with the entire periphery of the second semiconductor chip. In some embodiments, the trench region overlaps with a portion of the periphery of the second semiconductor chip. In some embodiments, the trench region is located near a corner or edge of the second semiconductor chip. In some embodiments, the second semiconductor chip is a memory core chip.

[0139] According to some aspects, a chip stack package is provided, the chip stack package comprising: a first semiconductor chip having an insulating layer; and a second semiconductor chip located on the insulating layer of the first semiconductor chip and having a periphery, wherein the first semiconductor chip includes a trench region located in the insulating layer, the trench region having a variable depth that increases laterally from an inner edge of the trench region toward an outer edge of the trench region, and wherein the trench region is positioned to laterally overlap with the periphery of the second semiconductor chip.

[0140] In some embodiments, the trench region has a stepped, concave, or convex shape that moves laterally from the inner edge of the trench region toward the outer edge of the trench region. In some embodiments, the trench region is square or triangular in the plane of the insulating layer. In some embodiments, the trench region is continuous in the plane of the insulating layer. In some embodiments, the trench region is discontinuous in the plane of the insulating layer.

[0141] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip has a device region and a pseudo-region surrounding the device region in a plan view; A second semiconductor chip is located on the upper surface of the device region of the first semiconductor chip; as well as A molding layer that covers at least a portion of the second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes: First semiconductor substrate; The first lower pad is disposed on the lower surface of the first semiconductor substrate; A first upper insulating layer is disposed on the upper portion of the first semiconductor substrate; and The first upper pad and trench region, each of the first upper pad and the trench region being arranged within the first upper insulating layer.

2. The semiconductor package according to claim 1, wherein: The first upper insulating layer includes a first insulating layer and a second insulating layer. The first upper pad and the trench region are arranged within the second insulating layer of the first upper insulating layer, and The width of the second semiconductor chip in the horizontal direction is less than the longest width of the trench region in the horizontal direction.

3. The semiconductor package according to claim 1, wherein: In the plan view, the trench region includes a first region and a second region, the first region overlapping with the second semiconductor chip, and the second region not overlapping with the second semiconductor chip. The trench region has a stepped structure, in which the vertical and horizontal dimensions of the first region and the second region are different from each other.

4. The semiconductor package according to claim 3, wherein, The vertical length of the second region is 1 μm, and the vertical length of the first region is less than half the vertical length of the second region.

5. The semiconductor package according to claim 1, wherein, When viewed from above, the trench regions are arranged at each vertex of the second semiconductor chip, and each of the trench regions is spaced apart from the other.

6. The semiconductor package according to claim 5, wherein, When viewed from above, the trench region is a right-angled triangle with at least a portion of its hypotenuse overlapping the second semiconductor chip.

7. The semiconductor package according to claim 1, wherein, When viewed from above, the trench regions are arranged at each vertex and each corner of the second semiconductor chip, with each trench region spaced apart from the others.

8. The semiconductor package according to claim 7, wherein, When viewed from above, the trench regions arranged at each vertex of the second semiconductor chip are right-angled triangles whose hypotenuses overlap with the second semiconductor chip.

9. The semiconductor package according to claim 1, wherein, When viewed from above, the trench region is arranged continuously along the outer surface of the second semiconductor chip.

10. The semiconductor package according to claim 1, wherein, The second semiconductor chip includes: Second semiconductor substrate; The second lower pad is disposed on the lower surface of the second semiconductor substrate; and The second upper pad is disposed on the upper part of the second semiconductor substrate, and in: The first semiconductor chip and the second semiconductor chip located at the bottom are formed by a hybrid bonding process, and The first upper pad and the second lower pad are in direct physical contact with each other.

11. A semiconductor package, comprising: First semiconductor chip; A second semiconductor chip is located on the upper surface of the first semiconductor chip; as well as A molding layer that covers at least a portion of the second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes: First semiconductor substrate, A first upper insulating layer is disposed on the upper surface of the first semiconductor substrate. The first upper pad is arranged within the first upper insulating layer. The first lower pad is disposed on the lower surface of the first semiconductor substrate, and The trench area is arranged within the first upper insulating layer; Each of the second semiconductor chips includes: Second semiconductor substrate, The second lower pad is disposed on the lower surface of the second semiconductor substrate, and The second upper pad is disposed on the upper part of the second semiconductor substrate; and In this configuration, the width of each second semiconductor chip in the horizontal direction is less than the longest width of the trench region in the horizontal direction.

12. The semiconductor package of claim 11, wherein, In the plan view, the trench region is triangular, the triangle having a vertical length that increases toward the edge of the first semiconductor chip and a constant slope.

13. The semiconductor package of claim 11, wherein, In the plan view, the trench region has a gradient curvature, which has a vertical length that increases toward the edge of the first semiconductor chip and a convex shape that protrudes toward the upper surface of the first semiconductor chip.

14. The semiconductor package of claim 11, wherein: In the plan view, the trench region has a gradient curvature, which has a vertical length that increases toward the edge of the first semiconductor chip and a concave shape toward the upper surface of the first semiconductor chip.

15. The semiconductor package of claim 11, wherein: In the plan view, the trench region includes a first region and a second region, the first region overlapping with each second semiconductor chip, and the second region not overlapping with each second semiconductor chip. The trench region has a stepped structure, in which the vertical and horizontal dimensions of the first region and the second region are different from each other.

16. The semiconductor package of claim 15, wherein, The vertical length of the second region is 1 μm, and the vertical length of the first region is less than half the vertical length of the second region.

17. The semiconductor package of claim 11, further comprising: Insert substrate; A bump is located between the insert substrate and the first semiconductor chip; as well as A semiconductor device disposed on the upper surface of the insert substrate and laterally spaced from the first semiconductor chip. in: The first semiconductor chip is electrically connected to the semiconductor device via the insert substrate. The first upper insulating layer includes a first insulating layer and a second insulating layer, and The first upper pad and the trench region are arranged within the second insulating layer of the first upper insulating layer.

18. The semiconductor package of claim 11, wherein: The first semiconductor chip and the lowermost of the second semiconductor chips are formed using a hybrid bonding process, with the first upper pad and the second lower pad in direct physical contact with each other. The second semiconductor chip is formed using a hybrid bonding process, and The second lower pad and the second upper pad closest to the second lower pad are in direct physical contact with each other.

19. A semiconductor package, comprising: The first semiconductor chip includes: First semiconductor substrate, A first upper insulating layer, comprising a first insulating layer and a second insulating layer, wherein the first upper insulating layer is disposed on the upper surface of the first semiconductor substrate. The first upper pad is disposed within the second insulating layer, and The trench area is disposed within the second insulating layer; A second semiconductor chip is located on the upper surface of the first semiconductor chip, each of the second semiconductor chips comprising: Second semiconductor substrate, A second upper insulating layer is disposed on the upper surface of the second semiconductor substrate. A second lower insulating layer is disposed on the lower surface of the second semiconductor substrate. The second upper pad is disposed within the second upper insulating layer, and The second lower pad is disposed within the second lower insulating layer; and A molding layer that covers at least one sidewall of a second semiconductor chip on the first semiconductor chip; In the plan view, the trench region includes a first region and a second region. The first region overlaps with the second semiconductor chip, while the second region does not overlap with the second semiconductor chip. The trench region has a stepped structure, in which the vertical and horizontal dimensions of the first region and the second region are different from each other.

20. The semiconductor package of claim 19, further comprising: A lower bump is disposed on the lower surface of the first semiconductor chip and electrically connected to the first lower pad; in: The vertical length of the second region is 1 μm; The vertical length of the first region is less than half the vertical length of the second region; The first semiconductor chip also includes: A first through-hole passes through the first semiconductor substrate. A first wiring pattern, electrically connected to the first via and the first upper pad and disposed within the first insulating layer, and The first lower pad is disposed on the lower surface of the first semiconductor substrate; When viewed from above, the trench regions are arranged at each vertex of the second semiconductor chip, and the trench regions are spaced apart from each other; and The shape of the trench region is one of a square and a right triangle whose hypotenuse overlaps with the second semiconductor chip.

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