Stack layout of high density metal oxide semiconductor (MOS) capacitors (MOSCAP) and metal oxide metal (MOM) capacitors (MOMCAP)

Abstract

An integrated circuit (IC) is described. The IC includes a metal oxide metal (MOM) capacitor (MOMCAP). The MOMCAP includes a first terminal coupled to a first plurality of fingers of the first metal interconnect layer. The MOMCAP also includes a second terminal coupled to the second plurality of fingers of the first metal interconnect layer and interdigitated with the first plurality of fingers of the first metal interconnect layer. The IC also includes a first metal oxide semiconductor (MOS) capacitor (MOSCAP). The first MOSCAP includes a polysilicon terminal coupled to a first plurality of fingers of the MOMCAP. The first MOSCAP also includes a diffusion terminal coupled to the second plurality of fingers of the MOMCAP.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 469,924, filed September 19, 2023, entitled “High Density Metal-oxide-semiconductor (MOS) Capacitor (MOSCAP) and Metal-oxide-metal (MOM) Capacitor (MOMCAP) Stacking Layout,” the entire disclosure of which is expressly incorporated herein by reference. background Technical Field

[0003] Various aspects of this disclosure relate to semiconductor devices, and more specifically, to stacked layouts of high-density metal-oxide-semiconductor (MOS) capacitors (MOSCAP) and metal-oxide-metal (MOM) capacitors (MOMCAP). Background Technology

[0004] Due to cost and power consumption considerations, mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep submicron process nodes. Additional circuitry for supporting communication enhancements, such as sixth-generation (6G) and fifth-generation (5G) New Radio (NR) communication systems, further complicates the design of mobile RF transceivers. Further design challenges for mobile RF transceivers include the use of passive components, which directly impact analog / RF performance considerations, including mismatch, noise, and other performance factors.

[0005] Passive devices can involve high-performance capacitor assemblies. For example, analog integrated circuits use several types of passive devices, such as integrated capacitors. These integrated capacitors can include metal-oxide-semiconductor (MOS) capacitors (MOSCAP), pn junction capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-polysilicon capacitors, metal-oxide-metal (MOM) capacitors (MOMCAP), and other similar capacitor structures. MOMCAP is also known as vertical parallel plate (VPP) capacitor, natural vertical capacitor (NVCAP), lateral flux capacitor, comb capacitor, and intersecting finger capacitor. Radio frequency (RF) analog (RFA) designs use capacitors extensively. Therefore, increasing capacitor density leads to reduced area and cost savings in RFA designs. An efficient stacking of MOSCAP and MOMCAP is desired for improved RFA designs. Summary of the Invention

[0006] An integrated circuit (IC) is described. The IC includes a metal-oxide-semiconductor (MOM) capacitor (MOMCAP). The MOMCAP includes a first terminal coupled to a first plurality of fingers of a first metal interconnect layer. The MOMCAP also includes a second terminal coupled to a second plurality of fingers of the first metal interconnect layer and intersecting with the first plurality of fingers of the first metal interconnect layer. The IC also includes a first metal-oxide-semiconductor (MOS) capacitor (MOSCAP). The first MOSCAP includes a polysilicon terminal coupled to the first plurality of fingers of the MOMCAP. The first MOSCAP also includes a diffused terminal coupled to the second plurality of fingers of the MOMCAP.

[0007] A method for forming a metal-oxide-semiconductor (MOS) capacitor (MOSCAP) and a metal-oxide-metal (MOM) capacitor (MOMCAP) is described. The method includes forming a MOMCAP. The MOMCAP includes a first terminal coupled to a first plurality of fingers of a first metal interconnect layer. The MOMCAP also includes a second terminal coupled to a second plurality of fingers of the first metal interconnect layer and intersecting with the first plurality of fingers of the first metal interconnect layer. The method may include forming a first MOSCAP. The first MOSCAP includes a polysilicon terminal coupled to the first plurality of fingers of the MOMCAP. The first MOSCAP also includes a diffused terminal coupled to the second plurality of fingers of the MOMCAP.

[0008] This has broadly outlined the features and technical advantages of this disclosure in order to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for performing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0009] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings.

[0010] Figure 1This is a schematic diagram of a radio frequency (RF) front-end (RFFE) module employing a stacked layout of metal oxide metal (MOM) capacitors (MOMCAP) and metal oxide semiconductor (MOS) capacitors (MOSCAP) according to various aspects of this disclosure.

[0011] Figure 2 This is a schematic diagram of a wireless local area network (WLAN) (e.g., Wi-Fi) module including a first duplexer and a radio frequency (RF) front-end (RFFE) module including a second duplexer for a chipset according to various aspects of this disclosure. The chipset includes an optimized stacked layout of high-density metal oxide semiconductor (MOS) capacitors (MOSCAP) and metal oxide metal (MOM) capacitors (MOMCAP).

[0012] Figure 3 This is a block diagram illustrating a cross-section of an analog integrated circuit (IC) device including an interconnect stack containing a conventional metal-oxide-semiconductor (MOM) capacitor (MOMCAP) structure.

[0013] Figure 4 This is a schematic layout diagram of a top view illustrating the stacked layout of metal oxide metal (MOM) capacitors (MOMCAP) and metal oxide semiconductor (MOS) capacitors (MOSCAP) according to various aspects of this disclosure.

[0014] Figure 5 This illustrates various aspects of this disclosure. Figure 4 A schematic top view of a metal oxide metal (MOM) capacitor (MOMCAP) arranged in a stacked layout with multiple metal oxide semiconductor (MOS) capacitors (MOSCAP).

[0015] Figures 6A to 6C This further illustrates various aspects of this disclosure. Figure 4 A schematic cross-sectional view of a stacked layout of metal oxide metal (MOM) capacitors (MOMCAP) and metal oxide semiconductor (MOS) capacitors (MOSCAP).

[0016] Figure 7 This is a process flow diagram illustrating methods for stacked layout of metal oxide semiconductor (MOS) capacitors (MOSCAP) and metal oxide metal (MOM) capacitors (MOMCAP) according to various aspects of this disclosure.

[0017] Figure 8 This is a block diagram illustrating an exemplary wireless communication system in which the configurations of this disclosure may be advantageously employed.

[0018] Figure 9 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. Detailed Implementation

[0019] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0020] As described herein, the term “and / or” is used to indicate “inclusive or”, and the term “or” is used to indicate “exclusive or”. As described herein, the term “exemplary” as used throughout the description means “serving as an example, instance, or illustration” and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” as used throughout the description means “direct or indirectly connected via an intermediate connection (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Furthermore, a connection can permanently or releasably connect objects. Connections can be made via switches. As described herein, the term “proximity” as used throughout the description means “adjacent, very close, adjacent, or near.” As described herein, the term “on” as used throughout the description means “directly on” in some configurations and “indirectly on” in others.

[0021] Due to cost and power consumption considerations, mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to deep submicron process nodes. Additional circuitry for supporting communication enhancements, such as sixth-generation (6G) and fifth-generation (5G) New Radio (NR) communication systems, further complicates the design of mobile RF transceivers. Further design challenges for mobile RF transceivers include the use of passive components, which directly impact analog RF performance considerations, including mismatch, noise, and other performance factors.

[0022] Passive components in mobile RF transceivers may include high-performance capacitor assemblies. For example, analog integrated circuits use several types of passive components, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors (MOSCAP), pn junction capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-polysilicon capacitors, metal-oxide-metal (MOM) capacitors (MOMCAP), and other similar capacitor structures. Capacitors are passive components used in integrated circuits to store charge. For example, parallel-plate capacitors are typically made using conductive plates or structures with insulating material between the plates. The storage capacity or capacitance of a given capacitor depends on the materials used to manufacture the plates and insulator, the area of ​​the plates, and the spacing between the plates. The insulating material is typically a dielectric material.

[0023] These parallel-plate capacitors occupy a large area on semiconductor chips because many designs place the capacitors above the chip's substrate. Unfortunately, this approach reduces the usable area for active devices. Another approach is to create a vertical structure, which can be called a vertical parallel-plate (VPP) capacitor. A VPP capacitor structure can be created by stacking interconnect layers on the chip.

[0024] However, VPP capacitor structures have lower capacitance storage or lower “density” because these structures do not store much charge. Specifically, the dimensions of the interconnects and via interconnect traces used to fabricate VPP capacitors can be very small. The spacing between the interconnects and via conductive traces in a VPP structure is limited by design rules, which often results in a large area for achieving some of the desired capacitance in such structures. Although described as “vertical,” these structures can be oriented in any direction perpendicular to the surface of the substrate, or at other angles not parallel to the substrate.

[0025] MOMCAP and MOSCAP are examples of VPP capacitors. Due to their beneficial properties, MOMCAP is one of the most widely used capacitors. Specifically, MOMCAP can provide high-quality capacitors in semiconductor processes without incurring the cost of additional processing steps compared to other capacitor structures. The MOMCAP structure achieves capacitance by using edge capacitance generated by groups of intersecting fingers. That is, MOMCAP utilizes lateral capacitive coupling between a plate formed by a metallization layer and wiring traces.

[0026] Radio frequency (RF) analog (RFA) designs utilize capacitors extensively. Therefore, increasing capacitor density leads to smaller RFA design area and cost savings. Unfortunately, current MOMCAP layouts are inefficiently stacked, and MOMCAP layouts can occupy 15% to 20% of the chip area. Consequently, stacking MOMCAP and MOMCAP layouts is not widely adopted, especially in cost-sensitive technologies with limited metal layers. Therefore, an efficient stacking method for MOMCAP and MOMCAP layouts is desired for improved RFA designs.

[0027] Various aspects of this disclosure provide an optimized stacked layout of high-density metal-oxide-semiconductor (MOS) capacitors (MOSCAPs) and metal-oxide-metal (MOM) capacitors (MOMCAPs). Process flows for fabricating capacitor arrays and inductors may include front-end (FEOL) processes, mid-end (MOL) processes, and back-end (BEOL) processes. It should be understood that the term "layer" includes films and will not be construed as indicating vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to a substrate of a diced wafer or a substrate of an undicated wafer. Similarly, the terms "chip" and "die" are used interchangeably.

[0028] As described, a BEOL interconnect layer can refer to a conductive interconnect layer (e.g., a first interconnect layer (M1) or metal one (M1), metal two (M2), metal three (M3), metal four (M4), etc.) used for electrical coupling to FEOL active devices of an integrated circuit. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, wherein the lower BEOL interconnect level uses a thinner metal layer relative to the upper BEOL interconnect level. BEOL interconnect layers can be electrically coupled to MOL interconnect layers, for example, to connect M1 to an oxide diffusion (OD) layer of the integrated circuit. Mid-process interconnect layers can include zero interconnect layers (M0) for connecting M1 to active device layers of the integrated circuit. A BEOL first via (V2) can connect M2 to M3 or other layers in the BEOL interconnect layer.

[0029] According to various aspects of this disclosure, an optimized stacked layout of a high-density metal-oxide-semiconductor (MOS) capacitor (MOSCAP) and a metal-oxide-metal (MOM) capacitor (MOMCAP) is described. The capacitor stacked layout includes a MOMCAP consisting of a first terminal coupled to a first set of fingers. The MOMCAP also includes a second terminal coupled to and intersecting with a second set of fingers consisting of first metal layer interconnects. The capacitor stacked layout further includes a MOSCAP consisting of a polysilicon region coupled to the first set of fingers of the first terminal. The MOSCAP includes a diffusion region coupled to the second set of fingers.

[0030] Figure 1 This is a schematic diagram of a radio frequency (RF) front-end (RFFE) module 100 employing passive devices including capacitors 116 (e.g., an optimized stacked layout of high-density metal-oxide-semiconductor (MOS) capacitors and metal-oxide-metal (MOM) capacitors). The RFFE module 100 includes a power amplifier 102, a duplexer / filter 104, and an RF switch module 106. The power amplifier 102 amplifies the signal to a certain power level for transmission. The duplexer / filter 104 filters the input / output signal according to various parameters, including frequency, insertion loss, rejection, or other similar parameters. Furthermore, the RF switch module 106 can select certain portions of the input signal to be passed to the remainder of the RFFE module 100.

[0031] The RFFE module 100 also includes tuner circuitry 112 (e.g., first tuner circuitry 112A and second tuner circuitry 112B), a duplexer 200, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. Tuner circuitry 112 (e.g., first tuner circuitry 112A and second tuner circuitry 112B) includes components such as a tuner, a portable data input terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). Tuner circuitry 112 can perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) on antenna 114. RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. Passive combiner 108 combines the power detected from first tuner circuitry 112A and second tuner circuitry 112B. Wireless transceiver 120 processes information from passive combiner 108 and provides this information to modem 130 (e.g., mobile station modem (MSM)). Modem 130 provides digital signals to application processor (AP) 140.

[0032] like Figure 1As shown, duplexer 200 is positioned between the tuner components of tuner circuitry 112 and capacitor 116, inductor 118, and antenna 114. Duplexer 200 can be placed between antenna 114 and tuner circuitry 112 to provide high system performance from RFFE module 100 to a chipset including WTR 120, modem 130, and application processor 140. Duplexer 200 also performs frequency domain multiplexing for both high-band and low-band frequencies. After duplexer 200 performs its frequency multiplexing function on the input signal, the output of duplexer 200 is fed to an optional inductor / capacitor (LC) network including capacitor 116 and inductor 118. The LC network can provide additional impedance matching components for antenna 114 when needed. Signals with specific frequencies are then transmitted or received by antenna 114. Although a single capacitor and inductor are shown, multiple components are conceivable.

[0033] Figure 2 This is a schematic diagram of a wireless local area network (WLAN) (e.g., Wi-Fi) module 170 including a first duplexer 200-1 and a radio frequency (RF) front-end (RFFE) module 150 including a second duplexer 200-2 for a chipset 160, according to various aspects of this disclosure. The chipset includes an optimized stacked layout of high-density metal-oxide-semiconductor (MOS) capacitors (MOSCAP) and metal-oxide-metal (MOM) capacitors (MOMCAP). The Wi-Fi module 170 includes a first duplexer 200-1 that communicatively couples an antenna 192 to a WLAN module (e.g., WLAN module 172). The RFFE module 150 includes a second duplexer 200-2 that communicatively couples an antenna 194 to a wireless transceiver (WTR) 120 via a duplexer 180. The WTR 120 and the WLAN module 172 of the Wi-Fi module 170 are coupled to a modem (MSM, e.g., a baseband modem) 130 powered by a power supply 152 via a power management integrated circuit (PMIC) 156. Chipset 160 also includes capacitors 162 and 164 and inductor 166 to provide signal integrity.

[0034] PMIC 156, MSM 130, WTR 120, and WLAN module 172 each include capacitors (e.g., 158, 132, 122, and 174) and operate according to clock 154. Additionally, inductor 166 couples MSM 130 to PMIC 156. The geometry and arrangement of the various capacitors and inductors in chipset 160 can occupy a significant amount of chip area. The design of chipset 160 involves a large number of capacitors. Therefore, increasing capacitor density leads to a reduction in the area and cost savings of the chipset 160 design. Unfortunately, the current MOMCAP layout is inefficiently stacked, and the MOSCAP layout can occupy 15% to 20% of the chip area of ​​a typical product. Therefore, stacking of MOSCAP and MOMCAP layouts is not widely used, especially in cost-sensitive technologies with limited metal layers. Therefore, an efficient stacking of MOSCAP and MOMCAP layouts for improved radio frequency analog (RFA) designs is desired.

[0035] Capacitors are widely used in analog integrated circuits. Figure 3 This is a block diagram illustrating a cross-section of an analog integrated circuit (IC) device 300 including an interconnect stack 310. The interconnect stack 310 of the IC device 300 includes conductive interconnect layers (M1, ..., M9, M10) on a semiconductor substrate (e.g., a diced silicon wafer) 302. The semiconductor substrate 302 supports metal-oxide-semiconductor (MOM) capacitors (MOMCAPs) 330 and / or metal-oxide-semiconductor (MOS) capacitors (MOSCAPs). In this example, MOMCAP 330 is formed in interconnect layers M3 and M4 below interconnect layers M5 and M6. MOMCAP 330 is formed using lateral conductive fingers of different polarities from the conductive interconnect layers (M3 and M4) of the interconnect stack 310. A dielectric (not shown) is provided between the conductive fingers.

[0036] In this example, MOMCAP 330 is formed within the lower conductive interconnect layers (e.g., M1 to M4) of the interconnect stack 310. The lower conductive interconnect layers of the interconnect stack 310 have a smaller interconnect width and spacing. For example, the dimensions of conductive interconnect layers M3 and M4 are half the size of conductive interconnect layers M5 and M6. Similarly, the dimensions of conductive interconnect layers M1 and M2 are half the size of conductive interconnect layers M3 and M4. The small interconnect width and spacing of the lower conductive interconnect layers enable the formation of MOMCAPs with increased capacitance density.

[0037] like Figure 3As shown, MOMCAP 330 utilizes lateral (intra-layer) capacitive coupling 340 between fingers (e.g., 350, 370) formed by standard metallization of conductive interconnects (e.g., wiring and vias). In various aspects of this disclosure, optimized high-density MOSCAP and MOMCAP stack layouts are provided, for example, as... Figure 4 As shown.

[0038] Figure 4 This is a schematic top view illustrating the stacked layout of metal oxide metal (MOM) capacitors (MOMCAP) and metal oxide semiconductor (MOS) capacitors (MOSCAP) according to various aspects of this disclosure. Figure 4 As shown, the stacked layout 400 of MOSCAP and MOMCAP includes a metal oxide metal (MOM) capacitor (MOMCAP) consisting of a first (T1) terminal coupled to a first set of fingers 410 (410-1, 410-2, ..., 410-10). The MOMCAP also includes a second (T2) terminal coupled to a second set of fingers 412 (412-1, 412-2, ..., 412-9) composed of first metal layer (M1) interconnects and intersecting with the first set of fingers 410 composed of M1 interconnects. The stacked layout 400 of MOSCAP and MOMCAP also includes a metal oxide semiconductor (MOS) capacitor (MOSCAP) consisting of polysilicon terminals 420 of the first set of fingers 410 coupled to the T1 terminal. The MOSCAP includes diffused terminals 430 of the second set of fingers 412 coupled to the T2 terminal of the MOMCAP.

[0039] In various aspects of this disclosure, the outer fingers (e.g., 410-1 and 410-10) of the first set of fingers 410 of the T1 terminal are coupled to the polysilicon terminal 420. As... Figure 4 As shown, the first outer finger 410-1 is coupled to the polysilicon terminal 420 via the first set of metal-to-polysilicon (MP) contacts 422, and the tenth outer finger 410-10 is coupled to the polysilicon terminal 420 via the second set of metal-to-polysilicon (MP) contacts 424. Additionally, the diffusion terminal 430 is coupled to the second set of fingers 412 and the T2 terminal. Figure 4 As shown, the first set of metal-to-diffusion (MD) contacts 432 (432-1, ..., 432-9) couples the diffusion terminal 430 to the end of the second set of fingers 412 away from the T2 terminal. Additionally, the second set of metal-to-diffusion (MD) contacts 434 (434-1, ..., 434-22) couples the diffusion terminal 430 to one end of the T2 terminal.

[0040] Figure 5 This illustrates various aspects of this disclosure. Figure 4 A schematic top view of a metal oxide metal (MOM) capacitor (MOMCAP) arranged in a stacked configuration with multiple metal oxide semiconductor (MOS) capacitors (MOSCAPs). Figure 5 As shown, a capacitor stacking layout of 500 is illustrated. Figure 4 The MOMCAP is arranged with multiple stacked MOSCAP 540s (540-1, 540-2, 540-3) to support high-voltage (e.g., six-volt (6V)) applications. In this example, the first polysilicon terminal 520-1 of the first MOSCAP 540-1 is coupled to the T1 terminal of the MOMCAP via a first polysilicon contact 522. Additionally, the first polysilicon terminal 520-1 of the first MOSCAP 540-1 is alternately coupled to the T1 terminal of the MOMCAP via a second polysilicon contact 524.

[0041] In these aspects of the present disclosure, the first diffusion terminal 530-1 of the first MOSCAP 540-1 is shorted to the second diffusion terminal 530-2 of the second MOSCAP 540-2. Additionally, the second polysilicon terminal 520-2 of the second MOSCAP 540-2 is shorted to the third polysilicon terminal 520-3 of the third MOSCAP 540-3. In various aspects of the present disclosure, the third diffusion terminal 530-3 of the third MOSCAP 540-3 is coupled to the T3 terminal of the third MOSCAP 540-3 via diffusion contacts 534 (534-1, ..., 534-22). In various aspects of the present disclosure, relative to lower voltage applications (e.g., 2.5V), Figure 5 The stacking of MOSCAP 540s in the capacitor stack layout 500 advantageously supports higher voltage applications (e.g., 6V applications). In this example, considering the space lost due to receiver (RX) separation, the capacitance density of the stacked MOMCAPs in the capacitor stack layout 500 is 1.6 femtofarads (fF) / micrometer. 2 .

[0042] Figures 6A to 6C This further illustrates various aspects of this disclosure. Figure 4 A schematic cross-sectional view of a stacked layout of metal oxide metal (MOM) capacitors (MOMCAP) and metal oxide semiconductor (MOS) capacitors (MOSCAP).

[0043] Figure 6A Examples are given along the cutting line AA' according to various aspects of this disclosure. Figure 4A cross-sectional view 600 of a stacked layout 400 of MOSCAP and MOMCAP is shown. As shown in cross-sectional view 600, the stacked layout 400 of MOSCAP and MOMCAP includes a semiconductor-on-insulator (SOI) substrate 401 that supports the N-type well (N-well), N+ diffusion region (e.g., source / drain region), and shallow trench isolation (STI) region of the MOSCAP. The MOSCAP also includes a polysilicon terminal 420 on oxide on the N-well to provide the polysilicon terminal 420 of the MOSCAP, and the N+ diffusion region to provide the diffusion terminal 430 of the MOSCAP in the stacked layout 400 of MOSCAP and MOMCAP. Additionally, the MOMCAP is shown as including M1 T1 terminal and M1 T2 terminal, which are coupled to the diffusion terminal 430 via metal-to-diffusion (MD) contacts 432 and 434 through the first interlayer dielectric (ILD). In this example, terminal M2 T1 is coupled to terminal T1 through a first BEOL via V1 in the second ILD, and terminal M2 T2 is coupled to terminal M1 T2 through a first BEOL via V1 in the second ILD.

[0044] Figure 6B Examples of various aspects of this disclosure along the cutting line BB' are illustrated. Figure 4 A cross-sectional view 650 of the stacked layout 400 of MOSCAP and MOMCAP is shown. As shown in cross-sectional view 650, the MOMCAP is shown as including an M1 T1 terminal not coupled to the diffusion terminal 430, and an M1 T2 terminal coupled to the diffusion terminal through an MD contact 434 passing through the first ILD. Additionally, the M2 T1 terminal is coupled to the M1 T1 terminal through a via V1 in the second ILD, and the M2 T2 terminal is coupled to the M1 T1 terminal through a via V1 in the second ILD.

[0045] Figure 6C Examples of various aspects of this disclosure along the cutting line CC' are illustrated. Figure 4 A cross-sectional view 670 of the stacked layout 400 of MOSCAP and MOMCAP is shown. As shown in cross-sectional view 670, the outer fingers (e.g., 1 and 19) of the first set of fingers of the MOMCAP are coupled to the polysilicon terminal 420 via metal-to-polysilicon (MP) contacts 422 and 424. Additionally, M2 T1 terminals (e.g., M2-1, M2-3, ..., M2-19) and M2 T2 terminals (e.g., M2-2, M2-4, ..., M2-18) are shown. The connections between the M2 T1 and T2 terminals and the M1 T1 and T2 terminals are not shown.

[0046] Figure 7This is a process flow diagram illustrating method 700 for forming a metal-oxide-semiconductor (MOS) capacitor (MOSCAP) and a metal-oxide-metal (MOM) capacitor (MOMCAP) according to various aspects of this disclosure. Method 700 begins at block 702, wherein a MOMCAP is formed, the MOMCAP including a first terminal coupled to a first finger of a first metal interconnect layer, and a second terminal coupled to a second finger of the first metal interconnect layer and intersecting the first finger of the first metal interconnect layer. For example, as Figure 4 As shown, the MOMCAP consists of a first (T1) terminal coupled to a first set of fingers 410 (410-1, 410-2, ..., 410-10). The MOMCAP also includes a second (T2) terminal coupled to a second set of fingers 412 (412-1, 412-2, ..., 412-9) composed of first metal layer (M1) interconnects and intersecting with the first set of fingers 410 composed of M1 interconnects.

[0047] At frame 740, a first MOSCAP is formed, the first MOSCAP including a polysilicon terminal of a first finger coupled to a first terminal of the MOSCAP, and a diffused terminal of a second finger coupled to a second terminal of the MOSCAP. For example, as Figure 4 As shown, the stacked layout 400 of MOSCAP and MOMCAP also includes a MOSCAP consisting of polysilicon terminals 420 of a first set of fingers 410 coupled to the T1 terminal. The MOSCAP includes diffused terminals 430 of a second set of fingers 412 coupled to the T2 terminal of the MOMCAP.

[0048] Figure 8 This is a block diagram illustrating an exemplary wireless communication system 800 in which aspects of this disclosure can be advantageously employed. For illustrative purposes, Figure 8 Three remote units 820, 830, and 850 and two base stations 840 are shown. It should be understood that the wireless communication system may have more remote units and base stations. Remote units 820, 830, and 850 include IC devices 825A, 825C, and 825B, which include a stacked arrangement of the disclosed capacitors. It should be understood that other devices may also include a stacked arrangement of the disclosed capacitors, such as base stations, switching devices, and network equipment. Figure 8 The forward link signal 880 from base station 840 to remote units 820, 830 and 850 is shown, as well as the reverse link signal 890 from remote units 820, 830 and 850 to base station 840.

[0049] exist Figure 8In this diagram, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal data assistant), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit (such as a meter reading device), or other devices that store or retrieve data or computer instructions, or combinations thereof. Figure 8 Remote units according to aspects of this disclosure are illustrated, but this disclosure is not limited to these exemplary illustrated units. Aspects of this disclosure may be adapted for use in a variety of devices including stacked arrangements of the disclosed capacitors.

[0050] Figure 9 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components, such as the capacitors disclosed above. Design workstation 900 includes a hard disk 901 containing operating system software, support files, and design software (such as Cadence or OrCAD). Design workstation 900 also includes a display 902 to facilitate the design of circuit 910 or RF component 912, such as the stacked layout of capacitors. Storage medium 904 is provided for tangibly storing the design of circuit 910 or RF component 912 (e.g., the disclosed stacked layout of capacitors). The design of circuit 910 or RF component 912 can be stored on storage medium 904 in file formats such as GDSII or GERBER. Storage medium 904 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, design workstation 900 includes a drive device 903 for accepting input from storage medium 904 or writing output to storage medium 904.

[0051] Data recorded on storage medium 904 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. Data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 904 facilitates the design of circuit 910 or RF component 912 (e.g., the disclosed stacked layout of capacitors) by reducing the number of processes used to design semiconductor wafers.

[0052] Specific implementation examples are described in the following numbered clauses: 1. An integrated circuit (IC), said integrated circuit (IC) comprising: Metal oxide metal (MOM) capacitor (MOMCAP), the metal oxide metal (MOMCAP) capacitor comprising: A first terminal, the first terminal being coupled to a first plurality of fingers of a first metal interconnect layer, and A second terminal, the second terminal being coupled to a second plurality of fingers of the first metal interconnect layer and intersecting with the first plurality of fingers of the first metal interconnect layer; and A first metal-oxide-semiconductor (MOS) capacitor (MOSCAP), the first metal-oxide-semiconductor (MOS) capacitor (MOSCAP) comprising: Polysilicon terminals, said polysilicon terminals being coupled to the first plurality of fingers of the MOMCAP, and A diffusion terminal, which is coupled to the second plurality of fingers of the MOMCAP.

[0053] 2. The IC according to Clause 1, wherein the outer finger of the first plurality of fingers is coupled to the polysilicon terminal via a plurality of polysilicon contacts.

[0054] 3. The IC according to any one of Clauses 1 or 2, wherein the diffusion terminal is coupled to the second terminal via a plurality of diffusion contacts.

[0055] 4. The IC according to any one of clauses 1 to 3, wherein the diffusion terminal is coupled to the end of the second plurality of fingers remote from the second terminal via a plurality of diffusion contacts.

[0056] 5. The IC according to any one of clauses 1 to 4, wherein the IC further comprises: The second MOSCAP is coupled to the first MOSCAP; and A third MOSCAP coupled to the second MOSCAP.

[0057] 6. The IC according to Clause 5, wherein the second diffusion terminal of the second MOSCAP is shorted to the diffusion terminal of the first MOSCAP.

[0058] 7. The IC according to any one of Clauses 5 or 6, wherein the second polysilicon terminal of the second MOSCAP is shorted to the third polysilicon terminal of the third MOSCAP.

[0059] 8. The IC according to any one of clauses 5 to 7, wherein the third diffusion terminal of the third MOSCAP is coupled to the second terminal of the MOMCAP.

[0060] 9. The IC according to any one of clauses 1 to 8, wherein the IC is integrated in a radio frequency (RF) front-end (RFFE) module.

[0061] 10. The IC according to Clause 9, wherein the RFFE module is integrated in a mobile phone, set-top box, music player, video player, entertainment unit, navigation device, computer, handheld personal communication system (PCS) unit, portable data unit, and / or fixed location data unit.

[0062] 11. A method for forming a metal-oxide-semiconductor (MOS) capacitor (MOSCAP) and a metal-oxide-metal (MOM) capacitor (MOMCAP), the method comprising: The MOMCAP is formed, and the MOMCAP includes: A first terminal, the first terminal being coupled to a first plurality of fingers of a first metal interconnect layer, and A second terminal, the second terminal being coupled to and intersecting with the first plurality of fingers of the first metal interconnect layer; and A first MOSCAP is formed, the first MOSCAP comprising: Polysilicon terminals, said polysilicon terminals being coupled to the first plurality of fingers of the MOMCAP, and A diffusion terminal, which is coupled to the second plurality of fingers of the MOMCAP.

[0063] 12. The method according to Clause 11, wherein the outer finger of the first plurality of fingers is coupled to the polysilicon terminal via a plurality of polysilicon contacts.

[0064] 13. The method according to any one of clauses 11 or 12, wherein the diffusion terminal is coupled to the second terminal via a plurality of diffusion contacts.

[0065] 14. The method according to any one of clauses 11 to 13, wherein the diffusion terminal is coupled to the end of the second plurality of fingers remote from the second terminal via a plurality of diffusion contacts.

[0066] 15. The method according to any one of clauses 11 to 14, the method further comprising: Forming a second MOSCAP coupled to the first MOSCAP; and A third MOSCAP is formed that is coupled to the second MOSCAP.

[0067] 16. The method according to Clause 15, wherein the second diffusion terminal of the second MOSCAP is shorted to the diffusion terminal of the first MOSCAP.

[0068] 17. The method according to any one of Clauses 15 or 16, wherein the second polysilicon terminal of the second MOSCAP is shorted to the third polysilicon terminal of the third MOSCAP.

[0069] 18. The method according to any one of Clauses 15 to 17, wherein the third diffusion terminal of the third MOSCAP is coupled to the second terminal of the MOMCAP.

[0070] 19. The method according to any one of Clauses 11 to 18, the method further comprising integrating the first MOSCAP and the MOMCAP in a radio frequency (RF) front-end (RFFE) module.

[0071] 20. The method according to Clause 19, further comprising integrating the RFFE module into a mobile phone, set-top box, music player, video player, entertainment unit, navigation device, computer, handheld personal communication system (PCS) unit, portable data unit, and / or fixed location data unit.

[0072] For specific firmware and / or software implementations, these methods can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media that tangibly embody instructions can be used to implement the methods described herein. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used herein, the term "memory" refers to various types of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type of memory or a particular number of memories, or the type of medium for storing information in memory.

[0073] If implemented in firmware and / or software, the functionality may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoding data structures and computer-readable media encoding computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium that a computer can access. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; as used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while optical discs use lasers to optically copy data. Combinations of the above should also be included within the scope of computer-readable media.

[0074] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals included on a transmission medium in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0075] Although this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the technology of this disclosure as defined in the appended claims. For example, relational terms such as “above” and “below” are used for substrates or electronic devices. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if it is laterally oriented, above and below may refer to the sides of the substrate or electronic device. Furthermore, the scope of this application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods, and steps described in the specification. As will be readily understood by those skilled in the art from this disclosure, processes, machines, manufactures, material compositions, components, methods, or steps that currently exist or will be developed later can be utilized to perform the same function or achieve the same result as the corresponding configuration described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0076] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with this disclosure can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been broadly described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0077] Using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or any combination thereof designed to perform the functions described herein, various exemplary logic blocks, modules, and circuits described in connection with the disclosure herein can be implemented or executed. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0078] The steps or algorithms of the methods described in this disclosure may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0079] In one or more exemplary designs, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a general-purpose or special-purpose computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store specified program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0080] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), said integrated circuit (IC) comprising: Metal oxide metal (MOM) capacitor (MOMCAP), the metal oxide metal (MOMCAP) capacitor comprising: A first terminal, the first terminal being coupled to a first plurality of fingers of a first metal interconnect layer, and A second terminal, the second terminal being coupled to a second plurality of fingers of the first metal interconnect layer and intersecting with the first plurality of fingers of the first metal interconnect layer; and A first metal-oxide-semiconductor (MOS) capacitor (MOSCAP), the first metal-oxide-semiconductor (MOS) capacitor (MOSCAP) comprising: Polysilicon terminals, said polysilicon terminals being coupled to the first plurality of fingers of the MOMCAP, and A diffusion terminal, which is coupled to the second plurality of fingers of the MOMCAP.

2. The IC according to claim 1, wherein the outer finger of the first plurality of fingers is coupled to the polysilicon terminal via a plurality of polysilicon contacts.

3. The IC according to claim 1, wherein the diffusion terminal is coupled to the second terminal through a plurality of diffusion contacts.

4. The IC according to claim 1, wherein the diffusion terminal is coupled to the end of the second plurality of fingers away from the second terminal via a plurality of diffusion contacts.

5. The IC according to claim 1, further comprising: A second MOSCAP coupled to the first MOSCAP; and A third MOSCAP coupled to the second MOSCAP.

6. The IC according to claim 5, wherein the second diffusion terminal of the second MOSCAP is shorted to the diffusion terminal of the first MOSCAP.

7. The IC according to claim 5, wherein the second polysilicon terminal of the second MOSCAP is shorted to the third polysilicon terminal of the third MOSCAP.

8. The IC of claim 5, wherein the third diffusion terminal of the third MOSCAP is coupled to the second terminal of the MOMCAP.

9. The IC according to claim 1, wherein the IC is integrated in a radio frequency (RF) front-end (RFFE) module.

10. The IC of claim 9, wherein the RFFE module is integrated in a mobile phone, set-top box, music player, video player, entertainment unit, navigation device, computer, handheld personal communication system (PCS) unit, portable data unit, and / or fixed location data unit.

11. A method for forming a metal-oxide-semiconductor (MOS) capacitor (MOSCAP) and a metal-oxide-metal (MOM) capacitor (MOMCAP), the method comprising: The MOMCAP is formed, and the MOMCAP includes: A first terminal, the first terminal being coupled to a first plurality of fingers of a first metal interconnect layer, and A second terminal, the second terminal being coupled to and intersecting with the first plurality of fingers of the first metal interconnect layer; and A first MOSCAP is formed, the first MOSCAP comprising: Polysilicon terminals, said polysilicon terminals being coupled to the first plurality of fingers of the MOMCAP, and A diffusion terminal, which is coupled to the second plurality of fingers of the MOMCAP.

12. The method of claim 11, wherein the outer finger of the first plurality of fingers is coupled to the polysilicon terminal via a plurality of polysilicon contacts.

13. The method of claim 11, wherein the diffusion terminal is coupled to the second terminal via a plurality of diffusion contacts.

14. The method of claim 11, wherein the diffusion terminal is coupled to the end of the second plurality of fingers remote from the second terminal via a plurality of diffusion contacts.

15. The method according to claim 11, further comprising: A second MOSCAP is formed that is coupled to the first MOSCAP; as well as A third MOSCAP is formed that is coupled to the second MOSCAP.

16. The method of claim 15, wherein the second diffusion terminal of the second MOSCAP is shorted to the diffusion terminal of the first MOSCAP.

17. The method of claim 15, wherein the second polysilicon terminal of the second MOSCAP is shorted to the third polysilicon terminal of the third MOSCAP.

18. The method of claim 15, wherein the third diffusion terminal of the third MOSCAP is coupled to the second terminal of the MOMCAP.

19. The method of claim 11, further comprising integrating the first MOSCAP and the MOMCAP in a radio frequency (RF) front-end (RFFE) module.

20. The method of claim 19, further comprising integrating the RFFE module into a mobile phone, set-top box, music player, video player, entertainment unit, navigation device, computer, handheld personal communication system (PCS) unit, portable data unit, and / or fixed location data unit.

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