Anti-electromagnetic interference band-gap reference voltage reference circuit and construction method thereof

Abstract

The invention provides an anti-electromagnetic interference band-gap reference voltage reference circuit and a construction method thereof. The anti-electromagnetic interference band-gap reference voltage reference circuit comprises a biasing circuit, a starting circuit, a double differential pair amplifier and a band-gap reference circuit, the biasing circuit is used for providing a working environment for an electronic device, and the biasing circuit does not depend on a power supply, so that the power consumption is reduced while the sensitivity of electromagnetic interference is reduced; the starting circuit is used for providing initial conditions when the reference circuit starts to operate; the double differential pair amplifier is used for amplifying the reference voltage and inhibiting direct current offset; the band-gap reference circuit is used for generating stable reference voltage so as to reduce the electromagnetic interference sensitivity of the reference circuit and keep a low temperature coefficient; therefore, the anti-electromagnetic interference capability of the circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic interference suppression technology, and more specifically, to an electromagnetic interference-suppressing bandgap reference voltage circuit and its construction method. Background Technology

[0002] Bandgap reference circuits are commonly used and precise reference circuits for achieving high-precision voltage references. They utilize the bandgap characteristics of semiconductors or insulators to maintain a stable output voltage at varying temperatures. By strategically configuring materials or circuits with positive and negative temperature coefficients, the effects of temperature are offset, resulting in a constant voltage output independent of temperature. This leads to a circuit with excellent temperature stability. The Kuijk BGR topology offers better electromagnetic interference (EMI) immunity. It employs PMOS pass-through devices and AC grounding compensation capacitors for operating the transconductance amplifier (OTA) to stabilize the gate-source voltage of the former, thereby eliminating the impact of low-frequency EMI on the drain current. However, due to the nonlinear output resistance of the input differential pair, this topology remains susceptible to high-frequency EMI. Traditional bandgap voltage reference circuits primarily focus on small-signal performance to achieve lower temperature coefficients, higher power supply rejection ratios, and lower power consumption. However, voltage interference caused by EMI can be several orders of magnitude higher than that caused by temperature variations; therefore, EMI injection can degrade the performance of bandgap voltage reference circuits.

[0003] In view of this, the present invention proposes an electromagnetic interference-resistant bandgap reference voltage circuit and its construction method, employing... The basic topology of bandgap circuits is achieved by using... Channel devices and active loads, as well as dual differential pairs and power supply-independent bias circuitry, are used to improve EMI immunity. Summary of the Invention

[0004] The present invention aims to provide an electromagnetic interference-resistant bandgap reference voltage circuit, comprising a bias circuit, a startup circuit, a dual differential amplifier, and a bandgap reference circuit; the bias circuit provides an operating environment for electronic devices and is power-independent, thereby saving power consumption while reducing electromagnetic interference sensitivity; the startup circuit provides initial conditions for the reference circuit to start operating; the dual differential amplifier amplifies the reference voltage and suppresses DC offset; and the bandgap reference circuit generates a stable reference voltage to reduce the electromagnetic interference sensitivity of the reference circuit and maintain a low temperature coefficient.

[0005] Furthermore, the bias circuit includes a MOS transistor and a resistor; an NMOS transistor. The source of the NMOS transistor The source and NMOS transistor Source and power supply Connection; the NMOS transistor The drain and PMOS transistor The drain and gate of the NMOS transistor are connected to the dual differential pair amplifier; the NMOS transistor is connected to the dual differential pair amplifier. The gate of the NMOS transistor The gate of the NMOS transistor The gate and drain of the PMOS transistor The drain connection of the NMOS transistor Mb5 is connected to the drain of the PMOS transistor. The drain and gate of the PMOS transistor gate, PMOS transistor The gate, the startup circuit, and the dual differential pair amplifier are connected; the PMOS transistor The source of the PMOS transistor The drain connection; the PMOS transistor The source and the PMOS transistor The source of the PMOS transistor is grounded; Source grounding resistance .

[0006] Furthermore, the startup circuit includes a MOS transistor and a PMOS transistor. The gate of the PMOS transistor is connected to the bias circuit and the dual differential pair amplifier. The drain of the PMOS transistor is connected to the dual differential amplifier, and the source of the PMOS transistor is connected to the bandgap reference circuit.

[0007] Furthermore, the dual differential pair amplifier includes MOS transistors and resistors; NMOS transistors The source and NMOS transistor Source and power supply Connection; the NMOS transistor The drain of the PMOS transistor and the bandgap reference circuit are connected. The drain and gate of the PMOS transistor The gate connection of the NMOS transistor; The gate of the NMOS transistor The gate and drain of the PMOS transistor The drain of the PMOS transistor is connected to the startup circuit; The source and PMOS transistor The drain and PMOS transistor The drain connection; the PMOS transistor The source and PMOS transistor The drain and PMOS transistor The drain connection; the PMOS transistor The gate and the bandgap reference circuit and the capacitor Connection, the PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection of the capacitor; The other end is connected to the resistor and the PMOS transistor The gate connection; the resistor The other end is connected to the resistor and the bias circuit connection; the PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection; the PMOS transistor The gate and the resistor The other end and the capacitor Connection; the capacitor The other end is connected to the PMOS transistor The gate of the PMOS transistor is connected to the bandgap reference circuit; The gate of the PMOS transistor The gate, the startup circuit, and the bias circuit are connected; the PMOS transistor The source and the PMOS transistor The source electrode is grounded.

[0008] Furthermore, the bandgap reference circuit includes resistors, capacitors, and MOS transistors; NMOS transistors The source and capacitor With power supply Connection; the NMOS transistor The gate and the capacitor The other end is connected to the dual differential pair amplifier; the NMOS transistor The drain of the circuit and the resistor ,resistance and grounding capacitor Connect and output the reference voltage. The resistor The other end is connected to the resistor and the dual differential pair amplifier connection; the resistor The other end is connected to the PMOS transistor The gate and drain are connected; the PMOS transistor The source of the resistor is grounded; The other end is connected to the PMOS transistor The drain and gate of the PMOS transistor are connected to the dual differential pair amplifier; the PMOS transistor is connected to the dual differential pair amplifier. The source electrode is grounded.

[0009] A method for constructing a bandgap reference voltage circuit for electromagnetic interference immunity as described in any of the above claims includes: determining a temperature-independent bandgap reference circuit; determining a dual differential pair amplifier; and determining a power supply-independent bias circuit and a startup circuit.

[0010] Further, determining a temperature-independent bandgap reference circuit includes: obtaining an original bandgap reference circuit and replacing the bipolar junction transistors (BJTs) in the original bandgap reference circuit with metal-oxide-semiconductor (MOSFETs) to obtain a new bandgap reference circuit; determining an expression for a reference voltage based on the structure of the new bandgap reference circuit; and determining an expression for a reference voltage based on the reference voltage. The expression is used to determine the parameters of the components in the new bandgap reference circuit, thereby obtaining a temperature-independent bandgap reference circuit.

[0011] Furthermore, the characteristic is that the expression for the reference voltage is:

[0012]

[0013] in, Indicates the reference voltage; This represents the gate-source voltage of the NMOS transistor M2; Indicates process constant; This represents the thermal voltage related to temperature. Represents the natural logarithm; This indicates the aspect ratio of the NMOS M11 transistor; Indicates resistance The resistance value; Indicates resistance The resistance value; This indicates the aspect ratio of the NMOS M10 transistor.

[0014] Furthermore, the feature is that the dual differential pair amplifier is characterized by: employing a dual differential pair combining DC-coupled and AC-coupled technologies, self-cancelling high-frequency input, obtaining stable output impedance and positive feedback; setting the high-pass frequency domain of the AC coupling network according to the full range of electromagnetic interference, and ensuring that the DC loop gain is non-zero and the PMOS transistor... Gate voltage and PMOS transistor The gate voltages are equal; determine the expression for the equivalent output load, and based on the expression for the equivalent output load, determine the resistance. ,resistance and resistance The resistance value and PMOS transistor and PMOS transistor The transconductance; where the resistance and resistance The resistance values ​​are equal; determine the dominant parasitic capacitance at high frequencies.

[0015] Furthermore, determining the bias circuit and startup circuit independent of the power supply includes: determining the expression for the bias current, ensuring that the threshold voltages of all transistors are the same and ignoring channel length modulation; adjusting the threshold voltages of the transistors and the channel lengths to ensure that the level of the bias current is within the voltage swing range of the transistors; and adding a startup circuit to ensure that the NMOS transistors... The drain output current is not zero.

[0016] The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects:

[0017] The bandgap reference voltage circuit for electromagnetic interference resistance proposed in this invention has better electromagnetic interference resistance.

[0018] The electromagnetic interference-resistant bandgap reference voltage circuit proposed in this invention reduces electromagnetic interference sensitivity while saving power consumption by employing a bias that is independent of power supply.

[0019] The electromagnetic interference-resistant bandgap reference voltage circuit proposed in this invention can suppress DC offset by employing a dual differential pair amplifier.

[0020] The electromagnetic interference-resistant bandgap reference voltage circuit proposed in this invention uses... (Metal-Oxide-Semiconductor Field-Effect Transistor) Replacement (Bipolar Junction Transistor) can further reduce the electromagnetic interference sensitivity of the circuit, improve the stability of the output reference voltage, and maintain a low temperature coefficient. Attached Figure Description

[0021] Figure 1 An exemplary circuit diagram of an electromagnetic interference-resistant bandgap reference voltage circuit provided by the present invention;

[0022] Figure 2 An enlarged view of the bias circuit provided by the present invention;

[0023] Figure 3 An enlarged view of the startup circuit provided by the present invention;

[0024] Figure 4 An enlarged view of the dual differential pair amplifier provided by the present invention;

[0025] Figure 5 An enlarged view of the bandgap reference circuit provided by this invention;

[0026] Figure reference numerals: 1-Bias circuit, 2-Start-up circuit, 3-Dual differential pair amplifier, 4-Bandgap reference circuit. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Figure 1 An exemplary circuit diagram of a bandgap reference voltage circuit for electromagnetic interference suppression provided by the present invention is shown. Figure 1 As shown, the electromagnetic interference-resistant bandgap reference voltage circuit provided by the present invention includes a bias circuit 1, a startup circuit 2, a dual differential pair amplifier 3, and a bandgap reference circuit 4.

[0029] Bias circuits are used to provide an operating environment for electronic devices. These bias circuits are independent of power supplies, thereby saving power consumption while reducing sensitivity to electromagnetic interference.

[0030] Electronic devices refer to components in a bandgap reference voltage circuit that is resistant to electromagnetic interference, and may include resistors, capacitors, and MOSFETs. The operating environment may include the voltage, current, and radiation of the electronic components.

[0031] The startup circuit provides initial conditions for the reference circuit to start operating. Initial conditions can refer to specific requirements such as voltage, circuit conditions, and states that must be met when the circuit starts working.

[0032] A dual differential amplifier is used to amplify the reference voltage and suppress DC offset.

[0033] Bandgap reference circuits are used to generate stable reference voltages to reduce the electromagnetic interference sensitivity of the reference circuit and maintain a low temperature coefficient. A low temperature coefficient means that a certain parameter in the circuit (such as resistance, capacitance, and voltage) does not change or changes very little with temperature.

[0034] Figure 2 An enlarged view of the bias circuit provided by this invention.

[0035] like Figure 2 As shown, the bias circuit includes a MOS transistor and a resistor; an NMOS transistor... The source of the NMOS transistor The source and NMOS transistor Source and power supply Connection; the NMOS transistor The drain and PMOS transistor The drain and gate of the NMOS transistor are connected to the dual differential pair amplifier; the NMOS transistor is connected to the dual differential pair amplifier. The gate of the NMOS transistor The gate of the NMOS transistor The gate and drain of the PMOS transistor The drain connection of the NMOS transistor Mb5 is connected to the drain of the PMOS transistor. The drain and gate of the PMOS transistor gate, PMOS transistor The gate, the startup circuit, and the dual differential pair amplifier are connected; the PMOS transistor The source of the PMOS transistor The drain connection; the PMOS transistor The source and the PMOS transistor The PMOS transistor with its source grounded Source grounding resistance .

[0036] Figure 3 An enlarged view of the startup circuit provided by this invention.

[0037] like Figure 3 As shown, the startup circuit includes a MOS transistor and a PMOS transistor. The gate of the PMOS transistor is connected to the bias circuit and the dual differential pair amplifier. The drain of the PMOS transistor is connected to the dual differential amplifier, and the source of the PMOS transistor is connected to the bandgap reference circuit.

[0038] Figure 4 This is an enlarged view of the dual differential pair amplifier provided by the present invention.

[0039] like Figure 4 As shown, the dual differential pair amplifier includes MOS transistors and resistors; NMOS transistors The source and NMOS transistor Source and power supply Connection; the NMOS transistor The drain of the PMOS transistor and the bandgap reference circuit are connected. The drain and gate of the PMOS transistor The gate connection of the NMOS transistor; The gate of the NMOS transistor The gate and drain of the PMOS transistor The drain of the PMOS transistor is connected to the startup circuit; The source and PMOS transistor The drain and PMOS transistor The drain connection; the PMOS transistor The source and PMOS transistor The drain and PMOS transistor The drain connection; the PMOS transistor The gate and the bandgap reference circuit and the capacitor Connection, the PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection of the capacitor; The other end is connected to the resistor and the PMOS transistor The gate connection; the resistor The other end is connected to the resistor and the bias circuit connection; the PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection; the PMOS transistor The gate and the resistor The other end and the capacitor Connection; the capacitor The other end is connected to the PMOS transistor The gate of the PMOS transistor is connected to the bandgap reference circuit; The gate of the PMOS transistor The gate, the startup circuit, and the bias circuit are connected; the PMOS transistor The source and the PMOS transistor The source electrode is grounded.

[0040] Figure 5 An enlarged view of the bandgap reference circuit provided by this invention.

[0041] like Figure 5 As shown, the bandgap reference circuit includes resistors, capacitors, and MOS transistors; NMOS transistors The source and capacitor With power supply Connection; the NMOS transistor The gate and the capacitor The other end is connected to the dual differential pair amplifier; the NMOS transistor The drain of the circuit and the resistor ,resistance and grounding capacitor Connect and output the reference voltage. The resistor The other end is connected to the resistor and the dual differential pair amplifier connection; the resistor The other end is connected to the PMOS transistor The gate and drain are connected; the PMOS transistor The source of the resistor is grounded; The other end is connected to the PMOS transistor The drain and gate of the PMOS transistor are connected to the dual differential pair amplifier; the PMOS transistor is connected to the dual differential pair amplifier. The source electrode is grounded.

[0042] The method for constructing an electromagnetic interference-resistant bandgap reference voltage circuit provided by this invention includes the following:

[0043] Determine a temperature-independent bandgap reference circuit. Derive the expressions for each physical quantity, and based on the parameters contained in the expressions, rationally select device dimensions and set necessary parameters such as channel width-to-length ratio and resistance value. Process constant This allows us to obtain a reference voltage that is highly insensitive to temperature. Temperature insensitivity means that temperature has little or no effect on the circuit and can be disregarded.

[0044] Among them, determining the temperature-independent bandgap reference circuit includes:

[0045] Obtain the original bandgap reference circuit, and replace the bipolar junction transistors (BJTs) in the original bandgap reference circuit with metal-oxide-semiconductor (MOS) field-effect transistors (FETs) to obtain a new bandgap reference circuit. middle, Complementary to absolute temperature The absolute temperature changes from positive to negative. The voltage across the junction or the base-emitter voltage under diode connection get. Taken from two The difference between the base and emitter voltages is proportional to the absolute temperature. In this design, due to quilt replace, Change to . The device dimensions should have a large aspect ratio to enable it to have Characteristics. The original bandgap reference circuit can refer to... Bandgap circuit.

[0046] Based on the structure of the new bandgap reference circuit, the expression for the reference voltage is determined:

[0047]

[0048] in, Indicates the reference voltage; This represents the gate-source voltage of the NMOS transistor M2; This represents a process constant, that is, a constant related to the process. This represents the thermal voltage related to temperature. Represents the natural logarithm; This indicates the aspect ratio of the NMOS M11 transistor; Indicates resistance The resistance value; Indicates resistance The resistance value; This indicates the aspect ratio of the NMOS M10 transistor. The structure of the new bandgap reference circuit includes... Subthreshold current and gate-source voltage of a (metal-oxide-semiconductor field-effect transistor). and The difference between the gate and source voltages and through Current, etc.

[0049] Based on the reference voltage The expression is used to determine the parameters of the components in the new bandgap reference circuit, thereby obtaining a temperature-independent bandgap reference circuit. According to... The expression, because Since this is temperature-dependent, the second term on the right side of the equation needs to be minimized as much as possible. One option is... The process achieves smaller Alternatively, you can choose... and The aspect ratio, and The resistance value should be configured appropriately to minimize the logarithmic term.

[0050] Determine the dual differential pair amplifier. Employ a dual differential pair combining DC and AC coupling techniques to cancel high-frequency inputs, achieving stable output impedance and positive feedback; set the high-pass frequency range of the AC coupling network to 150kHz across the entire electromagnetic interference (EMI) range from 150kHz to 1GHz; configure the resistors to... However, due to the high-pass frequency domain setting of the AC-coupled network, the nodes and The voltages are forced to have the same potential, therefore through and The current is the same.

[0051] Among them, determining the dual differential pair amplifier includes:

[0052] A dual differential pair combining DC and AC coupling technologies is employed, with self-cancelling high-frequency input, to achieve stable output impedance and positive feedback. Component selection is crucial. and With equal magnitudes, the output impedance is further simplified and is reflected by the current mirror. The positive feedback is masked, mainly by The channel length is determined by this. The high-frequency transconductance must satisfy the following conditions. This achieves zero gain and high-frequency differential input. This will be eliminated at the output node; the output node will only be affected by power supply. Injected The impact.

[0053] Based on the full range of electromagnetic interference, an AC coupling network is set up ( and The high-pass frequency domain (e.g., the full EMI range is typically from 150kHz to 1GHz, so the high-pass frequency domain of the AC-coupled network is set to 150kHz) and ensures that the DC loop gain is non-zero and the PMOS transistor... Gate voltage and PMOS transistor The gate voltages are equal.

[0054] Determine the expression for the equivalent output load, and based on the expression for the equivalent output load, determine the resistance. ,resistance and resistance The resistance value and PMOS transistor and PMOS transistor The transconductance; where the resistance and resistance The resistance values ​​are equal. The expression for the equivalent output load is:

[0055]

[0056] Properly configure resistors Meanwhile, due to the reasonable setting of the high-pass frequency domain in the AC-coupled network, the nodes and The voltages have the same potential, that is and Both have the same potential at one end, and their other ends are connected to the same node, so through and The current is the same.

[0057] Determine the dominant parasitic capacitance at high frequencies.

[0058] Determine the bias and startup circuits that are independent of the power supply. Adjust the bias current level to be within the transistor's voltage swing range to counteract the voltage fluctuations from the power supply. Adding a startup circuit prevents the circuit from operating at an unwanted operating point. Power supply independence means it is unaffected or minimally affected by power supply changes. For example, it is unaffected by electromagnetic interference from the power supply.

[0059] Among them, the bias circuit and startup circuit, which are independent of the power supply, are determined, including:

[0060] Determine the expression for the bias current, ensuring that the threshold voltage of all transistors is the same and ignoring channel length modulation. A transistor refers to a MOSFET. The channel length refers to the length of the semiconductor region between the source and drain of the MOSFET.

[0061] The threshold voltage and channel length of the transistor are adjusted to keep the bias current level within the transistor's voltage swing range. This ensures that the current is only related to the component size and resistance value, and adjusting these two factors keeps the bias current level within the transistor's voltage swing range to resist electromagnetic interference from the power supply. Here, the voltage swing range refers to the voltage range applied between the gate and source of the MOSFET.

[0062] Add a startup circuit to ensure the NMOS transistor The drain output current is not zero, preventing the circuit from operating at an unwanted operating point.

[0063] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A bandgap reference voltage circuit resistant to electromagnetic interference, characterized in that, This includes bias circuitry, startup circuitry, dual differential pair amplifiers, and bandgap reference circuitry. The bias circuit is used to provide an operating environment for electronic devices. The bias circuit is independent of power supply, so as to save power consumption while reducing electromagnetic interference sensitivity. The startup circuit is used to provide initial conditions when the reference circuit starts running. The dual differential pair amplifier is used to amplify the reference voltage and suppress DC offset; The bandgap reference circuit is used to generate a stable reference voltage to reduce the electromagnetic interference sensitivity of the reference circuit and maintain a low temperature coefficient.

2. The bandgap reference voltage circuit for electromagnetic interference suppression according to claim 1, characterized in that, The bias circuit includes a MOSFET and a resistor; NMOS transistor The source of the NMOS transistor The source and NMOS transistor Source and power supply connect; The NMOS transistor The drain and PMOS transistor The drain and gate of the NMOS transistor are connected to the dual differential pair amplifier; the NMOS transistor is connected to the dual differential pair amplifier. The gate of the NMOS transistor The gate of the NMOS transistor The gate and drain of the PMOS transistor Drain connection; The drain of the NMOS transistor Mb5 and the PMOS transistor The drain and gate of the PMOS transistor gate, PMOS transistor The gate, the startup circuit, and the dual differential pair amplifier are connected; The PMOS transistor The source of the PMOS transistor Drain connection; The PMOS transistor The source and the PMOS transistor Source grounding The PMOS transistor Source grounding resistance .

3. The bandgap reference voltage circuit for electromagnetic interference suppression according to claim 1, characterized in that, The startup circuit includes a MOSFET; PMOS transistor The gate of the PMOS transistor is connected to the bias circuit and the dual differential pair amplifier. The drain of the PMOS transistor is connected to the dual differential amplifier, and the source of the PMOS transistor is connected to the bandgap reference circuit.

4. The bandgap reference voltage circuit for electromagnetic interference suppression according to claim 1, characterized in that, The dual differential pair amplifier includes MOSFETs and resistors; NMOS transistor The source and NMOS transistor Source and power supply connect; The NMOS transistor The drain of the PMOS transistor is connected to the bandgap reference circuit. The drain and gate of the PMOS transistor The gate connection of the NMOS transistor; The gate of the NMOS transistor The gate and drain of the PMOS transistor The drain and the startup circuit are connected; The PMOS transistor The source and PMOS transistor The drain and PMOS transistor Drain connection; The PMOS transistor The source and PMOS transistor The drain and PMOS transistor Drain connection; The PMOS transistor The gate and the bandgap reference circuit and the capacitor Connection, the PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection; The capacitor The other end is connected to the resistor and the PMOS transistor Gate connection; The resistor The other end is connected to the resistor And the bias circuit connection; The PMOS transistor The source and PMOS transistor The drain and the PMOS transistor The source connection; The PMOS transistor The gate and the resistor The other end and the capacitor connect; The capacitor The other end is connected to the PMOS transistor The gate and the bandgap reference circuit are connected; The PMOS transistor The gate of the PMOS transistor The gate, the startup circuit, and the bias circuit are connected; the PMOS transistor The source and the PMOS transistor The source electrode is grounded.

5. The bandgap reference voltage circuit for electromagnetic interference suppression according to claim 1, characterized in that, The bandgap reference circuit includes resistors, capacitors, and MOSFETs; NMOS transistor The source and capacitor With power supply connect; The NMOS transistor The gate and the capacitor The other end is connected to the dual differential pair amplifier; the NMOS transistor The drain of the circuit and the resistor ,resistance and grounding capacitor Connect and output the reference voltage. ; The resistor The other end is connected to the resistor And the dual differential pair amplifier connection; The resistor The other end is connected to the PMOS transistor The gate and drain are connected; The PMOS transistor The source is grounded; The resistor The other end is connected to the PMOS transistor The drain and gate of the amplifier are connected to the dual differential pair amplifier. The PMOS transistor The source electrode is grounded.

6. A method for constructing a bandgap reference voltage circuit resistant to electromagnetic interference as described in any one of claims 1-5, characterized in that, include: Determine a temperature-independent bandgap reference circuit; Determine the dual differential pair amplifier; Determine the bias circuit and startup circuit that are independent of the power supply.

7. The method for constructing an electromagnetic interference-resistant bandgap reference voltage circuit according to claim 6, characterized in that, Determine a temperature-independent bandgap reference circuit, including: Obtain the original bandgap reference circuit and replace the bipolar junction transistor in the original bandgap reference circuit with a metal-oxide-semiconductor field-effect transistor to obtain a new bandgap reference circuit. Based on the structure of the new bandgap reference circuit, the expression for the reference voltage is determined; Based on the reference voltage The expression is used to determine the parameters of the components in the new bandgap reference circuit, thereby obtaining a temperature-independent bandgap reference circuit.

8. The method for constructing an electromagnetic interference-resistant bandgap reference voltage circuit according to claim 7, characterized in that, The expression for the reference voltage is: ； in, Indicates the reference voltage; This represents the gate-source voltage of the NMOS transistor M2; Indicates process constant; This represents the thermal voltage related to temperature. Represents the natural logarithm; This indicates the aspect ratio of the NMOS M11 transistor; Indicates resistance The resistance value; Indicates resistance The resistance value; This indicates the aspect ratio of the NMOS M10 transistor.

9. The method for constructing an electromagnetic interference-resistant bandgap reference voltage circuit according to claim 6, characterized in that, Determine the dual differential pair amplifier, including: It employs a dual differential pair combining DC and AC coupling technologies, with self-cancelling high-frequency input, to achieve stable output impedance and positive feedback; Based on the full range of electromagnetic interference, the high-pass frequency domain of the AC coupling network is set, and the non-zero DC loop gain and PMOS transistor are ensured. Gate voltage and PMOS transistor The gate voltages are equal; Determine the expression for the equivalent output load, and based on the expression for the equivalent output load, determine the resistance. ,resistance and resistance The resistance value and PMOS transistor and PMOS transistor The transconductance; where the resistance and resistance The resistance values ​​are equal; Determine the dominant parasitic capacitance at high frequencies.

10. The method for constructing an electromagnetic interference-resistant bandgap reference voltage circuit according to claim 1, characterized in that, Identify the bias circuit and startup circuit, which are independent of the power supply, including: Determine the expression for the bias current, ensuring that the threshold voltages of all transistors are the same and ignoring channel length modulation; Adjust the threshold voltage of the transistor and the channel length so that the level of the bias current is within the voltage swing range of the transistor; Add a startup circuit to ensure the NMOS transistor The drain output current is not zero.

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