Memory overclocking device and memory overclocking method

Abstract

A memory overclocking device includes a memory and a processor. The memory stores a plurality of instructions and a basic input / output system. The processor is used for executing the following steps according to a plurality of instructions of the memory: performing overclocking prediction on an object to be detected by the basic input / output system according to an overclocking algorithm; outputting optimal overclocking result information by the basic input / output system according to the overclocking prediction; and outputting at least two compliance result information according to the optimal overclocking result information, the hardware information of the object to be measured and the frequency threshold range information.

Description

Technical Field

[0001] This invention relates to an overclocking device and an overclocking method, and particularly to a memory overclocking device and a memory overclocking method. Background Technology

[0002] The past few years have witnessed an explosion in the application of artificial intelligence (AI). The emergence of generative AI has made people more eager to imagine the future AI world.

[0003] Furthermore, currently, most users lack the technical skills or ability to overclock Double Data Rate (DDR) memory to improve its performance. Only professionals or experienced memory overclockers have the capability or experience to successfully overclock DDR memory. Most users lack the necessary knowledge to perform DDR memory overclocking. This leads to frequent failures when overclocking DDR memory, or even if successful, compromised system stability.

[0004] Therefore, a device and / or method that can be easily used for DDR memory overclocking is an urgent project that needs to be researched and developed. Summary of the Invention

[0005] The present invention is intended to provide a simplified summary of this disclosure to enable the reader to have a basic understanding of it. This summary is not a complete overview of the present disclosure and is not intended to identify key / critical elements of the embodiments or define the scope of the present invention.

[0006] One technical embodiment of this invention relates to a memory overclocking device. The memory overclocking device includes a memory and a processor. The memory stores multiple instructions and a basic input / output system (PIS). The processor performs the following steps according to the multiple instructions in the memory: using the PIS to predict overclocking for a device under test (DUT) based on an overclocking algorithm; using the PIS to output optimal overclocking result information based on the overclocking prediction; and outputting at least two compliance result information based on the optimal overclocking result information, the hardware information of the DUT, and frequency threshold range information.

[0007] In one embodiment, the optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test (DUT), at least one time information of the DUT, and optimal voltage information.

[0008] In one embodiment, the frequency threshold range information includes 200 to 400 MHz.

[0009] In one embodiment, the processor further performs the following steps based on multiple instructions from the memory: determining whether the optimal overclocking result information is an optimal result based on the overclocking algorithm, an initial setting information of the device under test, and the hardware information of the device under test; and when the optimal overclocking result information is determined to be an optimal result, marking a suggestion symbol on the optimal overclocking result information.

[0010] In one embodiment, the processor further performs the following steps according to multiple instructions from the memory: determining whether at least two compliance result information conforms to a product specification based on an overclocking algorithm and hardware information of the device under test; and when it is determined that at least two compliance result information conforms to the product specification, outputting at least two compliance result information to an interface.

[0011] In one embodiment, the processor further performs the following steps according to a plurality of instructions from the memory: setting an operation interface; displaying initial setting information of the device under test, hardware information of the device under test, optimal overclocking result information and at least two compliance result information on the operation interface; and marking a suggestion symbol on the optimal overclocking result information according to the overclocking algorithm, the initial setting information of the device under test and the hardware information of the device under test.

[0012] In one embodiment, the processor further performs the following steps based on multiple instructions from the memory: determining, via the basic input / output system, whether to perform overclocking prediction training based on an initial setting information of the device under test; when it is determined that overclocking prediction training should be performed, recording a result of the overclocking prediction training into the memory via the basic input / output system; and updating the overclocking algorithm with the result of the overclocking prediction training via the basic input / output system.

[0013] In one embodiment, the initial settings include at least one of updating basic input / output system information, changing test object information, and changing test object time information.

[0014] In one embodiment, the device under test (DUT) and the memory are different from each other, and the DUT includes a dynamic random access memory.

[0015] In one embodiment, the memory overclocking device includes a motherboard.

[0016] Another technical embodiment of this case relates to a memory overclocking method. A memory overclocking method includes the following steps: storing a basic input / output system (PIS) in the memory; performing an overclocking prediction for a device under test (DUT) using the PIS based on an overclocking algorithm; outputting optimal overclocking result information based on the overclocking prediction using the PIS; and outputting at least two compliance result information based on the optimal overclocking result information, the hardware information of the DUT, and frequency threshold range information.

[0017] In one embodiment, the optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test (DUT), at least one time information of the DUT, and optimal voltage information.

[0018] In one embodiment, the frequency threshold range information includes 200 to 400 MHz.

[0019] In one embodiment, the memory overclocking method further includes the following steps: determining whether the optimal overclocking result information is an optimal result based on the overclocking algorithm, an initial setting information of the device under test, and the hardware information of the device under test; and when the optimal overclocking result information is determined to be an optimal result, marking a suggestion symbol on the optimal overclocking result information.

[0020] In one embodiment, the memory overclocking method further includes the following steps: determining whether at least two compliance result information conforms to a product specification based on an overclocking algorithm and hardware information of the device under test; and when it is determined that at least two compliance result information conforms to the product specification, outputting at least two compliance result information to an interface.

[0021] In one embodiment, the memory overclocking method further includes the following steps: setting an operation interface; displaying initial setting information of the device under test, hardware information of the device under test, optimal overclocking result information and at least two compliance result information on the operation interface; and marking a suggestion symbol on the optimal overclocking result information according to the overclocking algorithm, the initial setting information of the device under test and the hardware information of the device under test.

[0022] In one embodiment, the memory overclocking method further includes the following steps: determining whether to perform overclocking prediction training based on an initial setting information of the device under test using a basic input / output system; when it is determined that overclocking prediction training should be performed, recording a result of the overclocking prediction training into the memory using the basic input / output system; and updating the overclocking algorithm using the result of the overclocking prediction training using the basic input / output system.

[0023] In one embodiment, the initial settings include at least one of updating basic input / output system information, changing test object information, and changing test object time information.

[0024] In one embodiment, the device under test (DUT) and the memory are different from each other, and the DUT includes a dynamic random access memory.

[0025] In one embodiment, the memory overclocking method is performed by a motherboard.

[0026] Therefore, based on the technical content of this case, the memory overclocking device and memory overclocking method shown in the embodiments of this case can still achieve the effect of stable memory overclocking by means of the corresponding algorithm, without requiring the user to have professional double data rate synchronous memory overclocking technology.

[0027] After reading the following embodiments, those skilled in the art will be able to easily understand the basic concept and other inventive objectives of this invention, as well as the technical means and implementation methods adopted in this invention. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating a memory overclocking device according to an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram illustrating a usage scenario of a memory overclocking device according to an embodiment of this case.

[0030] Figure 3 This is a schematic diagram illustrating a usage scenario of a memory overclocking device according to an embodiment of this case.

[0031] Figure 4 This is a flowchart illustrating the steps of a memory overclocking method according to an embodiment of the present case.

[0032] The reference numerals in the attached figures are explained as follows:

[0033] 100: Memory overclocking device

[0034] 110: Memory

[0035] 111: Basic Input / Output System

[0036] 120: Processor

[0037] 900: Test Item

[0038] 200: Interface

[0039] 21: Information

[0040] 22: Information

[0041] 211: Options

[0042] 212: Options

[0043] 213: Options

[0044] 214: Options

[0045] 215: Options

[0046] SP: Symbol

[0047] N1: Information

[0048] N2: Information

[0049] N3: Information

[0050] N4: Information

[0051] 400: Memory Overclocking Methods

[0052] 410: Steps

[0053] 420: Steps

[0054] 430: Steps

[0055] 440: Steps Detailed Implementation

[0056] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this case are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this case. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and order of steps.

[0057] Unless otherwise defined in this specification, the scientific and technical terms used herein have the same meaning as understood and commonly used by one of ordinary skill in the art to which this application pertains. Furthermore, unless conflicting with the context, singular nouns used herein include their plural forms, and vice versa.

[0058] In addition, the term “coupled” or “connected” as used in this article may refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or acting on each other.

[0059] Some embodiments of this disclosure can be used in conjunction with the appendix. Figure 1 It should be understood that the accompanying drawings of the embodiments of this disclosure are also considered part of the description of the embodiments of this disclosure. It should be understood that the drawings of the embodiments of this disclosure are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of this disclosure. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments of this disclosure.

[0060] In this article, the term "device" is used to refer to an object consisting of one or more transistors and / or one or more active and passive components connected in a certain way to process signals.

[0061] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, meaning that the meaning of "about," "approximately," and "roughly" may be implied even without specific mention of them.

[0062] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but rather by differences in function. The term "comprising" as used in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to".

[0063] Figure 1 This is a block diagram illustrating a memory overclocking device according to an embodiment of the present invention. As shown, the memory overclocking device 100 includes a memory 110 and a processor 120. The memory 110 stores a plurality of instructions and a Basic Input / Output System (BIOS) 111. The memory 110 may be coupled to the processor 120. In some embodiments, the BIOS 111 may be additionally stored and / or executed in other elements within the memory overclocking device 100, but this is not a limitation of the present invention.

[0064] For example, the basic input / output system 111 can be any type of basic input / output system, or other programming languages, algorithms, software, firmware, etc. with similar functions, but this case is not limited to this.

[0065] In some embodiments, the processor 120 may be a microprocessor unit (MPU), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a server, etc., but this invention is not limited thereto.

[0066] In some embodiments, the memory 110 may be random-access memory (RAM), non-volatile random access memory (NVRAM), read-only memory (ROM), cache, flash memory, memory card, hard disk (such as cloud / network hard disk / external hard disk), optical disk, USB flash drive, or database, etc., but this application is not limited thereto.

[0067] In one embodiment, the processor 120 is configured to perform the following steps according to a plurality of instructions from the memory 110: performing overclocking prediction for the device under test 900 by means of an overclocking algorithm via the basic input / output system 111.

[0068] For example, the device under test 900 can be any algebraic or any type of double data rate synchronous (DDR) memory, the overclocking algorithm can be stored in memory 110, and the multiple instructions of memory 110 can be any type of programming language code, algorithm, software or firmware, but this case is not limited to this.

[0069] In some embodiments, the overclocking algorithm may be any type of artificial neural network (ANN) model, any type of big data algorithm, any type of machine learning algorithm, any type of artificial intelligence (AI) algorithm, and any type of chat generative pre-trained transformer (ChatGPT) algorithm, but this application is not limited thereto.

[0070] In one embodiment, processor 120 is configured to perform the following steps according to a plurality of instructions from memory 110: outputting optimal overclocking result information based on overclocking prediction via basic input / output system 111.

[0071] Furthermore, the processor 120 can predict the DDR overclocking capability through BIOS and AI calculations to obtain the target frequency, i.e., the optimal overclocking result information, but this application is not limited to this. For example, the original DDR frequency of a certain brand of DDR memory can be 5600 MT / s (million transfers per second). The overclocking algorithm in this application can obtain the optimal overclocking result information, which can be 7600 MT / s, but this application is not limited to this.

[0072] In one embodiment, the processor 120 is configured to perform the following steps according to a plurality of instructions from the memory 110: outputting at least two compliance result information based on the best overclocking result information, the hardware information of the device under test 900, and the frequency threshold range information.

[0073] For example, the hardware information of the device under test 900 can be the chip, brand, characteristics, model, etc. of the double data rate synchronous memory, the frequency threshold range information can be the frequency range that the device under test 900 can support, and the at least two compliance result information can be related information that the computer will not blue screen or crash when it is running, but this case is not limited to this.

[0074] Furthermore, the processor 120 may obtain first compliance result information (e.g., 7200MT / s), second compliance result information (e.g., 8000MT / s), and third compliance result information (e.g., 8200MT / s) based on the best overclocking result information of the DDR memory (e.g., 7600MT / s), the chip information, the model information, and the supported frequency information, but this application is not limited to this.

[0075] In some embodiments, the hardware information of the device under test 900 may be the algebraic information of the processor 120 or processor-related information, such as fifth-generation double data rate synchronous dynamic random access memory (DDR5), but this invention is not limited thereto.

[0076] In some embodiments, the memory overclocking device 100 may be coupled to a plurality of DDR memories, and the memory overclocking device 100 may perform overclocking prediction for each of the plurality of DDR memories.

[0077] For example, each (or group of) multiple DDR memory modules has different hardware capabilities depending on its chip manufacturer and features. Even DDR memory modules of the same model may have different capabilities, resulting in variations in their overclocking limits. When using AI calculations, these differences can be taken into account to provide users with the best settings. The overclocking limit may even exceed the target frequency achievable by the manufacturer's built-in XMP profile, but this case does not limit it.

[0078] In one embodiment, the optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test 900, at least one time information of the device under test 900, and optimal voltage information.

[0079] For example, the optimal overclocking frequency information could be 7600MT / s, the manufacturer information of the device under test could be, for example, SK Hynix, Micron, or Samsung, at least one timing information of the device under test could be the timing information of DDR memory, and the optimal voltage information could be 1.4 volts (V), but this case is not limited to these.

[0080] In one embodiment, the frequency threshold range information includes 200 to 400 MHz.

[0081] For example, the frequency threshold range information can be the frequency difference between at least two compliance result information. For instance, when the best overclocking result information is 7600MT / s, at least two compliance result information can be 7400, 7800, and 8000MT / s, but this case is not limited to this.

[0082] In one embodiment, the processor 120 further performs the following steps according to multiple instructions from the memory 110: determining whether the optimal overclocking result information is the optimal result based on the overclocking algorithm, the initial setting information of the device under test 900 and the hardware information of the device under test 900; and when the optimal overclocking result information is determined to be the optimal result, marking the optimal overclocking result information with a suggestion symbol.

[0083] For example, the initial settings of the device under test 900 can be the original frequency value of the DDR memory, the original time information of the DDR memory, etc. When the processor 120 determines that the best overclocking result information is the best result, the processor 120 can mark the best overclocking result information with a suggested symbol. The suggested symbol can be any type of symbol, such as a star, triangle, emoji or sticker, but this case is not limited to this.

[0084] In some embodiments, the processor 120 may further determine whether the optimal overclocking result information is truly the optimal result based on information related to the device under test 900. If the result is not, the DDR overclocking capability prediction is performed again to obtain a new target frequency and to reconfirm whether the new target frequency is the optimal result, but this application is not limited to this.

[0085] In one embodiment, the processor 120 further performs the following steps according to a plurality of instructions from the memory 110: determining whether at least two compliance result information conforms to the product specifications based on the overclocking algorithm and the hardware information of the device under test; and when it is determined that at least two compliance result information conforms to the product specifications, outputting at least two compliance result information to an interface.

[0086] For example, processor 120 can use an overclocking algorithm to compare the hardware information of the device under test with at least two compliance result information to determine whether it conforms to product specifications. The interface can be any display screen, monitor, or operating interface, but this invention is not limited thereto. In some embodiments, processor 120 can directly compare the hardware information of the device under test with at least two compliance result information to confirm whether it conforms to product specifications, but this invention is not limited thereto. In some embodiments, processor 120 can output at least two compliance result information to the following... Figure 2 The interface is limited to 200, but this case is not limited to that.

[0087] Figure 2 This is a schematic diagram illustrating a usage scenario of a memory overclocking device according to an embodiment of this case. As shown in the figure... Figure 2 It features interface 200, information 21, information 22, multiple options 211 to 215, and symbol SP.

[0088] For example, interface 200 may be a user interface, information 21 may be related to the initial setting information of the device under test 900 and / or the hardware information of the device under test 900, information 22 may be related to the overclocking algorithm and / or the best overclocking result information, multiple options 211 to 215 may be related to the best overclocking result information and / or at least two compliance result information, and symbol SP may correspond to suggested symbols, but this application is not limited to this.

[0089] In some embodiments, information 21 may be a booster profile, option 211 may be disable, multiple options 212, 214 and 215 may be compliance result information, and option 213 may be optimal overclocking result information, but this invention is not limited thereto.

[0090] In some embodiments, the number of options corresponding to information 21 may not be limited to 5; the number of options can be adjusted arbitrarily according to needs, but this embodiment is not limited to this. In some embodiments, the content of information 21 may come from the product specifications or hardware specifications of DDR memory.

[0091] Figure 3 This is a schematic diagram illustrating a usage scenario of a memory overclocking device according to an embodiment of this case. As shown in the figure, option 213 may have multiple pieces of information N1 to N4 and the symbol SP.

[0092] For example, Figure 3 Option 213 can correspond to Figure 2Option 213 may be related to the best overclocking result information. Multiple information N1 to N4 may be related to the hardware information of the device under test 900, the best overclocking frequency information, the manufacturer information of the device under test 900, at least one time information of the device under test 900, and the best voltage information, etc., but this case is not limited to this.

[0093] In some embodiments, 38-48-48-128 in information N3 may be the following information in sequence: a first time parameter (e.g., CAS (Column Address Strobe) Latency, tCL), a second time parameter (e.g., RAS to CASDelay Time, tRCD), a third time parameter (e.g., Row Precharge Delay Time, tRP), and a fourth time parameter (e.g., Active to Precharge Delay Time, tRAS), but this application is not limited thereto.

[0094] also, Figure 2 The presentation logic of the content for each of the multiple options 212 to 215 can be similar to... Figure 3 The logic behind option 213 is presented in a concise manner and will not be elaborated upon here.

[0095] Please refer to the following: Figures 1 to 3 In one embodiment, the processor 120 further performs the following steps according to a plurality of instructions from the memory 110: setting up an operating interface.

[0096] For example, the processor 120 can be configured with an operating interface on any display medium (e.g., a monitor), and the operating interface can be... Figure 2 The interface is limited to 200, but this case is not limited to that.

[0097] In this embodiment, the processor 120 further performs the following steps according to multiple instructions from the memory 110: displaying the initial setting information of the device under test 900, the hardware information of the device under test 900, the best overclocking result information, and at least two compliance result information on the operation interface.

[0098] For example, the information displayed in the user interface can be similar to... Figure 2 Information 21 and / or information 22, the initial setting information of the device under test 900 and / or the hardware information of the device under test 900 can correspond to Figure 2 Information 22, the best overclocking result information can correspond to Figure 2 Option 213, at least two compliance result information can correspond to Figure 2 Options 212, 214 and 215 are available, but this case is not limited to these.

[0099] In this embodiment, a suggested symbol is marked on the optimal overclocking result information based on the overclocking algorithm, the initial setting information of the device under test (DUT) 900, and the hardware information of the DUT 900.

[0100] For example, the suggestion symbol can correspond to Figure 2 or Figure 3 The symbol SP can be used, but this case is not limited to it.

[0101] In one embodiment, the processor 120 further performs the following steps based on a plurality of instructions from the memory 110: determining, via the basic input / output system 111, whether to perform overclocking prediction training based on the initial setting information of the device under test 900.

[0102] For example, the initial configuration information of the device under test 900 may be DDR information or DDR timing change information, but this invention is not limited to this. In some embodiments, the processor 120 determines whether to perform overclocking prediction training based on factors such as a recent BIOS update, DDR replacement, or changes in DDR timing, but this invention is not limited to this. In some embodiments, the initial configuration information of the device under test 900 may be at least one DDR timing information, but this invention is not limited to this.

[0103] In this embodiment, the processor 120 further performs the following steps according to a plurality of instructions from the memory 110: when it is determined that overclocking prediction training is to be performed, the results of the overclocking prediction training are recorded to the memory 110 by means of the basic input / output system.

[0104] For example, when it is determined that overclocking prediction training is to be performed, the BIOS can record the results of the overclocking prediction training to memory 110, such as non-volatile random access memory (NVRAM), but this case is not limited to this.

[0105] In some embodiments, when the processor 120 determines that overclocking prediction training is to be performed, the BIOS can calculate all DDR timings, but this invention is not limited thereto. In some embodiments, when the processor 120 determines that overclocking prediction training is to be performed, the processor 120 or the BIOS can record the current DDR state or related information (e.g., memory chip information, brand information, capacity information, voltage information, various timing information, signal margin information during training, etc.) in the memory 110, but this invention is not limited thereto.

[0106] In this embodiment, the processor 120 further performs the following steps according to a plurality of instructions from the memory 110: updating the overclocking algorithm with the results of overclocking prediction training via the basic input / output system 111.

[0107] For example, the BIOS can further update the overclocking algorithm with the results of overclocking prediction training, allowing users to make more accurate overclocking predictions when using the overclocking algorithm, but this case is not limited to this.

[0108] In one embodiment, the initial settings include at least one of updating basic input / output system information, changing the object under test (DUT) information, and changing the DUT time information.

[0109] In some embodiments, overclock prediction training may be performed before the operating system (OS) starts, but this invention is not limited thereto. In some embodiments, when the processor 120 determines that overclock prediction training should not be performed, the operating system may be started directly, but this invention is not limited thereto.

[0110] In one embodiment, the device under test 900 is different from the memory 110, and the device under test 900 includes dynamic random access memory.

[0111] For example, memory 110 can be NVRAM, and device under test 900 can be DDR memory, but this case is not limited to this.

[0112] In one embodiment, the memory overclocking device 100 includes a motherboard.

[0113] For example, the memory overclocking device 100 can be a mainboard, system board, or logic board, but this case is not limited to this.

[0114] In some embodiments, the device under test (DUT) 900 may be disposed within the memory overclocking device 100, but this invention is not limited thereto. In some embodiments, the DUT 900 may be the same as the memory 110, but this invention is not limited thereto. In some embodiments, the basic input / output system 111 may be disposed at (or stored in) any location within the memory overclocking device 100, but this invention is not limited thereto. In some embodiments, the basic input / output system 111 may be disposed at (or stored in) any location outside the memory overclocking device 100, but this invention is not limited thereto.

[0115] Figure 4 This is a flowchart illustrating the steps of a memory overclocking method according to an embodiment of this case. As shown in the figure, the memory overclocking method 400 includes multiple steps 410, 420, 430, and 440, which are described in detail below. Figures 1 to 4 For detailed steps, please refer to the following instructions.

[0116] In step 410, the basic input / output system is stored in the memory.

[0117] In one embodiment, processor 120 may store basic input / output system 111 via memory 110.

[0118] In step 420, the overclocking prediction of the device under test is performed by the basic input / output system based on the overclocking algorithm.

[0119] In one embodiment, the processor 120 may perform overclocking prediction for the device under test 900 using the basic input / output system 111 based on an overclocking algorithm.

[0120] In step 430, the basic input / output system outputs the best overclocking result information based on overclocking prediction.

[0121] In one embodiment, the processor 120 may output optimal overclocking result information based on overclocking prediction using the basic input / output system 111.

[0122] In step 440, at least two compliance result information is output based on the best overclocking result information, the hardware information of the device under test, and the frequency threshold range information.

[0123] In one embodiment, the processor 120 may output at least two compliance result information based on the best overclocking result information, the hardware information of the device under test 900, and the frequency threshold range information.

[0124] For example, Figure 4 The operation of the memory overclocking method 400 can be similar to Figure 1 The operation of the memory overclocking device 100 is described in the concise manual and will not be repeated here.

[0125] In one embodiment, the optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test (DUT), at least one time information of the DUT, and optimal voltage information.

[0126] In one embodiment, the frequency threshold range information includes 200 to 400 MHz.

[0127] In one embodiment, the memory overclocking method 400 further includes the following steps: determining whether the optimal overclocking result information is the optimal result based on the overclocking algorithm, the initial setting information of the device under test, and the hardware information of the device under test; and when the optimal overclocking result information is determined to be the optimal result, marking the optimal overclocking result information with a suggestion symbol.

[0128] In one embodiment, the memory overclocking method 400 further includes the following steps: determining whether at least two compliance result information conforms to product specifications based on the overclocking algorithm and the hardware information of the device under test; and when it is determined that at least two compliance result information conforms to product specifications, outputting at least two compliance result information to an interface.

[0129] In one embodiment, the memory overclocking method 400 further includes the following steps: setting up an operation interface; displaying the initial setting information of the device under test, the hardware information of the device under test, the best overclocking result information, and at least two compliance result information on the operation interface; and marking the best overclocking result information with suggested symbols based on the overclocking algorithm, the initial setting information of the device under test, and the hardware information of the device under test.

[0130] In one embodiment, the memory overclocking method 400 further includes the following steps: determining whether to perform overclocking prediction training based on the initial setting information of the device under test using a basic input / output system; when it is determined that overclocking prediction training is to be performed, recording the result of the overclocking prediction training to the memory 110 using a basic input / output system 111; and updating the overclocking algorithm using the result of the overclocking prediction training using a basic input / output system 111.

[0131] In one embodiment, the initial settings include at least one of updating basic input / output system information, changing the object under test (DUT) information, and changing the DUT time information.

[0132] In one embodiment, the device under test 900 is different from the memory 110, and the device under test 900 includes dynamic random access memory.

[0133] In one embodiment, the memory overclocking method 400 is executed by the motherboard.

[0134] In some embodiments, the memory overclocking method 400 may be implemented by the memory overclocking device 100, but this invention is not limited thereto. In some embodiments, the memory overclocking method 400 may be implemented by a non-transitory computer-readable storage medium, but this invention is not limited thereto. In some embodiments, the memory overclocking method 400 may be implemented by other systems or servers, but this invention is not limited thereto.

[0135] As can be seen from the above embodiments of this case, applying this case has the following advantages. The memory overclocking device and memory overclocking method shown in this embodiment can achieve stable memory overclocking effect through the corresponding algorithm without requiring the user to have professional double data rate synchronous memory overclocking technology.

[0136] The ordinal numbers in this specification and claims, such as "first," "second," "third," etc., are not sequential in any particular order; they are only used to distinguish between two different elements with the same name.

[0137] Although the above embodiments disclose specific embodiments of this case, they are not intended to limit this case. Those skilled in the art to which this case pertains may make various changes and modifications without departing from the principles and concepts of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

Claims

1. A memory overclocking apparatus, comprising: Include: A memory for storing multiple instructions and a basic input / output system; and A processor for executing the following steps based on a plurality of instructions from the memory: The basic input / output system performs an overclocking prediction for a device under test based on an overclocking algorithm. The basic input / output system outputs an optimal overclocking result information based on the overclocking prediction. as well as Based on the optimal overclocking result information, the hardware information of the device under test, and the frequency threshold range information, at least two compliance result information will be output.

2. The memory overclocking device of claim 1, wherein, The optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test, at least one time information of the device under test, and optimal voltage information.

3. The memory overclocking device of claim 1, wherein, This frequency threshold range information includes 200 to 400 MHz.

4. The memory overclocking device of claim 1, wherein, The processor further performs the following steps based on the multiple instructions from the memory: Based on the overclocking algorithm, the initial settings of the device under test (DUT), and the hardware information of the DUT, determine whether the optimal overclocking result is an optimal result; and When the optimal overclocking result is determined to be the optimal result, a suggestion symbol will be marked on the optimal overclocking result information.

5. The memory overclocking device of claim 4, wherein, The processor further performs the following steps based on the multiple instructions from the memory: Based on the overclocking algorithm and hardware information of the device under test, determine whether the at least two compliance results conform to a product specification; and When it is determined that at least two compliance result information conforms to the product specifications, the at least two compliance result information is output to an interface.

6. The memory overclocking device of claim 1, wherein, The processor further performs the following steps based on the multiple instructions from the memory: Set up an operation interface; The interface displays the initial setup information of the device under test (DUT), the hardware information of the DUT, the best overclocking result information, and the at least two compliance result information of the DUT; and Based on the overclocking algorithm, the initial settings of the device under test (DUT), and the hardware information of the DUT, a suggested symbol is marked on the optimal overclocking result information.

7. The memory overclocking device as described in claim 1, characterized in that, The processor further performs the following steps based on the multiple instructions from the memory: The basic input / output system determines whether to perform overclocking prediction training based on the initial setting information of the device under test. When it is determined that the overclocking prediction training is to be performed, the result of the overclocking prediction training is recorded in the memory by the basic input / output system; as well as The overclocking algorithm is updated using the results of the overclocking prediction training through the basic input / output system.

8. The memory overclocking device as described in claim 7, characterized in that, The initial setup information includes at least one of updating basic input / output system information, changing the device under test (DUT) information, and changing the DUT time information.

9. The memory overclocking device as described in claim 1, characterized in that, The device under test (DUT) and the memory are different from each other, and the DUT contains a dynamic random access memory.

10. The memory overclocking device as described in claim 1, characterized in that, The memory overclocking device includes a motherboard.

11. A method for overclocking a memory, characterized in that, Include: A basic input / output system is stored in a memory. The basic input / output system performs an overclocking prediction for a device under test based on an overclocking algorithm. The basic input / output system outputs an optimal overclocking result information based on the overclocking prediction. as well as Based on the optimal overclocking result information, the hardware information of the device under test, and the frequency threshold range information, at least two compliance result information will be output.

12. The memory overclocking method as described in claim 11, characterized in that, The optimal overclocking result information includes optimal overclocking frequency information, manufacturer information of the device under test, at least one time information of the device under test, and optimal voltage information.

13. The memory overclocking method as described in claim 11, characterized in that, This frequency threshold range information includes 200 to 400 MHz.

14. The memory overclocking method as described in claim 11, characterized in that, Also includes: Based on the overclocking algorithm, the initial settings of the device under test (DUT), and the hardware information of the DUT, determine whether the optimal overclocking result is an optimal result; and When the optimal overclocking result is determined to be the optimal result, a suggestion symbol will be marked on the optimal overclocking result information.

15. The memory overclocking method as described in claim 14, characterized in that, Also includes: Based on the overclocking algorithm and hardware information of the device under test, determine whether the at least two compliance results conform to a product specification; and When it is determined that at least two compliance result information conforms to the product specifications, the at least two compliance result information is output to an interface.

16. The memory overclocking method as described in claim 11, characterized in that, Also includes: Set up an operation interface; The interface displays the initial setup information of the device under test (DUT), the hardware information of the DUT, the best overclocking result information, and the at least two compliance result information of the DUT; and Based on the overclocking algorithm, the initial settings of the device under test (DUT), and the hardware information of the DUT, a suggested symbol is marked on the optimal overclocking result information.

17. The memory overclocking method as described in claim 11, characterized in that, Also includes: The basic input / output system determines whether to perform overclocking prediction training based on the initial setting information of the device under test. When it is determined that the overclocking prediction training is to be performed, the result of the overclocking prediction training is recorded in the memory by the basic input / output system; as well as The overclocking algorithm is updated using the results of the overclocking prediction training through the basic input / output system.

18. The memory overclocking method as described in claim 17, characterized in that, The initial setup information includes at least one of updating basic input / output system information, changing the device under test (DUT) information, and changing the DUT time information.

19. The memory overclocking method as described in claim 11, characterized in that, The device under test (DUT) and the memory are different from each other, and the DUT contains a dynamic random access memory.

20. The memory overclocking method as described in claim 11, characterized in that, The memory overclocking method is executed by a motherboard.

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