Ras network interconnection system based on die chip and data processing method
The die chip structure interconnected via I2C bus solves the routing and timing problems of the central node RAS query network, improves the robustness and communication reliability of multi-die designs, and reduces the complexity and cost of chip design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
- Filing Date
- 2026-03-23
- Publication Date
- 2026-06-16
AI Technical Summary
In existing chip designs, the RAS query network of the central node leads to excessive routing resources, timing issues are difficult to resolve, and multi-die designs increase the complexity of die-to-die data paths and the robustness challenges of communication links.
The die chip structure adopts I2C bus interconnection. The I2C master device inside each die chip is connected to the SCP, and the I2C slave device is connected to the RAS channel. Data transmission across dies is realized through the I2C bus, and APB requests are aggregated and decomposed. The RAS channel is accessed serially to reduce the dependence on die2die data channel.
It improves the robustness of the RAS system, saves routing resources, reduces the difficulty of later wiring and timing, and ensures that RAS information can still be obtained when the die2die high-speed link fails.
Smart Images
Figure CN121880249B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and specifically to a RAS network interconnection system and data processing method based on a die chip. Background Technology
[0002] As the design scale and complexity of modern chips increase, reliability, availability, and serviceability (RAS) are playing an increasingly important role in chip design. This is especially true in scenarios with high-performance and high-reliability requirements, such as data centers, servers, and network equipment, where its importance even surpasses performance itself. To reliably retrieve relevant information during debugging and problem localization, most chips now employ RAS networks independent of data and function to transmit relevant RAS debugging and fault reporting information.
[0003] In existing designs, a central node's Advanced Peripheral Bus (APB) network is typically used to query relevant RAS (Resource Automation System) information. This ensures simple and reliable data channels, independent of data and functional paths. However, the central node's query network using APB also introduces limitations, such as inability to cross-die paths. Furthermore, the central node's network leads to excessive back-end routing resources, requiring the use of the global clock network and causing various timing issues, resulting in back-end area expansion and timing non-convergence. As chip area and complexity increase, the central query network faces more and more back-end problems, leading to further increases in chip area, resulting in higher chip failure rates and costs.
[0004] Existing chip RAS solutions mostly use a central node directly connected to an independent data line or rely on a functional data bus to acquire and report RAS-related information. With increasing chip complexity and scale, the direct connection to an independent data line requires more and more routing resources. This leads to a significant increase in the number of data routing resources needed during the PR stage, and related processing clocks require clock balancing across the entire chip, thus increasing the burden on the PR stage and making it difficult to meet timing requirements.
[0005] To reduce design complexity and improve yield, more and more chip designs are now adopting multi-die designs. Generally, to reduce interconnect pins between dies, Universal Chip Interconnect Express (UCIE) or UCIE-like die-to-die links are used as data paths, thereby reducing interconnect lines between different dies and improving chip versatility and reusability. However, this also means that the data paths between different dies mainly rely on high-speed die-to-die links. While increasing the high bandwidth between die-to-die links, it also increases the complexity of the communication links, making the links themselves require RAS (Reliability, Availability, and Security) monitoring. Summary of the Invention
[0006] To address the problems in the prior art, embodiments of the present invention provide a RAS network interconnection system based on a die chip, which can at least partially solve the problems existing in the prior art.
[0007] On one hand, the present invention proposes a RAS network interconnection system based on die chips, including a group of I2C master devices and I2C slave devices. Each die chip is interconnected through an I2C bus. The I2C master device inside each die chip is connected to the SCP, and the I2C slave device inside each die chip is connected to the RAS channel.
[0008] The first SCP corresponding to the first die chip that is the request initiator in the die chip converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the first I2C master device in the first die chip.
[0009] The first I2C master device sends a cross-die I2C request to the second I2C slave device in the second die chip, which is the request responder in the die chip, via the I2C bus. The second I2C slave device converts the cross-die I2C request to obtain a cross-die APB request.
[0010] The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
[0011] Each APB data stream corresponds to multiple serially connected subsystems, and each subsystem has a built-in RAS processing module.
[0012] Each subsystem receives the upstream APB data stream sent by the upstream subsystem and obtains the data address in the upstream APB data stream through the RAS processing module. If it is determined that the accessed data is in the current subsystem based on the data address in the upstream APB data stream, the current subsystem will send back response information for the upstream APB data stream.
[0013] If the data to be accessed is determined to be outside the current subsystem based on the data address in the upstream APB data stream, then the upstream APB data stream is forwarded to the downstream subsystem of the current subsystem through the current subsystem.
[0014] The I2C bus encapsulates a frame format corresponding to the data operation type. The frame format includes a data transmission flag. If the data transmission flag is 0, it indicates that the first I2C master device is sending data to the second I2C slave device.
[0015] If the data transmission flag is 1, it indicates that data is being sent from the second I2C slave device to the first I2C master device.
[0016] Among them, the frame format corresponding to the data operation type of write operation is the first frame format, and the content of the first frame format includes the address information and data information of the operation to be converted.
[0017] Among them, the frame format corresponding to the data operation type of read operation is the second frame format. The content of the second frame format includes the address information of the operation to be converted, as well as the read data information that needs to be fed back.
[0018] In another aspect, embodiments of the present invention provide a data processing method for a RAS network interconnection system based on die chips. The die chip-based RAS network interconnection system includes at least two die chips, each die chip comprising a set of I2C master devices and I2C slave devices. Each die chip is interconnected via an I2C bus. The I2C master device within each die chip is connected to an SCP, and the I2C slave device within each die chip is connected to a RAS channel. The data processing method includes:
[0019] The first SCP corresponding to the first die chip that is the request initiator in the die chip converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the first I2C master device in the first die chip.
[0020] The first I2C master device sends a cross-die I2C request to the second I2C slave device in the second die chip, which is the request responder in the die chip, via the I2C bus. The second I2C slave device converts the cross-die I2C request to obtain a cross-die APB request.
[0021] The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
[0022] According to one aspect of this disclosure, a board is provided that includes the die-chip-based RAS network interconnect system described above.
[0023] According to one aspect of this disclosure, an electronic device is provided, the electronic device comprising the human board card as described above.
[0024] The RAS network interconnection system based on die chips provided in this embodiment of the invention includes at least two die chips. Each die chip includes a set of I2C master devices and I2C slave devices. The die chips are interconnected via an I2C bus. The I2C master device within each die chip is connected to an SCP, and the I2C slave device within each die chip is connected to a RAS channel. A first SCP corresponding to the first die chip (which initiates the request) converts cross-die APB requests into cross-die I2C requests and sends these requests to the first I2C master device in the first die chip. The first I2C master device sends the cross-die I2C requests to the second I2C slave device in the second die chip (which responds to the request) via the I2C bus. The second I2C slave device responds to the cross-die I2C requests. The request is converted to obtain cross-die APB requests. The second die chip aggregates the cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. These aggregated APB requests are then decomposed into multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip. Inter-die data communication is completed via an independent I2C bus, eliminating reliance on die-to-die data channels and improving the robustness of the RAS system. Using a serial APB network within a single die saves routing resources and reduces the difficulty of later PR (Profile Processing). Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0026] Figure 1 This is a schematic diagram of the structure of a RAS network interconnection system based on a die chip provided in an embodiment of the present invention.
[0027] Figure 2 This is a schematic diagram of the structure of a RAS network interconnection system based on a die chip provided in another embodiment of the present invention.
[0028] Figure 3 This is a schematic diagram of the structure of a RAS network interconnection system based on a die chip provided in another embodiment of the present invention.
[0029] Figure 4 This is a schematic diagram of the structure of a RAS network interconnection system based on a die chip provided in another embodiment of the present invention.
[0030] Figure 5 This is an illustrative diagram illustrating the first frame format provided in an embodiment of the present invention.
[0031] Figure 6 This is an illustrative diagram illustrating the second frame format provided in an embodiment of the present invention. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.
[0033] Figure 1 This is a schematic diagram of the structure of a RAS network interconnection system based on a die chip provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the RAS network interconnection system based on die chip provided in this embodiment of the invention includes at least two die chips. Each die chip includes a set of I2C master devices 1 and I2C slave devices 2. Each die chip is interconnected through an I2C bus 3. The I2C master device 1 inside each die chip is connected to SCP4, and the I2C slave device 2 inside each die chip is connected to RAS channel 5.
[0034] The first SCP4, corresponding to the first die chip that initiates the request in the die chip, converts the cross-die APB request into a cross-die I2C request and sends the cross-die I2C request to the first I2C master device 1 in the first die chip;
[0035] The first I2C master device 1 sends a cross-die I2C request to the second I2C slave device 2 in the second die chip, which is the request responder, through the I2C bus 3. The second I2C slave device 2 converts the cross-die I2C request to obtain a cross-die APB request.
[0036] The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
[0037] The I2C bus is explained as follows:
[0038] Its full name is Inter-Integrated Circuit. It is a bidirectional, two-wire bus that provides communication lines between integrated circuits. I2C is a serial expansion technology widely used in televisions, VCRs, and audio equipment. I2C means "a specification or protocol for exchanging information between integrated circuits or functional units," using one data line (SDA) and one clock line (SCL) to complete data transmission and the expansion of peripheral devices.
[0039] like Figure 2 As shown, the following explanation uses four die chips as an example:
[0040] Taking the first die chip of the request initiator as die1 and the second die chip of the request responder as die3 as an example, the explanation is as follows:
[0041] The SCP in die1 acquires the cross-die APB request, converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the I2C master device in die1.
[0042] The I2C master device in die1 sends a cross-die I2C request to the I2C slave device in die3 via the I2C bus. The I2C slave device in die3 converts the cross-die I2C request into a cross-die APB request.
[0043] like Figure 3As shown, "I2Ctoapb_converter" refers to the I2C slave device. Referring to the example above, the I2C slave device in die3 obtains the cross-die APB request and aggregates the cross-die APB request and the intra-die APB request through the 2-to-1 request aggregation unit "2to1" to obtain the aggregated APB request upstream_port. The intra-die APB request can be obtained from the SCP in die3.
[0044] The aggregated APB requests can be demultiplexed using a demultiplexer to obtain multiple APB data streams. The number N of APB data streams can be determined based on the PR (placement and routing). Figure 3 As shown, N independent APB data streams are obtained by decomposing them through an apb_1toN demultiplexer, denoted as downstream_port_0, downstream_port_1…downstream_port_N.
[0045] Taking one APB data stream downstream_port_0 as an example, its corresponding serially connected subsystems are subsystem_0_1…subsystem_0_n, and the value of n can be determined according to the number of subsystems.
[0046] The "RAS Information Collection" module in each subsystem, i.e., the RAS processing module.
[0047] Subsystem_0_1 receives the upstream APB data stream upstream_port (equivalent to downstream_port_0) sent by the upstream subsystem_0. It obtains the data address from upstream_port using the RAS processing module in subsystem_0_1. If this address matches the local address pre-stored in subsystem_0_1, it determines that the data to be accessed by die1 is in the current subsystem_0_1. The RAS processing module in subsystem_0_1 then obtains the response information for upstream_port and sends it back to die1. Specifically, the I2C slave device in die3 obtains the response information from the RAS channel, converts it to I2C response information, and sends it to the I2C master device in die1 via the I2C bus. The I2C master device converts the I2C response information to obtain the APB response information, thus enabling die1 to obtain the APB response information.
[0048] Referring to the example above, if the data address is different from the local address pre-stored in subsystem_0_1, it can be determined that the data that die1 wants to access is not in the current subsystem_0_1. The upstream APB data stream (equivalent to the downstream_port in subsystem_0_1) is then forwarded from the current subsystem_0_1 to subsystem_0_2. Figure 3 (not shown), and so on, until the response information from the corresponding subsystem is found.
[0049] like Figure 4 As shown, the RAS network interconnection system and data processing method based on die chip are further explained:
[0050] This describes a RAS network interconnection system consisting of one master_die (I2C master device) and two slave_die (I2C slave devices). The SCP (System Control Processor) on the master_die can directly generate requests for accessing the RAS channels within the die via the apb port within the master_die, which is used to access the RAS-related registers within the master_die.
[0051] The I2C toapb_converter on slave1_die and slave2_die can be accessed through the I2C SCL and SDA. The specific slave_die to access can be identified by the 7-bit I2C slave_address on each die (which will be explained in the subsequent frame structure).
[0052] After the master die's I2C master sends the corresponding data frame on the I2C SDA line, the slave die's I2Ctoapb_converter module converts it into the corresponding die's APB request, and then processes it according to... Figure 3 The steps shown are for accessing the RAS-related registers of each subsystem within the slave.
[0053] This invention Figure 2The diagram illustrates data transmission between dies via the I2C bus. An independent I2C network is used as the communication link for the RAS network. This eliminates the need for RAS information queries to rely on the main data path between dies, ensuring that even if the main data path (UCIE) between dies fails, RAS information can still be obtained across dies. Furthermore, it can be directly used to debug the UCIE link itself. This allows the system to promptly confirm the operational status of relevant UCIEs, report relevant issues, and perform debugging.
[0054] Data transmission based on the RAS network on each die only requires two bumps and two interconnects, reducing the need for bumps and minimizing chip substrate design scum.
[0055] This invention Figure 3 The diagram illustrates how serial connections ensure reliable RAS query channels for data transmission within the die. The serial connection of APBs reduces the need for cabling resources, thus avoiding resource utilization issues and cabling difficulties caused by line congestion between different subsystems.
[0056] like Figure 5 As shown, the format of the first frame corresponding to the write operation is explained as follows:
[0057] This first frame format can be used to write 32-bit data based on a 32-bit address and can be encapsulated in the I2C frame format. Here, S (start), SLAVE_ADDRESS (I2C 7-bit device ID), and R / W (0: indicates a data request is sent from the master to the slave; 1: indicates data is returned from the slave to the master). The "device ID" mentioned above is the "slave device ID," used to distinguish which I2C slave device is the requesting and responding party.
[0058] RS (restart flag), ACK, and P (Stop) are all definitions of the original I2C frame format.
[0059] The first four bytes of the data payload are used to pass the operation address, the fifth byte (CMD field) is used to pass the operator (8'h00 corresponds to a write operation; 8'h01 corresponds to a read operation), and the last four bytes pass the data to be written.
[0060] like Figure 6 As shown, the format of the second frame corresponding to the read operation is explained as follows:
[0061] This second frame format can be used to read 32-bit address and return the read 32-bit data, and can be encapsulated in the I2C frame format.
[0062] Description of content that differs from the format of the first frame:
[0063] The I2C 7-bit device ID and 1-bit R / W character field are transmitted starting from the RS field (here, setting it to 1 indicates reading the return data from the slave to the master).
[0064] The next bytes DATA3~DATA0 sent from the slave to the master represent the read data that needs to be fed back based on the address in the first I2C data structure. The fifth byte, flag, indicates the data feedback status from the slave to the master: 8'h00 indicates that the data feedback has not yet been completed; 8'h01 indicates that the data feedback has been successful; after the master sends back the corresponding byte ack, the current data transmission is completed with the standard P character.
[0065] The RAS network interconnection system based on die chips provided in this embodiment of the invention includes at least two die chips. Each die chip includes a set of I2C master devices and I2C slave devices. The die chips are interconnected via an I2C bus. The I2C master device within each die chip is connected to an SCP, and the I2C slave device within each die chip is connected to a RAS channel. A first SCP corresponding to the first die chip (which initiates the request) converts cross-die APB requests into cross-die I2C requests and sends these requests to the first I2C master device in the first die chip. The first I2C master device sends the cross-die I2C requests to the second I2C slave device in the second die chip (which responds to the request) via the I2C bus. The second I2C slave device responds to the cross-die I2C requests. The request is converted to obtain cross-die APB requests. The second die chip aggregates the cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. These aggregated APB requests are then decomposed into multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip. Inter-die data communication is completed via an independent I2C bus, eliminating reliance on die-to-die data channels and improving the robustness of the RAS system. Using a serial APB network within a single die saves routing resources and reduces the difficulty of later PR (Profile Processing).
[0066] In the above optional embodiments, each APB data stream corresponds to multiple serially connected subsystems, and each subsystem has a built-in RAS processing module. Refer to the above embodiments for further details; no further elaboration will be provided.
[0067] In the above optional embodiments, each subsystem receives the upstream APB data stream sent by the upstream subsystem, and obtains the data address in the upstream APB data stream through the RAS processing module. If it is determined that the accessed data is in the current subsystem based on the data address in the upstream APB data stream, the current subsystem sends back response information for the upstream APB data stream. This can be referred to the above embodiments for further explanation and will not be repeated here.
[0068] In the above optional embodiments, if it is determined from the data address in the upstream APB data stream that the accessed data is not in the current subsystem, then the upstream APB data stream is forwarded to the downstream subsystem of the current subsystem through the current subsystem. This can be referred to the above embodiments for further explanation, and will not be repeated here.
[0069] In the above optional embodiments, the I2C bus encapsulates a frame format corresponding to the data operation type. The frame format includes a data transmission flag bit. If the data transmission flag bit is 0, it indicates that the first I2C master device is sending data to the second I2C slave device. Please refer to the above embodiments for further details.
[0070] If the data transmission flag is 1, it indicates that data is being sent from the second I2C slave device to the first I2C master device. This can be referred to the above embodiment for further explanation, and will not be repeated here.
[0071] In the above optional embodiments, the frame format corresponding to the data operation type of write operation is the first frame format, and the content of the first frame format includes the address information and data information of the operation to be converted. Refer to the above embodiments for further details.
[0072] In the above optional embodiments, the frame format corresponding to the data operation type of read operation is the second frame format. The content of the second frame format includes the address information of the operation to be converted and the read data information that needs to be fed back. Refer to the above embodiments for further details.
[0073] This invention provides a data processing method for a RAS network interconnection system based on die chips. The die chip-based RAS network interconnection system includes at least two die chips, each die chip comprising a set of I2C master devices and I2C slave devices. Each die chip is interconnected via an I2C bus. The I2C master device within each die chip is connected to an SCP (Site Controller), and the I2C slave device within each die chip is connected to a RAS channel. The data processing method includes:
[0074] The first SCP corresponding to the first die chip that is the request initiator in the die chip converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the first I2C master device in the first die chip.
[0075] The first I2C master device sends a cross-die I2C request to the second I2C slave device in the second die chip, which is the request responder, through the I2C bus. The second I2C slave device converts the cross-die I2C request to obtain a cross-die APB request.
[0076] The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
[0077] The embodiments of the task allocation and scheduling method provided in this invention can be used to execute the processing flow of the above-described system embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above-described system embodiments.
[0078] This disclosure also proposes a board that includes the die chip-based RAS network interconnect system described above.
[0079] This disclosure also proposes an electronic device that includes the board described above.
[0080] Compared with existing technologies, the RAS network interconnection system based on die chips provided in this invention includes at least two die chips. Each die chip includes a set of I2C master devices and I2C slave devices. The die chips are interconnected via an I2C bus. The I2C master device within each die chip is connected to an SCP, and the I2C slave device within each die chip is connected to a RAS channel. The first SCP corresponding to the first die chip (which initiates the request) converts the cross-die APB request into a cross-die I2C request and sends it to the first I2C master device in the first die chip. The first I2C master device sends the cross-die I2C request to the second I2C slave device in the second die chip (which responds to the request) via the I2C bus. The second I2C slave device responds to the cross-die I2C request. The request is converted to obtain cross-die APB requests. The second die chip aggregates the cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. These aggregated APB requests are then decomposed into multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip. Inter-die data communication is completed via an independent I2C bus, eliminating reliance on die-to-die data channels and improving the robustness of the RAS system. Using a serial APB network within a single die saves routing resources and reduces the difficulty of later PR (Profile Processing).
[0081] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0082] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A RAS network interconnection system based on a die chip, characterized in that, It includes at least two die chips, each die chip includes a set of I2C master devices and I2C slave devices, each die chip is interconnected via an I2C bus, the I2C master device inside each die chip is connected to the SCP, and the I2C slave device inside each die chip is connected to the RAS channel; The first SCP corresponding to the first die chip that is the request initiator in the die chip converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the first I2C master device in the first die chip; The first I2C master device sends a cross-die I2C request to the second I2C slave device in the second die chip, which is the request responder, through the I2C bus. The second I2C slave device converts the cross-die I2C request to obtain a cross-die APB request. The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
2. The RAS network interconnection system based on die chip according to claim 1, characterized in that, Each APB data stream corresponds to multiple serially connected subsystems, and each subsystem has a built-in RAS processing module.
3. The RAS network interconnection system based on die chip according to claim 2, characterized in that, Each subsystem receives the upstream APB data stream sent by the upstream subsystem and obtains the data address in the upstream APB data stream through the RAS processing module. If it is determined that the data to be accessed is in the current subsystem based on the data address in the upstream APB data stream, the current subsystem will send back response information for the upstream APB data stream.
4. The RAS network interconnection system based on die chip according to claim 3, characterized in that, If the data to be accessed is determined to be outside the current subsystem based on the data address in the upstream APB data stream, then the upstream APB data stream is forwarded to the downstream subsystem of the current subsystem through the current subsystem.
5. The RAS network interconnection system based on die chip according to claim 1, characterized in that, The I2C bus encapsulates a frame format corresponding to the data operation type. The frame format includes a data transmission flag. If the data transmission flag is 0, it indicates that the first I2C master device is sending data to the second I2C slave device. If the data transmission flag is 1, it indicates that data is being sent from the second I2C slave device to the first I2C master device.
6. The RAS network interconnection system based on die chip according to claim 5, characterized in that, The frame format corresponding to the data operation type of write operation is the first frame format, and the content of the first frame format includes the address information and data information of the operation to be converted.
7. The RAS network interconnection system based on die chip according to claim 5, characterized in that, The frame format corresponding to the data operation type of read operation is the second frame format. The content of the second frame format includes the address information of the operation to be converted, as well as the read data information that needs to be fed back.
8. A data processing method for a RAS network interconnection system based on a die chip, characterized in that, The RAS network interconnection system based on die chips includes at least two die chips. Each die chip includes a set of I2C master devices and I2C slave devices. The die chips are interconnected via an I2C bus. The I2C master devices within each die chip are connected to the SCP, and the I2C slave devices within each die chip are connected to the RAS channel. The data processing method includes: The first SCP corresponding to the first die chip that is the request initiator in the die chip converts the cross-die APB request into a cross-die I2C request, and sends the cross-die I2C request to the first I2C master device in the first die chip; The first I2C master device sends a cross-die I2C request to the second I2C slave device in the second die chip, which is the request responder, through the I2C bus. The second I2C slave device converts the cross-die I2C request to obtain a cross-die APB request. The second die chip aggregates cross-die APB requests and intra-die APB requests to obtain aggregated APB requests. It then decomposes the aggregated APB requests to obtain multiple APB data streams. Each APB data stream serially accesses the second RAS channel corresponding to the second die chip.
9. A circuit board, characterized in that, The board includes a die-chip-based RAS network interconnect system as described in any one of claims 1 to 7.
10. An electronic device, characterized in that, The electronic device includes the board as described in claim 9.