Method for improving ADC multi-chip synchronization performance based on independent clock FIFO

Abstract

The invention discloses a method for improving multi-chip synchronization performance of an ADC (Analog to Digital Converter) based on an independent clock FIFO (First In First Out), aiming at the problem of difficulty in timing sequence alignment during synchronous acquisition of a multi-chip source synchronization interface ADC and an FPGA (Field Programmable Gate Array), the multi-chip synchronization performance of the ADC is improved by optimizing clock distribution and equal-length wiring design, optimizing connection logic of source synchronization interface signals in the FPGA and combining an automatic training mechanism of an ISERDES module in the FPGA. Automatic alignment of data bits is realized; and further synchronizing the data of each ADC to a unified clock domain by using a plurality of independent clock FIFOs (First In First Out). According to the invention, automatic and reliable synchronous sampling after the plurality of ADCs are powered on is realized, and the method has the advantages of high synchronization precision, strong anti-interference performance, support of multi-chip expansion, model self-adaption and the like.

Description

Technical Field

[0001] This invention relates to serial source synchronization data transmission technology between ADC and FPGA, specifically to a method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO. Background Technology

[0002] Analog sampling technology is widely used in detection fields such as radar, communication, and medical imaging. The system simultaneously samples multiple analog input signals using multiple analog-to-digital converters (ADCs), and then processes the sampled data to achieve synchronization of the various signal channels.

[0003] FPGA logic speeds generally cannot keep up with the bus speeds of high-speed converters. Therefore, most FPGAs have deserializer modules (ISERDES) to convert the fast, serial interface at the converter end into a slow, parallel interface at the FPGA end. The ADC outputs high-speed serial data, and the ISERDES at the FPGA end decodes the slow, parallel ADC data. This is the basic method of serial source synchronous interface data transmission.

[0004] Currently, there are two main methods for handling sampling synchronization of multiple serial source synchronous interface ADCs:

[0005] 1) The ADC outputs serial data and its corresponding bit clock to the FPGA. Inside the FPGA, the data passes through an IODELAY delay module before entering the ISERDES. Additionally, the FPGA receives a clock CLKSP, which is from the same source and has the same frequency as the ADC sampling clock, and connects directly to the ISERDES. By automatically adjusting the parameters of the IODELAY delay modules for each ADC and using bit-slip logic, the sampled data is synchronized to CLKSP. This method has a long training time, which becomes more pronounced with an increased number of ADC chips, and the sampling noise floor is relatively high even after successful training.

[0006] 2) The ADC outputs serial data to the FPGA, which directly connects to the ISERDES within the FPGA. Additionally, the FPGA inputs a clock CLKSP, which is from the same source and has the same frequency as the ADC sampling clock, and connects it to the clock phase-locked loop (DCM). The DCM outputs clocks CLKSP_1x and CLKSP_4x. The phase difference between CLKSP_1x and CLKSP_4x relative to CLKSP can be adjusted. CLKSP_1x and CLKSP_4x serve as global clocks, each connected to the ISERDES corresponding to multiple ADC data streams. By adjusting the phase of the DCM output clocks CLKSP_1x and CLKSP_4x, combined with bit-slip logic, the sampled data is synchronized to CLKSP_1x. This method has a shorter training time, but the sampling noise floor is relatively high after successful training, becoming more pronounced with an increased number of ADC chips. Summary of the Invention

[0007] The purpose of this invention is to provide a method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO.

[0008] The technical solution to achieve the purpose of this invention is as follows: a method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO, applied to a hardware system including a clock driver chip, multiple analog-to-digital converters (ADCs), and a field-programmable gate array (FPGA). The automatic synchronization method is as follows:

[0009] Step 1: After the external sampling clock passes through the clock driver chip, it is divided into N+1 differential clock signals, where N is the number of ADCs; the first differential clock signal is connected to the dedicated clock pin of the FPGA as the global sampling clock domain; the remaining N differential clock signals are respectively connected to the clock input pins of the N ADCs, and are converted into the frame clock in the source synchronization signal by each ADC; the N differential clock signals are connected with equal-length wiring, and the length error between pairs does not exceed the first threshold.

[0010] Step 2: Each ADC outputs one frame clock signal, one bit clock signal, and eight bit data signals as source synchronization signals; the source synchronization signals output by all ADCs use equal-length wiring, and the length error between pairs does not exceed the second threshold; all source synchronization signals output by the same ADC are connected to the same I / O group of the FPGA, and the frame clock signal and bit clock signal are connected to the dedicated clock pin of the I / O group.

[0011] Step 3: Inside the FPGA, the frame clock signal and the bit clock signal are connected to the serial-to-parallel converter module through the area clock buffer unit, respectively, and the bit data signal is connected to the serial-to-parallel converter module through the input buffer unit.

[0012] Step 4: Set each ADC to training mode and output a predetermined training data sequence; convert the received serial training data into parallel data through the serial-to-parallel converter module; if the converted parallel data does not match the predetermined training data, trigger a bit flip operation; if it still does not match after a preset number of bit flips, reset the corresponding ADC and serial-to-parallel converter module and retrain until a match is achieved, then switch the ADC to normal working mode.

[0013] Step 5: Obtain N parallel data streams through the serial-to-parallel converter module, with each data stream synchronized with its corresponding frame clock; set up an independent clock first-in-first-out queue for each data stream, write each parallel data stream and its corresponding frame clock into the write port of each queue, use the global sampling clock as the read clock, and synchronously read out N data streams from the read port of each queue, thereby synchronizing all ADC sampling data to the same global sampling clock domain.

[0014] Furthermore, both the first threshold and the second threshold are 10mil.

[0015] Furthermore, the regional clock buffer unit is a BUFR module within the FPGA, the input buffer unit is an IBUF module, and the serial-to-parallel converter module is an ISERDES module.

[0016] Furthermore, the bit-flipping operation is implemented by sending a BITSLIP control signal to the serial-to-parallel converter module.

[0017] Furthermore, the supported ADCs are ADCs based on a serial low-voltage differential signal source synchronization interface, with a sampling rate not exceeding 125 MHz.

[0018] Furthermore, the ADC model includes ADS6445, AD9653, LTC2175, SAD6445MC, B9653E or KHW14B125.

[0019] Furthermore, this applies to cases where N is greater than or equal to 2, meaning there are more than 2 ADCs.

[0020] An automatic synchronization system based on a serial source synchronization interface ADC implements the method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO, and executes steps 1 to 5 in five modules respectively.

[0021] Compared with the prior art, the significant advantages of this invention are: (1) the source synchronization training time is short and the basic noise of the AD sampling data is lower after successful training; (2) the compatibility of multi-chip synchronization is better, allowing for certain inherent deviations between different ADCs, and can be extended to more ADC chips. Attached Figure Description

[0022] Figure 1 This is a block diagram of a source-synchronous interface ADC synchronous sampling system.

[0023] Figure 2 This is a block diagram illustrating the source synchronization signal output by the ADC.

[0024] Figure 3 This is a block diagram showing the connection between the ADC and the FPGA source synchronization signal.

[0025] Figure 4 This is a block diagram of the FPGA internal connections for the source synchronization signal.

[0026] Figure 5 The logic block diagram for automatic training of ISERDES.

[0027] Figure 6 A logic block diagram for synchronizing AD data output. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] This invention discloses a method for improving the synchronization performance of multiple ADCs based on an independent clock FIFO. The hardware involved mainly includes an LVDS clock driver, a source-synchronous interface ADC, and a source-synchronous interface logic FPGA. For ease of understanding of the specific technical content, the number of ADCs N is set to 8, the clock driver is selected from Analog Devices' ADCLK948, the ADC is selected from Texas Instruments' ADS6445, and the FPGA is selected from Xilinx's XC7K325T. The specific implementation includes the following steps:

[0030] 1. Determine the connection method between the source synchronization signal and the sampling clock.

[0031] According to the appendix Figure 1 Each ADC chip outputs 10 differential source synchronization signals, including 1 frame clock signal, 1 bit clock signal, and 8 bit data signals. See the attached diagram for the analytical block diagram of the ADC output source synchronization signals. Figure 2 .

[0032] The sampling clock is divided into 9 (N+1) sampling clocks by the clock driver chip ADCLK948, which are connected to the FPGA and 8 ADCs respectively. The source synchronization signal output by the ADC is directly connected to the FPGA chip.

[0033] 2. Source Synchronization Signal Routing Design

[0034] according to Figure 3 Each ADC chip outputs 10 differential signals as the source synchronization signal. The 8 ADC chips have a total of 80 (N*10) differential signals. Considering the synchronization performance of multiple chips, the 80 differential signals need to be designed to maintain equal length, and the length error between pairs should not exceed 10mil.

[0035] In addition, the source synchronization signals output by the same ADC chip must be connected to the same I / O group of the FPGA, and the frame clock and bit clock signals must be connected to the dedicated clock pin of the same I / O group.

[0036] 3. Sampling clock signal wiring design

[0037] according to Figure 1 The sampling clock signal is fanned out by the clock driver chip and includes one FPGA sampling clock and eight ADC sampling clocks, all of which are differential signals. Considering the synchronization performance of multiple chips, the eight ADC sampling clocks need to maintain an equal length design, and the length error between pairs should not exceed 10mil.

[0038] 4. Construct the connection relationship of the source synchronization signal inside the FPGA.

[0039] according to Figure 4 The frame clock signal and bit clock signal of the source synchronization signal are connected to ISERDES through a BUFR, and the bit data signal is connected to ISERDES through an IBUF. The BUFR is a regional clock buffer unit within the same I / O group, the IBUF is a general buffer unit within the same I / O group, and ISERDES is a dedicated serial-to-parallel conversion unit inside the FPGA.

[0040] 5. Construct the FPGA internal ISERDES automatic training logic

[0041] according to Figure 5 After power-on, the ADC is first set to training mode. The ADC outputs specific serial training data, which is converted into parallel data by the ISERDES inside the FPGA. If it does not match the training data, the BIT SLIP signal is activated and fed back to the ISERDES. After several bit flips, if it still does not match the training data, the ADC and ISERDES are reset, and the training logic of the next cycle is performed until the parallel data matches the specific training data of the ADC. This indicates that the training is successful, and the ADC is set to normal working mode.

[0042] 6. Construct the FPGA internal AD data synchronization output logic

[0043] according to Figure 6 Eight ADCs output eight parallel data streams via ISERDES. These eight parallel data streams are synchronized with their respective frame clocks. To extract these eight parallel data streams simultaneously, an FPGA sampling clock is also required. Eight independent clock FIFOs are designed in the FPGA logic. The eight parallel data streams and eight frame clocks are connected to the inputs of the independent clock FIFOs, and the FPGA sampling clock and the eight ADC data outputs are connected to the outputs of the independent clock FIFOs. In this way, the sampled data from the eight ADCs are synchronized to the same clock domain (FPGA sampling clock), realizing the function of synchronous sampling.

[0044] In summary, this invention completely solves the sampling synchronization problem of multi-chip serial source synchronous interface ADCs, improves the signal-to-noise ratio and amplitude-phase stability accuracy of the sampling output, and is easy to expand to more ADC channels. This invention is applicable to imported ADCs (ADS6445, AD9653, LTC2175, etc.) and domestic ADCs (SAD6445MC, B9653E, KHW14B125, etc.) of the same type. Furthermore, for reflector radars, it can improve angle measurement accuracy and moving target improvement factor; for phased array radars, it can improve beam pointing accuracy and main-sidelobe ratio, thereby improving the moving target improvement factor.

[0045] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0046] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO, characterized in that, The automatic synchronization method, applied to a hardware system including a clock driver chip, multiple analog-to-digital converters (ADCs), and a field-programmable gate array (FPGA), is as follows: Step 1: After the external sampling clock passes through the clock driver chip, it is divided into N+1 differential clock signals, where N is the number of ADCs; the first differential clock signal is connected to the dedicated clock pin of the FPGA as the global sampling clock domain. The remaining N differential clock signals are respectively connected to the clock input pins of N ADCs, and are converted into the frame clock in the source synchronization signal by each ADC; the N differential clock signals are connected by equal-length wiring, and the length error between pairs does not exceed the first threshold. Step 2: Each ADC outputs one frame clock signal, one bit clock signal, and eight bit data signals as source synchronization signals; all source synchronization signals output by the ADCs use equal-length wiring, and the length error between pairs does not exceed the second threshold; all source synchronization signals output by the same ADC are connected to the same I / O group of the FPGA, and the frame clock signal and bit clock signal are connected to the dedicated clock pin of the I / O group. Step 3: Inside the FPGA, the frame clock signal and the bit clock signal are connected to the serial-to-parallel converter module through the area clock buffer unit, respectively, and the bit data signal is connected to the serial-to-parallel converter module through the input buffer unit. Step 4: Set each ADC to training mode and output a predetermined training data sequence; convert the received serial training data into parallel data through the serial-to-parallel converter module; if the converted parallel data does not match the predetermined training data, trigger a bit flip operation; if it still does not match after a preset number of bit flips, reset the corresponding ADC and serial-to-parallel converter module and retrain until a match is achieved, then switch the ADC to normal working mode. Step 5: Obtain N parallel data streams through the serial-to-parallel converter module, with each data stream synchronized with its corresponding frame clock; set up an independent clock first-in-first-out queue for each data stream, write each parallel data stream and its corresponding frame clock into the write port of each queue, use the global sampling clock as the read clock, and synchronously read out N data streams from the read port of each queue, thereby synchronizing all ADC sampling data to the same global sampling clock domain.

2. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, Both the first threshold and the second threshold are 10mil.

3. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, The regional clock buffer unit is a BUFR module within the FPGA, the input buffer unit is an IBUF module, and the serial-to-parallel converter module is an ISERDES module.

4. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, The bit-flipping operation is achieved by sending a BITSLIP control signal to the serial-to-parallel converter module.

5. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, The supported ADCs are ADCs based on a serial low-voltage differential signal source synchronization interface, with a sampling rate not exceeding 125 MHz.

6. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, The ADC models include ADS6445, AD9653, LTC2175, SAD6445MC, B9653E, or KHW14B125.

7. The method for improving the synchronization performance of multiple ADC chips based on an independent clock FIFO according to claim 1, characterized in that, This applies to cases where N is greater than or equal to 2, meaning there are more than 2 ADCs.

8. An automatic synchronization system based on a serial source synchronization interface ADC, characterized in that, The method for improving the synchronization performance of multiple ADC chips based on independent clock FIFO as described in any one of claims 1-7 is implemented by performing steps 1 to 5 in five modules respectively.

Images