High-reliability and high-sensitivity bus under-voltage protection circuit for satellite

Abstract

The invention discloses a high-reliability and high-sensitivity bus under-voltage protection circuit for a satellite, and belongs to the technical field of satellite circuits. The circuit comprises a reference source circuit, a driving pulse generation circuit, a driving pulse isolation circuit, a driving pulse self-locking circuit and a driving pulse differential amplification circuit which are sequentially connected in series. When the primary bus drops, the output of the driving pulse generating circuit is high, the driving pulse self-locking circuit enters a self-locking state and charges a charging and discharging module of the driving pulse differential amplification circuit, so that the output of a switch module of the driving pulse differential amplification circuit is high level, and the connected magnetic latching relay is switched from a normally closed state to a disconnected state. Power failure of a primary bus to a powered product is realized; the charging and discharging module is in an open-circuit state after charging is completed, so that the switch module outputs a low level. Power supply of the primary bus to a product can be cut off in a quick response mode, and the situation that surge current of the primary bus is too large when the primary bus recovers, and power supply and distribution safety and reliability of a whole satellite are affected is prevented.

Description

Technical Field

[0001] This invention relates to the field of satellite circuit technology, and in particular to a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites. Background Technology

[0002] With the rapid development of spacecraft, the requirements for the safety and reliability of satellite power supply are becoming increasingly stringent. Currently, satellite products are powered by the satellite's primary bus, but the undervoltage protection circuit for the primary bus is not yet sufficient to meet the required safety and reliability standards.

[0003] Therefore, there is an urgent need to provide a highly reliable and sensitive bus undervoltage protection circuit to meet the reliability and safety requirements of satellite power supply. Summary of the Invention

[0004] This invention provides a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites. The technical solution is as follows:

[0005] This invention provides a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites, comprising: a reference source circuit, a drive pulse generation circuit, a drive pulse isolation circuit, a drive pulse self-locking circuit, and a drive pulse differential amplifier circuit connected in series.

[0006] The reference source circuit provides a reference voltage for the drive pulse generating circuit based on the output voltage of the primary bus.

[0007] The drive pulse generating circuit compares the first reference voltage determined using the reference voltage with the primary bus voltage telemetry, and outputs a drive pulse signal based on the comparison result.

[0008] The drive pulse isolation circuit uses an optocoupler to convert the drive pulse signal from a primary signal to a secondary signal, thereby achieving isolation between the primary and secondary signals.

[0009] The drive pulse self-locking circuit is used to detect the input signal to determine whether to perform self-locking;

[0010] The drive pulse differential amplifier circuit includes a charging / discharging module and a switching module connected in series; the switching module is connected to the powered product via a magnetic latching relay.

[0011] When the primary bus is normal, the switch module outputs a low level, and the magnetic latching relay is in a normally closed state, so that the primary bus supplies power to the powered products. When the primary bus drops, the drive pulse generating circuit outputs a high level, the drive pulse self-locking circuit enters a self-locking state and charges the charging and discharging module, so that the switch module outputs a high level, and the magnetic latching relay switches from a normally closed state to an open state, so that the primary bus disconnects power to the powered products. When the charging and discharging module is fully charged, it is in an open circuit state, so that the switch module outputs a low level.

[0012] The technical solution provided by this invention can bring at least the following beneficial effects:

[0013] This undervoltage protection circuit has higher sensitivity. When the primary bus drops momentarily or recovers after a short period of time, it can quickly cut off the power supply from the primary bus to the product, preventing excessive surge current on the primary bus when it recovers from affecting the safety and reliability of the entire satellite's power supply and distribution. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a structural diagram of a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites provided in an embodiment of the present invention;

[0016] Figure 2 This is a circuit diagram of a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0018] The undervoltage protection circuit for satellite bus needs to meet three requirements. First, for safety reasons, for high-power products or onboard devices, the primary bus power supply should be immediately cut off upon a power outage to prevent large surge currents from affecting the overall satellite power supply when all individual units start simultaneously during the re-establishment of the satellite bus. Second, for reliability reasons, primary and secondary ground isolation is required, no external control command circuit is needed, and the failure of any component in the undervoltage protection circuit should not affect the functionality of any individual unit. Third, for availability reasons, the components selected for the undervoltage protection circuit should be conventional components with short procurement cycles and stable supply.

[0019] The following describes the specific implementation method of the bus undervoltage protection circuit that can meet the above three requirements.

[0020] Please refer to Figure 1 The present invention provides a high-reliability and high-sensitivity bus undervoltage protection circuit for satellites, comprising: a reference source circuit, a drive pulse generation circuit, a drive pulse isolation circuit, a drive pulse self-locking circuit, and a drive pulse differential amplifier circuit connected in series.

[0021] The reference source circuit provides a reference voltage for the drive pulse generating circuit based on the output voltage of the primary bus.

[0022] The drive pulse generating circuit compares the first reference voltage determined using the reference voltage with the primary bus voltage telemetry, and outputs a drive pulse signal based on the comparison result.

[0023] The drive pulse isolation circuit uses an optocoupler to convert the drive pulse signal from a primary signal to a secondary signal, thereby achieving isolation between the primary and secondary signals.

[0024] The drive pulse self-locking circuit is used to detect the input signal to determine whether to perform self-locking;

[0025] The drive pulse differential amplifier circuit includes a charging / discharging module and a switching module connected in series; the switching module is connected to the powered product via a magnetic latching relay.

[0026] When the primary bus is normal, the switch module outputs a low level, and the magnetic latching relay is in a normally closed state, enabling the primary bus to supply power to the powered products. When the primary bus drops, the drive pulse generating circuit outputs a high level, the drive pulse self-locking circuit enters a self-locking state and charges the charging and discharging module, causing the switch module output to a high level, and the magnetic latching relay switches from an open state to a normally closed state, thus de-energizing the primary bus from the powered products. When the charging and discharging module completes charging and is in an open-circuit state, the switch module outputs a low level.

[0027] In this embodiment of the invention, the undervoltage protection circuit has higher sensitivity. When the primary bus drops momentarily or drops briefly and then recovers, it can quickly respond and cut off the power supply of the primary bus to the product, preventing the surge current of the primary bus from being too large when the primary bus recovers, thus affecting the safety and reliability of the entire satellite's power supply and distribution.

[0028] Please refer to Figure 2 This is a circuit diagram of a high-reliability, high-sensitivity bus undervoltage protection circuit for satellites. The following utilizes... Figure 2 The circuit diagram shown is used to describe Figure 1 The implementation methods of each part of the circuit are shown.

[0029] For reference source circuits.

[0030] The reference source circuit is used to divide the output voltage of the primary bus so as to provide the working voltage for the drive pulse generation circuit using the obtained reference voltage.

[0031] In one implementation, the reference source circuit can be implemented using the following components and their connections:

[0032] The Zener diode network and the capacitor network are connected in parallel to form a first parallel circuit. The first parallel circuit is connected in series with the resistor network to form a reference source circuit. The end of the resistor network that is not connected to the first parallel circuit is connected to the output terminal of the primary bus, and the end of the first parallel circuit that is not connected to the resistor network is connected to the ground of the primary bus. The connection point between the first parallel circuit and the resistor network is the reference voltage VA.

[0033] The resistor network includes resistors R1 to R4. Resistors R1 and R2 are connected in series to form a first series sub-circuit, and resistors R3 and R4 are connected in series to form a second series sub-circuit. The first series sub-circuit and the second series sub-circuit are connected in parallel, and the connection terminals of the two resistors in the first series circuit are connected to the connection terminals of the two resistors in the second series circuit, thus forming a resistor network.

[0034] The Zener diode network includes Zener diodes Z1 to Z4. Zener diodes Z1 and Z2 are connected in reverse series to form a third series sub-circuit, and Zener diodes Z3 and Z4 are connected in reverse series to form a fourth series sub-circuit. The third and fourth series sub-circuits are connected in parallel, and the connection terminals of the two Zener diodes in the third series circuit are connected to the connection terminals of the two Zener diodes in the fourth series circuit, thus forming a Zener diode network.

[0035] The capacitor network includes capacitors C1 to C4. Capacitors C1 and C2 are connected in series in the forward direction to form the fifth series sub-circuit. Capacitors C3 and C4 are connected in series in the forward direction to form the sixth series sub-circuit. The fifth and sixth series sub-circuits are connected in parallel, and the connection terminals of the two capacitors in the fifth series circuit are connected to the connection terminals of the two capacitors in the sixth series circuit, thus forming the capacitor network.

[0036] For the drive pulse generation circuit.

[0037] In this embodiment of the invention, the drive pulse generating circuit is used to compare a first reference voltage determined using the reference voltage with a telemetry measurement of the primary bus voltage, so as to output a drive pulse signal based on the comparison result.

[0038] In one implementation, the drive pulse generating circuit includes: a sampling resistor, a hysteresis comparator, a first current-limiting resistor, a first Zener diode, and a first transistor;

[0039] The sampling resistor samples the output voltage of the primary bus to obtain a voltage telemetry signal, which is then output to the non-inverting input of the hysteresis comparator. The first reference voltage is input to the inverting input of the hysteresis comparator using the first current-limiting resistor and the first Zener diode connected in series. The hysteresis comparator is inverted through the first transistor to output a drive pulse signal through the collector of the first transistor.

[0040] When the primary bus is normal, the output of the hysteresis comparator is high, the first transistor is in the cut-off state, and the optocoupler does not output an electrical signal.

[0041] When the busbar drops, the output of the hysteresis comparator goes low, the first transistor is in the conducting state, and the optocoupler outputs an electrical signal.

[0042] Specifically, one implementation of this drive pulse generating circuit is as follows: Figure 2 As shown. This drive pulse generation circuit can be implemented using the following components and their connection methods:

[0043] The sampling resistors include resistors R7 to R9 and resistor R9A; resistors R7, R8 and R9 are connected in series to form a seventh series circuit, and capacitor C5 and resistor R9A are connected in parallel with resistor R9; one end of the seventh series circuit is connected to the output terminal of the primary bus, and the other end of the seventh series circuit is connected to the ground of the primary bus.

[0044] The hysteresis comparator includes comparator U1 and resistors R11 to R13; the reference voltage VA is connected to the positive power supply terminal of comparator U1;

[0045] The first current-limiting resistor R10 is connected to the cathode of the first Zener diode Z5 to form an eighth series circuit. The end of the first current-limiting resistor R10 that is not connected to the first Zener diode Z5 is connected to the reference voltage VA. The anode of the first Zener diode Z5 is connected to the primary bus ground and the negative power supply terminal of the comparator U1.

[0046] The output of comparator U1 is connected in series with resistor R14 and then connected to the base of the first transistor V1. One end of resistor R15 is connected to the reference voltage VA and the other end is connected to the base of the first transistor V1. One end of resistor R16 is connected to the reference voltage VA and the other end is connected to the emitter of the first transistor V1. One end of resistor R17 is connected to the collector of the first transistor V1 and the other end is connected to the drive pulse isolation circuit.

[0047] For drive pulse isolation circuits.

[0048] In this embodiment of the invention, the drive pulse isolation circuit uses an optocoupler J1 to convert the drive pulse signal from a primary signal to a secondary signal, thereby achieving isolation between the primary and secondary signals.

[0049] For one implementation method, please refer to Figure 2 The drive pulse isolation circuit can be implemented using the following components and their connection methods:

[0050] The resistor R18, capacitor C6, and optocoupler J1 are connected in parallel to form a parallel circuit. One end of this parallel circuit (i.e., the negative input terminal of optocoupler J1) is connected to the primary bus ground, and the other end (i.e., the positive and negative output terminals of optocoupler J1) is connected to the resistor R17. The base of optocoupler J1 is connected to the resistor R19, and the other end of the resistor R19 is grounded. The collector of optocoupler J1 is connected to the inverting input terminal of the self-locking comparator U2 through the resistor R21. The emitter of optocoupler J1 is connected to the negative power supply terminal of the self-locking comparator U2 through the resistor R20.

[0051] For the self-locking circuit of the drive pulse.

[0052] In this embodiment of the invention, the drive pulse self-locking circuit is used to detect the input signal to determine whether to perform self-locking.

[0053] In one implementation, the drive pulse self-locking circuit includes: a self-locking comparator, a second current-limiting resistor, a second Zener diode, and several series resistors; the drive pulse self-locking circuit is also connected to an external power supply voltage;

[0054] The external power supply voltage is used to obtain a second reference voltage from the external power supply voltage through the second current-limiting resistor and the second Zener diode connected in series, and then input to the non-inverting input terminal of the second comparator.

[0055] The external power supply voltage is connected to the inverting input of the second comparator through several series resistors; wherein the optocoupler is connected in parallel with the series circuit formed by the series resistors.

[0056] When the optocoupler does not output an electrical signal, the voltage value at the inverting input terminal of the self-locking comparator is higher than the voltage value at the non-inverting input terminal, and the output of the self-locking comparator is low.

[0057] When the optocoupler outputs an electrical signal, the voltage value at the inverting input terminal of the self-locking comparator is lower than the voltage value at the non-inverting input terminal, and the output of the self-locking comparator is high.

[0058] Specifically, one implementation of this drive pulse self-locking circuit is as follows: Figure 2 As shown. This drive pulse self-locking circuit can be implemented using the following components and their connection methods:

[0059] Resistors R20A, R21, and R21A are connected in series to form the ninth series circuit; one end of the second current-limiting resistor R22 is connected to the cathode of the second Zener diode Z6 to form the tenth series circuit; the ninth and tenth series circuits are connected in parallel to form the second parallel circuit, and one end of the second parallel circuit is connected to the external power supply voltage VB, while the other end (the anode of the second Zener diode Z6) is grounded.

[0060] The series connection point of the tenth series circuit is connected to the positive input terminal of comparator U2 through resistor R23. One end of resistor R24 ​​is connected to the positive input terminal of comparator U2, and the other end of resistor R24 ​​is connected to the cathode of diode D1. The anode of diode D1 is connected to the output terminal of comparator U2. One end of resistor R25 is connected to the external power supply voltage VB, and the other end of resistor R25 is connected to the output terminal of comparator U2. Resistors R23, R24, diode D1 and comparator U2 form a self-locking comparator.

[0061] If the preceding circuit is faulty, the drive pulse self-locking circuit can detect the fault and maintain the state.

[0062] For the driving pulse differential amplifier circuit.

[0063] In this embodiment of the invention, a charging / discharging module and a switching module are connected in series. The switching module is connected to the powered product via a magnetic latching relay, and is used to supply power to the powered product when the primary bus is normal, and to provide undervoltage protection to the powered product when the primary bus drops.

[0064] In one implementation, the driving pulse differentiating amplifier circuit includes: a DC blocking capacitor, a first transistor circuit, and a second transistor circuit connected in series.

[0065] When the output of the self-locking comparator is low, both transistors in the two transistor circuits are in the off state, the output of the drive pulse differentiating amplifier circuit is low, and the magnetic latching relay does not operate.

[0066] When the output of the self-locking comparator is high, the DC blocking capacitor is charged, both transistors in the two transistor circuits are in the conducting state, the output of the driving pulse differentiating amplifier circuit is high, and the magnetic latching relay is turned off, thus disconnecting the primary bus power supply. When the DC blocking capacitor is fully charged, it is in the open circuit state, the transistors in the two transistor circuits switch to the cutoff state, and the output of the driving pulse differentiating amplifier circuit is low.

[0067] Specifically, one implementation of this drive pulse differentiating amplifier circuit is as follows: Figure 2 As shown. This driving pulse differentiating amplifier circuit can be implemented using the following components and their connections:

[0068] The DC blocking capacitor includes capacitors C7 to C10. Capacitors C7 and C9 are connected in parallel to form a third parallel circuit, and capacitors C8 and C10 are connected in parallel to form a fourth parallel circuit. The third and fourth parallel circuits are connected in series to form a DC blocking capacitor circuit. The input terminal of the DC blocking capacitor circuit is connected to the output terminal of comparator U2 through resistor R26, and the output terminal of the DC blocking capacitor circuit is connected to the first transistor circuit.

[0069] In the first transistor circuit, the cathode of diode D2, one end of capacitor C11, and one end of resistor R27 are all connected to the base of transistor V2; the anode of diode D2 is connected to the output of the DC blocking capacitor circuit; the other end of capacitor C11 and the other end of resistor R27 are both connected to the emitter of transistor V2; the anode of diode D2, the cathode of diode D3, one end of capacitor C12, and one end of resistor R28 are all connected to the base of transistor V2A; the anode of diode D3, the other end of capacitor C12, the other end of resistor R28, and the emitter of transistor V2A are all grounded; the collector of transistor V2A is connected to the emitter of transistor V2; the collector of transistor V2 is connected to the input of the second transistor circuit.

[0070] In the second transistor circuit, one end of resistor R29, one end of resistor R30, and the cathode of diode D4 are connected and serve as the input terminal of the second transistor circuit; the other ends of resistor R29, the other end of resistor R30, and one end of resistor R33 are all connected to the base of transistor V3; the other end of resistor R33 is connected to the external power supply voltage VB, and the external power supply voltage VB is connected to the emitter of transistor V3; the collector of transistor V3 is connected to the emitter of transistor V3A; one end of resistor R31 and one end of resistor R32 are both connected to the anode of diode D4; the other ends of resistor R31, the other end of resistor R32, and one end of resistor R34 are all connected to the base of transistor V3A; the other end of resistor R34 is connected to the emitter of transistor V3A; and the collector of transistor V3A serves as the output terminal OFF_H of the drive pulse differentiating amplifier circuit, which is connected to the magnetic latching relay.

[0071] The aforementioned undervoltage protection circuit can protect the powered products in the event of a busbar drop.

[0072] Furthermore, considering the impact of primary bus overcurrent on the product, in one embodiment of the present invention, the satellite-use high-reliability, high-sensitivity bus undervoltage protection circuit may further include: an overcurrent protection circuit connected in series between the primary bus and the reference source circuit.

[0073] See also Figure 2 The overcurrent protection circuit may include several fuses; wherein the fuses are connected in balanced parallel or unbalanced parallel. When an overcurrent occurs on the primary bus, the power supply to the powered product can be interrupted by the fuses blowing.

[0074] The following uses Figure 2 The circuit shown will be explained again to illustrate the circuit principle:

[0075] When the primary bus is normal, if the voltage measured by the primary bus sampling is higher than the upper threshold of the hysteresis comparator U1, the output of comparator U1 is high, transistor V1 is in the cutoff state, and optocoupler J1 does not output an electrical signal. When the inverting input voltage of comparator U2 is higher than the non-inverting input voltage, the output of comparator U2 is low, transistors V2 and V2A are in the cutoff state, transistors V3 and V3A are in the cutoff state, the OFF_H output is low, and the magnetic latching relay does not operate.

[0076] When the primary bus drops, if the voltage measured by the primary bus sampling is lower than the lower threshold of the hysteresis comparator U1, the output of comparator U1 is low, transistor V1 is in the conducting state, and VA is input to optocoupler J1 through the current-limiting resistor. Optocoupler J1 is turned on, and the inverting input voltage of comparator U2 is lower than the non-inverting input voltage. The output of comparator U2 is locked high, charging the DC blocking capacitors C7-C10. During the charging process of capacitors C7-C10, transistors V2 and V2A are in the conducting state, transistors V3 and V3A are in the conducting state, the OFF_H output is high, the magnetic latching relay is turned off, and the primary bus power supply is disconnected. When capacitors C7-C10 are fully charged, capacitors C7-C10 are in the open circuit state, transistors V2 and V2A are in the cutoff state, transistors V3 and V3A are in the cutoff state, and the OFF_H output is low.

[0077] In this embodiment of the invention, the power supply to the primary bus can be quickly cut off during both instantaneous and short-term bus dips and recovery, preventing excessive surge current on the primary bus during recovery from affecting the overall satellite power supply and distribution safety and reliability. Furthermore, this circuit offers enhanced safety, featuring a fuse protection circuit at the input. If a short circuit occurs in the protection circuit, the fuse can quickly blow the protection bus. Primary and secondary signals are isolated using an optocoupler scheme to control the magnetic latching relay to turn off, thereby cutting off the primary bus power supply. Failure of any component in the undervoltage protection circuit will not affect the primary bus or the individual unit's functional performance. Moreover, this circuit offers higher reliability. The weak points in the undervoltage protection circuit employ redundant component design. All components in this circuit consume no power over long periods, and the output terminal features a differentiating circuit OFF_H to prevent constant high voltage.

[0078] It should be noted that, in this document, relational terms such as first, second, third, and fourth are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0079] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A high-reliability, high-sensitivity bus undervoltage protection circuit for satellites, characterized in that, include: The reference source circuit, drive pulse generation circuit, drive pulse isolation circuit, drive pulse self-locking circuit, and drive pulse differentiating amplifier circuit are connected in series in sequence. The reference source circuit provides a reference voltage for the drive pulse generating circuit based on the output voltage of the primary bus. The drive pulse generating circuit compares the first reference voltage determined using the reference voltage with the primary bus voltage telemetry, and outputs a drive pulse signal based on the comparison result. The drive pulse isolation circuit uses an optocoupler to convert the drive pulse signal from a primary signal to a secondary signal, thereby achieving isolation between the primary and secondary signals. The drive pulse self-locking circuit is used to detect the input signal to determine whether to perform self-locking; The drive pulse differential amplifier circuit includes a charging / discharging module and a switching module connected in series; the switching module is connected to the powered product via a magnetic latching relay. When the primary bus is normal, the switch module outputs a low level, and the magnetic latching relay is in a normally closed state, enabling the primary bus to supply power to the powered products. When the primary bus drops, the drive pulse generating circuit outputs a high level, the drive pulse self-locking circuit enters a self-locking state and charges the charging and discharging module, causing the switch module output to a high level, and the magnetic latching relay switches from an open state to a normally closed state, thus de-energizing the primary bus from the powered products. When the charging and discharging module completes charging and is in an open-circuit state, the switch module outputs a low level.

2. The high-reliability, high-sensitivity bus undervoltage protection circuit for satellites according to claim 1, characterized in that, The driving pulse generation circuit includes: a sampling resistor, a hysteresis comparator, a first current-limiting resistor, a first Zener diode, and a first transistor; The sampling resistor samples the output voltage of the primary bus to obtain a voltage telemetry signal, which is then output to the non-inverting input of the hysteresis comparator. The first reference voltage is input to the inverting input of the hysteresis comparator using the first current-limiting resistor and the first Zener diode connected in series. The hysteresis comparator is inverted through the first transistor to output a drive pulse signal through the collector of the first transistor. When the primary bus is normal, the output of the hysteresis comparator is high, the first transistor is in the cut-off state, and the optocoupler does not output an electrical signal. When the busbar drops, the output of the hysteresis comparator goes low, the first transistor is in the conducting state, and the optocoupler outputs an electrical signal.

3. The high-reliability, high-sensitivity bus undervoltage protection circuit for satellites according to claim 2, characterized in that, The driving pulse self-locking circuit includes: a self-locking comparator, a second current-limiting resistor, a second Zener diode, and several series resistors; the driving pulse self-locking circuit is also connected to an external power supply voltage; The external power supply voltage is used to obtain a second reference voltage from the external power supply voltage through the second current-limiting resistor and the second Zener diode connected in series, and then input to the non-inverting input terminal of the second comparator. The external power supply voltage is connected to the inverting input of the second comparator through several series resistors; wherein the optocoupler is connected in parallel with the series circuit formed by the series resistors. When the optocoupler does not output an electrical signal, the voltage value at the inverting input terminal of the self-locking comparator is higher than the voltage value at the non-inverting input terminal, and the output of the self-locking comparator is low. When the optocoupler outputs an electrical signal, the voltage value at the inverting input terminal of the self-locking comparator is lower than the voltage value at the non-inverting input terminal, and the output of the self-locking comparator is high.

4. The high-reliability, high-sensitivity bus undervoltage protection circuit for satellites according to claim 3, characterized in that, The driving pulse differentiating amplifier circuit includes: a DC blocking capacitor, a first transistor circuit, and a second transistor circuit connected in series. When the output of the self-locking comparator is low, the transistors in both transistor circuits are in the off state, the output of the drive pulse differentiating amplifier circuit is low, and the magnetic latching relay does not operate. When the output of the self-locking comparator is high, the DC blocking capacitor is charged, both transistors in the two transistor circuits are in the conducting state, the output of the driving pulse differentiating amplifier circuit is high, and the magnetic latching relay is turned off, thus disconnecting the primary bus power supply. When the DC blocking capacitor is fully charged, it is in the open circuit state, the transistors in the two transistor circuits switch to the cutoff state, and the output of the driving pulse differentiating amplifier circuit is low.

5. The high-reliability, high-sensitivity bus undervoltage protection circuit for satellites according to any one of claims 1-4, characterized in that, It also includes an overcurrent protection circuit connected in series between the primary bus and the reference source circuit.

6. The high-reliability, high-sensitivity bus undervoltage protection circuit for satellites according to claim 5, characterized in that, The overcurrent protection circuit includes several fuses; the fuses are connected in balanced parallel or unbalanced parallel.

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