Low-cost optical module adjusting and testing device

Abstract

The invention provides a low-cost optical module adjusting and testing device, which belongs to the technical field of digital optical fiber transmission and comprises a power supply module, an MCU, an oDSP module, an EEPROM, a first high-speed electrical interface module, a second high-speed electrical interface module, a serial port to USB module and an optional loopback assembly. According to the device, through cooperation of all modules, a large number of high-price special instruments in traditional testing are omitted; connection and operation processes are simplified, multi-station synchronous testing and full-process automation are supported, and the requirements for performance testing and reliability verification in research, development and production of the optical module are efficiently met.

Description

Technical Field

[0001] This invention relates to the field of optical communication equipment testing technology, and in particular to a low-cost optical module debugging and testing device. Background Technology

[0002] In the research and development and production of optical modules, performance testing of high-speed optical modules is a core step, requiring specialized and expensive testing equipment to ensure accuracy. Traditional optical module testing equipment suffers from the following key problems: High hardware costs: High-speed optical module testing requires a large number of expensive equipment, including but not limited to: optical coupling equipment, dispensing machines, plasma cleaning machines and other processing equipment, as well as optical module test boards, adjustable optical attenuators, high-speed signal generators, and multiple high-speed RF cables. For example, 800G optical module testing requires 16 high-speed electrical interface RF cables, bit error rate detectors, multi-channel optical switch switching equipment and other testing instruments. The overall equipment investment significantly increases the cost of optical module R&D and production. Moreover, existing testing devices all rely on external independent oDSP test instruments to generate test signals, without utilizing the oDSP chip integrated into the optical module itself, resulting in equipment redundancy and high costs.

[0003] High connection complexity and high operating threshold: Traditional test equipment requires the establishment of a large number of optical and electrical connections, such as optical port MPOCable connections and multiple sets of high-speed RF cable connections. Not only are there many connections and faults such as poor contact prone to occur, but it also places extremely high demands on the professional operation capabilities of test personnel, increasing the debugging time and troubleshooting difficulty during the test process.

[0004] Poor portability and limited testing scenarios: Traditional testing devices consist of multiple independent instruments and complex wiring, making them large and heavy, immobile, and only suitable for testing in fixed laboratory settings.

[0005] Furthermore, with the advancement of 6G technology research and development, 6G optical modules require higher bandwidth, more complex architecture, and more stringent reliability requirements. The high cost and complexity of traditional testing equipment will be further amplified in the mass R&D and production testing of 6G optical modules. 6G optical module testing needs to cover a wider range of signal frequency bands and more testing dimensions. Traditional equipment requires additional expensive dedicated instruments, such as terahertz band signal analyzers, to meet these requirements, further increasing testing costs. Moreover, the complex wiring and fixed scene characteristics cannot adapt to the reliability testing requirements of 6G optical modules in various environments such as high temperature, low temperature, and temperature cycling. At the same time, the large-scale deployment of WiFi 6 technology has led to a surge in the number of indoor and outdoor access points (APs). The supporting optical modules need to achieve low-cost, mass production. The high equipment investment and complex operation process of traditional testing equipment create a significant contradiction with the low-cost, large-scale mass production requirements of WiFi 6 optical modules. In addition, the inefficient mode of a single instrument testing only 1-2 modules at a time cannot meet the massive optical module testing needs brought about by WiFi 6 deployment.

[0006] To address the shortcomings of traditional testing devices, this invention proposes a low-cost optical module tuning and testing device. Summary of the Invention

[0007] This invention provides a low-cost optical module tuning and testing device to solve the aforementioned technical problems.

[0008] This invention provides a low-cost optical module debugging and testing device, comprising: a power module, an MCU, an oDSP module, an EEPROM, a first high-speed electrical interface module, a second high-speed electrical interface module, a serial-to-USB module, and an optional loopback component; The power module input is connected to a +12V power supply, and the output supplies power to the MCU, oDSP module, first high-speed electrical interface module, second high-speed electrical interface module, and serial-to-USB module; The MCU is connected to the oDSP module via the first I2C bus, and is used to send control commands to the oDSP module and receive test data fed back by the oDSP module; The MCU is connected to the first high-speed electrical interface module via the second I2C bus and to the second high-speed electrical interface module via the third I2C bus, and is used to send configuration instructions to the first high-speed electrical interface module and the second high-speed electrical interface module or read their status. The serial port pin of the MCU is connected to the serial-to-USB module for serial data transmission with an external host computer. The oDSP module is connected to the EEPROM via an SPI bus and is used to read configuration parameters from the EEPROM; The oDSP module is also bidirectionally connected to the first high-speed electrical interface module and the second high-speed electrical interface module via a high-speed electrical signal line, so as to generate and output test electrical signals to the optical module under test, and receive and analyze electrical signals returned from the optical module under test. The first high-speed electrical interface module and the second high-speed electrical interface module are used to physically interface with the high-speed electrical interface of the optical module under test, and to transmit test electrical signals and return electrical signals. The input of the serial port to USB module is connected to the serial port pin of the MCU, and the output is connected to the host computer through the USB interface. It is used to convert the serial port signal of the MCU into a USB signal to realize bidirectional communication between the host computer and the MCU. The host computer is used to send test commands to the test host, configure test parameters, display test data in real time, and generate test reports. The optional loopback component is used to construct the optical port or electrical port loopback path of the optical module under test in order to achieve self-loop testing.

[0009] Preferably, the oDSP module establishes communication with the oDSP chip of the optical module under test through SPI, I2C or high-speed serial interface, generates at least one PRBS code pattern, and configures the signal flow direction as normal service flow direction or loopback direction.

[0010] Preferably, the interface types of the first high-speed electrical interface module and the second high-speed electrical interface module include, but are not limited to, OSFP, QSFP-DD, QSFP112, SFP56, and CFP2.

[0011] Preferably, the host computer is equipped with debugging and control software, which includes a parameter configuration module, a real-time monitoring module, a batch control module, and a report generation module. The parameter configuration module supports selecting optical module packaging type, PRBS code type, test duration, signal flow direction, and environmental test parameter thresholds. The real-time monitoring module is used to dynamically display BER value, optical power, electrical signal amplitude and bit error count, and triggers an audible and visual alarm when the indicators exceed the threshold. The batch control module supports simultaneous connection to multiple testing hosts to achieve synchronous testing of multiple optical modules; The report generation module automatically records test data and generates standardized test reports in Excel or PDF format.

[0012] Preferably, the optional loopback assembly includes an MTP / MPO type fiber optic patch cord and a high-speed differential signal line, wherein the insertion loss of the fiber optic patch cord is ≤0.5dB and the operating wavelength covers 1310nm~1550nm.

[0013] Preferably, the MCU is an STM32 series microcontroller or an FPGA chip, used to coordinate the operation of the oDSP module with the first high-speed electrical interface module and the second high-speed electrical interface module, so as to realize the synchronous processing of host computer instruction reception and test data feedback.

[0014] Preferred options also include: A temperature detection unit corresponding to each high-speed electrical interface module is used to perform several synchronous periodic temperature tests on the first high-speed electrical interface module and the second high-speed electrical interface module to obtain a hyperbola for each test. The hyperbola includes a first curve for the first high-speed electrical interface module and a second curve for the second high-speed electrical interface module. The filtering module is used to filter the first temperature anomaly segment in the first curve and the second temperature anomaly segment in the second curve under the same periodic test. The ternary module is used to determine the first proportion of the abnormal segment under each curve, and at the same time, determine the abnormal start point and abnormal end point of each curve, construct a ternary array based on each hyperbola, and obtain the first reference variance based on each dimension. The ternary array includes: proportion difference, start point difference and end point difference, and the first reference variance includes the positive and negative signs of the cumulative sum of all differences under the corresponding dimension. The variance determination module is used to construct a first matrix based on all first curves and a second matrix based on all second curves, and to calculate the corresponding eigenvectors and element variances respectively. The element-wise variances based on the first curve and the element-wise variances based on the second curve in the same dimension are subtracted to obtain the second reference variance based on each dimension. The integrated vector analysis module is used to combine the eigenvectors of the first matrix and the second matrix with the first vector based on the first reference variance and the second vector based on the second reference variance, and input them into the first vector analysis model to obtain the temperature coordination factor group of the first high-speed electrical interface module and the second high-speed electrical interface module. Match a reference offset value consistent with the temperature co-factor group from the factor-bias lookup table; A separate vector analysis module is used to input the distribution vector of the hyperbolic temperature anomaly segment under the same periodicity into the second vector analysis model to obtain the first temperature factor based on the first high-speed electrical interface module and the second temperature factor based on the second high-speed electrical interface module. The comparison module is used to match a first offset value based on the first temperature factor and a second offset value based on the second temperature factor from the factor-deviation comparison table, respectively. The MCU is used to send a first control command carrying temperature compensation parameters to the oDSP module based on the reference offset value when the first high-speed electrical interface module and the second high-speed electrical interface module first show abnormal temperature points, which are obtained in real time by the temperature detection unit.

[0015] Preferably, the MCU is further configured to continue measuring the measured temperature after the first occurrence of an abnormal temperature point based on the current cycle, and progressively compare it with the distribution vector under each periodic temperature test to obtain a first estimated value and a second estimated value of the measured temperature based on a first offset value and a second offset value, and send a second control command carrying temperature compensation parameters to the oDSP module, wherein the progressive comparison is based on the measurement process of the current cycle, and the comparison is increased by a preset n time points until the measurement ends; After the measurement of the current cycle is completed, the latest distribution vector is used to obtain two new offset values ​​and saved. At the same time, a third control command carrying temperature compensation parameters is sent to the oDSP module based on the two new offset values, and the reference offset value is updated.

[0016] Preferred options also include: The acquisition module is used to acquire the temperature measurement data based on each current moment within the current period, which is considered as the first case; The loopback matching module is used to match a fourth control command carrying loopback compensation parameters from a preset temperature-loop link characteristic calibration table, which matches the dual temperature array of the first case and the current time, and dynamically adjusts the relevant parameters of the oDSP module. The relevant parameters include: the decision threshold of the return electrical signal, the signal compensation gain, or the clock recovery phase.

[0017] Compared with the prior art, the beneficial effects of this application are as follows: This device leverages the collaboration of various modules, reuses the optical module's own oDSP chip and combines it with the internal control and processing module, eliminating the need for a large number of expensive dedicated instruments in traditional testing and significantly reducing hardware costs; it simplifies connection and operation processes, supports simultaneous testing of multiple units and full-process automation, and can also adapt to optical modules with different packages, efficiently meeting the performance testing and reliability verification needs in the research and development and production of optical modules. Addressing the needs of 6G optical module R&D, this device offers precise adaptation: its integrated low insertion loss loopback component supports operating wavelengths from 1310nm to 1550nm, expanding its adaptability to potential 6G optical transmission frequency bands. Combined with temperature detection and dynamic compensation functions, it meets the stringent reliability requirements of 6G optical modules across a wide temperature range. Simultaneously, its multi-unit synchronous testing and automated process design can match the high-frequency testing needs of multiple batches of 6G optical modules during R&D, eliminating the need for additional ultra-wide bandwidth testing instruments to complete core performance testing, thus helping to reduce the R&D cost of 6G optical modules. For the large-scale production of WiFi 6 optical modules, the device's low-cost advantages and batch testing capabilities are particularly suitable: its design eliminates the need for expensive external oDSP instruments, reducing the hardware cost of single-module testing, aligning with the core demand for low-cost mass production of WiFi 6 optical modules. Supporting various common packages such as OSFP and QSFP-DD, it covers mainstream optical module types in WiFi 6 access networks, and can simultaneously test multiple modules in a single batch, improving the mass production testing efficiency of WiFi 6 optical modules by 2-3 times, effectively supporting the rapid deployment needs of WiFi 6 networks.

[0018] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0019] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a structural diagram of a low-cost optical module tuning and testing device according to an embodiment of the present invention; Figure 2 This is a detailed connection diagram of a low-cost optical module tuning and testing device according to an embodiment of the present invention. Detailed Implementation

[0021] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0022] This invention provides a low-cost optical module tuning and testing device, such as... Figure 1 As shown, it includes: a power module, an MCU, an oDSP module, an EEPROM, a first high-speed electrical interface module, a second high-speed electrical interface module, a serial-to-USB module, and an optional loopback component; The power module input is connected to a +12V power supply, and the output supplies power to the MCU, oDSP module, first high-speed electrical interface module, second high-speed electrical interface module, and serial-to-USB module; The MCU is connected to the oDSP module via the first I2C bus, and is used to send control commands to the oDSP module and receive test data fed back by the oDSP module; The MCU is connected to the first high-speed electrical interface module via the second I2C bus and to the second high-speed electrical interface module via the third I2C bus, and is used to send configuration instructions to the first high-speed electrical interface module and the second high-speed electrical interface module or read their status. The serial port pin of the MCU is connected to the serial-to-USB module for serial data transmission with an external host computer. The oDSP module is connected to the EEPROM via an SPI bus and is used to read configuration parameters from the EEPROM; The oDSP module is also bidirectionally connected to the first high-speed electrical interface module and the second high-speed electrical interface module via a high-speed electrical signal line, so as to generate and output test electrical signals to the optical module under test, and receive and analyze electrical signals returned from the optical module under test. The first high-speed electrical interface module and the second high-speed electrical interface module are used to physically interface with the high-speed electrical interface of the optical module under test, and to transmit test electrical signals and return electrical signals. The input of the serial port to USB module is connected to the serial port pin of the MCU, and the output is connected to the host computer through the USB interface. It is used to convert the serial port signal of the MCU into a USB signal to realize bidirectional communication between the host computer and the MCU. The host computer is used to send test commands to the test host, configure test parameters, display test data in real time, and generate test reports. The optional loopback component is used to construct the optical port or electrical port loopback path of the optical module under test in order to achieve self-loop testing.

[0023] Preferably, the oDSP module establishes communication with the oDSP chip of the optical module under test through SPI, I2C or high-speed serial interface, generates at least one PRBS code pattern, and configures the signal flow direction as normal service flow direction or loopback direction.

[0024] Preferably, the interface types of the first high-speed electrical interface module and the second high-speed electrical interface module include, but are not limited to, OSFP, QSFP-DD, QSFP112, SFP56, and CFP2.

[0025] Preferably, the host computer is equipped with debugging and control software, which includes a parameter configuration module, a real-time monitoring module, a batch control module, and a report generation module. The parameter configuration module supports selecting optical module packaging type, PRBS code type, test duration, signal flow direction, and environmental test parameter thresholds. The real-time monitoring module is used to dynamically display BER value, optical power, electrical signal amplitude and bit error count, and triggers an audible and visual alarm when the indicators exceed the threshold. The batch control module supports simultaneous connection to multiple testing hosts to achieve synchronous testing of multiple optical modules; The report generation module automatically records test data and generates standardized test reports in Excel or PDF format.

[0026] Preferably, the optional loopback assembly includes an MTP / MPO type fiber optic patch cord and a high-speed differential signal line, wherein the insertion loss of the fiber optic patch cord is ≤0.5dB and the operating wavelength covers 1310nm~1550nm.

[0027] Preferably, the MCU is an STM32 series microcontroller or an FPGA chip, used to coordinate the operation of the oDSP module with the first high-speed electrical interface module and the second high-speed electrical interface module, so as to realize the synchronous processing of host computer instruction reception and test data feedback.

[0028] In this embodiment, the test host adopts a modular and miniaturized design, with a volume ≤20cm×15cm×8cm and a weight ≤1.5kg. It supports 12V DC power supply and can be deployed in reliability testing environments such as high temperature chambers, low temperature chambers, and temperature cycling test chambers.

[0029] In this embodiment, such as Figure 2 As shown, its specific working principle is as follows: The optical module's integrated oDSP module generates and analyzes test signals. Combined with centralized control of the MCU and human-machine interaction with the host computer, it eliminates the need for expensive external instruments in traditional testing, such as high-speed signal generators and bit error rate testers, thus completing the performance debugging of the optical module. The workflow is divided into the following stages: Power supply and initialization phase: The power module converts the external +12V power supply into the operating voltage required by each internal module, powering on the device. The oDSP reads configuration parameters from the EEPROM via the SPI bus, such as the default PRBS code pattern and signal gain, to complete its own initialization; the MCU also completes the initialization of peripherals such as the serial port and I2C bus.

[0030] In the host computer command issuance phase: the host computer sends test commands through the debugging software, such as selecting the PRBS31Q code pattern, starting the loopback test, and setting the test duration to 1 hour. The commands are transmitted via the USB interface to the serial-to-USB module, converted into serial signals, and then transmitted to the MCU through the RxD pin.

[0031] MCU Control and Signal Configuration Stage: After parsing the host computer instructions, the MCU sends control commands to the oDSP via the I2C1 bus, configuring the oDSP to generate the specified PRBS test pattern, such as PRBS31Q, and setting the signal flow direction, such as loopback mode: the electrical signal output from Tx passes through the optical module and loopback fiber, and then returns from Rx. Simultaneously, the MCU sends configuration commands to the left and right high-speed electrical interface modules via the I2C0 and I2C2 buses to ensure that the electrical signal transmission parameters of the electrical interface and the optical module match, such as signal amplitude and timing.

[0032] Test signal generation and transmission stage: The oDSP generates a PRBS test electrical signal, which is transmitted to the high-speed electrical interface module via a high-speed electrical signal line, and then passed to the E / O unit of the optical module under test. The E / O unit of the optical module converts the electrical signal into an optical signal and outputs it from the Tx optical port; if it is a loopback test, the optical signal output from Tx is connected to the Rx optical port via an external loopback fiber, such as an MPO patch cord. The O / E unit of the optical module converts the optical signal received from the Rx optical port into an electrical signal, and then transmits it back to the oDSP via the high-speed electrical interface module.

[0033] Test data acquisition and feedback phase: The oDSP performs bit error detection on the received electrical signal (i.e., the loopback signal) and calculates core test indicators such as BER and bit error count. The oDSP feeds back test data, such as BER value, optical power feedback inside the optical module, and electrical signal amplitude, to the MCU via the I2C1 bus.

[0034] Data upload and host computer display stage: The MCU sends the collected test data to the serial-to-USB module through the TxD pin, which converts it into a USB signal and then uploads it to the host computer.

[0035] The host computer's testing software displays data such as BER value, optical power, and electrical signal parameters in real time. If the indicators exceed the limits, an alarm is triggered. After the test is completed, the software automatically generates a report containing all test results.

[0036] Through the above process, the device can complete the key performance testing of the optical module, such as bit error rate and optical / electrical signal integrity, without relying on external high-cost testing instruments. It can achieve the goal of low-cost and high-efficiency optical module testing by only coordinating the internal MCU, oDSP and optical module.

[0037] In this embodiment, an external 12V switching power adapter is connected. The device internally converts 12V to 5V through a DC-DC step-down chip, and then converts 5V to 3.3V through a linear voltage regulator chip AMS1117-3.3. This provides stable 5V or 3.3V voltages for the MCU, oDSP module, high-speed electrical interface module, serial-to-USB module, etc., ensuring stable power supply for each module.

[0038] In this embodiment, the MCU uses an STM32F103C8T6 microcontroller, which communicates with other modules via an I2C bus (including the SDA data line and the SCL clock line). The first I2C bus sends control commands to the oDSP module to generate PRBS31 codes, and simultaneously receives test data such as the bit error rate (BER) of 5e-13 from the oDSP. The second and third I2C buses send configuration commands to the first and second high-speed electrical interface modules to set the signal transmission rate to 100Gbps, or read status information indicating that the electrical interface connection is normal. In addition, the MCU's USART1 serial port pins (TXD, RXD) are connected to a serial-to-USB module to send test data such as the optical module's optical power of -2.5dBm to the host computer, and simultaneously receive commands from the host computer to start the test.

[0039] The oDSP module is dedicated to optical signal digital processing. It can generate test digital signals and analyze received digital signals to obtain optical module performance parameters. Internally, it integrates digital signal processing circuitry and connects to an EEPROM such as the AT24C256 via an SPI bus (including MOSI, MISO, and SCK lines) to read pre-stored configurations such as PRBS31 code generation parameters and a signal amplitude calibration value of 0.9V. It also connects bidirectionally to a high-speed electrical interface module via a 50-ohm high-speed differential signal line to generate a PRBS31 test electrical signal and output it to the optical module under test (converting the optical module's E / O unit to an optical signal). Furthermore, it receives the electrical signal returned from the optical module's O / E unit and performs bit error rate (BER) analysis to obtain the BER value. It can also communicate with the optical module's own oDSP chip via an I2C interface, configuring the signal flow to loop back, allowing the optical module's transmitted signals to loop directly back to the receiver.

[0040] In this embodiment, the EEPROM uses an AT24C256 chip, which is connected to the oDSP module via the SPI bus to store data such as clock parameters and signal gain compensation values ​​for the PRBS31 code generated by the oDSP. When the oDSP module starts up, it reads these data via SPI to ensure that the working parameters are consistent each time.

[0041] In this embodiment, when the interface types of the first high-speed electrical interface module and the second high-speed electrical interface module are QSFP-DD, the physical structure of the module matches the electrical interface of the QSFP-DD optical module. It contains a signal equalization circuit to compensate for high-speed signal transmission loss. It conditions the electrical signal from the oDSP and sends it to the optical module, and at the same time conditions the electrical signal returned by the optical module and sends it to the oDSP for analysis. If testing an OSFP packaged optical module, it can be replaced with an OSFP type high-speed electrical interface module.

[0042] In this embodiment, the serial-to-USB module uses the CH340 chip. The input is connected to the TXD and RXD pins of the MCU. It receives serial data such as BER: 1e-12 and optical power: -3dB sent by the MCU, converts it into a USB signal, and transmits it to the host computer through the USB interface. At the same time, it converts the USB command configured by the host computer with PRBS code type SSPRQ into a serial signal and transmits it to the MCU.

[0043] In this embodiment, a Windows laptop computer is used as the host computer, and the commissioning and control software is installed. The parameter configuration module allows selection of package type: QSFP112, PRBS code type: SSPRQ, test duration: 1 hour, BER threshold: 1e-12; the real-time monitoring module dynamically displays BER: 8e-13, optical transmission power: -2dBm, and electrical signal amplitude: 1.0V. If BER > 1e-12, the computer speaker alarms and a pop-up window appears on the interface; the batch control module can connect to 5 commissioning hosts simultaneously via USB to start the test synchronously; the report generation module generates a PDF report after the test, including the test time, optical module model XXX, and whether each indicator is qualified.

[0044] In this embodiment, the optical port loopback uses an MPO-12 type fiber optic patch cord to connect the TX optical port and the RX optical port of the optical module, allowing the optical signal to loop back; the electrical port loopback uses a 100-ohm impedance high-speed differential signal line to connect the electrical input and electrical output interfaces of the optical module, realizing the electrical signal loopback.

[0045] The beneficial effects of the above technical solution are: the device, by leveraging the collaboration of various modules, reuses the optical module's own oDSP chip and combines it with the internal control and processing module, eliminating the need for a large number of expensive dedicated instruments in traditional testing, thus significantly reducing hardware costs; it simplifies the connection and operation process, supports simultaneous testing of multiple units and full-process automation, and can also adapt to optical modules with different packages, efficiently meeting the performance testing and reliability verification needs in the research and development and production of optical modules.

[0046] This invention provides a low-cost optical module tuning and testing device, which further includes: A temperature detection unit corresponding to each high-speed electrical interface module is used to perform several synchronous periodic temperature tests on the first high-speed electrical interface module and the second high-speed electrical interface module to obtain a hyperbola for each test. The hyperbola includes a first curve for the first high-speed electrical interface module and a second curve for the second high-speed electrical interface module. The filtering module is used to filter the first temperature anomaly segment in the first curve and the second temperature anomaly segment in the second curve under the same periodic test. The ternary module is used to determine the first proportion of the abnormal segment under each curve, and at the same time, determine the abnormal start point and abnormal end point of each curve, construct a ternary array based on each hyperbola, and obtain the first reference variance based on each dimension. The ternary array includes: proportion difference, start point difference and end point difference, and the first reference variance includes the positive and negative signs of the cumulative sum of all differences under the corresponding dimension. The variance determination module is used to construct a first matrix based on all first curves and a second matrix based on all second curves, and to calculate the corresponding eigenvectors and element variances respectively. The element-wise variances based on the first curve and the element-wise variances based on the second curve in the same dimension are subtracted to obtain the second reference variance based on each dimension. The integrated vector analysis module is used to combine the eigenvectors of the first matrix and the second matrix with the first vector based on the first reference variance and the second vector based on the second reference variance, and input them into the first vector analysis model to obtain the temperature coordination factor group of the first high-speed electrical interface module and the second high-speed electrical interface module. Match a reference offset value consistent with the temperature co-factor group from the factor-bias lookup table; A separate vector analysis module is used to input the distribution vector of the hyperbolic temperature anomaly segment under the same periodicity into the second vector analysis model to obtain the first temperature factor based on the first high-speed electrical interface module and the second temperature factor based on the second high-speed electrical interface module. The comparison module is used to match a first offset value based on the first temperature factor and a second offset value based on the second temperature factor from the factor-deviation comparison table, respectively. The MCU is used to send a first control command carrying temperature compensation parameters to the oDSP module based on the reference offset value when the first high-speed electrical interface module and the second high-speed electrical interface module first show abnormal temperature points, which are obtained in real time by the temperature detection unit.

[0047] A temperature detection unit corresponds one-to-one with each high-speed electrical interface module, used to collect the temperature of the high-speed electrical interface module in real time, realizing synchronous periodic temperature testing. Specifically, a DS18B20 digital temperature sensor is used, which is installed on the housing surface of the first and second high-speed electrical interface modules respectively, and connected to the MCU via a single bus. The test cycle is set to 5 minutes, and temperature data is collected at 1-second intervals in each cycle, acquiring 300 temperature sampling points per cycle. This allows for synchronous temperature testing of the first and second high-speed electrical interface modules, generating their respective temperature-time change curves, namely the subsequent first curve and second curve. For example, in a certain 5-minute test cycle, the temperature change curve of the first high-speed electrical interface module is: 0-100 seconds, the temperature rises from 25℃ to 32℃, 100-200 seconds maintains 32℃, and 200-300 seconds drops to 28℃; the temperature change curve of the second high-speed electrical interface module is: 0-120 seconds, the temperature rises from 24℃ to 31℃, 120-180 seconds maintains 31℃, and 180-300 seconds drops to 27℃. These two curves are the hyperbolas under this period.

[0048] The time periods where the temperature exceeds the preset normal range are selected from the hyperbola; these periods are designated as temperature anomaly segments. The first temperature anomaly segment corresponds to the first curve, and the second temperature anomaly segment corresponds to the second curve. The preset normal operating temperature range for the optical module is 20℃-30℃. For the first curve, the temperature is 32℃ from 100-200 seconds, which exceeds the normal range; this period is the first temperature anomaly segment. For the second curve, the temperature is 31℃ from 120-180 seconds, which also exceeds the normal range; this period is the second temperature anomaly segment. The time-temperature data of the curves is traversed to determine whether the temperature at each time point is within the normal range, thus marking the start and end times of the anomaly segments.

[0049] In this embodiment, the first proportion is the proportion of the duration of the temperature anomaly segment to the total test cycle duration, the anomaly start point is the time point at which the temperature anomaly segment begins, and the anomaly end point is the time point at which the temperature anomaly segment ends.

[0050] A ternary array is an array consisting of percentage differences, starting point differences, and ending point differences. The percentage difference is the difference between the first and second percentages in the same period. The starting point difference is the difference between the first abnormal starting point of each curve in the hyperbola in the same period. The ending point difference is the difference between the last abnormal ending point of each curve in the hyperbola in the same period.

[0051] The first reference variance is calculated by performing variance calculations on the proportion difference, starting point difference, and ending point difference in the ternary arrays across multiple test periods. The sign of the cumulative sum of all differences under each dimension is then determined and added to the variance of the corresponding dimension.

[0052] The first matrix is ​​formed by arranging the percentage of abnormal segments, the start point of abnormality, and the end point of abnormality in the first curve of multiple test periods in a row. If there are n1 periods, it is an n1×3 matrix.

[0053] The principle for obtaining the second matrix is ​​similar to that of the first matrix, and will not be repeated here.

[0054] Eigenvectors are vectors obtained after performing eigenvalue decomposition on a matrix, reflecting the main direction of change in the matrix data. For example, the first matrix decomposition yields [v1,v2,v3], and the second matrix decomposition yields [u1,u2,u3].

[0055] Element variance is the variance of the data in each dimension of a matrix, used to measure the dispersion of the data in that dimension.

[0056] The second reference variance is the difference between the element variances of the first matrix and the element variances of the second matrix in the same dimension.

[0057] The first vector analysis model is a pre-trained model used to fuse the eigenvectors of the first matrix, the eigenvectors of the second matrix, and the first vector formed by the first reference variance, and the second vector formed by the second reference variance. It outputs a temperature coordination factor set reflecting the coordinated temperature change patterns of the two high-speed electrical interface modules. The model is trained on a neural network using samples from different input combination vectors and the temperature coordination factor set for those input combination vectors. For example, the temperature coordination factor set for input combination vector A includes the degree of coordination in temperature changes between the first and second high-speed electrical interface modules in three dimensions: proportion difference, starting point difference, and ending point difference. The training samples exceed 1000. The first vector analysis model is a 3-layer fully connected neural network: 12 neurons in the input layer (3D of the first matrix eigenvector + 3D of the second matrix eigenvector + 3D of the first vector + 3D of the second vector), 8 neurons in the hidden layer (with ReLU activation function), and 3 neurons in the output layer (corresponding to the temperature coordination factor set). The training data consists of 1000 samples (each sample containing the aforementioned 12-dimensional input and 3-dimensional output), generated by collecting temperature data in an environment of -40℃ to 85℃.

[0058] In this embodiment, the factor-deviation lookup table is a pre-stored table of correspondence between temperature coordinating factor group and reference offset value, and temperature factor and reference offset value. It is calibrated through a large amount of test data. For example, in the lookup table, the reference offset value corresponding to the temperature coordinating factor group (0.8, 0.2, 0.5) is: temperature compensation coefficient + 0.3.

[0059] The second vector analysis model is a pre-trained neural network model used to analyze distribution vectors and output the temperature factor of a single high-speed electrical interface module. It has more than 1,000 training samples. Its input is the distribution vector and its output is the temperature factor of the corresponding high-speed electrical interface module.

[0060] The first temperature factor is a factor that reflects the temperature characteristics of the first high-speed electrical interface module itself. For example, the model outputs a first temperature factor of 0.6.

[0061] The second temperature factor is a factor that reflects the temperature characteristics of the second high-speed electrical interface module itself. For example, the model outputs a second temperature factor of 0.4.

[0062] In this embodiment, the first offset value is matched with the first temperature factor and is used as a parameter value for temperature compensation of the first high-speed electrical interface module. For example, in the factor-deviation lookup table, the first temperature factor of 0.6 corresponds to the first offset value: electrical signal amplitude compensation +0.2V.

[0063] The principle for obtaining the second offset value is similar to that of the first offset value, and will not be repeated here. For example, the second temperature factor of 0.4 corresponds to the second offset value: electrical signal amplitude compensation +0.1V.

[0064] The first control command is a control command sent by the MCU to the oDSP module, carrying temperature compensation parameters. The temperature compensation parameters are used to adjust the test signal parameters of the oDSP module, such as drive current, signal amplitude, and decision threshold, based on a reference offset value. For example, when the temperature detection unit detects an abnormal temperature of 32°C for the first time in the first high-speed electrical interface module, the MCU generates the first control command based on the reference offset value: temperature compensation coefficient + 0.3 and sends it to the oDSP module to adjust the drive current of the PRBS test signal generated by the oDSP to compensate for the impact of temperature changes on the optical module test.

[0065] The beneficial effects of the above technical solution are as follows: by synchronously collecting the temperature of multiple modules through the temperature detection unit, and combining the multi-dimensional data processing flow of screening, ternary analysis, matrix operation, and vector model, the abnormal temperature characteristics and temperature coordination patterns between modules are accurately extracted; and by dynamically adjusting the oDSP test signal through graded matching temperature compensation parameters, the problem of insufficient accuracy caused by temperature drift in traditional optical module testing is solved, and the consistency of parallel testing of multiple modules is improved through collaborative analysis, which greatly improves the accuracy and efficiency of optical module commissioning.

[0066] This invention provides a low-cost optical module tuning and testing device. The MCU is further configured to continue measuring the measured temperature after the first occurrence of an abnormal temperature point based on the current cycle, and progressively compare it with the distribution vector under each cycle of temperature testing to obtain a first estimated value and a second estimated value of the measured temperature based on a first offset value and a second offset value. The MCU is then sent to the oDSP module with a second control command carrying temperature compensation parameters. The progressive comparison is based on the measurement process of the current cycle, with the comparison increasing by a preset n time points until the measurement ends. After the measurement of the current cycle is completed, the latest distribution vector is obtained by saving two new offset values. At the same time, based on the two new offset values, a third control command carrying temperature compensation parameters is sent to the oDSP module, and the reference offset value is updated.

[0067] In this embodiment, the current period refers to the temperature test cycle of the current preset duration, which is consistent with the duration of the historical periodic test. It is the basic time unit for temperature data acquisition and analysis. For example, if each temperature test cycle is preset to 5 minutes, and the current test is in the 4th 5-minute temperature test, then the 5-minute cycle is the current period. Specifically, the current period is defined by the preset cycle duration of the timer built into the MCU, such as the TIM2 timer of the STM32 series. When the timer interrupt is triggered, the cycle is marked to start, and when the next interrupt is triggered, the cycle is marked to end.

[0068] The first abnormal temperature point is the time point and corresponding temperature value at which the temperature detection unit first collects the temperature of the high-speed electrical interface module exceeding the preset normal range within the current cycle. This is the trigger point for starting subsequent progressive comparison and compensation. For example, if the temperature detection unit collects the temperature of the first high-speed electrical interface module at 31℃ at the 120th second within the current cycle, this exceeds the upper limit, and the 120th second and 31℃ is the first abnormal temperature point.

[0069] The measured temperature status refers to the set of all temperature data collected by the temperature detection unit within the current cycle, from the first occurrence of an abnormal temperature point to the current moment. It includes the timestamp and temperature value corresponding to each data point, reflecting the temperature change trend after the abnormality. For example, if the first occurrence of an abnormal temperature point in the current cycle is at the 120th second and the current moment is at the 180th second, the measured temperature status would be the temperature data corresponding to the 120th second, 121st second, ..., 180th second, such as 31℃ at 120 seconds, 32℃ at 125 seconds, 32℃ at 150 seconds, 31℃ at 180 seconds, etc.

[0070] The distribution vector is a vector constructed based on the core distribution characteristics of the temperature anomaly segment in each historical periodic test, such as the duration of the anomaly segment, the extreme temperature value, and the temperature change amplitude. It is used to compare with the measured temperature of the current period and provide historical reference. Specifically, the MCU or host computer saves the temperature anomaly segment feature data of all historical periodic tests through the Flash storage module. According to a fixed dimension, such as the anomaly duration minus the extreme temperature value and the temperature change amplitude, the feature data of each period is converted into a 3-dimensional vector to form a historical distribution vector library for subsequent comparison and retrieval.

[0071] Progressive comparison involves gradually adding measured temperature data at preset n time points after the first abnormal temperature point in the current cycle. This data is then compared with each distribution vector in the historical distribution vector library for similarity, rather than comparing the entire dataset at once. This allows for dynamic tracking and adjustment. For example, if n=5 and the first abnormal point is 120 seconds: The first comparison is at 125 seconds: using measured data from 120 to 125 seconds, compare it with the historical distribution vector; The second comparison is at 130 seconds: using the measured data from 120 to 130 seconds, compare it with the historical distribution vector; This continues until the current cycle ends.

[0072] Specifically, the MCU presets a comparison interval trigger condition in the program, that is, a comparison is triggered every n newly added temperature data. Each time it is triggered, all measured data from the first abnormal point to the current time are read from the buffer, and its features are extracted, such as the current measured abnormal duration and the current temperature extreme value, to form a temporary vector. Then, the similarity between the temporary vector and each historical distribution vector is calculated by the Euclidean distance algorithm.

[0073] The preset n time points are the number of temperature acquisition time points added each time in the progressive comparison. In the MCU initialization program, the value of n is set by a macro definition, such as #defineCOMPARE_STEP10. This value can be adjusted according to the test accuracy requirements. For example, n=5 when pursuing high accuracy, and n=20 when pursuing efficiency. The MCU counts the number of time points added after the first abnormal point through a counter. When the counter reaches n, the comparison is triggered and the counter is reset.

[0074] The first and second estimated values ​​are calculated based on a progressive comparison between measured temperature data and historical distribution vectors. Combined with the first and second offset values, they represent the compensation amount for the impact of the current periodic abnormal temperature on the test signal. For example: The first offset value is preset to be +0.1V for the test signal amplitude compensation for every 1℃ that the temperature exceeds the normal range; through progressive comparison, it is found that the measured temperature in the current period is 2℃ higher than the average over-temperature amplitude of similar historical distribution vectors, so the first estimated value = 0.1V / ℃ × 2℃ = +0.2V; The second offset value is preset to compensate the test signal decision threshold g1 for every 1℃ that the temperature exceeds the normal range. If the average temperature exceedance of the measured temperature in the current cycle is 1.5℃ higher, then the second estimated value = -g1 / ℃ × 1.5℃ = -1.5g1. Specifically, the estimated value = offset value × temperature exceedance, where the temperature exceedance is calculated by subtracting the upper limit of the normal temperature from the average temperature of the measured temperature. After each progressive comparison, the MCU automatically substitutes the first offset value, the second offset value, and the temperature exceedance to calculate the first and second estimated values, which are then stored in a temporary variable.

[0075] The second control instruction is a control instruction generated by the MCU based on the first and second estimated values, carrying temperature compensation parameters for the first and second high-speed electrical interface modules. It is used to adjust the test signal output of the oDSP module in real time. For example, if the first estimated value is +0.2V and the second estimated value is -1.5g1, the content of the second control instruction is: oDSP module: first module signal amplitude +0.2V, second module decision threshold -1.5g1. Specifically, the MCU organizes the data according to a preset instruction format, such as start bit (0xAA) + first compensation parameter (2 bytes) + second compensation parameter (4 bytes) + check bit (1 byte), and sends the instruction to the oDSP module through the I2C bus. After receiving the instruction, the oDSP module parses the compensation parameters and adjusts the configuration of the internal signal drive circuit and decision circuit.

[0076] The latest distribution vector is calculated by the MCU based on the complete data of the temperature anomaly segment of the entire cycle after the current cycle measurement ends. The vector reflects the temperature anomaly characteristics of the current cycle in the same dimensions as the historical distribution vector, such as the anomaly duration, temperature extreme value, and temperature change range. For example, after the current cycle ends, the statistics show that "the total duration of the anomaly segment is 90 seconds, the temperature extreme value is 33℃, and the temperature change range is 6℃, such as from 27℃ to 33℃". The corresponding latest distribution vector is [90, 33, 6].

[0077] The two new offset values ​​are obtained by matching the latest distribution vector from a preset factor-bias lookup table, similar to the principle used to obtain the first and second offset values.

[0078] The third control instruction is a control instruction generated by the MCU based on two new offset values, carrying the final temperature compensation parameters for the first and second high-speed electrical interface modules. It is used to perform final calibration of the test signal of the oDSP module before the end of the current cycle. The principle of the two new offset values ​​is similar to that of the first and second estimated values, and will not be elaborated here.

[0079] The beneficial effects of the above technical solution are as follows: By using the MCU to progressively compare the current periodic abnormal temperature, issue second and third control commands, and synchronously update the reference offset value, accurate compensation for the impact of temperature anomalies on optical module testing is achieved throughout the entire cycle. This solves the problem that traditional fixed compensation cannot adapt to dynamic changes in abnormal temperatures, and iteratively optimizes the compensation benchmark through historical data, significantly improving the accuracy and stability of optical module testing in complex temperature scenarios. Simultaneously, it reduces manual intervention and improves testing efficiency. This invention provides a low-cost optical module commissioning device, which also includes: The acquisition module is used to acquire the temperature measurement data based on each current moment within the current period, which is considered as the first case; The loopback matching module is used to match a fourth control command carrying loopback compensation parameters from a preset temperature-loop link characteristic calibration table, which matches the dual temperature array of the first case and the current time, and dynamically adjusts the relevant parameters of the oDSP module. The relevant parameters include: the decision threshold of the return electrical signal, the signal compensation gain, or the clock recovery phase.

[0080] The temperature measurements taken before each current moment are the collection of all temperature data collected by the temperature detection unit from the start of the current period to the current temperature acquisition moment. This includes the timestamp (acquisition time) and temperature value corresponding to each data point, reflecting the cumulative temperature change trend within the current period.

[0081] In this embodiment, the preset temperature-loop link characteristic calibration table is a table of correspondence between the first case, dual temperature array, and loopback compensation parameters that has been calibrated in advance through a large number of experiments and stored in the device. The loop link characteristics refer to the transmission characteristics of optional loopback components, such as MTP / MPO type fiber optic patch cords and high-speed differential signal lines, at different temperatures, such as fiber loss and signal attenuation. The table is used to quickly match and adapt the loopback compensation parameters to the current temperature scenario, as shown in Table 1.

[0082] Table 1

[0083] In this embodiment, at the current moment of temperature acquisition, the two-dimensional array composed of the temperature values ​​of the first high-speed electrical interface module and the second high-speed electrical interface module synchronously acquired by the temperature detection unit directly reflects the real-time temperature status of the two high-speed electrical interface modules at the current moment, and is another core input basis for the loopback matching module to look up the calibration table.

[0084] For example, if the current time is 180 seconds, and the temperature of the first high-speed electrical interface module is 31℃ and the temperature of the second high-speed electrical interface module is 30℃, then the current dual temperature array is [31℃, 30℃].

[0085] Loopback compensation parameters are used to compensate for the degradation of transmission characteristics of the optional loopback component (optical / electrical loopback path) due to temperature changes. These parameters must correspond to the adjustable parameters of the oDSP module. The initial draft of the invention explicitly includes three types of parameters: the decision threshold for the return electrical signal, the signal compensation gain, and the clock recovery phase. For example: The decision threshold for the returned electrical signal: refers to the critical value at which the oDSP module judges the 0 and 1 levels of the returned electrical signal, such as 1e-12 (BER decision threshold). Signal compensation gain: refers to the amplitude compensation value of the oDSP module for the returned electrical signal, such as +0.2dB; Clock recovery phase: refers to the phase adjustment value when the oDSP module recovers the clock signal of the transmission signal, such as +0.1π.

[0086] The fourth control command is a control command generated by the loopback matching module that carries loopback compensation parameters. It is used to send parameter adjustment instructions to the oDSP module to realize the dynamic calibration of relevant parameters of the oDSP module. If the matched loopback compensation parameters are decision threshold 1e-12, signal compensation gain +0.2dB, and clock recovery phase +0.1π, then the format of the fourth control command is start bit (0x55) + decision threshold (4 bytes, 1e-12) + signal compensation gain (2 bytes, +0.2dB) + clock recovery phase (2 bytes, +0.1π) + check bit (0xAA).

[0087] The decision threshold for the returned electrical signal is the critical level value or corresponding bit error rate (BER) threshold that the oDSP module uses to determine whether the signal is logic 0 or logic 1 when it receives the returned electrical signal via the loopback link. If the quality of the returned signal is lower than this threshold, it is judged as a bit error, and the threshold needs to be adjusted through compensation parameters to reduce the BER. For example, if the loopback link causes signal attenuation due to increased temperature, the original decision threshold 1e-13 of the oDSP module cannot be adapted and needs to be adjusted to 1e-12 to ensure normal recognition of the returned signal. Specifically, the oDSP module has a built-in decision threshold register, such as address 0x08. The MCU writes a new threshold value to this register through the fourth control instruction, such as the hexadecimal value 0x3F800000 corresponding to 1e-12. The oDSP module automatically makes signal decisions according to the new threshold.

[0088] The signal compensation gain is a compensation value used by the oDSP module to amplify the amplitude of the electrical signal transmitted back via the loopback link. It is used to compensate for signal attenuation caused by temperature changes in the loopback link, such as optical fiber or differential signal line, ensuring that the amplitude of the transmitted signal is within the normal processing range of the oDSP module. For example, if the signal attenuation is 0.2dB at 31℃, the oDSP module needs to adjust the signal compensation gain to +0.2dB to restore the amplitude of the transmitted signal to a normal level, such as 0.9V. Specifically, the oDSP module has a built-in gain control register, such as address 0x09. The MCU writes a gain value to this register through the fourth control instruction, such as the hexadecimal value 0x0002 corresponding to +0.2dB. The operational amplifier inside the oDSP module then performs amplitude compensation on the transmitted signal according to this gain value.

[0089] Clock phase recovery is a parameter used by the oDSP module to adjust the clock phase when recovering the clock signal from the electrical signal transmitted back via the loopback link. It is used to solve the signal-clock phase offset problem caused by temperature changes, ensure that the clock signal is synchronized with the electrical signal, and avoid bit errors caused by phase offset. Specifically, the oDSP module has a built-in phase adjustment register, such as address 0x0A. The MCU writes a phase value to this register through the fourth control instruction, such as the hexadecimal value 0x0001 corresponding to +0.1π. The phase-locked loop (PLL) circuit inside the oDSP module adjusts the clock signal phase according to this phase value.

[0090] The beneficial effects of the above technical solution are as follows: by acquiring and integrating the temperature change data of the current cycle in real time by the acquisition module, and combining the loopback matching module to accurately match the loopback compensation parameters from the preset calibration table, the fourth control command is generated to dynamically adjust the decision threshold, signal compensation gain and clock recovery phase of the oDSP module. This effectively offsets the degradation of transmission characteristics caused by temperature changes in the loopback link, solves the test error problem caused by uncompensated temperature effects in traditional loopback testing, significantly improves the accuracy and stability of optical module loopback testing, and further improves the automation efficiency of optical module commissioning without manual intervention.

[0091] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A low-cost optical module commissioning device, characterized by, include: Power supply module, MCU, oDSP module, EEPROM, first high-speed electrical interface module, second high-speed electrical interface module, serial port to USB module, optional loopback component; The power module input is connected to a +12V power supply, and the output supplies power to the MCU, oDSP module, first high-speed electrical interface module, second high-speed electrical interface module, and serial-to-USB module; The MCU is connected to the oDSP module via the first I2C bus, and is used to send control commands to the oDSP module and receive test data fed back by the oDSP module; The MCU is connected to the first high-speed electrical interface module via the second I2C bus and to the second high-speed electrical interface module via the third I2C bus, and is used to send configuration instructions to the first high-speed electrical interface module and the second high-speed electrical interface module or read their status. The serial port pin of the MCU is connected to the serial-to-USB module for serial data transmission with an external host computer. The oDSP module is connected to the EEPROM via an SPI bus and is used to read configuration parameters from the EEPROM; The oDSP module is also bidirectionally connected to the first high-speed electrical interface module and the second high-speed electrical interface module via a high-speed electrical signal line, so as to generate and output test electrical signals to the optical module under test, and receive and analyze electrical signals returned from the optical module under test. The first high-speed electrical interface module and the second high-speed electrical interface module are used to physically interface with the high-speed electrical interface of the optical module under test, and to transmit test electrical signals and return electrical signals. The input of the serial port to USB module is connected to the serial port pin of the MCU, and the output is connected to the host computer through the USB interface. It is used to convert the serial port signal of the MCU into a USB signal to realize bidirectional communication between the host computer and the MCU. The host computer is used to send test commands to the test host, configure test parameters, display test data in real time, and generate test reports. The optional loopback component is used to construct the optical port or electrical port loopback path of the optical module under test in order to achieve self-loop testing.

2. The low-cost optical module adjustment and testing device according to claim 1, characterized in that, The oDSP module establishes communication with the oDSP chip of the optical module under test through SPI, I2C or high-speed serial interface, generates at least one PRBS code pattern, and configures the signal flow direction as normal service flow direction or loopback direction.

3. The low-cost optical module tuning and testing device according to claim 1, characterized in that, The interface types of the first high-speed electrical interface module and the second high-speed electrical interface module include, but are not limited to, OSFP, QSFP-DD, QSFP112, SFP56, and CFP2.

4. The low-cost optical module commissioning device of claim 1, wherein, The host computer is equipped with commissioning and control software, which includes a parameter configuration module, a real-time monitoring module, a batch control module, and a report generation module. The parameter configuration module supports selecting optical module packaging type, PRBS code type, test duration, signal flow direction, and environmental test parameter thresholds. The real-time monitoring module is used to dynamically display BER value, optical power, electrical signal amplitude and bit error count, and triggers an audible and visual alarm when the indicators exceed the threshold. The batch control module supports simultaneous connection to multiple testing hosts to achieve synchronous testing of multiple optical modules; The report generation module automatically records test data and generates standardized test reports in Excel or PDF format.

5. The low-cost optical module commissioning device of claim 1, wherein, The optional loopback assembly includes an MTP / MPO type fiber optic patch cord and a high-speed differential signal line. The fiber optic patch cord has an insertion loss of ≤0.5dB and an operating wavelength covering 1310nm~1550nm.

6. The low-cost optical module commissioning device of claim 1, wherein, The MCU uses an STM32 series microcontroller or FPGA chip to coordinate the operation of the oDSP module with the first high-speed electrical interface module and the second high-speed electrical interface module, so as to realize the synchronous processing of host computer instruction reception and test data feedback.

7. The low-cost optical module commissioning device of claim 1, wherein, Also includes: A temperature detection unit corresponding to each high-speed electrical interface module is used to perform several synchronous periodic temperature tests on the first high-speed electrical interface module and the second high-speed electrical interface module to obtain a hyperbola for each test. The hyperbola includes a first curve for the first high-speed electrical interface module and a second curve for the second high-speed electrical interface module. The filtering module is used to filter the first temperature anomaly segment in the first curve and the second temperature anomaly segment in the second curve under the same periodic test. The ternary module is used to determine the first proportion of the abnormal segment under each curve, and at the same time, determine the abnormal start point and abnormal end point of each curve, construct a ternary array based on each hyperbola, and obtain the first reference variance based on each dimension. The ternary array includes: proportion difference, start point difference and end point difference, and the first reference variance includes the positive and negative signs of the cumulative sum of all differences under the corresponding dimension. The variance determination module is used to construct a first matrix based on all first curves and a second matrix based on all second curves, and to calculate the corresponding eigenvectors and element variances respectively. The element-wise variances based on the first curve and the element-wise variances based on the second curve in the same dimension are subtracted to obtain the second reference variance based on each dimension. The integrated vector analysis module is used to combine the eigenvectors of the first matrix and the second matrix with the first vector based on the first reference variance and the second vector based on the second reference variance, and input them into the first vector analysis model to obtain the temperature coordination factor group of the first high-speed electrical interface module and the second high-speed electrical interface module. Match a reference offset value consistent with the temperature co-factor group from the factor-bias lookup table; A separate vector analysis module is used to input the distribution vector of the hyperbolic temperature anomaly segment under the same periodicity into the second vector analysis model to obtain the first temperature factor based on the first high-speed electrical interface module and the second temperature factor based on the second high-speed electrical interface module. The comparison module is used to match a first offset value based on the first temperature factor and a second offset value based on the second temperature factor from the factor-deviation comparison table, respectively. The MCU is used to send a first control command carrying temperature compensation parameters to the oDSP module based on the reference offset value when the first high-speed electrical interface module and the second high-speed electrical interface module first show abnormal temperature points, which are obtained in real time by the temperature detection unit.

8. The low-cost optical module commissioning device of claim 7, wherein, The MCU is also used to continue measuring the measured temperature after the first abnormal temperature point based on the current cycle, and to perform a progressive comparison with the distribution vector under each cycle temperature test to obtain a first estimated value and a second estimated value of the measured temperature based on a first offset value and a second offset value, and to send a second control command carrying temperature compensation parameters to the oDSP module. The progressive comparison is based on the measurement process of the current cycle, and the comparison is increased by a preset n time points until the measurement ends. After the measurement of the current cycle is completed, the latest distribution vector is used to obtain two new offset values ​​and saved. At the same time, a third control command carrying temperature compensation parameters is sent to the oDSP module based on the two new offset values, and the reference offset value is updated.

9. The low-cost optical module commissioning device of claim 7, wherein, Also includes: The acquisition module is used to acquire the temperature measurement data based on each current moment within the current period, which is considered as the first case; The loopback matching module is used to match a fourth control command carrying loopback compensation parameters from a preset temperature-loop link characteristic calibration table, which matches the dual temperature array of the first case and the current time, and dynamically adjusts the relevant parameters of the oDSP module. The relevant parameters include: the decision threshold of the return electrical signal, the signal compensation gain, or the clock recovery phase.

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