System-level packaging method and packaging structure

Abstract

The invention provides a system-level packaging method and a packaging structure, and the method comprises the steps: forming a preformed packaging middle layer with a flat surface, and correcting the flatness of the packaging middle layer through the arrangement of a middle plastic packaging layer and a first conductive column, the defect of poor coplanarity caused by the fact that the packaging middle layer is subjected to a surface mounting process or the thickness of the middle chip is different is overcome, various defects caused by the poor coplanarity of the chip cannot be generated by the packaging structure, and the reliability, the yield and the performance of the system-level packaging structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to a system-level packaging method and packaging structure. Background Technology

[0002] With the continuous development of integrated circuit technology, electronic products are increasingly moving towards miniaturization, intelligence, high performance, and high reliability. Integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules, and even the entire device, but also constrains the miniaturization, low cost, and reliability of the entire electronic system.

[0003] System-in-Package (SIP) is an advanced integrated circuit packaging technology that integrates multiple chips with different functions (such as processors, memory, and sensors) into a single package to achieve complete system functionality. It employs a 2.5D or 3D stacked structure and utilizes high-density interconnect technologies such as through-silicon vias (TSVs) and micro-bumps to improve performance while reducing size. Compared to traditional single-chip packaging, SIP offers higher integration density, shorter interconnect latency, and lower power consumption, and is widely used in smartphones, the Internet of Things (IoT), automotive electronics, and other fields, serving as a crucial solution for heterogeneous integration and miniaturization.

[0004] The core of SiP (System-in-Package) integrated circuit packaging technology lies in integrating multiple chips of the same or different sizes and functions (such as logic chips, memory, RF modules, sensors, etc.) into a single package structure to form a complete subsystem or system-level solution. However, due to differences in chip thickness and the influence of packaging processes, SiP integrated circuit packaging technology suffers from poor chip coplanarity, which can seriously affect the reliability, yield, and performance of the package.

[0005] Therefore, how to solve the problem of poor chip coplanarity in system-in-package (SiP) has become one of the key research focuses. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a system-level packaging method and packaging structure that can solve the problem of poor chip coplanarity in system-level packaging and improve the reliability and yield of the packaging structure.

[0007] To address the aforementioned problems, this invention provides a system-level packaging method, comprising the following steps: providing a packaging bottom layer; forming one or more packaging intermediate layers stacked along a first direction on the packaging bottom layer, wherein the method for forming the packaging intermediate layers includes: setting a plurality of intermediate chips spaced apart along a second direction, the second direction being perpendicular to the first direction; forming a first conductive pillar on the surface of the intermediate chips; molding to form an intermediate molding layer, the intermediate molding layer covering the intermediate chips and the first conductive pillar; removing a portion of the intermediate molding layer to form a flat surface, wherein the intermediate molding layer exposes the first conductive pillar, the intermediate chips, the first conductive pillar, and the intermediate molding layer serving as the packaging intermediate layer; and forming a packaging top layer on the packaging intermediate layer.

[0008] In one specific embodiment, in the step of providing a packaging underlayer, the packaging underlayer is a substrate, the surface of the substrate having solder pads; the method of forming the packaging intermediate layer on the substrate includes: forming solder on the solder pads of the substrate; a plurality of the intermediate chips are mounted on the substrate and electrically connected to the substrate through the solder.

[0009] In one specific embodiment, the step of forming solder on the pads of the substrate further includes: forming the solder using a screen printing process.

[0010] In one specific embodiment, the step of forming solder on the pads of the substrate further includes: forming the solder using a dispensing process.

[0011] In one specific embodiment, the step of forming the intermediate layer on the packaging substrate further includes: forming a second conductive pillar on the packaging substrate; molding to form an intermediate molding layer, wherein the intermediate molding layer further covers the second conductive pillar; and removing a portion of the intermediate molding layer to form a flat surface, wherein the intermediate molding layer exposes the second conductive pillar.

[0012] In one specific embodiment, the step of setting a plurality of intermediate chips spaced apart along a second direction further includes: the plurality of intermediate chips having the same thickness in the first direction.

[0013] In one specific embodiment, the step of setting a plurality of intermediate chips spaced apart along a second direction further includes: at least some of the intermediate chips having different thicknesses in the first direction.

[0014] In one specific embodiment, the step of forming a first conductive post on the surface of the intermediate chip further includes: forming solder on the surface of the intermediate chip; and mounting the first conductive post on the solder.

[0015] In one specific embodiment, the step of forming solder on the surface of the intermediate chip includes: forming the solder using a screen printing process.

[0016] In one specific embodiment, the step of forming solder on the surface of the intermediate chip includes: forming the solder using a dispensing process.

[0017] In one specific embodiment, the step of removing a portion of the intermediate molding layer to form a flat surface further includes: removing a portion of the intermediate molding layer to expose the first conductive pillar; and continuing to remove a portion of the intermediate molding layer and a portion of the first conductive pillar to form a flat surface.

[0018] In one specific embodiment, the step of removing a portion of the intermediate encapsulation layer to form a flat surface further includes: removing a portion of the intermediate encapsulation layer using a chemical mechanical polishing process.

[0019] In one specific embodiment, when a plurality of package intermediate layers stacked along the first direction are formed on the package bottom layer, a method for forming one package intermediate layer on one package intermediate layer includes: forming solder on the first conductive pillar of the lower package intermediate layer; mounting a plurality of intermediate chips on the first conductive pillar and electrically connecting them to the first conductive pillar of the lower package intermediate layer through the solder.

[0020] In one specific embodiment, the step of forming solder on the first conductive pillar located in the lower intermediate layer of the package includes: forming the solder using a screen printing process.

[0021] In one specific embodiment, the step of forming solder on the first conductive pillar located in the lower intermediate layer of the package includes: forming the solder using a dispensing process.

[0022] In one specific embodiment, when a plurality of package intermediate layers stacked along the first direction are formed on the package bottom layer, a method for forming another package intermediate layer on one package intermediate layer includes: disposing of a plurality of intermediate chips on the lower package intermediate layer, wherein at least one intermediate chip is electrically connected to two intermediate chips of the lower package intermediate layer through a first conductive post.

[0023] In one specific embodiment, the method of forming another encapsulation intermediate layer on one of the encapsulation intermediate layers further includes: disposing a third conductive post on the lower encapsulation intermediate layer, the third conductive post being electrically connected to the lower encapsulation intermediate layer; molding, in the step of forming an intermediate molding layer, the intermediate molding layer further covering the third conductive post; and removing a portion of the intermediate molding layer to form a flat surface, in the step of exposing the third conductive post in the intermediate molding layer.

[0024] In one specific embodiment, the step of forming a top package layer on the intermediate package layer further includes: forming solder on the intermediate package layer; providing at least one top package chip, the top package chip being mounted on the intermediate package layer and electrically connected to the intermediate package layer through the solder; and molding to form a top molding layer, the top molding layer covering the intermediate package layer and encapsulating the top package chip.

[0025] In one specific embodiment, in the step of forming a top layer on the intermediate layer of the package, the top layer of the package is a package cover plate, the surface of the package cover plate has solder pads, and the solder pads are electrically connected to the intermediate layer of the package.

[0026] The present invention also provides a system-level packaging structure, comprising: a packaging bottom layer; one or more packaging intermediate layers stacked along a first direction disposed on the packaging bottom layer, the packaging intermediate layers comprising: a plurality of intermediate chips arranged at intervals along a second direction, the second direction being perpendicular to the first direction; a first conductive post disposed on the intermediate chip; an intermediate molding layer covering the intermediate chip and the first conductive post, wherein the end of the first conductive post facing away from the intermediate chip is not covered by the intermediate molding layer; and a packaging top layer disposed on the packaging intermediate layers.

[0027] In one specific embodiment, the packaging bottom layer is a substrate, the surface of the substrate has solder pads, the surface of the solder pads is provided with solder, and the intermediate chip of the packaging intermediate layer, which is directly disposed on the packaging bottom layer, is mounted on the substrate and electrically connected to the substrate through the solder.

[0028] In one specific embodiment, a second conductive post is further provided on the bottom layer of the package, and the intermediate molding layer of the intermediate package layer directly disposed on the bottom layer of the package further covers the second conductive post, exposing the end of the second conductive post away from the bottom layer of the package.

[0029] In one specific embodiment, the plurality of intermediate chips have the same thickness in the first direction.

[0030] In one specific embodiment, at least some of the intermediate chips have different thicknesses in the first direction.

[0031] In one specific embodiment, the first conductive post is attached to the surface of the intermediate chip by solder.

[0032] In one specific embodiment, when the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom layer of the package, the intermediate chip of the upper intermediate packaging layer is mounted on the first conductive pillar of the lower intermediate packaging layer by solder.

[0033] In one specific embodiment, when the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom layer of the package, the upper intermediate packaging layer includes a plurality of intermediate chips, wherein at least one intermediate chip is electrically connected to two intermediate chips of the lower intermediate packaging layer through a first conductive post.

[0034] In one specific embodiment, when the system-in-package structure includes a plurality of package intermediate layers stacked along a first direction disposed on the bottom layer of the package, a third conductive post is provided in at least one of the package intermediate layers, and the third conductive post is electrically connected to the package intermediate layer below it and the package intermediate layer above it; or the third conductive post is electrically connected to the package intermediate layer below it and the package top layer above it.

[0035] In one specific embodiment, the top layer of the package is a package cover plate, the surface of which has solder pads, and the solder pads are electrically connected to the middle layer of the package.

[0036] In one specific embodiment, the top layer of the package includes: at least one top layer chip, mounted on the intermediate layer of the package and electrically connected to the intermediate layer of the package via solder; and a top layer molding compound, covering the intermediate layer of the package and encapsulating the top layer chip.

[0037] The system-level packaging method and packaging structure provided by this invention do not require uniform molding after stacking multiple chips. Instead, a pre-formed packaging intermediate layer with a flat surface is formed. The packaging intermediate layer corrects the flatness of the packaging intermediate layer through the setting of the intermediate molding layer and the first conductive pillar, which makes up for the defects of poor coplanarity caused by the mounting process or the different thickness of the intermediate chips. This ensures that the packaging structure will not produce various defects caused by poor chip coplanarity, thereby improving the reliability, yield and performance of the system-level packaging structure.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of forming the first chip layer in a packaging method of a system-level packaging structure; Figure 2 This is a schematic diagram of forming a second chip layer in a system-level packaging structure. Figure 3 This is a schematic diagram of forming the first chip layer in another system-level packaging structure. Figure 4 This is a schematic diagram of forming a second chip layer in another system-in-package (SI) structure. Figure 5 This is a schematic diagram of the steps of a system-level encapsulation method provided in a specific embodiment of the present invention; Figure 6 This is a schematic diagram of a packaging layer provided in the first specific embodiment of the system-level packaging method provided by the present invention; Figure 7 This is a schematic diagram of setting an intermediate chip on the bottom layer of the package in the first specific embodiment of the system-level packaging method provided by the present invention; Figure 8 This is a schematic diagram of forming a first conductive pillar on the surface of an intermediate chip located on the bottom layer of the package in a first specific embodiment of the system-level packaging method provided by the present invention. Figure 9 This is a schematic diagram of forming an intermediate molding layer on the bottom layer of the system-level packaging method provided by the present invention in the first specific embodiment. Figure 10 This is a schematic diagram of removing a portion of the intermediate molding compound layer in the first specific embodiment of the system-level packaging method provided by the present invention; Figure 11 This is a schematic diagram of solder forming on the first conductive pillar of the lower intermediate layer of the encapsulation in a first specific embodiment of the system-in-package method provided by the present invention. Figure 12 This is a schematic diagram of multiple intermediate chips mounted on a first conductive post in a first specific embodiment of the system-level packaging method provided by the present invention. Figure 13 This is a schematic diagram of forming a first conductive pillar on an intermediate chip located on the surface of a lower intermediate packaging layer in a first specific embodiment of the system-in-package method provided by the present invention. Figure 14 This is a schematic diagram of an intermediate molding layer formed on the surface of the lower intermediate packaging layer in a first specific embodiment of the system-level packaging method provided by the present invention; Figure 15This is a schematic diagram of the removal of the intermediate molding layer on the surface of the lower intermediate packaging layer in the first specific embodiment of the system-level packaging method provided by the present invention. Figure 16 This is a schematic diagram of forming multiple encapsulation intermediate layers in the first specific embodiment of the system-level encapsulation method provided by the present invention; Figure 17 This is a schematic diagram of the system-level packaging structure formed by the first specific embodiment of the system-level packaging method provided by the present invention; Figure 18 This is a schematic diagram of the system-level packaging structure formed by the second specific embodiment of the system-level packaging method provided by the present invention; Figure 19 This is a schematic diagram of the system-level packaging structure formed by the third specific embodiment of the system-level packaging method provided by the present invention; Figure 20 This is a schematic diagram of the system-level packaging structure formed by the fourth specific embodiment of the system-level packaging method provided by the present invention; Figure 21 This is a schematic diagram of the system-level packaging structure formed by the fifth specific embodiment of the system-level packaging method provided by the present invention.

[0041] Explanation of reference numerals in the attached figures: 100 substrates 110 First Chip Layer 111 chip 112 chip 120 Second Chip Layer 121 chip 300 substrates 310 First Chip Layer 311 chip 312 chip 320 Second Chip Layer 321 chip 400 package bottom layer 401 solder pad 410 package intermediate layer 411 intermediate chip 412 solder 413 First Conductive Post 414 solder 415 intermediate molding layer 420 package intermediate layer 421 intermediate chip 422 solder 423 First Conductive Post 424 solder 425 intermediate molding layer 450 package top layer 451 top-level chip 452 solder 455 Top Layer Molding Coating 550 package top layer 551 solder pad 600 package bottom layer 610 package intermediate layer 611 intermediate chip 613 First Conductive Post 615 intermediate molding layer 616 Second Conductive Post 620 package intermediate layer 621 intermediate chip 700 package bottom layer 710 package intermediate layer 711 intermediate chip 713 First Conductive Post 720 package intermediate layer 721 intermediate chip 723 First Conductive Post 725 intermediate molding layer 726 Third Conductive Post 730 package intermediate layer 731 intermediate chip 820 package intermediate layer 821 intermediate chip 823 First Conductive Post 825 intermediate molding layer 827 intermediate chip. Detailed Implementation

[0042] Existing SIP integrated circuit packaging technology suffers from poor chip coplanarity, which can seriously affect the reliability, yield, and performance of the package.

[0043] For example, a packaging method for a system-in-package (SIP) structure that integrates multiple chips of the same thickness into a single package structure includes the following steps: like Figure 1 As shown, solder is formed on a substrate 100, and multiple chips of the same thickness are mounted to form a first chip layer 110.

[0044] Due to the influence of the mounting process, such as uneven solder printing or coating, or inconsistent solder height caused by uneven temperature during reflow soldering, the surface of some chips in the first chip layer facing away from the substrate may be lower or higher than the surface of other chips facing away from the substrate. For example... Figure 1The surface of chip 111 facing away from the substrate 100 is lower than the surface of other chips (e.g., chip 112) facing away from the substrate, forming a significant height difference H. This causes the flatness of the first chip layer 110 in the horizontal direction (X direction in the figure) to change, resulting in poor chip coplanarity.

[0045] like Figure 2 As shown, solder is formed on the first chip layer 110, and multiple chips of the same thickness are mounted to form the second chip layer 120.

[0046] The chip in the second chip layer 120 is disposed on the surface of the chip in the first chip layer 110. Due to the problem of poor chip coplanarity, the chip in the second chip layer 120 may not make complete contact with the solder, resulting in open circuits or high-resistance connections. Alternatively, local interconnect points may be subjected to additional mechanical stress, which may lead to breakage after long-term use. Or, during reflow soldering, one end of the chip may detach from the solder and lift up, standing upright like a "tombstone," causing electrical connection failure, i.e., the tombstone effect defect. These defects all lead to a decrease in the reliability, yield, and performance of the package structure. As an example, such as Figure 2 As shown, chip 121 is disposed above chip 111 of the first chip layer 110. One end of chip 121 detaches from the solder and lifts up, forming a tombstone effect defect.

[0047] For example, a system-in-package (SIP) method for integrating multiple chips of different thicknesses into a single package structure includes the following steps: like Figure 3 As shown, solder is formed on a substrate 300, and multiple chips are mounted to form a first chip layer 310, wherein at least one chip has a thickness greater than the thickness of the other chips. As an example, in... Figure 3 In this process, the thickness of chip 311 is greater than that of other chips (such as chip 312), which causes the flatness of the first chip layer 310 in the horizontal direction (X direction in the figure) to change, resulting in poor chip coplanarity.

[0048] like Figure 4 As shown, solder is formed on the first chip layer 310, and multiple chips are mounted to form the second chip layer 320.

[0049] As an example, in the second chip layer 320, chip 321 is connected to chips 311 and 312 in the first chip layer 310. The different thicknesses of chips 311 and 312 cause chip 321 in the second chip layer 320 to tilt. Chip 321 may not be in complete contact with the solder, resulting in an open circuit or high resistance connection. Alternatively, local interconnect points may be subjected to additional mechanical stress, which may lead to breakage after long-term use. Or, during reflow soldering, one end of chip 321 may detach from the solder and tilt up, standing upright like a "tombstone", causing electrical connection failure, i.e., the tombstone effect defect. These defects can all lead to a decrease in the reliability, yield and performance of the package structure.

[0050] In both a system-in-package (SiP) method for integrating multiple chips of the same thickness into a single package structure and a SiP method for integrating multiple chips of different thicknesses into a single package structure, the step of forming a second chip layer is repeatedly performed to form multiple chip layers, followed by molding to form the SiP structure. As the number of chip layers increases, the problem of poor chip coplanarity gradually accumulates, ultimately severely impacting the reliability, yield, and performance of the package structure.

[0051] To address the issue of poor chip coplanarity in system-in-package (SiP) structures and improve their reliability, yield, and performance, this invention provides a SiP method and structure. The SiP method and structure provided by this invention eliminate the need for uniform molding after stacking multiple chips. Instead, a pre-formed intermediate packaging layer with a flat surface is formed. This intermediate packaging layer corrects its flatness through the intermediate molding layer and the first conductive pillars, compensating for the poor coplanarity caused by mounting processes or variations in chip thickness. This prevents various defects caused by poor chip coplanarity in the packaging structure, thereby improving the reliability, yield, and performance of the SiP.

[0052] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] like Figure 5 As shown, in a first specific embodiment, the system-level encapsulation method provided by the present invention includes the following steps: Step S50: Provide a packaged bottom layer.

[0054] Step S51: Form one or more package intermediate layers stacked along a first direction on the bottom layer of the package, wherein the method for forming the package intermediate layer includes: Step S510: Deposit a plurality of intermediate chips arranged at intervals along a second direction, the second direction being perpendicular to the first direction; Step S511: Form a first conductive pillar on the surface of the intermediate chip; Step S512: Mold encapsulate to form an intermediate molding layer, the intermediate molding layer covering the intermediate chip and the first conductive pillar; Step S513: Remove a portion of the intermediate molding layer to form a flat surface, and expose the first conductive pillar in the intermediate molding layer, wherein the intermediate chip, the first conductive pillar, and the intermediate molding layer constitute the package intermediate layer.

[0055] Step S52: Form the top layer of the package on the intermediate layer of the package.

[0056] Figures 6-12 This is a schematic diagram of the process of the first specific embodiment of the system-level packaging method provided by the present invention. The following is in conjunction with... Figures 5-12 The first specific embodiment of the system-level encapsulation method provided by the present invention will be described in detail.

[0057] Please see Figure 6 And in step S50, a packaging bottom layer 400 is provided. The surface of the packaging bottom layer 400 is a flat surface to further provide a flat working plane for the subsequent formation of the packaging intermediate layer.

[0058] In this specific embodiment, the bottom layer of the package 400 is a substrate, and the surface of the substrate has solder pads 401. The substrate can be an existing ceramic substrate, a multilayer substrate, a MIS (Molded Interconnect System) plastic-encapsulated interconnect substrate, or a redistribution stack layer, etc. The substrate includes an upper surface and a lower surface that are relatively distributed. A circuit layer (not shown in the figures) is disposed within the substrate for the transmission and distribution of electrical signals. In some specific embodiments, a plurality of lead-out solder balls (not shown in the figures) electrically connected to the circuit layer are disposed on the lower surface of the substrate. The lead-out solder balls are used to realize the electrical interconnection between the substrate and an external circuit board. A plurality of solder pads 401 electrically connected to the circuit layer are disposed on the upper surface of the substrate. The solder pads 401 are formed by etching or electroplating processes and are used to realize the electrical interconnection between the package intermediate layer and the substrate.

[0059] In another specific embodiment, the bottom layer of the package 400 is a composite package layer containing an embedded chip. The chip is embedded inside the composite package layer, and the upper and lower surfaces have interconnection structures to realize the electrical interconnection between the composite package layer and the intermediate package layer and the external circuit board.

[0060] Please refer to step S51, where one or more encapsulation intermediate layers stacked along a first direction are formed on the encapsulation base layer 400. Each of the encapsulation intermediate layers extends along a second direction and a third direction. The first direction is perpendicular to the surface of the encapsulation base layer 400, and the second direction and the third direction are parallel to the surface of the encapsulation base layer 400, and the first direction, the second direction, and the third direction are perpendicular to each other. In a specific embodiment of the present invention, as an example, the first direction is the Z direction in a Cartesian coordinate system, the second direction is the X direction in a Cartesian coordinate system, and the third direction is the Y direction in a Cartesian coordinate system.

[0061] In this step, a single encapsulation intermediate layer may be formed on the encapsulation base layer 400, or multiple encapsulation intermediate layers stacked along the first direction may be formed on the encapsulation base layer 400. As an example, in this specific embodiment, multiple encapsulation intermediate layers stacked along the first direction are formed on the encapsulation base layer 400. The step of forming multiple encapsulation intermediate layers stacked along the first direction on the encapsulation base layer 400 includes: forming an encapsulation intermediate layer 410 directly disposed on the surface of the encapsulation base layer 400; and forming another encapsulation intermediate layer on one of the encapsulation intermediate layers.

[0062] Figures 7-10 This is a schematic diagram of the process of forming the intermediate layer 410 of the package directly disposed on the surface of the package bottom layer 400.

[0063] like Figure 7 As shown, a plurality of intermediate chips 411 are disposed on the bottom layer 400 and spaced apart along the second direction. In some specific embodiments, the plurality of intermediate chips 411 are also spaced apart along the third direction, that is, the plurality of intermediate chips 411 are arranged in an array in the plane formed by the second direction and the third direction.

[0064] The intermediate chip 411 may be a chip with the same or different functions. In some specific embodiments, the intermediate chip 411 has a through-silicon via (TSV), through which the package bottom layer 400 and another package intermediate layer 420 located above the package intermediate layer 410 are connected (see [link]). Figure 15 Electrical interconnection of ).

[0065] In some embodiments, the plurality of intermediate chips 411 have the same thickness in the first direction. Specifically, in this embodiment, the plurality of intermediate chips 411 have identical dimensions, including their thickness in the first direction, their length in the second direction, and their width in the third direction. In other embodiments, the plurality of intermediate chips 411 have the same thickness in the first direction, but their length in the second direction or their width in the third direction differs.

[0066] In this specific embodiment, the bottom layer 400 of the package is a substrate, and the method for forming the intermediate layer of the package on the substrate includes: forming solder 412 on the pads 401 of the substrate; mounting a plurality of intermediate chips 411 on the substrate and electrically connecting them to the substrate through the solder 412. The solder 412 may be composed of solder powder, flux and adhesive.

[0067] In this specific embodiment, the step of forming solder 412 on the pads 401 of the substrate further includes: forming the solder 412 using a screen printing process. As an example, the method for forming the solder 412 using screen printing specifically includes: pressing the solder 412 onto the pads using a squeegee through a screen template with a specific pattern to form a precise solder layer. Screen printing can batch print multiple solder joints with high efficiency; it precisely controls the solder position and thickness, resulting in high accuracy; the template is reusable, reducing cost; it is compatible with various solders and substrates, offering strong adaptability; and it provides high welding strength, excellent conductivity, and good reliability.

[0068] In another specific embodiment, the step of forming solder 412 on the pads 401 of the substrate further includes: forming the solder 412 using a dispensing process. As an example, the method of forming the solder 412 using a dispensing process specifically includes: precisely controlling a dispensing device (e.g., a jet valve or screw pump) to directly apply liquid solder onto the pads. The dispensing process can adapt to complex solder joint layouts and three-dimensional structures, offering high flexibility; on-demand dispensing reduces material waste and increases utilization; and micron-level control of solder quantity and position ensures high precision.

[0069] Multiple intermediate chips 411 are mounted on the substrate using surface mount technology (SMT). As an example, the method for mounting the intermediate chips 411 on the substrate using SMT specifically includes: using a pick-and-place machine to rapidly and precisely mount the intermediate chips 411 onto the solder 412 positions, followed by reflow soldering to melt and solidify the solder, forming a reliable electrical connection, and finally cleaning and testing. Surface mount technology supports micro-components and fine-pitch designs, enabling high-density connections; it also offers high mounting speeds, with automated placement reaching tens of thousands of points per hour; and it reduces human error, improving packaging consistency.

[0070] Due to the influence of the mounting process, such as uneven solder printing or coating, or inconsistent solder height caused by uneven temperature during reflow soldering, the surface of some intermediate chips 411 may be lower than the surface of other intermediate chips.

[0071] like Figure 8 As shown, after multiple intermediate chips 411 are mounted on the substrate, a first conductive post 413 is formed on the surface of the intermediate chip 411. Specifically, the first conductive post 413 is formed on the surface of the intermediate chip 411 facing away from the substrate. The first conductive post 413 is electrically connected to the intermediate chip 411. For example, the first conductive post 413 is connected to an electrical connection point of the intermediate chip 411, which includes, but is not limited to, through-silicon vias and functional area pads of the intermediate chip 411. In one specific embodiment, surface mount technology (SMT) can be used to mount the first conductive post 413 onto the surface of the intermediate chip 411.

[0072] In this specific embodiment, the step of forming the first conductive pillar 413 on the surface of the intermediate chip 411 further includes: Solder 414 is formed on the surface of the intermediate chip 411. Specifically, the solder 414 is formed on the surface of the intermediate chip 411 opposite to the substrate, and the solder 414 is disposed on the surface of the electrical connection point on the surface of the intermediate chip 411. In one specific embodiment, the step of forming solder 414 on the surface of the intermediate chip 411 includes: forming the solder 414 using a screen printing process or a dispensing process. As an example, the method of forming the solder 414 by screen printing specifically includes: pressing the solder 414 onto the pads using a squeegee through a screen template with a specific pattern to form a precise solder layer. Screen printing can print multiple solder joints in batches with high efficiency; it can precisely control the position and thickness of the solder with high accuracy; the template can be reused, resulting in low cost; it is compatible with various solders and substrates, offering strong adaptability; and it provides high welding strength, excellent conductivity, and good reliability. As an example, the method for forming the solder 414 using the dispensing process specifically includes: precisely controlling the dispensing equipment (e.g., a jet valve or screw pump) to directly apply liquid solder onto the pads. The dispensing process is adaptable to complex solder joint layouts and three-dimensional structures, offering high flexibility; on-demand dispensing reduces material waste and increases utilization; and micron-level control of solder quantity and position ensures high precision.

[0073] The first conductive post 413 is mounted on the solder 414, and the first conductive post 413 is electrically connected to the intermediate chip 411 through the solder 414. In this step, surface mount technology can be used to mount the first conductive post 413 on the solder 414.

[0074] In another specific embodiment, the first conductive post 413 can be fixed to the surface of the electrical connection point of the intermediate chip 411 by an adhesive layer. The adhesive layer can be an anisotropic conductive film (ACF) or conductive adhesive (epoxy resin or silicone containing conductive fillers such as silver and copper).

[0075] like Figure 9 As shown, after forming the first conductive pillar 413 on the surface of the intermediate chip 411, it is encapsulated to form an intermediate encapsulation layer 415. The intermediate encapsulation layer 415 covers the intermediate chip 411 and the first conductive pillar 413, and also fills the gap between the intermediate chip 411 and the substrate. As an example, after forming the first conductive pillar 413 on the surface of the intermediate chip 411, the intermediate encapsulation layer 415 is formed using an injection molding process. The intermediate encapsulation layer 415 uses a thermosetting material such as epoxy resin to uniformly encapsulate the intermediate chip 411 and the first conductive pillar 413, forming a reliable physical protective layer, while also providing support for the formation of another encapsulation intermediate layer on top of the encapsulation intermediate layer.

[0076] like Figure 10As shown, after forming the intermediate molding compound 415, a portion of the intermediate molding compound 415 is removed to form a flat surface, and the intermediate molding compound 415 exposes the first conductive post 413. The intermediate chip 411, the first conductive post 413, and the intermediate molding compound 415 constitute the encapsulation intermediate layer 410. The length of the first conductive post 413 disposed on the intermediate chip 411 with a lower surface area is greater than the length of the first conductive post 413 disposed on the intermediate chip 411 with a higher surface area.

[0077] The above steps can form the package intermediate layer 410 with a flat surface. Even if the solder height is inconsistent due to uneven solder printing or coating or uneven temperature during reflow soldering when mounting the intermediate chip 411, and the surface of some intermediate chips 411 facing away from the substrate is lower or higher than the surface of other intermediate chips 411 facing away from the substrate, the difference can be corrected by setting the intermediate molding layer 415 and the first conductive pillar 413. Therefore, when another package intermediate layer or package top layer is formed on the package intermediate layer 410, various defects caused by poor chip coplanarity will not occur.

[0078] In one specific embodiment, if only a portion of the intermediate molding layer 415 is removed, the first conductive post 413 may still protrude from the surface of the intermediate molding layer 415. Therefore, in one specific embodiment, the step of removing a portion of the intermediate molding layer 415 to form a flat surface further includes: removing a portion of the intermediate molding layer 415 to expose the first conductive post 413; continuing to remove a portion of the intermediate molding layer 415 and a portion of the first conductive post 413 to form a flat surface, thereby further ensuring the flatness of the surface of the intermediate packaging layer and avoiding the problem of chip coplanarity.

[0079] As an example, a chemical mechanical polishing (CMP) process is used to remove part of the intermediate molding compound 415 and part of the first conductive pillar 413. The CMP process softens the surface material through chemical etching, and then removes the protrusions through mechanical polishing, achieving nanoscale surface smoothness and possessing multi-material compatibility, thus simultaneously removing both the intermediate molding compound 415 and the first conductive pillar 413.

[0080] After performing the above steps, the encapsulation intermediate layer 410 is formed on the encapsulation bottom layer 400, which is directly disposed on the surface of the encapsulation bottom layer 400.

[0081] Figures 11-14 This is a schematic diagram of the process of forming another packaging intermediate layer 420 on one of the packaging intermediate layers 410.

[0082] Please see Figure 11 Solder 422 is formed on the first conductive pillar 413 of the lower encapsulation intermediate layer 410.

[0083] The solder 422 may be composed of solder powder, flux, and binder. In this specific embodiment, the step of forming solder 422 on the first conductive post 413 of the lower encapsulation intermediate layer 410 further includes forming the solder 422 using a screen printing process. In another specific embodiment, the step of forming solder 422 on the first conductive post 413 of the lower encapsulation intermediate layer 410 includes forming the solder 422 using a dispensing process. The method of forming the solder 422 using screen printing can refer to the method of forming the solder 412 using screen printing, and the method of forming the solder 422 using a dispensing process can refer to the method of forming the solder 412 using a dispensing process.

[0084] Please see Figure 12 After the solder 422 is formed, a plurality of intermediate chips 421 are mounted on the first conductive post 413 and electrically connected to the first conductive post 413 of the lower package intermediate layer 410 through the solder 422.

[0085] In this specific embodiment, a plurality of intermediate chips 421 are mounted on the first conductive pillars 413 of the lower packaging intermediate layer 410 using surface mount technology (SMT). The intermediate chips 421 may be chips with the same or different functions, and may be chips with the same or different functions as the intermediate chips 411 of the lower packaging intermediate layer 410. In this specific embodiment, the plurality of intermediate chips 421 are all identical in size, that is, the thickness of the plurality of intermediate chips 421 in the first direction, the length in the second direction, and the width in the third direction are all the same. Further, in this specific embodiment, the size of the intermediate chips 421 is the same as the size of the intermediate chips 411 of the lower packaging intermediate layer 410. In another specific embodiment, the thickness of the intermediate chips 421 in the first direction is different from the thickness of the intermediate chips 411 of the lower packaging intermediate layer 410 in the first direction, while the length of the intermediate chips 421 in the second direction and the width in the third direction are the same as the length of the intermediate chips 411 of the lower packaging intermediate layer 410 in the second direction and the width in the third direction.

[0086] In this step, the flat surface of the lower encapsulation intermediate layer 410 serves as the mounting plane for the intermediate chip 421, and it does not affect the flatness of the multiple intermediate chips 421. Due to the influence of the mounting process, such as uneven solder printing or coating, or inconsistent solder height caused by uneven temperature during reflow soldering, the surface of some intermediate chips 421 may be lower than the surface of other intermediate chips.

[0087] Please see Figure 13 After the intermediate chip 421 is mounted, a first conductive post 423 is formed on the surface of the intermediate chip 421. Specifically, the first conductive post 423 is formed on the surface of the intermediate chip 421 opposite to the underlying encapsulation intermediate layer 410. In this specific embodiment, after the intermediate chip 421 is mounted, solder 424 is formed on the surface of the intermediate chip 421, and the first conductive post 423 is mounted on the solder 424. The mounting method of the first conductive post 423 and its connection relationship with the intermediate chip 421 can be referred to the description of the mounting method of the first conductive post 413 in the encapsulation intermediate layer 410 and its connection relationship with the intermediate chip 413.

[0088] Please see Figure 14 After forming the first conductive pillar 423 on the surface of the intermediate chip 421, it is encapsulated to form an intermediate encapsulation layer 425. The intermediate encapsulation layer 425 covers the intermediate chip 421 and the first conductive pillar 423, and also fills the gap between the intermediate chip 421 and the underlying encapsulation intermediate layer 410. The intermediate encapsulation layer 425 is made of thermosetting materials such as epoxy resin, uniformly covering the intermediate chip 421 and the first conductive pillar 423 to form a reliable physical protective layer, while providing support for the formation of another encapsulation intermediate layer.

[0089] Please see Figure 15 After forming the intermediate molding compound 425, a portion of the intermediate molding compound 425 is removed to form a flat surface, and the intermediate molding compound 425 exposes the first conductive post 423. The intermediate chip 421, the first conductive post 423, and the intermediate molding compound 425 serve as an intermediate packaging layer 420. In one specific embodiment, the step of removing a portion of the intermediate molding compound 425 to form a flat surface further includes: removing a portion of the intermediate molding compound 425 until the first conductive post 423 is exposed; continuing to remove a portion of the intermediate molding compound 425 and a portion of the first conductive post 423 to form a flat surface, further ensuring the flatness of the surface of the intermediate packaging layer.

[0090] The above steps can form the package intermediate layer with a flat surface. Even if the solder height is inconsistent due to uneven solder printing or coating or uneven temperature during reflow soldering when mounting the intermediate chip 421, and the surface of some intermediate chips 421 is lower or higher than the surface of other intermediate chips 421, the difference can be corrected by setting the intermediate molding layer 425 and the first conductive pillar 423. Therefore, when another package intermediate layer or package top layer is formed on the package intermediate layer 420, various defects caused by poor chip coplanarity will not occur.

[0091] Please see Figure 16 Repeat the above steps for forming the encapsulation intermediate layer to form multiple encapsulation intermediate layers. Figure 16 The diagram schematically illustrates the four-layer encapsulation intermediate layer.

[0092] Since the flatness of each encapsulation intermediate layer is corrected by the intermediate molding layer and the first conductive pillar, as the number of stacked layers increases, the problem of poor chip coplanarity will not gradually accumulate, which greatly improves the reliability, yield and performance of the system-in-package structure.

[0093] Please see Figure 17 In step S52, a top packaging layer 450 is formed on the intermediate packaging layer. The top packaging layer 450 is formed on the flat surface of the intermediate packaging layer, thus avoiding defects caused by poor coplanarity of the intermediate packaging layer.

[0094] In this specific embodiment, the step of forming the top package 450 on the intermediate package layer further includes: forming solder 452 on the intermediate package layer; providing at least one top layer chip 451, the top layer chip 451 being mounted on the intermediate package layer and electrically connected to the intermediate package layer via the solder 452; and molding to form a top molding layer 455, the top molding layer 455 covering the intermediate package layer and encapsulating the top layer chip 451. In this specific embodiment, the side of the top layer chip 451 facing away from the intermediate package layer is exposed, so that heat inside the system-in-package structure can be dissipated through the back side of the top layer chip 451.

[0095] After executing steps S50 to S52, a system-in-package (SIP) structure is formed. The bottom package 400, the multiple intermediate package layers, and the top package 450 together constitute the SIP structure. In some specific embodiments, only one intermediate package layer may be formed on the bottom package 400, and the top package 450 may be disposed on the intermediate package layer. The bottom package 400, the intermediate package layer, and the top package 450 together constitute the SIP structure.

[0096] In the second specific embodiment, please refer to Figure 18 The top layer 550 of the package is a package cover plate, and the surface of the package cover plate facing the package intermediate layer has solder pads 551, which are electrically connected to the package intermediate layer. In one specific embodiment, the package cover plate has conductive lines inside (not shown in the figures), and the side of the package cover plate facing away from the package intermediate layer has lead-out solder balls (not shown in the figures). Both the solder pads and the lead-out solder balls are connected to the conductive lines, thereby realizing the electrical lead-out of the package intermediate layer.

[0097] In the third specific embodiment, such as Figure 19 As shown, the system-in-package method of the present invention can also form a second conductive pillar 616 in the intermediate packaging layer 610 directly disposed on the surface of the packaging bottom layer 600. Specifically, the step of forming the intermediate packaging layer 610 directly disposed on the surface of the packaging bottom layer 600 includes: The step of setting a plurality of intermediate chips 611 spaced apart along the second direction on the package bottom layer 600 further includes: forming a second conductive post 616 on the package bottom layer 600. The surface of the second conductive post 616 facing away from the package bottom layer 600 is higher than the surface of the intermediate chips 611 facing away from the package bottom layer 600.

[0098] In the step of molding to form an intermediate molding layer 615, the intermediate molding layer 615 covers the intermediate chip 611, the first conductive post 613 and the second conductive post 616.

[0099] In the step of removing part of the intermediate molding layer 615 to form a flat surface, the intermediate molding layer 615 exposes the first conductive post 613 and the second conductive post 616.

[0100] When another packaging intermediate layer 620 is formed on the packaging intermediate layer 610, a portion of the intermediate chip 621 of the other packaging intermediate layer 620 is attached to the surface of the second conductive post 616, and another portion of the intermediate chip 621 is attached to the surface of the first conductive post 613 to achieve interconnection.

[0101] In the fourth specific implementation, such as Figure 20As shown, when a plurality of package intermediate layers stacked along the first direction are formed on the package bottom layer 700, at least one intermediate chip of the package intermediate layer can be electrically connected to two intermediate chips of the package intermediate layer below it through a first conductive post. Specifically, a method for forming another package intermediate layer 720 on one package intermediate layer 710 includes: providing a plurality of intermediate chips 721 on the package intermediate layer 710 below it, wherein at least one intermediate chip 721 is electrically connected to two intermediate chips 711 of the package intermediate layer 710 below it through a first conductive post 713, and the intermediate chip 721 serves as a bridge chip for the two intermediate chips 711 of the package intermediate layer 710 below it.

[0102] Furthermore, a third conductive pillar is formed in some encapsulation intermediate layers, through which the two encapsulation intermediate layers located above and below this intermediate layer can be electrically connected. For example, please refer to... Figure 20 A third conductive post 726 is also formed in the encapsulation intermediate layer 720, and the encapsulation intermediate layer 730 above the encapsulation intermediate layer 720 and the encapsulation intermediate layer 710 below the encapsulation intermediate layer 720 can be electrically connected through the third conductive post 726. Therefore, the method of forming one encapsulation intermediate layer on one of the encapsulation intermediate layers of the present invention further includes: The step of mounting the intermediate chip 721 on the lower package intermediate layer 710 further includes: providing a third conductive post 726 on the lower package intermediate layer 710, the third conductive post 726 being electrically connected to the lower package intermediate layer 710. A first conductive post 723 is formed after mounting the intermediate chip 721.

[0103] In the step of molding and forming an intermediate molding layer 725, the intermediate molding layer 725 covers the intermediate chip 721, the first conductive post 723 and the third conductive post 726.

[0104] In the step of removing part of the intermediate molding layer 725 to form a flat surface, the intermediate molding layer 725 exposes the first conductive post 723 and the third conductive post 726.

[0105] When another intermediate packaging layer 730 is formed on the intermediate packaging layer 720, a portion of the intermediate chip 731 of the other intermediate packaging layer 730 is attached to the surface of the third conductive post 726, and another portion of the intermediate chip 731 is attached to the surface of the first conductive post 723 to achieve interconnection.

[0106] In a first embodiment, all the intermediate chips in the same packaging intermediate layer have the same thickness in the first direction. In a fifth embodiment, the step of setting a plurality of intermediate chips spaced apart along the second direction in the step of forming the packaging intermediate layer further includes: at least some of the intermediate chips have different thicknesses in the first direction, such that at least some of the intermediate chips in the same packaging intermediate layer have different thicknesses in the first direction. In one embodiment, the length of the intermediate chips with different thicknesses in the second direction and the width in the third direction may be the same or different.

[0107] As an example, such as Figure 21 As shown, the intermediate chip 821 and intermediate chip 827 of the encapsulation intermediate layer 820 have different thicknesses in the first direction. The thickness of intermediate chip 821 is greater than that of intermediate chip 827. The height of the first conductive post 823 on the intermediate chip 821 is less than that on the intermediate chip 827. The surface of the first conductive post 823 is flush with the surface of the encapsulation intermediate layer 825. The encapsulation intermediate layer 820 has a flat surface.

[0108] Different chip thicknesses within the same layer can cause poor chip coplanarity. If another chip layer is directly formed on top of an intermediate chip with a different thickness, such as... Figure 4 As shown, this can lead to various defects. The system-in-package method of the present invention corrects the flatness of the intermediate packaging layer by setting the intermediate molding layer and the first conductive pillar, which solves the problem of poor coplanarity caused by the different thicknesses of the intermediate chips in the intermediate packaging layer. This ensures that the packaging structure will not produce various defects caused by poor chip coplanarity, thereby improving the reliability, yield and performance of the system-in-package structure.

[0109] The present invention also provides a system-level packaging structure formed using the above-described packaging method.

[0110] like Figures 6-17 As shown, the system-in-package structure includes: a bottom package 400; one or more intermediate package layers stacked along a first direction disposed on the bottom package 400, the intermediate package layers including: a plurality of intermediate chips arranged at intervals along a second direction, the second direction being perpendicular to the first direction; a first conductive pillar disposed on the intermediate chip; an intermediate molding layer covering the intermediate chip and the first conductive pillar, wherein the end of the first conductive pillar facing away from the intermediate chip is not covered by the intermediate molding layer; and a top package 450 disposed on the intermediate package layers.

[0111] A single encapsulation intermediate layer may be disposed on the encapsulation base layer 400, or multiple encapsulation intermediate layers stacked along the first direction may be disposed thereon. As an example, in this specific embodiment, multiple encapsulation intermediate layers stacked along the first direction are disposed on the encapsulation base layer 400. Specifically, the encapsulation base layer 400 includes an encapsulation intermediate layer 410 directly in contact with the encapsulation base layer 400, an encapsulation intermediate layer 420 disposed on the encapsulation intermediate layer 410, and multiple other encapsulation intermediate layers stacked along the first direction on the encapsulation intermediate layer 420.

[0112] In this specific embodiment, the packaging bottom layer 400 is a substrate, the surface of the substrate has a solder pad 401, the surface of the solder pad 401 is provided with solder 412, the intermediate chip 411 of the packaging intermediate layer 410 directly disposed on the packaging bottom layer 400 is mounted on the substrate and electrically connected to the substrate through the solder 412.

[0113] In this specific embodiment, all the intermediate chips have the same thickness in the first direction. In other specific embodiments, all the intermediate chips in the same packaging intermediate layer have the same thickness in the first direction, but the intermediate chips in different packaging intermediate layers may have different thicknesses in the first direction.

[0114] In this specific embodiment, the first conductive post 413 is attached to the surface of the intermediate chip 411 by solder 414, and the intermediate chip 421 of the upper packaging intermediate layer 420 is attached to the first conductive post 413 of the lower packaging intermediate layer 410 by solder 422.

[0115] In this specific embodiment, the top layer of the package 450 includes: at least one top layer chip 451, mounted on the intermediate package layer and electrically connected to the intermediate package layer via solder 452; and a top layer molding compound 455, covering the intermediate package layer and encapsulating the top layer chip 451. In another specific embodiment, as... Figure 18 As shown, the top layer 550 of the package is a package cover plate, and the surface of the package cover plate has solder pads 551, which are electrically connected to the middle layer of the package.

[0116] In another specific implementation, such as Figure 19As shown, a second conductive post 616 is further provided on the bottom layer 600 of the package. The intermediate molding layer 615 of the intermediate layer 610, which is directly disposed on the bottom layer 600 of the package, also covers the second conductive post 616 and exposes the end of the second conductive post 616 away from the bottom layer 60 of the package. A portion of the intermediate chip 621 of another intermediate layer 620 located above the intermediate layer 610 of the package is mounted on the surface of the second conductive post 616, and another portion of the intermediate chip 621 is mounted on the surface of the first conductive post 613 to achieve interconnection.

[0117] In another specific implementation, such as Figure 20 As shown, when the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom packaging layer 700, the upper intermediate packaging layer 720 includes a plurality of intermediate chips 721, wherein at least one intermediate chip 721 is electrically connected to two intermediate chips 711 of the lower intermediate packaging layer 710 through a first conductive post 713.

[0118] Furthermore, when the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom packaging layer 700, a third conductive pillar is provided in at least one of the intermediate packaging layers, the third conductive pillar being electrically connected to the intermediate packaging layer below it and the intermediate packaging layer above it; or the third conductive pillar being electrically connected to the intermediate packaging layer below it and the top packaging layer above it. Figure 20 As shown, a third conductive post 726 is provided within the encapsulation intermediate layer 720 located in the middle region. The third conductive post 726 is connected to a first conductive post 713 of another encapsulation intermediate layer 710 located below the encapsulation intermediate layer 720. A portion of the intermediate chip 731 of another encapsulation intermediate layer 730 located above the encapsulation intermediate layer 720 is mounted on the surface of the third conductive post 726, and another portion of the intermediate chip 731 is mounted on the surface of the first conductive post 723 of the encapsulation intermediate layer 720 to achieve interconnection.

[0119] In another specific embodiment, at least some of the intermediate chips have different thicknesses in the first direction. For example... Figure 21 As shown, the intermediate chip 821 and intermediate chip 827 of the encapsulation intermediate layer 820 have different thicknesses in the first direction. The thickness of intermediate chip 821 is greater than that of intermediate chip 827. The height of the first conductive post on the intermediate chip 821 is less than that of the first conductive post on the intermediate chip 827. The surface of the first conductive post is flush with the surface of the encapsulation intermediate layer 825. The encapsulation intermediate layer 820 has a flat surface.

[0120] Each of the intermediate packaging layers in the system-in-package structure of the present invention is a pre-formed structure. The flatness of the intermediate packaging layer is corrected by the intermediate molding layer and the first conductive pillar, which makes up for the defects of poor coplanarity caused by the mounting process or the different thickness of the intermediate chip. There will be no situation where the poor coplanarity of the chip in the intermediate packaging layer affects the performance of other intermediate packaging layers or the top packaging layer, thereby improving the reliability, yield and performance of the system-in-package structure.

[0121] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0122] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0123] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A system-in-a-package method, comprising: Includes the following steps: Provide a wrapper layer; One or more intermediate packaging layers stacked along a first direction are formed on the bottom layer of the package. The method of forming the intermediate packaging layers includes: setting a plurality of intermediate chips spaced apart along a second direction, the second direction being perpendicular to the first direction; forming a first conductive pillar on the surface of the intermediate chips; molding to form an intermediate molding layer, the intermediate molding layer covering the intermediate chips and the first conductive pillar; removing a portion of the intermediate molding layer to form a flat surface, and exposing the first conductive pillar; the intermediate chips, the first conductive pillar, and the intermediate molding layer constitute the intermediate packaging layers. A top layer of the encapsulation is formed on the intermediate layer of the encapsulation.

2. The system-in-a-package method of claim 1, wherein, In the step of providing a packaging substrate, the packaging substrate is a substrate, and the surface of the substrate has solder pads. The method of forming the encapsulation intermediate layer on the substrate includes: Solder is formed on the pads of the substrate; Multiple intermediate chips are mounted on the substrate and electrically connected to the substrate via solder.

3. The system-in-a-package method of claim 1, wherein, The step of forming the intermediate layer on the bottom layer of the package further includes: A second conductive pillar is formed on the bottom layer of the package; In the step of molding and forming an intermediate molding layer, the intermediate molding layer further covers the second conductive post; In the step of removing part of the intermediate molding layer to form a flat surface, the intermediate molding layer exposes the second conductive pillar.

4. The system-level packaging method according to claim 1, characterized in that, The step of setting up a plurality of intermediate chips spaced apart along the second direction further includes: the plurality of intermediate chips having the same thickness in the first direction.

5. The system-level packaging method according to claim 1, characterized in that, The step of setting up a plurality of intermediate chips spaced apart along the second direction further includes: at least some of the intermediate chips having different thicknesses in the first direction.

6. The system-level packaging method according to claim 1, characterized in that, The step of forming the first conductive pillar on the surface of the intermediate chip further includes: Solder is formed on the surface of the intermediate chip; The first conductive post is attached to the solder.

7. The system-level packaging method according to claim 1, characterized in that, The step of removing part of the intermediate molding layer to form a flat surface further includes: Remove part of the intermediate molding layer to expose the first conductive pillar; Continue removing a portion of the intermediate molding layer and a portion of the first conductive pillar to form a flat surface.

8. The system-level packaging method according to claim 1, characterized in that, The step of removing a portion of the intermediate encapsulation layer to form a flat surface further includes: removing a portion of the intermediate encapsulation layer using a chemical mechanical polishing process.

9. The system-level packaging method according to claim 1, characterized in that, When forming a plurality of package intermediate layers stacked along the first direction on the package bottom layer, the method of forming one package intermediate layer on one of the package intermediate layers includes: Solder is formed on the first conductive pillar located in the lower intermediate layer of the package; Multiple intermediate chips are mounted on the first conductive post and electrically connected to the first conductive post of the underlying package intermediate layer via solder.

10. The system-level packaging method according to claim 1, characterized in that, When forming a plurality of package intermediate layers stacked along the first direction on the package bottom layer, a method for forming another package intermediate layer on one package intermediate layer includes: disposing of a plurality of intermediate chips on the lower package intermediate layer, wherein at least one intermediate chip is electrically connected to two intermediate chips of the lower package intermediate layer via a first conductive post.

11. The system-level packaging method according to claim 10, characterized in that, The method of forming another package intermediate layer on one of the package intermediate layers further includes: A third conductive post is disposed on the lower encapsulation intermediate layer, and the third conductive post is electrically connected to the lower encapsulation intermediate layer. In the step of molding and forming an intermediate molding layer, the intermediate molding layer further covers the third conductive post; In the step of removing part of the intermediate molding layer to form a flat surface, the intermediate molding layer exposes the third conductive pillar.

12. The system-level packaging method according to claim 1, characterized in that, The step of forming the top layer of the package on the intermediate layer of the package further includes: Solder is formed on the intermediate layer of the package; At least one top-level chip is provided, which is mounted on the intermediate layer of the package and electrically connected to the intermediate layer of the package via solder; The top layer is formed by molding, which covers the intermediate packaging layer and encapsulates the top chip.

13. The system-level packaging method according to claim 1, characterized in that, In the step of forming the top layer of the package on the intermediate layer, the top layer of the package is a package cover plate, the surface of the package cover plate has solder pads, and the solder pads are electrically connected to the intermediate layer of the package.

14. A system-level packaging structure, characterized in that, include: Encapsulate the underlying layer; One or more intermediate packaging layers stacked along a first direction are disposed on the bottom layer of the package. The intermediate packaging layer includes: a plurality of intermediate chips arranged at intervals along a second direction, the second direction being perpendicular to the first direction; a first conductive post disposed on the intermediate chip; and an intermediate molding layer covering the intermediate chip and the first conductive post, wherein the end of the first conductive post facing away from the intermediate chip is not covered by the intermediate molding layer. The top layer of the package is disposed on the middle layer of the package.

15. The system-in-package structure according to claim 14, characterized in that, The bottom layer of the package is a substrate with solder pads on its surface and solder on the surface of the solder pads. The intermediate chip of the intermediate layer of the package, which is directly disposed on the bottom layer of the package, is mounted on the substrate and electrically connected to the substrate through the solder.

16. The system-in-package structure according to claim 14, characterized in that, A second conductive post is also provided on the bottom layer of the package. The intermediate molding layer of the intermediate package layer, which is directly disposed on the bottom layer of the package, also covers the second conductive post and exposes the end of the second conductive post that is away from the bottom layer of the package.

17. The system-in-package structure according to claim 14, characterized in that, The intermediate chips have the same thickness in the first direction.

18. The system-in-package structure according to claim 14, characterized in that, At least some of the intermediate chips have different thicknesses in the first direction.

19. The system-in-package structure according to claim 14, characterized in that, The first conductive post is attached to the surface of the intermediate chip by solder.

20. The system-in-package structure according to claim 14, characterized in that, When the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom layer of the package, the intermediate chip of the upper intermediate packaging layer is mounted on the first conductive pillar of the lower intermediate packaging layer by solder.

21. The system-in-package structure according to claim 14, characterized in that, When the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom layer of the package, the upper intermediate packaging layer includes a plurality of intermediate chips, wherein at least one intermediate chip is electrically connected to two intermediate chips of the lower intermediate packaging layer through a first conductive post.

22. The system-in-package structure according to claim 14, characterized in that, When the system-in-package structure includes a plurality of intermediate packaging layers stacked along a first direction disposed on the bottom layer of the package, a third conductive post is provided in at least one of the intermediate packaging layers, and the third conductive post is electrically connected to the intermediate packaging layer below it and the intermediate packaging layer above it; or the third conductive post is electrically connected to the intermediate packaging layer below it and the top layer of the package above it.

23. The system-in-package structure according to claim 14, characterized in that, The top layer of the package is a package cover plate, and the surface of the package cover plate has solder pads, which are electrically connected to the middle layer of the package.

24. The system-in-package structure according to claim 14, characterized in that, The top layer of the encapsulation includes: At least one top-layer chip is mounted on the intermediate layer of the package and is electrically connected to the intermediate layer of the package via the solder; The top molding layer covers the intermediate packaging layer and encapsulates the top chip.

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