Floating power domain circuit

Abstract

This application discloses a floating power domain circuit. The circuit includes: an impulse-resistant output unit, a first voltage correlation unit, a second voltage correlation unit, and a bias power supply unit. The impulse-resistant output unit includes a common-gate amplifier structure for receiving an external high-voltage input and outputting a floating power supply terminal, suppressing the impact of external high-voltage input jumps on the floating power supply terminal through the common-gate amplifier structure. The first voltage correlation unit is electrically connected between the floating power supply terminal and an external reference voltage, establishing a voltage correspondence between the floating power supply terminal and the external reference voltage. The second voltage correlation unit is electrically connected between the floating power supply terminal and a floating ground terminal, establishing a voltage correspondence between the floating power supply terminal and the floating ground terminal, such that the voltage difference between them is formed by the superposition of the threshold voltages or gate-source voltages of at least two active devices. The bias power supply unit provides a stable bias current to each unit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and more specifically, to a floating power domain circuit. Background Technology

[0002] In electronic systems such as power management and high-voltage drive, it is often necessary to provide a stable low-voltage operating range for the internal core circuits to avoid damage to sensitive circuits caused by drastic fluctuations in the external high-voltage input VIN. Therefore, the floating power domain has become a key circuit protection and power supply architecture.

[0003] In the prior art, floating power domains typically use P-type metal-oxide-semiconductor common-source amplifiers, i.e. PMOS common-source amplifiers, as the output stage. A stable low-voltage window is constructed by superimposing the gate-source voltage Vgs of the PMOS transistor with the voltage of the resistor.

[0004] However, this approach has significant drawbacks: First, the output impedance of the PMOS common-source amplifier is relatively high, which can easily cause a voltage surge at the positive terminal FVIN of the floating power supply when the external high-voltage input VIN changes rapidly, directly threatening the safety of subsequent circuits; second, the bandwidth of PMOS devices is low, resulting in a slow response to voltage fluctuations and an inability to suppress voltage jitter caused by high-voltage surges in a timely manner; in addition, the bias circuit relied upon by the traditional architecture lacks dynamic voltage regulation capability, and small bias fluctuations can further affect the voltage drop stability of the floating power supply domain, making it difficult to meet the high reliability requirements under wide-voltage input scenarios. Summary of the Invention

[0005] The main purpose of this application is to provide a floating power domain circuit to solve the problems of significant voltage surge, slow response, and poor voltage drop stability during high voltage transitions in traditional floating power domains. It can effectively suppress voltage surge, improve response speed, and stabilize output voltage drop.

[0006] To achieve the above objectives, a first aspect of this application proposes a floating power domain circuit, comprising: an impulse-resistant output unit, a first voltage correlation unit, a second voltage correlation unit, and a bias power supply unit; the impulse-resistant output unit includes a common-gate amplification structure for receiving an external high-voltage input and outputting a floating power terminal, thereby suppressing the impact of external high-voltage input jumps on the floating power terminal; the first voltage correlation unit is electrically connected between the floating power terminal and an external reference voltage, for establishing a voltage correspondence relationship in which the floating power terminal adjusts synchronously with the external reference voltage; the second voltage correlation unit is electrically connected between the floating power terminal and a floating ground terminal, for establishing a voltage correspondence relationship between the floating power terminal and the floating ground terminal, such that the voltage difference between the floating power terminal and the floating ground terminal is composed of the superposition of the threshold voltages or gate-source voltages of at least two active devices; the bias power supply unit is used to provide a stable bias current to the impulse-resistant output unit, the first voltage correlation unit, and the second voltage correlation unit.

[0007] According to a floating power domain circuit provided in this application, the common-gate amplification structure includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first current source; the drain of the first NMOS transistor is connected to the external high-voltage input, the source is connected to the drain of the second NMOS transistor, and the gate is connected to the floating power supply terminal; the gate of the second NMOS transistor is biased by the first current source, and the source outputs the floating power supply terminal; the gate of the third NMOS transistor is connected to an external reference voltage, the source is connected to the floating power supply terminal, and the drain is connected to the gate of the second NMOS transistor.

[0008] According to a floating power domain circuit provided in this application, the surge-resistant output unit further includes a Zener diode and a filter capacitor; the Zener diode and the filter capacitor are connected in parallel between the floating power terminal and the floating ground terminal; the Zener diode is used to limit the maximum amplitude of the voltage difference between the floating power terminal and the floating ground terminal; the filter capacitor is used to filter out the voltage ripple at the floating power terminal.

[0009] According to a floating power domain circuit provided in this application, the first voltage correlation unit includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, a second resistor, and a third resistor; the fourth NMOS transistor and the fifth NMOS transistor form a current mirror; the source of the fourth NMOS transistor is connected to a first node via the first resistor, and the source of the fifth NMOS transistor is connected to a second node via the second resistor; the gate of the sixth NMOS transistor is connected to the floating power terminal, and its drain is connected to the drain of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the external reference voltage, and its source is connected to the first node via the third resistor.

[0010] According to a floating power domain circuit provided in this application, the voltage superposition relationship between the floating power terminal and the external reference voltage is: FVIN≈ADJ+Vgs_MN3; where FVIN represents the floating power terminal, ADJ represents the external reference voltage, and Vgs_MN3 is the gate-source voltage of the fourth NMOS transistor.

[0011] According to a floating power domain circuit provided in this application, the second voltage correlation unit includes a first PMOS transistor, a second PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source of the first PMOS transistor is connected to the floating power terminal, and the drain is connected to the gate of the eighth NMOS transistor; the source of the second PMOS transistor is connected to the floating power terminal, and the drain is connected to the drain of the ninth NMOS transistor; the source of the eighth NMOS transistor outputs the floating ground terminal; and the gate of the ninth NMOS transistor is connected to the floating ground terminal.

[0012] According to a floating power domain circuit provided in this application, the second voltage correlation unit further includes a fourth resistor, a fifth resistor, a sixth resistor, and a compensation capacitor; the fourth resistor is connected in series between the source of the second PMOS transistor and the floating power terminal; the fifth resistor and the sixth resistor are connected in series between the source of the ninth NMOS transistor and ground; the compensation capacitor is connected in parallel across the fifth resistor.

[0013] According to the floating power domain circuit provided in this application, the first PMOS transistor and the second PMOS transistor are high-voltage isolation transistors used to achieve electrical isolation between the floating power terminal and the internal low-voltage circuit.

[0014] According to a floating power domain circuit provided in this application, the voltage difference relationship between the floating power terminal and the floating ground terminal is: FVIN-FVSS=Vgs_MN3+Vgs_MP1+Vgs_MN7; where FVIN represents the floating power terminal, FVSS represents the floating ground terminal, Vgs_MN3 represents the gate-source voltage of the fourth NMOS transistor, Vgs_MP1 represents the gate-source voltage of the first PMOS transistor, and Vgs_MN7 represents the gate-source voltage of the eighth NMOS transistor.

[0015] According to a floating power domain circuit provided in this application, the bias power supply unit includes a tenth NMOS transistor, an eleventh NMOS transistor, and a bias voltage terminal; the gate of the tenth NMOS transistor is connected to the bias voltage terminal, the drain is connected to the gate of the eleventh NMOS transistor, and the drain of the eleventh NMOS transistor is connected to a second node, providing bias current for the first voltage association unit and the second voltage association unit.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0017] Because the surge-resistant output unit integrates a common-gate amplification structure, and this common-gate amplification structure suppresses the impact of external high-voltage input jumps on the floating power supply terminal, it can effectively reduce the voltage overshoot amplitude at the floating power supply terminal, avoid the safety threat caused by high-voltage jumps to the subsequent circuits, and solve the problems of high output impedance and significant voltage overshoot in the traditional PMOS common-source amplification architecture.

[0018] Because of the first voltage correlation unit and the establishment of a voltage correspondence relationship where the floating power supply terminal adjusts synchronously with the external reference voltage, combined with the low output impedance characteristics of the common gate amplification structure, the circuit's response speed to voltage fluctuations is greatly improved. It can suppress voltage jitter caused by high voltage surges in a timely manner and overcome the defects of low bandwidth and slow response of traditional PMOS devices.

[0019] Since the second voltage correlation unit establishes the voltage correspondence between the floating power supply terminal and the floating ground terminal, and makes the voltage difference between the two the superposition of the threshold voltage or gate-source voltage of at least two active devices, and with the stable bias current provided by the bias power supply unit to each unit, the voltage difference of the floating power domain is not affected by the wide range of changes in the external reference voltage, and always remains basically constant. At the same time, it eliminates the interference of bias fluctuations on the voltage difference stability, and solves the problem of poor voltage difference stability in the traditional architecture.

[0020] In this way, multiple technical effects such as voltage overshoot suppression, fast response and voltage drop stabilization are achieved in wide voltage input scenarios, which significantly improves the working reliability of the floating power domain circuit and provides a stable and safe low-voltage operating range for the internal core sensitive circuit. Attached Figure Description

[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0022] Figure 1 A schematic diagram illustrating the basic principle of the floating power domain provided in this application;

[0023] Figure 2 This is a schematic diagram of the signal relationships of the floating power domain system provided in this application;

[0024] Figure 3 This is a schematic diagram of the circuit structure of a floating power domain architecture in the prior art;

[0025] Figure 4 A schematic diagram illustrating the voltage overshoot problem of floating power domains during high-voltage transitions in existing technologies;

[0026] Figure 5 This is a schematic diagram of the overall structure of the floating power domain circuit provided in the embodiments of this application;

[0027] Figure 6 This is a schematic diagram comparing the signals of the embodiments of this application with those of the prior art in a high-voltage switching scenario. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0031] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0032] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linked," and "socketing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0033] This application describes some exemplary embodiments for illustrative purposes. It should be understood that this application may be implemented in other ways not specifically shown in the accompanying drawings.

[0034] The concepts involved in this application will be explained in detail below.

[0035] Floating power domain: This is a power supply architecture that redefines the power supply and ground, allowing the internal circuit modules being powered to always operate within a fixed low-voltage range, completely unaffected by high-voltage fluctuations in the external system.

[0036] like Figure 1 The diagram illustrates the basic principle of a floating power domain. The power supply voltage VIN is the energy source for the entire circuit; its voltage is typically high and may fluctuate. A floating power domain completely isolates the internal circuitry from the high voltage and fluctuations of the power supply voltage VIN. Even if the power supply voltage VIN changes drastically, the internal circuitry is always supplied with a fixed low-voltage window and is not directly affected by the power supply voltage VIN.

[0037] Specifically, an external reference voltage ADJ is provided, and the floating power supply FVIN dynamically adjusts according to changes in the reference voltage ADJ. The floating power supply FVIN and the floating ground FVSS together form a fixed low-voltage window, with the voltage difference FVIN-FVSS remaining constant. In other words, within the adjustable range of the reference voltage ADJ, regardless of how ADJ changes, the floating power supply FVIN and the floating ground FVSS increase or decrease synchronously, ensuring a stable low-voltage window between them. This stable low-voltage window can then serve as the power supply for the internal circuit modules.

[0038] For example, the low-voltage window can power the error amplifier EA and the loop control. Although the reference voltage ADJ varies over a wide voltage range, the power supply to the internal error amplifier EA is always locked within a fixed low-voltage window, thus ensuring the stable operation of the module.

[0039] like Figure 2The diagram shows the signal relationships of the system. When the system starts, the external power supply voltage VIN can rise to 40V and remain stable, causing the enable signal EN to rise to 5V and trigger the system to operate. The reference voltage ADJ can change in stages over a wide voltage range, serving as the voltage target command for the entire system. The floating power supply FVIN and floating ground FVSS can change synchronously with the reference voltage ADJ. For example, when the reference voltage ADJ changes for the first time (from 5V to 25V), the floating power supply FVIN rises from around 6.5V to around 26.5V, and the floating ground FVSS rises from around 4V to around 24V. The voltage difference between them, FVIN-FVSS, remains stable at 2.5V, forming a fixed low-voltage operating window for the internal circuitry. Simultaneously, the system output voltage VOUT will rise in stages under loop control, precisely following the command value of the reference voltage ADJ. This process relies on an error amplifier powered by the floating power supply domain to achieve stable feedback, thereby ensuring that even if the external power supply voltage VIN remains constant at 40V, the internal circuitry always operates within a safe low-voltage range.

[0040] like Figure 3 As shown, the floating power domain architecture in the prior art typically adopts the form of a buffer. The external reference voltage ADJ is processed by a voltage divider network consisting of resistors R0, R1, and R2, and then fed into the five-transistor differential operational amplifier structure of the input stage. In the input stage, NMOS transistors MN1 and MN2 act as a differential pair to receive the signal and convert it into a differential current. The current mirror load consisting of PMOS transistors MP1 and MP2 converts this current into a single-ended voltage signal. Combined with the stable bias provided by the bias current source, this completes the initial amplification of the external reference voltage ADJ signal. The amplified signal drives the PMOS transistor MP3 in the output stage. This transistor takes the power supply voltage VIN as a high-voltage input and converts energy into a floating power supply voltage FVIN that follows the changes in the external reference voltage ADJ. Resistor R3, capacitor C1, and resistor R4 form a compensation network to optimize frequency response, prevent self-oscillation, and improve load-driving capability. Resistors R5 and R6 form a resistor voltage divider network, which, through the differential operational amplifier, allows FVIN to be adjusted according to changes in ADJ. Subsequently, the MOS diode structure composed of PMOS transistors MP4, MP5, and NMOS transistor MN3, through its fixed gate-source voltage drop, establishes a basic low-voltage window between the floating power supply FVIN and the floating ground FVSS. The parallel Zener diode D1 acts as a voltage clamping protection, clamping the voltage difference between the floating power supply FVIN and the floating ground FVSS near its breakdown voltage to avoid overvoltage damage.

[0041] like Figure 4As shown, under ideal conditions, the voltage difference between the floating power supply FVIN and the floating ground FVSS is fixed and the system output voltage VOUT follows the change of the external reference voltage ADJ. However, when the power supply voltage VIN changes rapidly, due to the high output impedance of the PMOS common-source output stage composed of PMOS transistor MP3, the floating power supply FVIN will have a significant voltage surge. Although Zener diode D1 can control the voltage difference within a certain range, it will still affect the stability of the system output voltage VOUT through the loop.

[0042] To address the aforementioned issues, this application provides a floating power domain circuit that can simultaneously achieve the effects of "high voltage jump resistance, output following reference voltage, and constant floating voltage difference" under a wide voltage input range.

[0043] like Figure 5 As shown, this application provides a floating power domain circuit, including: an anti-surge output unit 100, a first voltage association unit 200, a second voltage association unit 300, and a bias power supply unit 400.

[0044] The surge-resistant output unit 100 includes a common-gate amplification structure for receiving external high-voltage input VIN and outputting a floating power supply terminal FVIN. The common-gate amplification structure suppresses the impact of external high-voltage input VIN transitions on the floating power supply terminal FVIN.

[0045] The first voltage correlation unit 200 is electrically connected between the floating power supply terminal FVIN and the external reference voltage ADJ, and is used to establish a voltage correspondence relationship in which the floating power supply terminal FVIN is synchronously adjusted in accordance with the external reference voltage ADJ.

[0046] The second voltage correlation unit 300 is electrically connected between the floating power supply terminal FVIN and the floating ground terminal FVSS, and is used to establish the voltage correspondence between the floating power supply terminal FVIN and the floating ground terminal FVSS, so that the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS is composed of the superposition of the threshold voltage or gate-source voltage of at least two active devices.

[0047] The bias power supply unit 400 is used to provide a stable bias current to the surge-resistant output unit 100, the first voltage association unit 200 and the second voltage association unit 300.

[0048] Specifically, the bias power supply unit 400 can provide a unified and stable bias current for the surge-resistant output unit 100, the first voltage correlation unit 200, and the second voltage correlation unit 300, ensuring that the operating point of each unit remains constant. The first voltage correlation unit 200 can establish a voltage following mechanism based on the electrical connection between the external reference voltage ADJ and the floating power supply terminal FVIN, allowing the floating power supply terminal FVIN to adjust synchronously with the external reference voltage ADJ. The surge-resistant output unit 100 can suppress the jumps of the external high-voltage input VIN through a common-gate amplification structure, reducing the voltage overshoot of the floating power supply terminal FVIN and providing a stable output node for the first voltage correlation unit 200 and the second voltage correlation unit 300. The second voltage correlation unit 300 can generate a corresponding floating ground terminal FVSS based on the potential of the floating power supply terminal FVIN, maintaining a constant voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS formed by the superposition of the threshold voltage of the active device or the gate-source voltage. Even under scenarios where the external high voltage input VIN changes rapidly and the external reference voltage ADJ varies over a wide range, the floating power domain circuit of this application can still output a floating power domain with stable voltage drop and strong shock resistance, thereby providing a safe and reliable power supply for the subsequent low-voltage circuit.

[0049] Optionally, the common-gate amplification structure may include a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, and a first current source I1; the drain of the first NMOS transistor MN0 is connected to the external high-voltage input VIN, the source is connected to the drain of the second NMOS transistor MN1, and the gate is connected to the floating power supply terminal FVIN; the gate of the second NMOS transistor MN1 is biased by the first current source I1, and the source outputs the floating power supply terminal FVIN; the gate of the third NMOS transistor MN2 is connected to the external reference voltage ADJ, the source is connected to the floating power supply terminal FVIN, and the drain is connected to the gate of the second NMOS transistor MN1.

[0050] The surge-resistant output unit may further include a Zener diode D1 and a filter capacitor C0; the Zener diode D1 and the filter capacitor C0 are connected in parallel between the floating power supply terminal FVIN and the floating ground terminal FVSS; the Zener diode D1 is used to limit the maximum amplitude of the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS; the filter capacitor C0 is used to filter out the voltage ripple of the floating power supply terminal FVIN.

[0051] Specifically, the first NMOS transistor MN0 serves as a high-voltage isolation and buffer device. Its drain can receive the external high-voltage input VIN, and its gate is controlled by the potential feedback of the floating power supply terminal FVIN. When the external high-voltage input VIN undergoes a rapid change, the potential change of the floating power supply terminal FVIN can adjust the conduction level of the first NMOS transistor MN0 in real time, blocking the impact of the external high-voltage input VIN at the front end and preventing it from being directly conducted to the second NMOS transistor MN1.

[0052] The second NMOS transistor MN1 is the core device for common gate amplification. It can obtain stable bias through the first current source I1. Its source is used as a low-impedance output node to output the floating power supply terminal FVIN. With the characteristics of fast response speed and low output impedance of the common gate structure, it can quickly absorb the voltage fluctuation caused by the external high voltage input VIN jump, and significantly reduce the overshoot of the floating power supply terminal FVIN.

[0053] The third NMOS transistor MN2 is used to construct a feedback link, which transmits the potential relationship between the external reference voltage ADJ and the floating power supply terminal FVIN to the gate of the second NMOS transistor MN1, so that the gate-source voltage of the second NMOS transistor MN1 remains dynamically stable, ensuring that the floating power supply terminal FVIN can accurately follow the changes of the external reference voltage ADJ synchronously, while maintaining the shock resistance performance of the common gate amplification structure.

[0054] Zener diode D1 is connected in parallel between the floating power supply terminal FVIN and the floating ground terminal FVSS. It can act as an overvoltage clamp. When the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS rises abnormally under extreme conditions, Zener diode D1 can conduct in time and limit the voltage difference within a safe threshold, preventing damage to subsequent circuits due to overvoltage. Filter capacitor C0 is connected in parallel with Zener diode D1. Utilizing the energy storage characteristics of the capacitor, it can filter out high-frequency voltage ripple on the floating power supply terminal FVIN, smooth the output voltage waveform, and reduce voltage jitter.

[0055] It should be noted that the surge-resistant output unit effectively suppresses rapid fluctuations in external high-voltage input, ensuring the accuracy of the floating power supply in following changes in the external reference voltage. At the same time, it can output a low-ripple, highly stable floating power supply voltage, thus laying the foundation for the stable operation of the subsequent voltage correlation unit.

[0056] Optionally, the first voltage correlation unit includes a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, a first resistor R1, a second resistor R2, and a third resistor R3; the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 form a current mirror; the source of the fourth NMOS transistor MN3 is connected to the first node Vb via the first resistor R1; the source of the fifth NMOS transistor MN4 is connected to the second node Vc via the second resistor R2; the gate of the sixth NMOS transistor MN5 is connected to the floating power supply terminal FVIN, and its drain is connected to the drain of the seventh NMOS transistor MN6; the gate of the seventh NMOS transistor MN6 is connected to the external reference voltage ADJ, and its source is connected to the first node Vb via the third resistor R3.

[0057] Specifically, the current mirror formed by the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 can provide a stable reference current for the entire cell. Through the current limiting matching of the first resistor R1 and the second resistor R2, the current of the two branches is kept consistent, providing a stable current basis for establishing the voltage relationship. The gate of the sixth NMOS transistor MN5 is controlled by the floating power supply terminal FVIN potential. Its conduction state is dynamically adjusted with the change of the floating power supply terminal FVIN, thereby regulating the drain potential of the seventh NMOS transistor MN6, forming the feedback regulation of the branch current by the floating power supply terminal FVIN. The gate of the seventh NMOS transistor MN6 receives the external reference voltage ADJ, and the source is grounded through the third resistor R3. Its gate-source voltage and the voltage division of the third resistor R3 together form the voltage link between the external reference voltage ADJ and the first node Vb. Combined with the feedback regulation of the sixth NMOS transistor MN5, the voltage correspondence between the floating power supply terminal FVIN and the external reference voltage ADJ is finally established.

[0058] Optionally, the voltage superposition relationship between the floating power supply terminal FVIN and the external reference voltage ADJ is: FVIN≈ADJ+V_offset, where V_offset is a fixed voltage offset.

[0059] Specifically, during normal operation, all MOSFETs in the circuit are in the saturation region. The second NMOS transistor MN1, the third NMOS transistor MN2, and the seventh NMOS transistor MN6 are all low-threshold devices with very small threshold voltages Vth. Based on the circuit structure, the following node voltage relationships can be established:

[0060] The voltage at the first node, Va, is approximately equal to FVIN.

[0061] The voltage at the second node, Vb, is approximately equal to FVIN - Vgs_MN3 - I1. R1; and Vb = ADJ - Vgs_MN6 - I3 R3;

[0062] The voltage at the third node, Vc, is approximately equal to FVIN - Vgs_MN3 - I1. R1-Vgs_MP1;

[0063] Combining the two equations for the voltage Vb at the second node, we get:

[0064] FVIN Vgs_MN3 I1 R1=ADJ Vgs_MN6 I3 R3;

[0065] Summarized as follows:

[0066] FVIN=ADJ Vgs_MN6 I3 R3+Vgs_MN3+I1 R1

[0067] In actual circuits, due to Vgs_MN6 and I3 R3, I1 The values ​​of R1 are all very small, approximately 20~30mV, which can be ignored compared to the overall voltage. Therefore, the above equation can be simplified to:

[0068] FVIN≈ADJ+Vgs_MN3;

[0069] Vgs_MN3 is the gate-source voltage of the fourth NMOS transistor MN3. When the bias current is stable, Vgs_MN3 is basically constant, thus ensuring a stable voltage following relationship between the floating power supply terminal FVIN and the external reference voltage ADJ.

[0070] It should be noted that the first voltage correlation unit, on the one hand, ensures the stability of the branch current through the current mirror structure, avoiding the interference of current fluctuations on the voltage relationship; on the other hand, through the cooperation of dual NMOS transistors and resistors, it realizes the linear correlation between the external reference voltage and the floating power supply terminal, enabling the floating power supply terminal to accurately follow the external reference voltage and adjust synchronously over a wide range, while maintaining a fixed voltage offset, providing a stable front-end input for the second voltage correlation unit to build a constant voltage difference, and ensuring the voltage regulation accuracy and stability of the entire floating power supply domain circuit.

[0071] Optionally, the second voltage correlation unit includes a first PMOS transistor MP1, a second PMOS transistor MP2, an eighth NMOS transistor MN7, and a ninth NMOS transistor MN8; the source of the first PMOS transistor MP1 is connected to the floating power supply terminal FVIN, and the drain is connected to the gate of the eighth NMOS transistor MN7; the source of the second PMOS transistor MP2 is connected to the floating power supply terminal FVIN, and the drain is connected to the drain of the ninth NMOS transistor MN8; the source of the eighth NMOS transistor MN7 outputs the floating ground terminal FVSS; the gate of the ninth NMOS transistor MN8 is connected to the floating ground terminal FVSS.

[0072] The second voltage correlation unit further includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a compensation capacitor C1; the fourth resistor R4 is connected in series between the source of the second PMOS transistor MP2 and the floating power supply terminal FVIN; the fifth resistor R5 and the sixth resistor R6 are connected in series between the source of the ninth NMOS transistor MN8 and ground; the compensation capacitor C1 is connected in parallel across the fifth resistor R5.

[0073] Specifically, the first PMOS transistor MP1 serves as a high-voltage isolation and signal transmission device. Its source is connected to a stable floating power supply terminal FVIN, and its conduction state is regulated by the drain load characteristics. It provides an adaptation potential to the gate of the eighth NMOS transistor MN7, laying the foundation for the generation of the floating ground terminal FVSS. The eighth NMOS transistor MN7 is the core device for the floating ground terminal FVSS output. Its gate is controlled by the drain potential of the first PMOS transistor MP1, and its source outputs the floating ground terminal FVSS. Its gate-source voltage and the gate-source voltage of the first PMOS transistor MP1 together constitute the basis of the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS, so that the voltage difference between the two is stabilized as the sum of the gate-source voltages of the first PMOS transistor MP1 and the eighth NMOS transistor MN7, and is not affected by the wide range of changes in the floating power supply terminal FVIN.

[0074] The second PMOS transistor MP2 and the fourth resistor R4 form a bias branch. The fourth resistor R4 limits the current to set a stable operating current for the second PMOS transistor MP2, ensuring that the conduction state of the second PMOS transistor MP2 is constant, thereby providing a stable drain drive for the ninth NMOS transistor MN8. The gate of the ninth NMOS transistor MN8 is connected to its own source output floating ground terminal FVSS, forming a self-biased structure. Together with the series voltage divider of the fifth resistor R5 and the sixth resistor R6, a feedback calibration loop for the floating ground terminal FVSS is constructed. When the floating ground terminal FVSS experiences a small fluctuation, the conduction degree of the ninth NMOS transistor MN8 adjusts with the gate-source voltage change. Dynamic calibration of the floating ground terminal FVSS is achieved through the potential feedback of the voltage divider resistor, further improving the voltage drop stability. The compensation capacitor C1 is connected in parallel across the fifth resistor R5. Through phase compensation, it suppresses loop oscillation, reduces voltage jitter, and ensures the smooth response of the second voltage correlation unit under a wide range of operating conditions.

[0075] It should be noted that the second voltage correlation unit can, on the one hand, fix the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS through the superposition effect of the gate-source voltage of the PMOS and NMOS transistors, thus achieving the requirement of constant voltage difference; on the other hand, it can improve the voltage difference accuracy and loop stability through resistor voltage division feedback and capacitor compensation, providing a floating power supply domain power supply environment with stable voltage difference, small fluctuation and high reliability for the subsequent low voltage circuit.

[0076] Optionally, the first PMOS transistor MP1 and the second PMOS transistor MP2 are high-voltage isolation transistors used to achieve electrical isolation between the floating power supply terminal FVIN and the internal low-voltage circuit.

[0077] Specifically, the first PMOS transistor MP1 and the second PMOS transistor MP2 adopt a high-voltage withstand device structure. Their drain-source junction can withstand the high potential difference brought by the external high-voltage input VIN, forming a dual physical and electrical isolation barrier in the circuit. On the one hand, it isolates the high-voltage potential of the floating power supply terminal FVIN from the control terminals of internal low-voltage devices such as the eighth NMOS transistor MN7 and the ninth NMOS transistor MN8, preventing high voltage from being directly conducted to the low-voltage side and causing device breakdown. On the other hand, it blocks the leakage path between the high-voltage and low-voltage domains through its own high-voltage withstand characteristics, reducing the coupling interference of high-voltage noise to the internal low-voltage circuit. At the same time, while achieving electrical isolation, it does not affect the normal signal transmission and potential control functions. The first PMOS transistor MP1 can still stably transmit the potential signal of FVIN to control the gate of the eighth NMOS transistor MN7, and the second PMOS transistor MP2 can still provide a stable bias for the ninth NMOS transistor MN8 with the cooperation of the fourth resistor R4, ensuring that the isolation function and the core performance of the circuit do not conflict with each other, thereby further improving the reliability and safety of the entire floating power supply domain circuit under high-voltage conditions.

[0078] Optionally, the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS is: FVIN-FVSS=Vgs_MN3+Vgs_MP1+Vgs_MN7, where Vgs_MN3 represents the gate-source voltage of the fourth NMOS transistor, Vgs_MP1 represents the gate-source voltage of the first PMOS transistor, and Vgs_MN7 represents the gate-source voltage of the eighth NMOS transistor.

[0079] Specifically, the relationship between the second node voltage Vc and the voltage at the floating ground terminal FVSS is as follows:

[0080] Vc≈FVIN-Vgs_MN3-I1 R1-Vgs_MP1;

[0081] Vc-Vgs_MN7=FVSS;

[0082] Substituting the first expression into the second expression, we obtain the initial expression for FVSS:

[0083] FVSS=FVIN Vgs_MN3 I1 R1 Vgs_MP1 Vgs_MN7;

[0084] In actual circuits, I1 The value of R1 is very small (approximately 20~30mV), negligible compared to the overall voltage. Therefore, the expression can be further simplified to:

[0085] FVSS=FVIN Vgs_MN3 Vgs_MP1 Vgs_MN7;

[0086] At this point, the voltage difference relationship between the floating power supply terminal FVIN and the floating ground terminal FVSS can be deduced as follows:

[0087] FVIN-FVSS=Vgs_MN3+Vgs_MP1+Vgs_MN7;

[0088] Under stable bias current conditions, the three gate-source voltages mentioned above remain basically constant. Therefore, the voltage difference between the floating power supply terminal FVIN and the floating ground terminal FVSS is also basically constant and is not affected by changes in the external high voltage input VIN or the external reference voltage ADJ.

[0089] Optionally, the bias power supply unit includes a tenth NMOS transistor MN9, an eleventh NMOS transistor MN10, and a bias voltage terminal V_bias1; the gate of the tenth NMOS transistor MN9 is connected to the bias voltage terminal V_bias1, the drain is connected to the gate of the eleventh NMOS transistor MN10, and the drain of the eleventh NMOS transistor MN10 is connected to the second node Vc, providing bias current for the first voltage association unit and the second voltage association unit.

[0090] Specifically, the bias voltage terminal V_bias1 can provide a fixed reference voltage. By controlling the gate potential of the tenth NMOS transistor MN9, the conduction level of the tenth NMOS transistor MN9 can be precisely controlled. As the first-stage current stabilizing device, the drain current of the tenth NMOS transistor MN9 exhibits linear regulation characteristics with the change of the gate-source voltage, which can convert the fluctuation of the bias voltage into a stable drain output current, providing precise gate drive for the eleventh NMOS transistor MN10. As the second-stage current output device, the gate of the eleventh NMOS transistor MN10 is controlled by the drain potential of the tenth NMOS transistor MN9, forming a follower-type current stabilizing structure. Its drain can be connected to the first voltage association unit and the second voltage association unit through the second node Vc, delivering the constant current after two stages of current stabilization to each functional unit.

[0091] It should be noted that the bias power supply unit, on the one hand, significantly reduces the impact of minute fluctuations in the bias voltage V_bias1 on the output current through the series regulation of two NMOS transistors, thereby significantly reducing the ripple coefficient of the output bias current. On the other hand, based on the current saturation characteristics of NMOS transistors, the output current remains essentially constant under wide voltage input and temperature variations, providing a stable current basis for the current mirror structure of the first voltage correlation unit and the bias branch of the second voltage correlation unit, avoiding problems such as voltage correlation shifts and decreased voltage drop stability caused by bias current fluctuations. Through precise current stabilization, the bias power supply unit ensures that each functional unit always operates at its preset optimal operating point, thereby improving the environmental adaptability and long-term reliability of the entire floating power domain circuit.

[0092] like Figure 6As shown, after the system starts up, the external high-voltage input VIN can jump in stages (4.5V, 40V, 20V, 40V in sequence), while the external reference voltage ADJ remains constant at 2V as the system's voltage target command. In the existing structure, when the external high-voltage input VIN jumps rapidly from 4.5V to 40V, the system output voltage VOUT shows a significant overshoot, jumping from 2V to 3.7V, an overshoot of 1.7V; simultaneously, the floating power supply voltage difference FVIN-FVSS jumps from 2.5V to 4V, and this high-voltage jump significantly impacts output stability. Under the structure of this application, when the external high voltage input VIN also jumps rapidly from 4.5V to 40V, the overshoot of the system output voltage VOUT is significantly suppressed, rising only slightly from 2V to 2.2V, with an overshoot of only 0.2V; at the same time, the floating power supply voltage difference FVIN-FVSS rises only slightly from 2.5V to 2.7V, effectively alleviating the voltage overshoot phenomenon caused by high voltage jumps and improving the stability and reliability of the system under wide voltage input scenarios.

[0093] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A floating power domain circuit, comprising: include: The system includes an anti-surge output unit, a first voltage correlation unit, a second voltage correlation unit, and a bias power supply unit. The surge-resistant output unit includes a common-gate amplification structure for receiving external high-voltage input and outputting a floating power supply terminal. The common-gate amplification structure suppresses the impact of external high-voltage input jumps on the floating power supply terminal. The first voltage correlation unit is electrically connected between the floating power supply terminal and the external reference voltage, and is used to establish a voltage correspondence relationship in which the floating power supply terminal adjusts synchronously with the external reference voltage; The second voltage correlation unit is electrically connected between the floating power supply terminal and the floating ground terminal, and is used to establish the voltage correspondence between the floating power supply terminal and the floating ground terminal, so that the voltage difference between the floating power supply terminal and the floating ground terminal is composed of the superposition of the gate-source voltages of at least two active devices. The bias power supply unit is used to provide a stable bias current to the surge-resistant output unit, the first voltage correlation unit and the second voltage correlation unit; The common-gate amplification structure includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first current source; The drain of the first NMOS transistor is connected to the external high voltage input, the source is connected to the drain of the second NMOS transistor, and the gate is connected to the floating power supply terminal. The gate of the second NMOS transistor is biased by the first current source, and the source outputs the floating power supply terminal; The gate of the third NMOS transistor is connected to an external reference voltage, the source is connected to a floating power supply terminal, and the drain is connected to the gate of the second NMOS transistor.

2. The floating power domain circuit according to claim 1, characterized in that, The shock-resistant output unit also includes a Zener diode and a filter capacitor; The Zener diode and the filter capacitor are connected in parallel between the floating power supply terminal and the floating ground terminal; The Zener diode is used to limit the maximum amplitude of the voltage difference between the floating power supply terminal and the floating ground terminal; The filter capacitor is used to filter out the voltage ripple at the floating power supply terminal.

3. The floating power domain circuit according to claim 1, characterized in that, The first voltage correlation unit includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first resistor, a second resistor, and a third resistor; The fourth NMOS transistor and the fifth NMOS transistor form a current mirror. The source of the fourth NMOS transistor is connected to the first node via the first resistor, and the source of the fifth NMOS transistor is connected to the second node via the second resistor. The gate of the sixth NMOS transistor is connected to the floating power supply terminal, and the drain is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the external reference voltage, and the source is connected to the first node via the third resistor.

4. The floating power domain circuit according to claim 3, characterized in that, The voltage superposition relationship between the floating power supply terminal and the external reference voltage is as follows: FVIN≈ADJ+Vgs_MN3; Wherein, FVIN represents the floating power supply terminal, ADJ represents the external reference voltage, and Vgs_MN3 is the gate-source voltage of the fourth NMOS transistor.

5. The floating power domain circuit according to claim 3, characterized in that, The second voltage correlation unit includes a first PMOS transistor, a second PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The source of the first PMOS transistor is connected to the floating power supply terminal, and the drain is connected to the gate of the eighth NMOS transistor. The source of the second PMOS transistor is connected to the floating power supply terminal, and the drain is connected to the drain of the ninth NMOS transistor. The source of the eighth NMOS transistor outputs the floating ground terminal; The gate of the ninth NMOS transistor is connected to the floating ground terminal.

6. The floating power domain circuit according to claim 5, characterized in that, The second voltage correlation unit also includes a fourth resistor, a fifth resistor, a sixth resistor, and a compensation capacitor; The fourth resistor is connected in series between the source of the second PMOS transistor and the floating power supply terminal. The fifth resistor and the sixth resistor are connected in series between the source of the ninth NMOS transistor and ground; The compensation capacitor is connected in parallel across the fifth resistor.

7. The floating power domain circuit according to claim 6, characterized in that, The first PMOS transistor and the second PMOS transistor are high-voltage isolation transistors used to achieve electrical isolation between the floating power supply terminal and the internal low-voltage circuit.

8. In the floating power supply domain circuit according to claim 6, the voltage difference relationship between the floating power supply terminal and the floating ground terminal is as follows: FVIN-FVSS=Vgs_MN3+Vgs_MP1+Vgs_MN7; in, FVIN represents the floating power supply terminal, FVSS represents the floating ground terminal, Vgs_MN3 represents the gate-source voltage of the fourth NMOS transistor, Vgs_MP1 represents the gate-source voltage of the first PMOS transistor, and Vgs_MN7 represents the gate-source voltage of the eighth NMOS transistor.

9. The floating power domain circuit according to claim 3, wherein the bias power supply unit includes a tenth NMOS transistor, an eleventh NMOS transistor, and a bias voltage terminal; The gate of the tenth NMOS transistor is connected to the bias voltage terminal, and the drain is connected to the gate of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the second node, providing bias current for the first voltage association unit and the second voltage association unit.

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