DCU-based performance modeling and code generation method and device

Abstract

The invention provides a DCU-based performance modeling and code generation method, which comprises the following steps of: constructing a performance model, namely constructing a calculation, memory access and synchronization three-in-one performance model according to acquired DCU hardware characteristics; a parameter analysis model construction step: constructing a parameter analysis model by combining the performance model according to DCU hardware resource constraints, and automatically screening out optimized parameters through the parameter analysis model; and an assembly code generation step: constructing a customized code generation tool, and automatically generating assembly codes of double-precision dense matrix multiplication by the code generation tool according to the optimization parameters. The invention further provides a DCU-based performance modeling and code generation device, a storage medium and electronic equipment. In this way, through an integrated automatic tool chain of performance modeling, parameter analysis and code generation, autonomous and efficient optimization of DCU-DGEMM is achieved.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing optimization technology, and in particular to a performance modeling and code generation method, apparatus, storage medium and electronic device based on DCU. Background Technology

[0002] DGEMM (Double-Precision Dense Matrix Multiplication) is a core operator in the field of high-performance computing. It is a key indicator for measuring the performance of computing acceleration hardware such as CPUs (Central Processing Units) and GPGPUs (General-Purpose Graphics Processing Units) (as seen in the TOP500 supercomputer evaluation), and also a fundamental computing unit for scientific computing, neural network training, and other scenarios. As a core acceleration component of high-performance computing clusters, the optimization of DGEMM in DCUs, such as Hygon DCUs, has become a crucial step in building an independent high-performance computing system.

[0003] Currently, the DCU is custom-developed based on AMD's GCN (Graphics Core Next) architecture. Its DGEMM optimization mainly relies on two approaches: one is to generate basic code using existing AMD tuning tools (such as Tensile) and then perform further manual optimization; the other is to rely on developers' experience for assembly-level manual optimization. However, both approaches have significant limitations: on the one hand, the code generated by tools such as Tensile contains redundant instructions, and parameter searching relies on brute-force testing, resulting in insufficient customization for the DCU and difficulty in fully unleashing hardware performance. On the other hand, manual optimization requires developers to have a deep understanding of the DCU hardware architecture and assembly instruction set, which has an extremely high learning cost, such as SIMD (Single Instruction Multiple Data) scheduling and LDS (Local Data Share) memory structure, and the optimization results are difficult to migrate quickly with hardware iterations.

[0004] Furthermore, international DGEMM performance modeling techniques for GPUs (such as the SGEMM model based on the NVIDIA Fermi / Kepler architecture) and code generation technologies cannot be directly adapted to Hygon DCUs due to differences in hardware architecture (such as register allocation and memory access paths). Hygon DCUs exhibit "black box" characteristics in their hardware design; some microarchitectural details, such as the TCC (Texture Cacheper Channel) scheduling mechanism and L2 Cache (Level 2 Cache) hit rules, are not fully disclosed, further increasing the difficulty of performance optimization and model construction.

[0005] Currently, most optimization methods for matrix multiplication employ traditional static optimization techniques. These methods typically optimize during the compilation phase for specific hardware and matrix shapes, lacking adaptability to dynamic computational requirements. Especially when dealing with irregularly shaped matrices, existing solutions exhibit significant limitations. The main problems and drawbacks are as follows:

[0006] (1) Performance optimization relies on experience and external tools, resulting in insufficient independent controllability. Hygon DCU's DGEMM optimization has long relied on tuning tools and historical experience provided by AMD, lacking independent optimization theories and toolchains based on hardware architecture. The development of algorithm libraries is deeply coupled with hardware design, requiring a large amount of resources to be reinvested in optimization during hardware iteration, which increases the development cycle and cost.

[0007] (2) High barriers to entry for developers and difficulty in building an ecosystem. To achieve DGEMM that matches the theoretical performance of DCU hardware, developers need to master low-level knowledge such as assembly-level programming and hardware microarchitecture (such as Wavefront scheduling and LDS Bank conflict avoidance), which has a very high learning cost, making it difficult for the DCU application ecosystem to expand rapidly.

[0008] (3) Low performance prediction accuracy and high degree of blindness in parameter selection. Existing solutions lack a DGEMM performance model for Hygon DCU, and parameter selection (such as thread block size and loop unrolling count) relies on brute-force search or heuristic methods. Brute-force search requires traversing a massive number of parameter combinations, which is time-consuming; heuristic parameters are prone to failure as hardware architecture changes, and cannot guarantee optimal performance.

[0009] (4) Low code generation efficiency and poor adaptability. Existing code generation tools (such as Tensile) generate code with redundant instructions for Hygon DCU (Deep Computing Unit) and do not make full use of DCU hardware features, such as LDS direct memory access and WGM (Work Group Manager) thread block rearrangement. It is difficult to balance code performance and readability, and it cannot quickly adapt to the hardware differences of different generations of DCU.

[0010] In conclusion, the existing technology obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the Invention

[0011] To address the aforementioned shortcomings, the present invention aims to provide a performance modeling and code generation method, apparatus, storage medium, and electronic device based on DCU, which achieves autonomous and efficient optimization of DCU-DGEMM through an integrated automatic toolchain of "performance modeling-parameter analysis-code generation".

[0012] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0013] In a first aspect, embodiments of the present invention provide a performance modeling and code generation method based on DCU, including:

[0014] The steps for building a performance model are as follows: Based on the collected DCU hardware characteristics, a performance model integrating computing, memory access, and synchronization is constructed.

[0015] The steps for constructing a parameter analysis model are as follows: based on the DCU hardware resource constraints and combined with the performance model, a parameter analysis model is constructed, and optimization parameters are automatically selected through the parameter analysis model.

[0016] The assembly code generation step involves building a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters.

[0017] According to the DCU-based performance modeling and code generation method of the present invention, the step of constructing the performance model further includes:

[0018] The main computational modeling sub-steps of the loop are combined with the instruction issuance rules and computational pipeline characteristics of the DCU's single instruction multiple data, and the instruction execution time when the thread computes the submatrix is ​​analyzed, taking into account the superposition effect of parallel computation of multiple thread groups.

[0019] The memory access process modeling sub-steps analyze the impact of memory conflicts on bandwidth and quantify memory access time for local shared memory access, and calculate the time overhead of data reading and writing by combining cache hit rules and texture cache channel scheduling characteristics for global memory access.

[0020] The synchronization and data dependency modeling sub-steps analyze the data dependencies within the thread group, quantify the parallel synergy between computation and memory access, and consider the impact of the execution latency of thread block synchronization instructions on overall performance.

[0021] According to the DCU-based performance modeling and code generation method of the present invention, the step of constructing the parameter analysis model further includes:

[0022] The hardware resource constraint sub-step limits the DCU hardware resource constraints to register capacity and LDS storage size, defines the range of thread block size and / or loop unrolling times, and excludes infeasible parameter combinations.

[0023] The sub-step for defining the thread block size involves determining the partition size of the thread block in the matrix dimension based on the local shared memory capacity limit.

[0024] Determine the number of loop unrolling sub-steps: Based on register capacity limitations, clarify the reasonable range for loop unrolling;

[0025] Defining thread block reordering parameters: Based on the characteristics of texture cache channel scheduling, determine the available schemes for thread block reordering;

[0026] The optimal parameter selection sub-step involves evaluating parameter combinations that meet the DCU hardware constraints, with the goal of calculating instruction ratio, cache hit rate, and / or performance prediction value, and selecting the parameter combination with the best overall performance.

[0027] According to the DCU-based performance modeling and code generation method of the present invention, the assembly code generation step further includes:

[0028] The sub-step of constructing a code generation tool involves building the code generation tool with automated code generation logic based on the DCU instruction set and the double-buffered DGEMM algorithm.

[0029] The metadata generation sub-step involves the code generation tool automatically generating the metadata required at runtime.

[0030] The register assignment sub-step involves the code generation tool automatically allocating registers for storing matrix data, temporary results, and / or address information based on the optimization parameters output by the parameter analysis model.

[0031] The memory access instruction generation sub-step optimizes address allocation when generating local shared memory access instructions by the code generation tool and enables direct memory access features when generating global memory access instructions.

[0032] The loop and synchronization implementation sub-steps are generated by the code generation tool based on the number of loop unrollings, which integrates double-buffered soft pipelining and thread block rearrangement logic, and generates tail loop processing code for non-standard matrix sizes.

[0033] The data write-back sub-step involves the code generation tool generating a result matrix and writing it back to global storage.

[0034] The code simplification sub-step involves the code generation tool removing redundant instructions.

[0035] According to the DCU-based performance modeling and code generation method of the present invention, the step of constructing the performance model includes the following prior to:

[0036] The hardware feature extraction step, which involves collecting DCU hardware features and constructing a hardware feature library using the DCU hardware features, further includes:

[0037] The sub-step for extracting computing unit features involves collecting the number of computing units, the number of single instruction multiple data units (SIDs) per computing unit, the number of double precision computing channels, and / or the core clock frequency.

[0038] The sub-step for extracting storage structure features includes collecting data on local shared storage size, number and bit width of storage volumes, L2 cache size, global storage bandwidth, and / or number of texture cache channels.

[0039] The thread scheduling feature extraction sub-step involves collecting the thread group size, the maximum number of thread groups supported by each computing unit, and / or the register capacity.

[0040] The microarchitecture feature verification sub-step verifies key microarchitecture details of the DCU, including local shared memory access paths, texture cache channel scheduling rules, and / or thread group synchronization latency, through custom assembly test cases.

[0041] According to the DCU-based performance modeling and code generation method of the present invention, the assembly code generation step is followed by:

[0042] The performance testing steps involve running the generated assembly code on the target DCU to test the actual performance metrics under different matrix sizes.

[0043] The model correction step involves comparing the actual performance indicators with the model predictions and adjusting the predetermined key parameters in the performance model and the parameter analysis model to make the prediction error less than a predetermined threshold.

[0044] In the iterative optimization step, if the performance of the assembly code does not meet the predetermined conditions, the parameter analysis step is backtracked to adjust the parameter combination, new assembly code is regenerated and tested, until the performance meets the predetermined conditions.

[0045] According to the DCU-based performance modeling and code generation method of the present invention, the DCU is Hygon DCU.

[0046] Secondly, embodiments of the present invention provide a DCU-based performance modeling and code generation apparatus constructed based on any one of the methods described above, the apparatus comprising:

[0047] The performance model building module is used to build a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics.

[0048] A parameter analysis model building module is used to build a parameter analysis model based on the DCU hardware resource constraints and the performance model, and to automatically select optimization parameters through the parameter analysis model.

[0049] An assembly code generation module is used to build a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters.

[0050] Thirdly, embodiments of the present invention provide a storage medium for storing a computer program for performing any of the methods described herein.

[0051] Fourthly, embodiments of the present invention provide an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement any of the methods described above.

[0052] Therefore, this invention provides a DCU-based performance modeling and code generation technology, including: (1) constructing a performance model: based on the collected DCU hardware characteristics, constructing a three-in-one performance model of computation, memory access, and synchronization, achieving an average relative error of ≤5% for matrix performance prediction, providing a theoretical basis for the selection of optimization parameters. (2) constructing a parameter analysis model: based on the DCU hardware resource constraints, constructing a parameter analysis model in conjunction with the performance model, and automatically selecting optimization parameters through the parameter analysis model, automatically selecting the optimal algorithm parameters (such as thread block size, loop unrolling times), which can greatly reduce the threshold for developers. (3) assembly code generation: constructing a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters. After receiving the optimal parameters, it automatically generates efficient assembly code, and the code performance reaches more than 93.9% of the theoretical performance of DCU. Therefore, this invention supports the rapid adaptation of DCUs of different generations through an integrated automatic toolchain of "performance modeling-parameter analysis-code generation", realizing the autonomous and efficient optimization of DCU-DGEMM. Attached Figure Description

[0053] Figure 1 This is a flowchart illustrating the DCU-based performance modeling and code generation method provided in Embodiment 1 of the present invention.

[0054] Figure 2 This is a flowchart illustrating the DCU-based performance modeling and code generation method provided in Embodiment 2 of the present invention.

[0055] Figure 3 This is a schematic diagram of the DCU-based performance modeling and code generation device provided in Embodiment 3 of the present invention;

[0056] Figure 4 This is a schematic diagram of the structure of the DCU-based performance modeling and code generation device provided in Embodiment 4 of the present invention;

[0057] Figure 5 This is a schematic diagram of the structure of the electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0059] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0060] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0061] The performance modeling and code generation method based on DCU provided in this invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0062] This invention relates to high-performance computing hardware adaptation technology, double-precision matrix multiplication (DGEMM) performance optimization technology, DCU platform code automatic generation technology, and heterogeneous computing performance modeling method. This invention is particularly applicable to Hygon DCU, but it is also applicable to DCUs from other brands.

[0063] To address the aforementioned issues in DCU-DGEMM optimization, two major technical challenges arise: First, how to construct an accurate performance model and quantify the time overhead of computation, memory access, and synchronization processes when the details of the DCU hardware are opaque. Second, how to design code generation logic that adapts to hardware characteristics, automatically avoiding memory access conflicts and optimizing instruction scheduling.

[0064] This invention first uses Microbenchmark tools (such as custom assembly-level test cases) to reverse engineer the characteristics of the DCU microarchitecture, clarifying the SIMD (Single Instruction Multiple Data) instruction issuance rules, such as single instruction issuance per cycle and wavefront (thread group) polling scheduling; LDS memory structure, such as 32-bank design and 512-bit / cycle memory access bandwidth; and GM (Global Memory) / L2 Cache access paths, thus overcoming the modeling obstacles caused by the hardware "black box". Subsequently, for the dual-cache DGEMM block algorithm, the three-stage execution flow of "global memory access - local memory access - computation" is decomposed, and data dependency models are established for the main computation loop, LDS / GM memory access, and wavefront (thread group) synchronization, overcoming the prediction error problem caused by traditional models ignoring hardware resource contention (such as LDS path bandwidth sharing).

[0065] In the code generation stage, this invention addresses the problem of "dynamic mapping between parameters and instructions": that is, how to automatically convert the optimal parameters output by the performance model, such as TTI / TTJ computation size and Depth loop unrolling count, into assembly code conforming to the DCU ISA, and integrate optimization strategies such as LDS memory bank conflict avoidance and WGM thread block rearrangement. Ultimately, by linking the performance model with the code generation tool, a closed loop of "hardware parameter input → performance prediction → optimal parameter output → automatic code generation" is formed, solving the problem of model-implementation disconnect in existing solutions.

[0066] This invention aims to solve four major problems in DGEMM performance optimization and code generation on DCU: poor self-control, high developer threshold, inaccurate performance prediction, and low code adaptability, and provides a complete solution based on hardware architecture:

[0067] (1) Construct an autonomous and controllable DCU-DGEMM performance model to achieve an average relative error of ≤5% in matrix performance prediction, providing a theoretical basis for optimizing parameter selection;

[0068] (2) Design a parameter analysis model based on hardware constraints to automatically select the optimal algorithm parameters (such as thread block size and loop unrolling times) and reduce the threshold for developers;

[0069] (3) Develop a customized code generation tool that automatically generates high-efficiency assembly code after receiving the optimal parameters, with code performance reaching more than 93.9% of the theoretical performance of DCU;

[0070] (4) Achieve linkage between performance model, parameter analysis and code generation to form an integrated toolchain of “modeling-analysis-generation”, supporting rapid adaptation of DCUs of different generations.

[0071] Figure 1 This is a flowchart illustrating the DCU-based performance modeling and code generation method provided in Embodiment 1 of the present invention. The method includes:

[0072] Step S101, the performance model construction step, constructs a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics.

[0073] Preferably, the DCU is a Haiguang DCU.

[0074] Preferably, the step of constructing the performance model further includes:

[0075] (11) The main body of the loop is to calculate the modeling sub-step. Combining the instruction issuance rules of the DCU with the characteristics of the computation pipeline, the instruction execution time when the thread calculates the sub-matrix is ​​analyzed, and the superposition effect of the parallel computation of the multi-thread group is considered.

[0076] (12) Modeling sub-steps for memory access process: For local shared memory access, analyze the impact of memory conflicts on bandwidth and quantify memory access time; for global memory access, combine cache hit rules and texture cache channel scheduling characteristics to calculate the time overhead of data reading and writing.

[0077] (13) Synchronization and data dependency modeling sub-steps: analyze the data dependency relationship within the thread group, quantify the parallel collaboration effect of computation and memory access, and consider the impact of the execution delay of thread block synchronization instructions on the overall performance.

[0078] Step S102, the parameter analysis model construction step, involves constructing a parameter analysis model based on the DCU hardware resource constraints and the performance model, and automatically selecting optimization parameters through the parameter analysis model.

[0079] Preferably, the step of constructing the parameter analysis model further includes:

[0080] (31) Define the hardware resource constraints sub-step, limit the DCU hardware resource constraints to register capacity and LDS storage size, define the range of thread block size and / or loop unrolling times, and exclude infeasible parameter combinations.

[0081] (32) Define the thread block size sub-step. Based on the local shared storage capacity limit, determine the partition size of the thread block in the matrix dimension.

[0082] (33) Defining the number of loop unrolling sub-steps: Based on the register capacity limit, determine the reasonable range of loop unrolling.

[0083] (34) Define the thread block reordering parameter sub-step: Based on the texture cache channel scheduling characteristics, determine the available schemes for thread block reordering.

[0084] (35) Optimal parameter selection sub-step: With the goal of calculating instruction ratio, cache hit rate and / or performance prediction value, evaluate the parameter combination that meets the DCU hardware constraints and select the parameter combination with the best overall performance.

[0085] Step S103, Assembly code generation step: Build a customized code generation tool. The code generation tool automatically generates assembly code for double-precision dense matrix multiplication based on optimization parameters.

[0086] Preferably, the assembly code generation step further includes:

[0087] (31) The code generation tool sub-step is to build a code generation tool with automated code generation logic based on the DCU instruction set and the double-buffered DGEMM algorithm.

[0088] (32) Meta-information generation sub-step: The code generation tool automatically generates the meta-information required for runtime.

[0089] (33) Register assignment sub-step: The code generation tool automatically allocates registers for storing matrix data, temporary results and / or address information based on the optimization parameters output by the parameter analysis model.

[0090] (34) The memory access instruction generation sub-step optimizes address allocation when the code generation tool generates local shared memory access instructions and enables direct memory access features when generating global memory access instructions.

[0091] (35) The loop and synchronization implementation sub-steps are generated by the code generation tool based on the number of loop expansions. The main loop code is integrated with the double-buffered soft pipeline and thread block rearrangement logic, and the tail loop processing code is generated for non-standard matrix sizes.

[0092] (36) The data write-back sub-step is an instruction generated by the code generation tool to write the result matrix back to global storage.

[0093] (37) Code simplification sub-step: redundant instructions are removed by code generation tools.

[0094] This invention achieves autonomous and efficient optimization of DCU-DGEMM through an integrated toolchain of "performance modeling-parameter analysis-code generation". The core technical effects are as follows:

[0095] (1) Improved autonomy and controllability: Get rid of dependence on external tuning tools, build an independent model and code generation logic based on the DCU hardware architecture, and only need to update the hardware parameter configuration when iterating the hardware, without reconstructing the toolchain, shortening the development cycle by more than 60%.

[0096] (2) The threshold for developers is significantly reduced: developers do not need to master the underlying hardware and assembly knowledge. They only need to input the DCU hardware parameters (such as the number of CUs and the size of LDS) and the matrix size. The toolchain can automatically output the optimal parameters and code, reducing the learning cost by 80%.

[0097] (3) Dual optimization of performance and efficiency: the performance model prediction error is ≤5%, the parameter screening efficiency is improved by 90%; the generated code performance reaches 93.9% of the theoretical peak of DCU, and the code volume is reduced by more than 60%, significantly improving readability and maintainability.

[0098] (4) Cross-generational adaptability: The toolchain already supports Z100 and K100 DCU through hardware parameter configuration files. When the DCU is iterated in the future, only the hardware feature library (such as the number of FP64 computing units and the number of TCC channels) needs to be updated to adapt quickly, shortening the adaptation cycle from several months to several days.

[0099] This invention has been verified on the Z100 model DCU. The generated DGEMM code outperforms the ROCm native BLAS library (by about 12%), and performs stably in relevant scenarios of the TOP500 evaluation, providing key technical support for the independent construction of domestic high-performance computing clusters.

[0100] Figure 2 This is a flowchart illustrating the DCU-based performance modeling and code generation method provided in Embodiment 2 of the present invention. The implementation process of the present invention consists of five major steps: "hardware feature extraction → performance model construction → parameter analysis → code generation → performance verification". The specific steps are as follows:

[0101] Step S201: Extract hardware features. Collect DCU hardware features and build a hardware feature library using the DCU hardware features.

[0102] Preferably, core DCU hardware features are collected and a feature library is built using the official DCU documentation and testing tools.

[0103] Preferably, the DCU is a Haiguang DCU.

[0104] Preferably, the step of extracting hardware features further includes:

[0105] (11) Extract the features of the computing unit, and collect the number of computing units (CU), the number of single instruction multiple data (SIMD) components of each computing unit, the number of double precision computing channels and / or the core frequency, etc.

[0106] (12) Extract storage structure features sub-step, collect LDS (Local Shared Storage) size, number and bit width of storage banks, size of L2 cache, global storage bandwidth and / or number of TCC (Texture Cache Channels), etc.

[0107] (13) Extract thread scheduling features sub-step, collect Wavefront (thread group) size, maximum number of Wavefront (thread groups) supported by each computing unit and / or register (VGPR / SGPR) capacity, etc.

[0108] (14) Micro-architecture feature verification sub-step: Through custom assembly test cases, verify the key micro-architecture details of DCU, including LDS (Local Shared Storage) memory access path, TCC (Texture Cache Channel) scheduling rules and / or thread group synchronization delay, etc., to provide a basis for subsequent modeling.

[0109] Step S202, the performance model construction step, constructs a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics.

[0110] Preferably, starting from the DCU (Deep Computing Unit) microarchitecture, the DGEMM execution flow is decomposed into three major modules: “computation-memory access-synchronization”, and a refined model is established for each module.

[0111] Preferably, the step of constructing the performance model further includes:

[0112] (21) The main body of the loop is to calculate the modeling sub-step. Combining the instruction issuance rules of SIMD (Single Instruction Multiple Data) of DCU with the characteristics of the computation pipeline, the instruction execution time when the thread calculates the sub-matrix is ​​analyzed, and the superposition effect of parallel computation of multi-thread groups is considered.

[0113] Preferably, based on the characteristics of the DCU SIMD components (4 per SIMD, 16 channels per lane) and the FMA instruction pipeline, the instruction issue time and latency are quantitatively calculated, taking into account the impact of Wavefront (thread group) scheduling on instruction parallelism.

[0114] (22) Modeling sub-steps for memory access process: For local shared memory access, analyze the impact of bank conflicts on bandwidth and quantify memory access time; for global memory access, combine cache hit rules and TCC (texture cache channel) scheduling characteristics to calculate the time overhead of data reading and writing.

[0115] Preferably, a memory bank conflict avoidance model is established for LDS storage (32 banks, 512bit / Cycle Path bandwidth), and the memory access time overhead is quantified by combining the L2 Cache FIFO queue assumption with GM (Global Memory) memory access (HBM2 bandwidth, TCC scheduling).

[0116] (23) Synchronization and data dependency modeling sub-steps: analyze the data dependency relationship within the thread group, quantify the parallel collaboration effect of computation and memory access, and consider the impact of the execution delay of thread block synchronization instructions on the overall performance.

[0117] Preferably, based on the lifecycle of the Wavefront (thread group) within the CU, a time model is established for data dependencies (such as the S_waitcnt instruction waiting logic) and thread block synchronization (S_barrier) to avoid scheduling empty bubbles.

[0118] Technical results: Validated on the Z100 model DCU, the average relative error of the matrix performance prediction is ≤5%, and the prediction error of large-scale matrices (such as 8192×8192) is ≤4%. The accuracy is significantly better than existing heuristic methods, and it can replace brute-force search to guide parameter selection.

[0119] Step S203, the parameter analysis model construction step, involves constructing a parameter analysis model based on the DCU hardware resource constraints and the performance model, and automatically selecting optimization parameters through the parameter analysis model.

[0120] Preferably, a parameter filtering engine is constructed by taking DCU hardware resources (number of registers, LDS size, number of CU computing units) as constraints and combining them with a performance model.

[0121] Preferably, the step of constructing the parameter analysis model further includes:

[0122] (31) Define hardware resource constraints: limit DCU hardware resource constraints to register capacity and LDS storage size, define the range of thread block size and / or loop unrolling times, and exclude infeasible parameter combinations. Based on the DCU hardware constraints, narrow down the parameter search range.

[0123] Preferably, the selectable range of thread block size (MTI / MTJ) and loop unrolling count (Depth) is defined based on the VGPR / SGPR register capacity and LDS storage size, excluding infeasible parameter combinations.

[0124] (32) Define the thread block size sub-step. Based on the LDS (Local Shared Storage) capacity limit, determine the partition size of the thread block in the matrix dimension.

[0125] (33) Defining the number of loop unrolling sub-steps: Based on the register capacity limit, determine the reasonable range of loop unrolling.

[0126] (34) Define the thread block reordering parameter sub-step: Based on the TCC (texture cache channel) scheduling characteristics, determine the available schemes for thread block reordering.

[0127] (35) Optimal parameter selection sub-step: With the goal of calculating instruction ratio, cache hit rate and / or performance prediction value, evaluate the parameter combinations that meet the DCU hardware constraints and select the parameter combination with the best overall performance. For example, thread block size 16×16, loop unrolling count 4, thread block rearrangement parameters 8, etc.

[0128] Preferably, with the goal of "maximizing the proportion of FMA instructions, maximizing the L2 cache hit rate, and optimizing the performance model prediction value", the optimal parameters (such as MTI=MTJ=16, TTI=TTJ=8, Depth=4, WGM=8) are quickly selected by calculating the difference between the parameter combination and the theoretical optimal solution through normalized Euclidean distance.

[0129] Technical results: The parameter search space is reduced by more than 90%, avoiding the time-consuming problem of brute-force search; the selected optimal parameters achieve a DGEMM efficiency of ≥92% on the Z100 model DCU, which is better than the performance of the default parameters generated by the Tensile tool (improvement of about 15%).

[0130] Step S204, Assembly code generation step: Build a customized code generation tool. The code generation tool automatically generates assembly code for double-precision dense matrix multiplication based on optimization parameters.

[0131] Preferably, the assembly code generation step further includes:

[0132] (41) The code generation tool sub-step is to build a code generation tool with automated code generation logic based on the DCU instruction set and the double-buffered DGEMM algorithm.

[0133] Preferably, an automated code generation logic is designed based on the DCU GFX9 instruction set and the dual-buffered DGEMM algorithm.

[0134] (42) Meta-information generation sub-step: The code generation tool automatically generates the meta-information required for runtime, clarifying key configurations such as code version, instruction set version, and register usage.

[0135] Preferably, based on the VGPR / SGPR usage output by the parameter analysis model, HSA runtime metadata (such as .hsa_code_object_version, workitem_vgpr_count) and register mapping table are automatically generated.

[0136] (43) Register assignment sub-step: The code generation tool automatically allocates registers for storing matrix data, temporary results and / or address information based on the optimization parameters output by the parameter analysis model.

[0137] (44) The memory access instruction generation sub-step optimizes address allocation and avoids bank conflicts when the code generation tool generates local shared memory access instructions; and enables direct memory access features to reduce data transfer when generating global memory access instructions.

[0138] Preferably, the LDS memory access address calculation logic is automatically generated (avoiding bank conflicts) and the GM (Global Memory) direct access instruction is generated (utilizing the DCU Direct to LDS feature) to reduce data transfer paths.

[0139] (45) The loop and synchronization implementation sub-steps are generated by the code generation tool based on the number of loop expansions, integrating double-buffered soft pipeline and thread block rearrangement logic; and generating tail loop processing code for non-standard matrix sizes.

[0140] Preferably, the loop unrolling code is automatically generated based on the Depth parameter, and the WGM thread block rearrangement and double-buffered soft pipeline logic are integrated. The tail loop processing supports matrix sizes that are not powers of 2.

[0141] (46) The data write-back sub-step is an instruction generated by the code generation tool to write the result matrix back to the global storage, ensuring that the data storage location is accurate.

[0142] (47) Code simplification sub-step: redundant instructions are removed by code generation tools.

[0143] Preferably, redundant instructions (such as useless Magic Numbers) are removed, and the code size is kept to within 1200 lines, far less than the 4000+ lines of code generated by Tensile.

[0144] Technical results: The generated code achieves 93.9% of the theoretical peak performance on the Z100 model DCU, which is comparable to the performance of manually optimized code; the code generation time is ≤10 seconds, and it supports automatic adaptation to Z100 and K100 DCUs without the need to modify the generation logic.

[0145] Step S205, performance testing step: run the generated assembly code on the target DCU to test the actual performance indicators under different matrix sizes, and record indicators such as cache hit rate and global storage bandwidth utilization.

[0146] Step S206, model correction step: compare the actual performance indicators with the model predictions, and adjust the predetermined key parameters in the performance model and parameter analysis model to make the prediction error less than a predetermined threshold. Preferably, the prediction error is controlled within 5%.

[0147] Step S207, iterative optimization step: if the performance of the assembly code does not meet the predetermined conditions (e.g., below 90%), backtrack the parameter analysis stage to adjust the parameter combination (e.g., increase the expansion depth and optimize the thread block mapping), regenerate new assembly code and test it until the performance meets the predetermined conditions.

[0148] Through the above steps, this invention can quickly realize the automatic generation and optimization of high-performance DGEMM code on DCU, and supports flexible adaptation to different generations of DCU, providing key technical support for the construction of a domestic high-performance computing ecosystem.

[0149] It should be noted that the DCU-based performance modeling and code generation method provided in this embodiment of the invention can be executed by an electronic device, a apparatus, or a control module within that apparatus for executing the method. This embodiment of the invention uses an apparatus executing the method as an example to illustrate the DCU-based performance modeling and code generation apparatus provided in this embodiment of the invention.

[0150] Figure 3 This is a schematic diagram of the DCU-based performance modeling and code generation device provided in Embodiment 3 of the present invention. The device 100 includes a performance model building module 10, a parameter analysis model building module 20, and an assembly code generation module 30, wherein:

[0151] The performance model building module 10 is used to build a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics.

[0152] Preferably, the performance model building module 10 further performs the following actions:

[0153] The computation modeling of the loop body is based on the instruction issuance rules and computational pipeline characteristics of the DCU's single instruction multiple data (SID) architecture. The instruction execution time when the thread computes the submatrix is ​​analyzed, and the superposition effect of parallel computation of multiple thread groups is considered.

[0154] The memory access process is modeled. For local shared memory access, the impact of memory conflicts on bandwidth is analyzed and memory access time is quantified. For global memory access, the time overhead of data reading and writing is calculated by combining cache hit rules and texture cache channel scheduling characteristics.

[0155] Synchronization and data dependency modeling are used to analyze data dependencies within thread groups, quantify the parallel synergy between computation and memory access, and consider the impact of the execution latency of thread block synchronization instructions on overall performance.

[0156] The parameter analysis model construction module 20 is used to construct a parameter analysis model based on the DCU hardware resource constraints and the performance model, and to automatically select optimization parameters through the parameter analysis model.

[0157] Preferably, the parameter analysis model construction module 20 further performs the following actions:

[0158] Define hardware resource constraints, limiting DCU hardware resource constraints to register capacity and LDS storage size, defining the range of thread block size and / or loop unrolling times, and excluding infeasible parameter combinations.

[0159] Define the size of the thread block and determine the partition size of the thread block in the matrix dimension based on the local shared memory capacity limit.

[0160] Define the number of loop unrolls: Based on the register capacity limit, determine the reasonable range of loop unrolls.

[0161] Define thread block reordering parameters: Based on the texture cache channel scheduling characteristics, determine the available thread block reordering schemes.

[0162] Optimal parameter selection: Using the proportion of computational instructions, cache hit rate and / or performance prediction as objectives, parameter combinations that meet the DCU hardware constraints are evaluated, and the parameter combination with the best overall performance is selected.

[0163] The assembly code generation module 30 is used to build a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on optimization parameters.

[0164] Preferably, the assembly code generation module 30 further performs the following actions:

[0165] A code generation tool with automated code generation logic is built based on the DCU instruction set and the double-buffered DGEMM algorithm.

[0166] Metadata generation: The code generation tool automatically generates the metadata required for runtime.

[0167] Register assignment is the automatic allocation of registers for storing matrix data, temporary results, and / or address information by the code generation tool based on the optimization parameters output by the parameter analysis model.

[0168] Memory access instruction generation: When generating local shared memory access instructions, the code generation tool optimizes address allocation, and when generating global memory access instructions, it enables direct memory access.

[0169] The loop and synchronization are implemented by a code generation tool that generates the main loop code based on the number of loop unrollings. It integrates double-buffered soft pipelining and thread block rearrangement logic, and generates tail loop processing code for non-standard matrix sizes.

[0170] The data is written back, and the result matrix generated by the code generation tool is written back to global storage.

[0171] The code is streamlined by removing redundant instructions using a code generation tool.

[0172] Preferably, the DCU is a Haiguang DCU.

[0173] Figure 4 This is a schematic diagram of the DCU-based performance modeling and code generation device provided in Embodiment 4 of the present invention. The device 100 includes a performance model building module 10, a parameter analysis model building module 20, an assembly code generation module 30, a performance testing module 40, a model correction module 50, an iterative optimization module 60, and a hardware feature extraction module 70, wherein:

[0174] The hardware feature extraction module 70 is used to collect DCU hardware features and construct a hardware feature library based on the DCU hardware features, which is further used for execution:

[0175] Extract computing unit features, and collect the number of computing units, the number of single instruction multiple data components in each computing unit, the number of double precision computing channels, and / or the core clock frequency.

[0176] Extract storage structure features, including local shared storage size, number and bit width of storage volumes, L2 cache size, global storage bandwidth, and / or number of texture cache channels.

[0177] Extract thread scheduling features, and collect thread group size, maximum number of thread groups supported by each computing unit, and / or register capacity.

[0178] Microarchitectural feature verification involves verifying key microarchitectural details of the DCU, including local shared memory access paths, texture cache channel scheduling rules, and / or thread group synchronization latency, through custom assembly test cases.

[0179] The performance model building module 10 is used to build a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics.

[0180] Preferably, the performance model building module 10 further performs the following actions:

[0181] The computation modeling of the loop body is based on the instruction issuance rules and computational pipeline characteristics of the DCU's single instruction multiple data (SID) architecture. The instruction execution time when the thread computes the submatrix is ​​analyzed, and the superposition effect of parallel computation of multiple thread groups is considered.

[0182] The memory access process is modeled. For local shared memory access, the impact of memory conflicts on bandwidth is analyzed and memory access time is quantified. For global memory access, the time overhead of data reading and writing is calculated by combining cache hit rules and texture cache channel scheduling characteristics.

[0183] Synchronization and data dependency modeling are used to analyze data dependencies within thread groups, quantify the parallel synergy between computation and memory access, and consider the impact of the execution latency of thread block synchronization instructions on overall performance.

[0184] The parameter analysis model construction module 20 is used to construct a parameter analysis model based on the DCU hardware resource constraints and the performance model, and to automatically select optimization parameters through the parameter analysis model.

[0185] Preferably, the parameter analysis model construction module 20 further performs the following actions:

[0186] Define hardware resource constraints, limiting DCU hardware resource constraints to register capacity and LDS storage size, defining the range of thread block size and / or loop unrolling times, and excluding infeasible parameter combinations.

[0187] Define the size of the thread block and determine the partition size of the thread block in the matrix dimension based on the local shared memory capacity limit.

[0188] Define the number of loop unrolls: Based on the register capacity limit, determine the reasonable range of loop unrolls.

[0189] Define thread block reordering parameters: Based on the texture cache channel scheduling characteristics, determine the available thread block reordering schemes.

[0190] Optimal parameter selection: Using the proportion of computational instructions, cache hit rate and / or performance prediction as objectives, parameter combinations that meet the DCU hardware constraints are evaluated, and the parameter combination with the best overall performance is selected.

[0191] The assembly code generation module 30 is used to build a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on optimization parameters.

[0192] Preferably, the assembly code generation module 30 further performs the following actions:

[0193] A code generation tool with automated code generation logic is built based on the DCU instruction set and the double-buffered DGEMM algorithm.

[0194] Metadata generation: The code generation tool automatically generates the metadata required for runtime.

[0195] Register assignment is the automatic allocation of registers for storing matrix data, temporary results, and / or address information by the code generation tool based on the optimization parameters output by the parameter analysis model.

[0196] Memory access instruction generation: When generating local shared memory access instructions, the code generation tool optimizes address allocation, and when generating global memory access instructions, it enables direct memory access.

[0197] The loop and synchronization are implemented by a code generation tool that generates the main loop code based on the number of loop unrollings. It integrates double-buffered soft pipelining and thread block rearrangement logic, and generates tail loop processing code for non-standard matrix sizes.

[0198] The data is written back, and the result matrix generated by the code generation tool is written back to global storage.

[0199] The code is streamlined by removing redundant instructions using a code generation tool.

[0200] The performance testing module 40 is used to run the generated assembly code on the target DCU to test the actual performance indicators under different matrix sizes.

[0201] The model correction module 50 is used to compare the actual performance indicators with the model prediction values, and adjust the predetermined key parameters in the performance model and parameter analysis model so that the prediction error is less than a predetermined threshold.

[0202] The iterative optimization module 60 is used to adjust the parameter combination by backtracking the parameter analysis stage, regenerate new assembly code, and test it if the performance of the assembly code does not meet the predetermined conditions, until the performance meets the predetermined conditions.

[0203] The DCU-based performance modeling and code generation apparatus provided in this embodiment of the invention can achieve Figures 1-2 The various processes implemented in the DCU-based performance modeling and code generation method embodiment shown are not described in detail here to avoid repetition.

[0204] The DCU-based performance modeling and code generation device provided in this embodiment includes: (1) a performance model building module, used to build a three-in-one performance model of computation, memory access, and synchronization based on the collected DCU hardware characteristics, so as to achieve an average relative error of ≤5% in matrix performance prediction, providing a theoretical basis for the selection of optimization parameters. (2) a parameter analysis model building module, used to build a parameter analysis model based on the DCU hardware resource constraints and the performance model, and automatically select optimization parameters through the parameter analysis model, and automatically select the optimal algorithm parameters (such as thread block size, loop unrolling times), which can greatly reduce the threshold for developers. (3) an assembly code generation module, used to build a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters. After receiving the optimal parameters, efficient assembly code is automatically generated, and the code performance reaches more than 93.9% of the theoretical performance of DCU. Thus, this invention supports the rapid adaptation of different generations of DCU through an integrated automatic toolchain of "performance modeling-parameter analysis-code generation", and realizes the autonomous and efficient optimization of DCU-DGEMM.

[0205] The present invention also provides a storage medium for storing, for example, Figures 1-2 The computer program of any of the DCU-based performance modeling and code generation methods, such as computer program instructions, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operation of the computer, and can achieve the same technical effect. To avoid repetition, it will not be described again here. The program instructions that invoke the methods of the present invention may be stored in a fixed or removable storage medium, and / or transmitted through a data stream in a broadcast or other signal carrying medium, and / or stored in the storage medium of a computer device that operates according to the program instructions.

[0206] According to one embodiment of the present invention, the present invention also provides such a Figure 5The illustrated electronic device 400 may optionally include a storage medium 200 for storing computer programs and a processor 300 for executing the computer programs. When the computer program is executed by the processor 300, it implements any of the aforementioned DCU-based performance modeling and code generation methods, triggering the electronic device 400 to execute methods and / or technical solutions based on the foregoing embodiments, achieving the same technical effect. To avoid repetition, these methods will not be elaborated upon here. It should be noted that the electronic devices in this embodiment include mobile electronic devices and non-mobile electronic devices. For example, mobile electronic devices may be mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, wearable devices, super mobile personal computers, netbooks, or personal digital assistants, etc., while non-mobile electronic devices may be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This embodiment does not specifically limit the scope of the invention.

[0207] It should be noted that the present invention can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of the present invention can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present invention (including associated data structures) can be stored in a computer-readable recording medium, such as RAM memory, a magnetic or optical drive, a floppy disk, or similar devices. Furthermore, some steps or functions of the present invention can be implemented in hardware, for example, as circuitry that works with a processor to perform the various steps or functions.

[0208] This invention can be implemented on a computer as a computer-based method, or in dedicated hardware, or a combination of both. Executable code or portions thereof for the method according to the invention can be stored on a computer program product. Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Optionally, the computer program product includes non-transitory program code components stored on a computer-readable medium so as to execute the method according to the invention when the program product is executed on a computer.

[0209] In an optional embodiment, the computer program includes computer program code components adapted to perform all the steps of the method according to the invention when the computer program is run on a computer. Optionally, the computer program is embodied on a computer-readable medium.

[0210] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0211] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A performance modeling and code generation method based on DCU, characterized in that, include: The steps for building a performance model are as follows: Based on the collected DCU hardware characteristics, a performance model integrating computing, memory access, and synchronization is constructed. The steps for constructing a parameter analysis model are as follows: based on the DCU hardware resource constraints and combined with the performance model, a parameter analysis model is constructed, and optimization parameters are automatically selected through the parameter analysis model. The assembly code generation step involves building a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters.

2. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, The step of constructing the performance model further includes: The main computational modeling sub-steps of the loop are combined with the instruction issuance rules and computational pipeline characteristics of the DCU's single instruction multiple data, and the instruction execution time when the thread computes the submatrix is ​​analyzed, taking into account the superposition effect of parallel computation of multiple thread groups. The memory access process modeling sub-steps analyze the impact of memory conflicts on bandwidth and quantify memory access time for local shared memory access, and calculate the time overhead of data reading and writing by combining cache hit rules and texture cache channel scheduling characteristics for global memory access. The synchronization and data dependency modeling sub-steps analyze the data dependencies within the thread group, quantify the parallel synergy between computation and memory access, and consider the impact of the execution latency of thread block synchronization instructions on overall performance.

3. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, The step of constructing the parameter analysis model further includes: The hardware resource constraint sub-step limits the DCU hardware resource constraints to register capacity and LDS storage size, defines the range of thread block size and / or loop unrolling times, and excludes infeasible parameter combinations. The sub-step for defining the thread block size involves determining the partition size of the thread block in the matrix dimension based on the local shared memory capacity limit. Determine the number of loop unrolling sub-steps: Based on register capacity limitations, clarify the reasonable range for loop unrolling; Defining thread block reordering parameters: Based on the characteristics of texture cache channel scheduling, determine the available schemes for thread block reordering; The optimal parameter selection sub-step involves evaluating parameter combinations that meet the DCU hardware constraints, with the goal of calculating instruction ratio, cache hit rate, and / or performance prediction value, and selecting the parameter combination with the best overall performance.

4. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, The assembly code generation step further includes: The sub-step of constructing a code generation tool involves building the code generation tool with automated code generation logic based on the DCU instruction set and the double-buffered DGEMM algorithm. The metadata generation sub-step involves the code generation tool automatically generating the metadata required at runtime. The register assignment sub-step involves the code generation tool automatically allocating registers for storing matrix data, temporary results, and / or address information based on the optimization parameters output by the parameter analysis model. The memory access instruction generation sub-step optimizes address allocation when generating local shared memory access instructions by the code generation tool and enables direct memory access features when generating global memory access instructions. The loop and synchronization implementation sub-steps are generated by the code generation tool based on the number of loop unrollings, which integrates double-buffered soft pipelining and thread block rearrangement logic, and generates tail loop processing code for non-standard matrix sizes. The data write-back sub-step involves the code generation tool generating a result matrix and writing it back to global storage. The code simplification sub-step involves the code generation tool removing redundant instructions.

5. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, Prior to the step of constructing the performance model, the following is included: The hardware feature extraction step, which involves collecting DCU hardware features and constructing a hardware feature library using the DCU hardware features, further includes: The sub-step for extracting computing unit features involves collecting the number of computing units, the number of single instruction multiple data units (SIDs) per computing unit, the number of double precision computing channels, and / or the core clock frequency. The sub-step for extracting storage structure features includes collecting data on local shared storage size, number and bit width of storage volumes, L2 cache size, global storage bandwidth, and / or number of texture cache channels. The thread scheduling feature extraction sub-step involves collecting the thread group size, the maximum number of thread groups supported by each computing unit, and / or the register capacity. The microarchitecture feature verification sub-step verifies key microarchitecture details of the DCU, including local shared memory access paths, texture cache channel scheduling rules, and / or thread group synchronization latency, through custom assembly test cases.

6. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, The assembly code generation step is followed by: The performance testing steps involve running the generated assembly code on the target DCU to test the actual performance metrics under different matrix sizes. The model correction step involves comparing the actual performance indicators with the model predictions and adjusting the predetermined key parameters in the performance model and the parameter analysis model to make the prediction error less than a predetermined threshold. In the iterative optimization step, if the performance of the assembly code does not meet the predetermined conditions, the parameter analysis step is backtracked to adjust the parameter combination, new assembly code is regenerated and tested, until the performance meets the predetermined conditions.

7. The DCU-based performance modeling and code generation method according to claim 1, characterized in that, The DCU is a Haiguang DCU.

8. A DCU-based performance modeling and code generation apparatus constructed based on the method described in any one of claims 1 to 7, characterized in that, The device includes: The performance model building module is used to build a three-in-one performance model of computing, memory access, and synchronization based on the collected DCU hardware characteristics. A parameter analysis model building module is used to build a parameter analysis model based on the DCU hardware resource constraints and the performance model, and to automatically select optimization parameters through the parameter analysis model. An assembly code generation module is used to build a customized code generation tool, which automatically generates assembly code for double-precision dense matrix multiplication based on the optimization parameters.

9. A storage medium, characterized in that, Used to store a computer program for performing the method according to any one of claims 1 to 7.

10. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 7.

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