Data driver and electronic device

Abstract

A data driver of a display device and an electronic device are provided, the data driver including: first to Nth data latches, where N is an integer greater than 1; first to (N + 1) th channel circuits; a first multiplexer; and a second multiplexer. In a first period, the first multiplexer connects the first to Nth data latches to the first to Nth channel circuits, respectively, and the second multiplexer connects the first to Nth data lines to the first to Nth channel circuits, respectively. In a second period, the first multiplexer connects the first to Nth data latches to the second to (N + 1) th channel circuits, respectively, and the second multiplexer connects the first to Nth data lines to the second to (N + 1) th channel circuits, respectively.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device, and more specifically to a data driver and an electronic device including the data driver. Background Technology

[0002] Typically, a display device may include a display panel comprising multiple pixels, a data driver, a scan driver, and a controller. The data driver provides data voltages to the multiple pixels, the scan driver provides scan signals to the multiple pixels, and the controller controls the data driver and the scan driver.

[0003] A data driver may include multiple channels or multiple channel circuits that output data voltages to multiple data lines of a display panel. Summary of the Invention

[0004] In a display device, image quality may be degraded due to voltage deviations or offsets between the data voltages output by multiple channel circuits in the display device's data driver. Furthermore, if the offset between the data voltages output by the multiple channel circuits exceeds a reference offset, the data driver may be rendered unusable.

[0005] Some embodiments provide a data driver capable of reducing voltage deviations or offsets between data voltages supplied to multiple data lines.

[0006] Some embodiments provide an electronic device that includes a data driver.

[0007] According to an embodiment, a data driver for a display device is provided. The data driver includes: a first data latch to an Nth data latch, where N is an integer greater than 1; a first channel circuit to an (N+1)th channel circuit; a first multiplexer connected between the first data latches to the Nth data latch and the first channel circuit to the (N+1)th channel circuit; and a second multiplexer connected between the first channel circuit to the (N+1)th channel circuit and the first data line to the Nth data line. In such an embodiment, during a first time period, the first multiplexer connects the first data latches to the Nth data latch to the first channel circuit to the Nth channel circuit, and the second multiplexer connects the first data line to the Nth data line to the first channel circuit to the Nth channel circuit, respectively. In such an embodiment, during a second time period, the first multiplexer connects the first data latches to the Nth data latch to the second channel circuit to the (N+1)th channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the second channel circuit to the (N+1)th channel circuit, respectively.

[0008] In an embodiment, during a first time period, the Kth channel circuit among the first channel circuit to the N+1th channel circuit can output a data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N. Furthermore, during a second time period, the K+1th channel circuit among the first channel circuit to the N+1th channel circuit can output a data voltage to the Kth data line.

[0009] In an embodiment, the Kth channel circuit among the first channel circuit to the (N+1)th channel circuit may include: a level shifter that performs a level shift operation on image data received from the Kth data latch among the first data latch to the Nth data latch in a first time period, and performs a level shift operation on image data received from the (K-1)th data latch among the first data latch to the Nth data latch in a second time period; a digital-to-analog converter that generates a data voltage by performing a digital-to-analog conversion operation on the image data output from the level shifter; and an output buffer that outputs the data voltage to the Kth data line among the first data line to the Nth data line in the first time period, and outputs the data voltage to the (K-1)th data line among the first data line to the Nth data line in the second time period, wherein K is an integer greater than or equal to 2 and less than or equal to N.

[0010] In the embodiment, during the second time period, the first channel circuit may not be connected to the first data latch to the Nth data latch and the first data line to the Nth data line, and during the first time period, the N+1 channel circuit may not be connected to the first data latch to the Nth data latch and the first data line to the Nth data line.

[0011] In an embodiment, the first multiplexer may include: a plurality of first switches, which, in response to a first switch signal, respectively connect a first data latch to a Nth data latch to a first channel circuit to a Nth channel circuit; and a plurality of second switches, which, in response to a second switch signal, respectively connect a first data latch to a Nth data latch to a second channel circuit to a N+1th channel circuit.

[0012] In an embodiment, the second multiplexer may include: a plurality of third switches, which, in response to a first switch signal, respectively connect the first data line to the Nth data line to the first channel circuit to the Nth channel circuit; and a plurality of fourth switches, which, in response to a second switch signal, respectively connect the first data line to the Nth data line to the second channel circuit to the N+1th channel circuit.

[0013] In an embodiment, the data driver may further include: a switch signal generator that generates a first switch signal with an effective level in a first time period and generates a second switch signal with an effective level in a second time period.

[0014] In an embodiment, the first time period and the second time period can alternate with each other at each horizontal time.

[0015] In an embodiment, during odd-numbered horizontal times of the frame period, the first channel circuit to the Nth channel circuit can output data voltage to the first data line to the Nth data line, and during even-numbered horizontal times of the frame period, the second channel circuit to the N+1th channel circuit can output data voltage to the first data line to the Nth data line.

[0016] In an embodiment, the first time period and the second time period can alternate with each other every L horizontal time periods, where L is an integer greater than 1.

[0017] In an embodiment, the first time period and the second time period can alternate with each other in each frame cycle.

[0018] In an embodiment, during odd-numbered frame periods, the first channel circuit to the Nth channel circuit can output data voltage to the first data line to the Nth data line, and during even-numbered frame periods, the second channel circuit to the N+1th channel circuit can output data voltage to the first data line to the Nth data line.

[0019] In an embodiment, the first time period and the second time period can alternate with each other every L frame periods, where L is an integer greater than 1.

[0020] According to an embodiment, a data driver for a display device is provided. In such an embodiment, the data driver includes: a first data latch to an Nth data latch, wherein N is an integer greater than 1; a first channel circuit to an (N+M)th channel circuit, wherein M is an integer greater than 1; a first multiplexer connected between the first data latches to the Nth data latch and the first channel circuit to the (N+1)th channel circuit; and a second multiplexer connected between the first channel circuit to the (N+1)th channel circuit and the first data line to the Nth data line. In such an embodiment, during a (P+1)th time period, the first multiplexer connects the first data latches to the Nth data latch to the (P+1)th channel circuit to the (N+P)th channel circuit, and the second multiplexer connects the first data line to the Nth data line to the (P+1)th channel circuit to the (N+P)th channel circuit, wherein P is an integer greater than or equal to 0 and less than or equal to M.

[0021] In an embodiment, during the P+1th time period, the K+Pth channel circuit among the first channel circuit to the N+Mth channel circuit can output the data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N.

[0022] According to an embodiment, an electronic device is provided, comprising: a processor for providing input image data; and a display device for receiving the input image data from the processor and displaying an image based on the input image data. In such an embodiment, the display device includes: a display panel including first data lines to Nth data lines and a plurality of pixels connected to the first data lines to Nth data lines, wherein N is an integer greater than 1; a scan driver for providing scan signals to the plurality of pixels; a data driver for providing data voltages to the plurality of pixels via the first data lines to Nth data lines; and a controller for controlling the scan driver and the data driver. In such an embodiment, the data driver includes: first data latches to Nth data latches; a first channel circuit to an (N+1)th channel circuit; a first multiplexer connected between the first data latches to Nth data latches and the first channel circuit to the (N+1)th channel circuit; and a second multiplexer connected between the first channel circuit to the (N+1)th channel circuit and the first data lines to Nth data lines. In this embodiment, during a first time period, a first multiplexer connects the first data latch to the Nth data latch to the first channel circuit to the Nth channel circuit, respectively, and a second multiplexer connects the first data line to the Nth data line to the first channel circuit to the Nth channel circuit, respectively. In this embodiment, during a second time period, the first multiplexer connects the first data latch to the Nth data latch to the second channel circuit to the (N+1)th channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the second channel circuit to the (N+1)th channel circuit, respectively.

[0023] In an embodiment, during a first time period, the Kth channel circuit among the first channel circuit to the N+1th channel circuit can output a data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N. Furthermore, during a second time period, the K+1th channel circuit among the first channel circuit to the N+1th channel circuit can output a data voltage to the Kth data line.

[0024] In an embodiment, the Kth channel circuit among the first channel circuit to the (N+1)th channel circuit may include: a level shifter that performs a level shift operation on image data received from the Kth data latch among the first data latch to the Nth data latch in a first time period, and performs a level shift operation on image data received from the (K-1)th data latch among the first data latch to the Nth data latch in a second time period; a digital-to-analog converter that generates a data voltage by performing a digital-to-analog conversion operation on the image data output from the level shifter; and an output buffer that outputs the data voltage to the Kth data line among the first data line to the Nth data line in the first time period, and outputs the data voltage to the (K-1)th data line among the first data line to the Nth data line in the second time period, wherein K is an integer greater than or equal to 2 and less than or equal to N.

[0025] In one embodiment, the first multiplexer may include: a plurality of first switches, each responding to a first switch signal to connect a first data latch to an Nth data latch to a first channel circuit to an Nth channel circuit; and a plurality of second switches, each responding to a second switch signal to connect a first data latch to an Nth data latch to a second channel circuit to an (N+1)th channel circuit. In such an embodiment, the second multiplexer may include: a plurality of third switches, each responding to a first switch signal to connect a first data line to an Nth data line to a first channel circuit to an Nth channel circuit; and a plurality of fourth switches, each responding to a second switch signal to connect a first data line to an Nth data line to a second channel circuit to an (N+1)th channel circuit.

[0026] In an embodiment, the data driver may further include: a switch signal generator that generates a first switch signal with an effective level in a first time period and generates a second switch signal with an effective level in a second time period.

[0027] As described above, in the data driver and electronic device according to the embodiments, the data driver may include a first channel circuit to a (N+1)th channel circuit relative to the first data line to the Nth data line, where N is an integer greater than 1. During a first time period, the first channel circuit to the Nth channel circuit may respectively output data voltages to the first data line to the Nth data line. During a second time period, the second channel circuit to the (N+1)th channel circuit may respectively output data voltages to the first data line to the Nth data line. Therefore, the voltage deviation or offset between the data voltages output to the first data line to the Nth data line can be reduced. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1This is a block diagram illustrating a data driver according to an embodiment.

[0030] Figure 2 It is used to describe Figure 1 A circuit diagram illustrating an example of the operation of a data driver in the first time period.

[0031] Figure 3 It is used to describe Figure 1 A circuit diagram illustrating an example of the operation of a data driver in the second time period.

[0032] Figure 4 It is used to describe from Figure 1 A diagram illustrating an example of the data voltage output by the data driver.

[0033] Figure 5 This is a signal timing diagram used to describe an example of the operation of a data driver according to an embodiment.

[0034] Figure 6 This is a signal timing diagram used to describe another example of the operation of a data driver according to an embodiment.

[0035] Figure 7 This is a signal timing diagram for describing yet another example of the operation of a data driver according to an embodiment.

[0036] Figure 8 This is a signal timing diagram for describing yet another example of the operation of a data driver according to an embodiment.

[0037] Figure 9 This is a block diagram illustrating a data driver according to an embodiment.

[0038] Figure 10 This is a signal timing diagram used to describe an example of the operation of a data driver according to an embodiment.

[0039] Figure 11 This is a signal timing diagram used to describe another example of the operation of a data driver according to an embodiment.

[0040] Figure 12 This is a block diagram illustrating a display device according to an embodiment.

[0041] Figure 13 This is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0042] Figure 14 This is a block diagram illustrating an example of an electronic device according to an embodiment. Detailed Implementation

[0043] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout denote the same elements.

[0044] It should be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be other elements or intermediary elements between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” and “the,” as well as “at least one,” do not indicate a limitation of quantity but are intended to include both the singular and plural forms. Thus, a reference to “the” element following a reference to an element in a claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” will not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising,” “including,” and / or variations thereof are used in this specification, it indicates the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to include different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be positioned “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can include both “below” and “above” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will subsequently be positioned “above” the other element. Thus, the terms “below” or “under” can include both “above” and “below” orientations.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless clearly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the context of this disclosure, and shall not be interpreted in an idealized or overly formalized sense.

[0049] Here, embodiments are described with reference to illustrative drawings of idealized embodiments. Thus, variations in the shapes of the drawings, for example, due to manufacturing techniques and / or tolerances, will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but will include, for example, deviations in shape due to manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the given claims.

[0050] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 This is a block diagram illustrating a data driver according to an embodiment. Figure 2 It is used to describe Figure 1 A circuit diagram illustrating an example of the operation of a data driver in the first time period. Figure 3 It is used to describe Figure 1 A circuit diagram illustrating an example of the operation of the data driver in the second time period. Figure 4 It is used to describe from Figure 1 A diagram showing an example of the data voltage output by the data driver.

[0052] Reference Figure 1 According to the embodiment, the data driver 100 may include a first data latch LAT1, a second data latch LAT2, a third data latch LAT3, a fourth data latch LAT4, ..., an (N-3)th data latch LATN-3, an (N-2)th data latch LATN-2, an (N-1)th data latch LATN-1 and an Nth data latch LATN (where N is an integer greater than 1), a first multiplexer MUX1, a first channel circuit CH1, a second channel circuit CH2, a third channel circuit CH3, a fourth channel circuit CH4, ..., an (N-3)th channel circuit CHN-3, an (N-2)th channel circuit CHN-2, an (N-1)th channel circuit CHN-1, an Nth channel circuit CHN and an N+1th channel circuit CHN+1, a second multiplexer MUX2, and a switch signal generator 150.

[0053] The first data latch LAT1 to the Nth data latch LATN can store data from the controller (e.g., Figure 12 The controller 750 shown receives image data (e.g., Figure 12 The output image data (ODAT) shown is illustrated. In an embodiment, for example, the first data latch LAT1 to the Nth data latch LATN can store image data for connecting to the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, ..., the (N-3)th data line DLN-3, the (N-2)th data line DLN-2, the (N-1)th data line DLN-1, and the Nth data line DLN in each horizontal time (or horizontal period). In some embodiments, the data driver 100 may also include, but is not limited to, a shift register that sequentially generates sampling signals and a plurality of sampling latches that sample image data received from the controller in response to the sampling signals. The first data latch LAT1 to the Nth data latch LATN can receive and store image data from the plurality of sampling latches in response to a load signal.

[0054] The first multiplexer MUX1 can be connected between the first data latches LAT1 to the Nth data latch LATN and the first channel circuits CH1 to the (N+1)th channel circuits CHN+1. The first multiplexer MUX1 can connect the first data latches LAT1 to the Nth data latch LATN to the first channel circuits CH1 to CHN respectively during a first time period, and can connect the first data latches LAT1 to the Nth data latch LATN to the second channel circuits CH2 to CHN+1 respectively during a second time period. In some embodiments, to perform such operation, a first multiplexer MUX1 may include N first switches SW1 and N second switches SW2. The N first switches SW1, in response to a first switch signal SWS1 having a valid level (e.g., a high level) during a first time period, respectively connect the first data latch LAT1 to the Nth data latch LATN to the first channel circuit CH1 to the Nth channel circuit CHN. The N second switches SW2, in response to a second switch signal SWS2 having a valid level during a second time period, respectively connect the first data latch LAT1 to the Nth data latch LATN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1.

[0055] The first channel circuit CH1 to the (N+1)th channel circuit CHN+1 can receive image data from the first data latch LAT1 to the Nth data latch LATN through the first multiplexer MUX1, and can output the data voltage corresponding to the image data to the first data line DL1 to the Nth data line DLN through the second multiplexer MUX2. In some embodiments, the first channel circuit CH1 to the (N+1)th channel circuit CHN+1 may include a first level shifter LS1, a second level shifter LS2, a third level shifter LS3, a fourth level shifter LS4, ..., the (N-3)th level shifter LSN-3, the (N-2)th level shifter LSN-2, the (N-1)th level shifter LSN-1, the Nth level shifter LSN and the (N+1)th level shifter LSN+1, a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a third digital-to-analog converter DAC3, and a fourth digital-to-analog converter DAC4. ..., the N-3rd digital-to-analog converter DACN-3, the N-2nd digital-to-analog converter DACN-2, the N-1st digital-to-analog converter DACN-1, the Nth digital-to-analog converter DACN and the N+1th digital-to-analog converter DACN+1, and the first output buffer OB1, the second output buffer OB2, the third output buffer OB3, the fourth output buffer OB4, ..., the N-3rd output buffer OBN-3, the N-2nd output buffer OBN-2, the N-1st output buffer OBN-1, the Nth output buffer OBN and the N+1th output buffer OBN+1.

[0056] In an embodiment, for example, the Kth channel circuit (where K is an integer greater than or equal to 2 and less than or equal to N) among the first channel circuit CH1 to the (N+1)th channel circuit CHN+1 (e.g., the second channel circuit CH2) may include a level shifter (e.g., the second level shifter LS2), a digital-to-analog converter (e.g., the second digital-to-analog converter DAC2), and an output buffer (e.g., the second output buffer OB2). The level shifter (e.g., the second level shifter LS2) may perform a level shift operation on image data received from the Kth data latch (e.g., the second data latch LAT2) in a first time period, and may perform a level shift operation on image data received from the (K-1)th data latch (e.g., the first data latch LAT1) in a second time period. The digital-to-analog converter (e.g., the second digital-to-analog converter DAC2) may generate a data voltage by performing a digital-to-analog conversion operation on the image data output from the level shifter (e.g., the second level shifter LS2). The output buffer (e.g., the second output buffer OB2) can output the data voltage to the Kth data line (e.g., the second data line DL2) in the first time period and output the data voltage to the (K-1)th data line (e.g., the first data line DL1) in the second time period.

[0057] The second multiplexer MUX2 can be connected between the first channel circuit CH1 to the (N+1)th channel circuit CHN+1 and the first data lines DL1 to the (N)th data lines DLN. The second multiplexer MUX2 can connect the first data lines DL1 to the (N)th data lines DLN to the first channel circuit CH1 to the (N)th channel circuit CHN respectively during a first time period, and can connect the first data lines DL1 to the (N)th data lines DLN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 respectively during a second time period. In some embodiments, to perform such operation, the second multiplexer MUX2 may include N third switches SW3 and N fourth switches SW4. The N third switches SW3, in a first time period, respond to a first switch signal SWS1 with an active level and respectively connect the first data line DL1 to the Nth data line DLN to the first channel circuit CH1 to the Nth channel circuit CHN. The N fourth switches SW4, in a second time period, respond to a second switch signal SWS2 with an active level and respectively connect the first data line DL1 to the Nth data line DLN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1.

[0058] The switch signal generator 150 can generate a first switch signal SWS1 with an active level and a second switch signal SWS2 with an inactive level (e.g., low level) during a first time period, and can generate the first switch signal SWS1 with an inactive level and the second switch signal SWS2 with an active level during a second time period. In some embodiments, such as Figure 5 As shown, the first and second time periods can alternate between each horizontal time period or each horizontal time period. In other embodiments, such as Figure 6 As shown, the first and second time periods can alternate every L horizontal time intervals or every L horizontal time intervals, where L is an integer greater than 1. In other embodiments, such as Figure 7 As shown, the first time period and the second time period can alternate with each other in each frame cycle. In other embodiments, such as... Figure 8 As shown, the first time period and the second time period can alternate with each other every L frame cycles, where L is an integer greater than 1.

[0059] In an embodiment, such as Figure 2 As shown, during the first time period P1, in response to the first switch signal SWS1 with an active level, the first switch SW1 of the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively. Similarly, the third switch SW3 of the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively. Therefore, during the first time period P1, the first channel circuit CH1 to the Nth channel circuit CHN can generate data voltages based on the image data stored in the first data latch LAT1 to the Nth data latch LATN, and output the data voltages to the first data lines DL1 to the Nth data lines DLN. Furthermore, during the first time period P1, the N+1th channel circuit CHN+1 can be disconnected from the first data latch LAT1 to the Nth data latch LATN and the first data lines DL1 to the Nth data lines DLN.

[0060] In such an embodiment, such as Figure 3As shown, in the second time period P2, in response to the second switch signal SWS2 with an active level, the second switch SW2 of the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1, respectively. The fourth switch SW4 of the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1, respectively. Therefore, in the second time period P2, the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 can generate a data voltage based on the image data stored in the first data latch LAT1 to the Nth data latch LATN, and can output the data voltage to the first data line DL1 to the Nth data line DLN. Furthermore, in the second time period P2, the first channel circuit CH1 can be disconnected from the first data latch LAT1 to the Nth data latch LATN and the first data line DL1 to the Nth data line DLN.

[0061] Therefore, since the first data line DL1 to the Nth data line DLN receive data voltages from the first channel circuit CH1 to the Nth channel circuit CHN respectively in the first time period P1, and receive data voltages from the second channel circuit CH2 to the N+1th channel circuit CHN+1 respectively in the second time period P2, the voltage deviation or offset between the data voltages output by the data driver 100 to the first data line DL1 to the Nth data line DLN according to the embodiment can be significantly reduced.

[0062] Figure 4 Examples are shown, including a distribution 220 of data voltages output to first data lines DL1 to Nth data lines DLN during a first time period P1, a distribution 240 of data voltages output to first data lines DL1 to Nth data lines DLN during a second time period P2, and a distribution 260 of the average data voltage between the data voltages in the first time period P1 and the data voltages in the second time period P2. In embodiments, for example, such as... Figure 4 As shown, in the first time period P1, the Kth channel circuit can output a first data voltage DV1 to the Kth data line DLK, and the first data voltage DV1 can have a first offset OFS1 relative to the average value AVG_DV of all data voltages output to the first data line DL1 to the Nth data line DLN. Figure 4In the example, the first offset OFS1 of the first data voltage DV1 output by the Kth channel circuit can be the largest offset among the offsets of the data voltages output to the first data line DL1 to the Nth data line DLN, and in this case, the first offset OFS1 can be referred to as the bias voltage output (“DVO”) of the data driver 100. In this case, the image quality may be degraded due to the first offset OFS1 (or DVO), or the data driver 100 may be discarded if the first offset OFS1 (or DVO) is greater than the reference offset. However, in the data driver 100 according to the embodiment, in the second time period P2, the K+1th channel circuit can output a second data voltage DV2 with an offset less than the first offset OFS1 to the Kth data line DLK. Furthermore, as referred to below Figures 5 to 8 As described, the first time period P1 and the second time period P2 can periodically alternate with each other. Therefore, as... Figure 4 As shown, the data voltage output to the Kth data line DLK can correspond to the average value ADV of the first data voltage DV1 and the second data voltage DV2, and the offset of the data voltage output to the Kth data line DLK can be reduced from the first offset OFS1 to the second offset OFS2. Therefore, even if the first offset OFS1 through the Kth channel circuit is greater than the reference offset, the offset of the data voltage output to the Kth data line DLK can become less than or equal to the reference offset, thereby improving image quality or effectively preventing the data driver 100 from being discarded.

[0063] As described above, the data driver 100 according to the embodiment may include first channel circuits CH1 to N+1 channel circuits CHN+1 relative to the first data lines DL1 to Nth data lines DLN. During a first time period P1, the first channel circuits CH1 to Nth channel circuits CHN can respectively output data voltages to the first data lines DL1 to Nth data lines DLN. During a second time period P2, the second channel circuits CH2 to N+1 channel circuits CHN+1 can respectively output data voltages to the first data lines DL1 to Nth data lines DLN. The first time period P1 and the second time period P2 can periodically alternate with each other. Therefore, the voltage deviation or offset between the data voltages output to the first data lines DL1 to Nth data lines DLN can be significantly reduced, and the DVO of the data driver 100 can be significantly reduced.

[0064] Figure 5 This is a signal timing diagram used to describe an example of the operation of a data driver according to an embodiment.

[0065] Reference Figure 1 and Figure 5The first channel circuit CH1 to the Nth channel circuit CHN respectively output data voltage to the first data line DL1 to the Nth data line DLN for a first time period P1, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 respectively output data voltage to the first data line DL1 to the Nth data line DLN for a second time period P2, which can alternate with each other for each horizontal time period. Here, the horizontal time (or horizontal time period) can be the duration or time period allocated to a pixel row of the display panel, and can correspond to the duration obtained by dividing the frame period FP by the number of pixel rows of the display panel.

[0066] During the first horizontal time HT1 when the data voltage is provided to the first pixel row, the first switch signal SWS1 can have an active level (e.g., high level), while the second switch signal SWS2 can have an inactive level (e.g., low level). Therefore, in response to the active first switch signal SWS1, the first switch SW1 of the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively, and the third switch SW3 of the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively. In this case, the Kth channel circuit can output the data voltage DV_CHK to the Kth data line DLK.

[0067] Subsequently, during the second horizontal time HT2 in which the data voltage is provided to the second pixel row, the first switch signal SWS1 can have an invalid level, while the second switch signal SWS2 can have an active level. Therefore, in response to the active level of the second switch signal SWS2, the second switch SW2 of the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1, respectively, and the fourth switch SW4 of the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the second channel circuit CH2 to the (N+1)th channel circuit CHN+1, respectively. In this case, the (K+1)th channel circuit can output the data voltage DV_CHK+1 to the Kth data line DLK.

[0068] Subsequently, during the third level time HT3 when the data voltage is provided to the third pixel row, the first switch signal SWS1 can be active, while the second switch signal SWS2 can be inactive. Furthermore, during the fourth level time HT4 when the data voltage is provided to the fourth pixel row, the first switch signal SWS1 can be inactive, while the second switch signal SWS2 can be active. Therefore, the first channel circuit CH1 to the Nth channel circuit CHN can output the data voltage to the first data line DL1 to the Nth data line DLN during odd level times HT1, HT3, etc., of the frame period FP, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 can output the data voltage to the first data line DL1 to the Nth data line DLN during even level times HT2, HT4, etc., of the frame period FP. Therefore, the data voltage output to the Kth data line DLK can alternate between the data voltage DV_CHK generated by the Kth channel circuit and the data voltage DV_CHK+1 generated by the K+1th channel circuit, and the offset of the data voltage output to the Kth data line DLK can be reduced.

[0069] Figure 6 This is a signal timing diagram used to describe another example of the operation of a data driver according to an embodiment.

[0070] Reference Figure 1 and Figure 6 The first channel circuit CH1 to the Nth channel circuit CHN respectively output data voltage to the first data line DL1 to the Nth data line DLN in the first time period P1, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 respectively output data voltage to the first data line DL1 to the Nth data line DLN in the second time period P2. These circuits can alternate every L horizontal time intervals, where L is an integer greater than 1. Although Figure 6 An embodiment with L=2 is shown, but the period of alternation between the first time period P1 and the second time period P2 is not limited to this. Figure 6 Examples.

[0071] In an embodiment, for example, such as Figure 6As shown, during the first level time HT1, second level time HT2, fifth level time HT5, and sixth level time HT6, the first switch signal SWS1 can have an active level (e.g., high level), the second switch signal SWS2 can have an inactive level (e.g., low level), and the first channel circuit CH1 to the Nth channel circuit CHN can respectively output data voltages to the first data line DL1 to the Nth data line DLN. In such an embodiment, during the third level time period HT3, fourth level time period HT4, seventh level time period HT7, and eighth level time period HT8, the first switch signal SWS1 can have an inactive level, the second switch signal SWS2 can have an active level, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 can respectively output data voltages to the first data line DL1 to the Nth data line DLN. Therefore, the data voltage output to the Kth data line DLK can alternate between the data voltage DV_CHK generated by the Kth channel circuit and the data voltage DV_CHK+1 generated by the (K+1)th channel circuit, and the offset of the data voltage output to the Kth data line DLK can be reduced.

[0072] Figure 7 This is a signal timing diagram for describing yet another example of the operation of a data driver according to an embodiment.

[0073] Reference Figure 1 and Figure 7 The first channel circuit CH1 to the Nth channel circuit CHN respectively outputs data voltage to the first data line DL1 to the Nth data line DLN in the first time period P1, and the second channel circuit CH2 to the N+1th channel circuit CHN+1 respectively outputs data voltage to the first data line DL1 to the Nth data line DLN in the second time period P2, which can alternate with each other in each frame period FP.

[0074] In an embodiment, for example, such as Figure 7As shown, in odd-numbered frame periods FP1, FP3, etc., the first switch signal SWS1 can have an active level (e.g., high level), the second switch signal SWS2 can have an inactive level (e.g., low level), and the first channel circuit CH1 to the Nth channel circuit CHN can respectively output data voltages to the first data line DL1 to the Nth data line DLN. In such an embodiment, in even-numbered frame periods FP2, FP4, etc., the first switch signal SWS1 can have an inactive level, the second switch signal SWS2 can have an active level, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 can respectively output data voltages to the first data line DL1 to the Nth data line DLN. Therefore, the data voltage output to the Kth data line DLK can alternate between the data voltage DV_CHK generated by the Kth channel circuit and the data voltage DV_CHK+1 generated by the (K+1)th channel circuit, and the offset of the data voltage output to the Kth data line DLK can be reduced.

[0075] Figure 8 This is a signal timing diagram for describing yet another example of the operation of a data driver according to an embodiment.

[0076] Reference Figure 1 and Figure 8 The first channel circuit CH1 to the Nth channel circuit CHN respectively output data voltage to the first data line DL1 to the Nth data line DLN in the first time period P1, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 respectively output data voltage to the first data line DL1 to the Nth data line DLN in the second time period P2. These circuits can alternate every L frame periods, where L is an integer greater than 1. Although Figure 8 An embodiment where L is 2 is shown, but the period in which the first time period P1 and the second time period P2 alternate is not limited to... Figure 8 Examples.

[0077] In an embodiment, for example, such as Figure 8As shown, in the first frame period FP1, the second frame period FP2, the fifth frame period FP5, and the sixth frame period FP6, the first switch signal SWS1 can have an active level (e.g., high level), the second switch signal SWS2 can have an inactive level (e.g., low level), and the first channel circuit CH1 to the Nth channel circuit CHN can respectively output data voltages to the first data line DL1 to the Nth data line DLN. In such an embodiment, in the third frame period FP3, the fourth frame period FP4, the seventh frame period FP7, and the eighth frame period FP8, the first switch signal SWS1 can have an inactive level, the second switch signal SWS2 can have an active level, and the second channel circuit CH2 to the (N+1)th channel circuit CHN+1 can respectively output data voltages to the first data line DL1 to the Nth data line DLN. Therefore, the data voltage output to the Kth data line DLK can alternate between the data voltage DV_CHK generated by the Kth channel circuit and the data voltage DV_CHK+1 generated by the (K+1)th channel circuit, and the offset of the data voltage output to the Kth data line DLK can be reduced.

[0078] Figure 9 This is a block diagram illustrating a data driver according to an embodiment. Figure 10 This is a signal timing diagram used to describe an example of the operation of a data driver according to an embodiment. Figure 11 This is a signal timing diagram used to describe another example of the operation of a data driver according to an embodiment.

[0079] Reference Figure 9 According to the embodiment, the data driver 300 may include a first data latch LAT1 to the Nth data latch LATN, a first channel circuit CH1, a second channel circuit CH2, a third channel circuit CH3, a fourth channel circuit CH4, ..., the (N-3)th channel circuit CHN-3, the (N-2)th channel circuit CHN-2, the (N-1)th channel circuit CHN-1, the Nth channel circuit CHN, the (N+1)th channel circuit CHN+1, ..., the (N+M)th channel circuit CHN+M (where M is an integer greater than 1), a first multiplexer MUX1 connected between the first data latch LAT1 to the Nth data latch LATN and the first channel circuit CH1 to the (N+M)th channel circuit CHN+M, a second multiplexer MUX2 connected between the first channel circuit CH1 to the (N+M)th channel circuit CHN+M and the first data line DL1 to the Nth data line DLN, and a switch signal generator 350. In addition to the data driver 300 including the first channel circuit CH1 to the (N+M)th channel circuit CHN+M relative to the first data line DL1 to the Nth data line DLN, Figure 9 The data drive 300 can have the same characteristics as... Figure 1The data drive 100 has a similar construction and similar operation.

[0080] The switch signal generator 350 can generate first switch signals SWS1 to M+1th switch signals SWSM+1. During the P+1th time period, where P is an integer greater than or equal to 0 and less than or equal to M, the P+1th switch signal among the first switch signals SWS1 to the M+1th switch signals SWSM+1 can have an active level. In an embodiment, for example, the first switch signal SWS1 can have an active level during the first time period, and the M+1th switch signal SWSM+1 can have an active level during the M+1th time period. Furthermore, during the P+1th time period, the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the P+1th to N+Pth channel circuits, respectively, and the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the P+1th to N+Pth channel circuits, respectively. Therefore, during the P+1th time period, the K+Pth channel circuit can output a data voltage to the Kth data line DLK. In an embodiment, for example, during a first time period, the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively, and the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the first channel circuit CH1 to the Nth channel circuit CHN, respectively. Furthermore, during the M+1 time period, the first multiplexer MUX1 can connect the first data latch LAT1 to the Nth data latch LATN to the M+1 channel circuit to the N+M channel circuit CHN+M, respectively, and the second multiplexer MUX2 can connect the first data line DL1 to the Nth data line DLN to the M+1 channel circuit to the N+M channel circuit CHN+M, respectively.

[0081] In some embodiments, such as Figure 10As shown, the first time period P1 to the (M+1)th time period PM+1 can alternate with each other in each horizontal time period. In an embodiment, for example, the first switch signal SWS1 to the (M+1)th switch signal SWSM+1 can each have an active level in the first horizontal time period HT1 to the (M+1)th horizontal time period HTM+1, respectively. Therefore, the Kth channel circuit to the K+Mth channel circuit can each output the data voltages DV_CHK, ..., and DV_CHK+M to the Kth data line DLK in the first horizontal time period HT1 to the (M+1)th horizontal time period HTM+1, respectively. In such an embodiment, the first switch signal SWS1 to the (M+1)th switch signal SWSM+1 can each have an active level sequentially in the (M+2)th horizontal time period HTM+2 to the (2M+2)th horizontal time period HT2M+2, and the Kth channel circuit to the K+Mth channel circuit can each output the data voltages DV_CHK, ..., and DV_CHK+M to the Kth data line DLK in the (M+2)th horizontal time period HTM+2 to the (2M+2)th horizontal time period HT2M+2, respectively. Therefore, the offset of the data voltages DV_CHK, ..., and DV_CHK+M output to the Kth data line DLK can be reduced. Figure 10 An example is shown in which each horizontal time period from the first time period P1 to the (M+1)th time period PM+1 alternates with each other. In other embodiments, the first time period P1 to the (M+1)th time period PM+1 may alternate with each other every two or more horizontal time periods.

[0082] In other embodiments, such as Figure 11 As shown, the first time period P1 to the (M+1)th time period PM+1 can alternate with each other in each frame period. In an embodiment, for example, the first switch signal SWS1 to the (M+1)th switch signal SWSM+1 can sequentially have valid levels in the first frame period FP1 to the (M+1)th frame period FPM+1, and the Kth channel circuit to the (K+M)th channel circuit can respectively output data voltages DV_CHK, ..., and DV_CHK+M to the Kth data line DLK in the first frame period FP1 to the (M+1)th frame period FPM+1. In such an embodiment, the first switch signal SWS1 to the (M+1)th switch signal SWSM+1 can sequentially have valid levels in the (M+2)th frame period FPM+2 to the (2M+2)th frame period FP2M+2, and the Kth channel circuit to the (K+M)th channel circuit can respectively output data voltages DV_CHK, ..., and DV_CHK+M to the Kth data line DLK in the (M+2)th frame period FPM+2 to the (2M+2)th frame period FP2M+2. Therefore, the offset of the data voltages DV_CHK, ..., DV_CHK+M output to the Kth data line DLK can be reduced. Figure 11An example is shown in which each frame period from the first time period P1 to the (M+1)th time period PM+1 alternates with each other. In other embodiments, the first time period P1 to the (M+1)th time period PM+1 may alternate with each other every two or more frame periods.

[0083] As described above, the data driver 300 according to the embodiment may include first channel circuits CH1 to N+M channel circuits CHN+M relative to the first data lines DL1 to Nth data lines DLN. During a first time period P1, the first channel circuits CH1 to Nth channel circuits CHN can respectively output data voltages to the first data lines DL1 to Nth data lines DLN, and during the M+1 time period PM+1, the M+1 channel circuits to N+M channel circuits CHN+M can respectively output data voltages to the first data lines DL1 to Nth data lines DLN. Therefore, the voltage deviation or offset between the data voltages output to the first data lines DL1 to Nth data lines DLN can be reduced, and the DVO of the data driver 300 can be improved or reduced.

[0084] Figure 12 This is a block diagram illustrating a display device according to an embodiment.

[0085] Reference Figure 12 The display device 700 according to an embodiment may include a display panel 710, a data driver 720, a scan driver 730, and a controller 750. In some embodiments, the display device 700 may further include a transmit driver 740.

[0086] Display panel 710 may include first data lines to Nth data lines and a plurality of pixels PX connected to the first data lines to Nth data lines. In some embodiments, each pixel PX may include at least two transistors, at least one capacitor, and a light-emitting element, and display panel 710 may be a light-emitting display panel. In embodiments, for example, the light-emitting element may be an organic light-emitting diode (“OLED”), a nano-light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. Furthermore, display panel 710 is not limited to a light-emitting display panel and may be any suitable display panel.

[0087] The data driver 720 can provide a data voltage DV to multiple pixels PX based on the data control signal DCTRL received from the controller 750 and the output image data ODAT. The data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. According to an embodiment, the data driver 720 may be... Figure 1 The data drive 100 shown Figure 9The data driver 300, etc., is shown. In an embodiment, the first to Nth channel circuits of the data driver 720 can output data voltage DV to the first to Nth data lines respectively in a first time period, and the second to N+1th channel circuits of the data driver 720 can output data voltage DV to the first to Nth data lines respectively in a second time period. Therefore, the voltage deviation or offset between the data voltages DV output to the first to Nth data lines can be reduced. In some embodiments, the data driver 720 and the controller 750 can be implemented as a single integrated circuit, and the single integrated circuit can be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, the data driver 720 and the controller 750 can be implemented as separate integrated circuits.

[0088] The scan driver 730 can provide a scan signal SS to multiple pixels PX based on a scan control signal SCTRL received from the controller 750. The scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 730 may be integrated or formed in the display panel 710. In other embodiments, the scan driver 730 may be implemented using one or more integrated circuits.

[0089] The transmit driver 740 can provide a transmit signal EM to multiple pixels PX based on a transmit control signal EMCTRL received from the controller 750. The transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. In some embodiments, the transmit driver 740 may be integrated or formed in the display panel 710. In other embodiments, the transmit driver 740 may be implemented using one or more integrated circuits.

[0090] Controller 750 (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 750 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Controller 750 can control data driver 720 by providing the output image data ODAT and the data control signal DCTRL to data driver 720, control scan driver 730 by providing the scan control signal SCTRL to scan driver 730, and control transmit driver 740 by providing the transmit control signal EMCTRL to transmit driver 740.

[0091] Figure 13 This is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0092] Reference Figure 13 Embodiments of electronic device 1100 may include processor 1110, memory device 1120, storage device 1130, input / output (I / O) device 1140, power supply 1150, and display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0093] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be integrated with other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can also be integrated with an expansion bus (such as a peripheral component interconnect (“PCI”) bus).

[0094] The memory device 1120 may store data for the operation of the electronic device 1100. In embodiments, for example, the memory device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“Mobile DRAM”) device, etc.).

[0095] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be input devices (such as a keyboard, keypad, mouse, touchscreen, etc.) and output devices (such as a printer, speaker, etc.). Power supply 1150 can supply power to the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0096] In the display device 1160, as described above, the data driver may include a first channel circuit to a (N+1)th channel circuit (where N is an integer greater than 1) relative to the first data line to the Nth data line. During a first time period, the first channel circuit to the Nth channel circuit may each output a data voltage to the first data line to the Nth data line. During a second time period, the second channel circuit to the (N+1)th channel circuit may each output a data voltage to the first data line to the Nth data line. Therefore, the voltage deviation or offset between the data voltages output to the first data line to the Nth data line can be reduced.

[0097] The inventive concept can be applied to any electronic device 1100 including display device 1160. In embodiments, for example, the inventive concept can be applied to virtual reality (“VR”) devices, augmented reality (“AR”) devices, mixed reality (“MR”) devices, extended reality (“XR”) devices, mobile phones, smartphones, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0098] Figure 14 This is a block diagram illustrating an example of an electronic device according to an embodiment.

[0099] Embodiments of electronic device 2101 can output various information via display module 2140 in the operating system. When processor 2110 executes an application stored in memory 2120, display module 2140 can provide application information to the user via display panel 2141.

[0100] Processor 2110 can obtain external input via input module 2130 or sensor module 2161, and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 2141, processor 2110 can obtain user input via input sensor 2161-2 and activate camera module 2171. Processor 2110 can transmit image data corresponding to the image captured by camera module 2171 to display module 2140. Display module 2140 can display the image corresponding to the captured image via display panel 2141.

[0101] As another example, when personal information authentication is performed in display module 2140, fingerprint sensor 2161-1 can obtain input fingerprint information as input data. Processor 2110 can compare the input data obtained by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and can execute the application based on the comparison result. Display module 2140 can display the information executed according to the application logic via display panel 2141.

[0102] As another example, when a music stream icon displayed on display module 2140 is selected, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music execution command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide sound information corresponding to the music execution command to the user.

[0103] The operation of electronic device 2101 has been briefly described above. The construction of electronic device 2101 will be described in detail below. Some components of electronic device 2101 described below can be integrated and configured as a single component, or a single component can be configured as two or more separate components.

[0104] Reference Figure 14 Embodiments of electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In some embodiments, electronic device 2101 may include processor 2110, memory 2120, input module 2130, display module 2140, power management module 2150, internal module 2160, and external module 2170. In some embodiments, at least one of the components may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. In some embodiments, some components (e.g., sensor module 2161, antenna module 2162, or sound output module 2163) may be implemented as a single component (e.g., display module 2140).

[0105] Processor 2110 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 2101 combined with processor 2110, and can perform various data processing or calculations. According to some embodiments, as at least part of data processing or calculation, processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0106] Processor 2110 may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include at least one selected from a central processing unit (“CPU”) 2111-1 and an application processor (“AP”). Main processor 2111 may also include at least one selected from a graphics processing unit (“GPU”) 2111-2, a communication processor (“CP”), and an image signal processor (“ISP”). Main processor 2111 may also include a neural processing unit (“NPU”) 2111-3. NPU 2111-3 may be a processor specifically designed to process artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be, but are not limited to, deep neural networks (“DNN”), convolutional neural networks (“CNN”), recurrent neural networks (“RNN”), restricted Boltzmann machines (“RBM”), deep belief networks (“DBN”), bidirectional recurrent deep neural networks (“BRDNN”), deep Q-networks, or combinations of two or more of these. The artificial intelligence model may additionally or alternatively include software structures in addition to hardware structures. At least two of the processing units and processors selected above can be implemented as integrated components (e.g., a single chip), or each processing unit and processor can be implemented as independent components (e.g., multiple chips).

[0107] The auxiliary processor 2112 may include a controller. The controller included in the auxiliary processor 2112 can interact with... Figure 12 The controller 750 shown corresponds to this. The controller may include interface conversion circuitry and timing control circuitry. The controller can receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications with the display module 2140, and output image data. The controller can output various control signals required to drive the display module 2140.

[0108] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, a rendering circuit 2112-4, etc. The data conversion circuit 2112-2 can receive image data from the controller. The data conversion circuit 2112-2 can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device 2101 or user settings, or it can convert the image data to reduce power consumption or eliminate afterimages. The gamma correction circuit 2112-3 can convert the image data or gamma reference voltage so that the image displayed on the electronic device 2101 has the desired gamma characteristics. The rendering circuit 2112-4 can receive image data from the controller and can render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one selected from the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, gamma correction circuit 2112-3, and rendering circuit 2112-4 can be integrated into the data driver 2143 described below.

[0109] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). The various data may include, for example, input or output data for commands associated with it. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0110] The input module 2130 can receive commands or data from outside the electronic device 2101 (e.g., a user or external electronic device 2102) that will be used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or voice output module 2163).

[0111] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables the electronic device 2101 to be connected to the external electronic device 2102 via wired or wireless means. In some embodiments, the second input module 2132 may include a High Definition Multimedia Interface (“HDMI”), a Universal Serial Bus (“USB”) interface, an SD card interface, or an audio interface. The second input module 2132 may include a connector that allows the electronic device 2101 to be physically connected to the external electronic device 2102. In embodiments, for example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0112] Display module 2140 can visually provide information to the user. Display module 2140 may include display panel 2141, scan driver 2142, and data driver 2143. Display module 2140 may also include a window, base, and bracket for protecting display panel 2141.

[0113] Display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. Display panel 2141 may be a rigid display panel or a flexible display panel that can be rolled or folded. Display module 2140 may also include a support, bracket, or heat dissipation component that supports display panel 2141.

[0114] The scan driver 2142 can be mounted as a driver chip on the display panel 2141. Optionally, the scan driver 2142 can be integrated into the display panel 2141. In embodiments, for example, the scan driver 2142 may include an amorphous silicon TFT gate driver circuit (“ASG”), a low-temperature polycrystalline silicon (“LTPS”) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (“OSG”) embedded in the display panel 2141. The scan driver 2142 can receive control signals from a controller and can output scan signals to the display panel 2141 in response to the control signals.

[0115] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed separately from the scan driver 2142, or it may be integrated into the scan driver 2142.

[0116] The data driver 2143 can receive control signals from the controller and, in response to the control signals, convert image data into analog voltages (e.g., data voltages), which can then be output to the display panel 2141. In an embodiment, as described above, the data driver 2143 may include first to N+1 channel circuits relative to the first to Nth data lines (where N is an integer greater than 1). During a first time period, the first to Nth channel circuits can output data voltages to the first to Nth data lines respectively. During a second time period, the second to N+1 channel circuits can output data voltages to the first to Nth data lines respectively. Therefore, the voltage deviation or offset between the data voltages output to the first to Nth data lines can be reduced.

[0117] The data driver 2143 can be incorporated into other components (e.g., a controller). Furthermore, the interface conversion circuitry and timing control circuitry of the aforementioned controller can be integrated into the data driver 2143.

[0118] The display module 2140 may also include a transmitter driver, a voltage generator circuit, etc. The voltage generator circuit can output various voltages for driving the display panel 2141.

[0119] Power management module 2150 can supply power to components of electronic device 2101. Power management module 2150 may include a battery that supplies power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power management module 2150 may include a power management integrated circuit (“PMIC”). The PMIC can supply optimal power to each of the modules described above and below. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0120] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0121] Sensor module 2161 can detect input from the user's body or from the pen of the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0122] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 may include at least one selected from optical fingerprint sensors and capacitive fingerprint sensors.

[0123] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of a user's body or pen input. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input from a passive pen, or can send data to / receive data from an active pen.

[0124] Input sensor 2161-2 can measure biosignals such as blood pressure, water content, or body fat. In an embodiment, for example, when a part of a user's body touches the sensor layer or sensing panel and remains stationary for a specific period of time, input sensor 2161-2 can detect biosignals based on changes in the electric field caused by the part of the body and output the user's desired information to display module 2140.

[0125] The digitizer 2161-3 can generate data values ​​corresponding to the coordinate information input by the pen. The digitizer 2161-3 can convert electromagnetic changes caused by the input into data values. The digitizer 2161-3 can detect input from a passive pen, or send data to / receive data from an active pen.

[0126] At least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be disposed above the display panel 2141, or at least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be disposed below the display panel 2141.

[0127] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel using the same process. In such an embodiment, when two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel 2141 and a window positioned above the display panel 2141. In some embodiments, the sensing panel can be positioned on the window, but the location of the sensing panel is not limited thereto.

[0128] At least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be embedded in the display panel 2141. In other words, at least one of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0129] Additionally, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 2101. Sensor module 2161 may also include, for example, gesture sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (“IR”) sensors, biosensors, temperature sensors, humidity sensors, or illuminance sensors.

[0130] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In some embodiments, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or input sensor 2161-2.

[0131] The audio output module 2163 can output audio signals to the outside of the electronic device 2101. The audio output module 2163 may include, for example, a speaker or a receiver. The speaker can be used for general purposes (such as playing multimedia or playing recordings). The receiver can be used to receive incoming calls. In some embodiments, the receiver can be implemented separately from the speaker or as part of the speaker. The audio output pattern of the audio output module 2163 can be integrated into the display module 2140.

[0132] Camera module 2171 can capture still images and moving images. In some embodiments, camera module 2171 may include one or more lenses, image sensors, or image signal processors. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0133] The light module 2172 can provide light. The light module 2172 may include a light-emitting diode or a xenon lamp. The light module 2172 can operate in conjunction with the camera module 2171, or it can operate independently of the camera module 2171.

[0134] Communication module 2173 can support the establishment of a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and perform communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (“GNSS”) communication module) or a wired communication module (e.g., a Local Area Network (“LAN”) communication module or a Power Line Communication (“PLC”) module). Communication module 2173 can communicate with external electronic device 2102 via a short-range communication network (e.g., Bluetooth™, Wi-Fi Direct, or Infrared Data Association (“IrDA”)) or a long-range communication network (e.g., a cellular network, the Internet, or a computer network (e.g., a LAN or a Wide Area Network (“WAN”)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips that are separate from each other.

[0135] The input module 2130, sensor module 2161, camera module 2171, etc., can be combined with the processor 2110 to control the operation of the display module 2140.

[0136] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on the input data received from the input module 2130. In an embodiment, for example, the processor 2110 can generate image data corresponding to input data applied via a mouse or active pen, and can output the image data to the display module 2140. Optionally, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 for a certain period of time, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0137] Processor 2110 can output commands or data to display module 2140, sound output module 2163, camera module 2171, or optical module 2172 based on sensing data received from sensor module 2161. In an embodiment, for example, processor 2110 can compare authentication data applied by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and then execute an application based on the comparison result. Processor 2110 can execute commands or output corresponding image data to display module 2140 based on sensing data sensed by input sensor 2161-2 or digitizer 2161-3. If sensor module 2161 includes a temperature sensor, processor 2110 can receive temperature data from sensor module 2161 and can also perform brightness correction on image data based on the temperature data.

[0138] Processor 2110 can receive measurement data from camera module 2171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 2110 can also perform brightness correction on image data based on the measurement data. In an embodiment, for example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0139] At least some of the aforementioned components can be combined with each other and transmit signals (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input and output (“GPIO”), serial peripheral interface (“SPI”), mobile industry processor interface (“MIPI”), or hyperpath interconnect (“UPI”)). Processor 2110 can communicate with display module 2140 via a pre-defined interface. Furthermore, at least one of the communication methods selected from the above descriptions can be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to the aforementioned methods.

[0140] The electronic device 2101 according to the various embodiments described above can be of various types. In embodiments, for example, the electronic device 2101 may include at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. However, the electronic device 2101 according to the embodiments is not limited to the devices described above.

[0141] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0142] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A data driver for a display device, the data driver comprising: Data latches from the first data latch to the Nth data latch, where N is an integer greater than 1; The first channel circuit to the N+1th channel circuit; A first multiplexer is connected between the first data latch to the Nth data latch and the first channel circuit to the N+1th channel circuit; and The second multiplexer is connected between the first channel circuit to the (N+1)th channel circuit and the first data line to the Nth data line. In the first time period, the first multiplexer connects the first data latch to the Nth data latch to the first channel circuit to the Nth channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the first channel circuit to the Nth channel circuit, respectively. During the second time period, the first multiplexer connects the first data latch to the Nth data latch to the second channel circuit to the N+1 channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the second channel circuit to the N+1 channel circuit, respectively.

2. The data driver according to claim 1, wherein, During the first time period, the Kth channel circuit among the first channel circuit to the (N+1)th channel circuit outputs the data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N. During the second time period, the K+1 channel circuit among the first channel circuit to the N+1 channel circuit outputs the data voltage to the Kth data line.

3. The data driver according to claim 1, wherein, The Kth channel circuit among the first channel circuit to the (N+1)th channel circuit includes: A level shifter performs a level shift operation on image data received from the Kth data latch among the first data latch to the Nth data latch during the first time period, and performs a level shift operation on image data received from the (K-1)th data latch among the first data latch to the Nth data latch during the second time period. A digital-to-analog converter generates a data voltage by performing a digital-to-analog conversion operation on image data output from the level shifter; and An output buffer outputs the data voltage to the Kth data line among the first data lines to the Nth data line during the first time period, and outputs the data voltage to the (K-1)th data line among the first data lines to the Nth data line during the second time period. Where K is an integer greater than or equal to 2 and less than or equal to N.

4. The data driver according to claim 1, wherein, During the second time period, the first channel circuit is not connected to the first data latch to the Nth data latch and the first data line to the Nth data line, and During the first time period, the N+1 channel circuit is not connected to the first data latch to the Nth data latch and the first data line to the Nth data line.

5. The data driver according to claim 1, wherein, The first multiplexer includes: Multiple first switches, in response to a first switch signal, respectively connect the first data latch to the Nth data latch to the first channel circuit to the Nth channel circuit; and Multiple second switches, in response to second switch signals, respectively connect the first data latch to the Nth data latch to the second channel circuit to the N+1th channel circuit.

6. The data driver according to claim 5, wherein, The second multiplexer includes: Multiple third switches, in response to the first switch signal, respectively connect the first data line to the Nth data line to the first channel circuit to the Nth channel circuit; and Multiple fourth switches, in response to the second switch signal, respectively connect the first data line to the Nth data line to the second channel circuit to the N+1th channel circuit.

7. The data driver according to claim 6, further comprising: A switch signal generator generates a first switch signal with an effective level during a first time period and generates a second switch signal with an effective level during a second time period.

8. The data driver according to claim 1, wherein, The first time period and the second time period alternate with each other at each horizontal time.

9. The data driver according to claim 8, wherein, During odd-numbered horizontal periods of the frame period, the first channel circuit to the Nth channel circuit outputs data voltages to the first data line to the Nth data line, and During the even-numbered horizontal time of the frame period, the second channel circuit to the (N+1)th channel circuit outputs data voltage to the first data line to the Nth data line.

10. The data driver according to claim 1, wherein, The first time period and the second time period alternate every L horizontal time intervals, where L is an integer greater than 1.

11. The data driver according to claim 1, wherein, The first time period and the second time period alternate each frame cycle.

12. The data driver according to claim 11, wherein, During odd-numbered frame periods, the first channel circuit to the Nth channel circuit outputs data voltage to the first data line to the Nth data line, and In even-numbered frame periods, the second channel circuit to the (N+1)th channel circuit outputs data voltage to the first data line to the Nth data line.

13. The data driver according to claim 1, wherein, The first time period and the second time period alternate every L frame cycles, where L is an integer greater than 1.

14. A data driver for a display device, the data driver comprising: Data latches from the first data latch to the Nth data latch, where N is an integer greater than 1; The circuit consists of the first channel circuit to the (N+M)th channel circuit, where M is an integer greater than 1; A first multiplexer is connected between the first data latch to the Nth data latch and the first channel circuit to the N+1th channel circuit; and The second multiplexer is connected between the first channel circuit to the (N+1)th channel circuit and the first data line to the Nth data line. Specifically, during the P+1th time period, the first multiplexer connects the first data latch to the Nth data latch to the P+1th channel circuit to the N+Pth channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the P+1th channel circuit to the N+Pth channel circuit, respectively. Where P is an integer greater than or equal to 0 and less than or equal to M.

15. The data driver according to claim 14, wherein, During the P+1th time period, the K+Pth channel circuit among the first channel circuit to the N+Mth channel circuit outputs the data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N.

16. An electronic device, the electronic device comprising: The processor provides the input image data; as well as The display device receives the input image data from the processor and displays an image based on the input image data. The display device includes: a display panel including first data lines to Nth data lines and a plurality of pixels connected to the first data lines to the Nth data lines, wherein N is an integer greater than 1; a scan driver that provides scan signals to the plurality of pixels; a data driver that provides data voltage to the plurality of pixels through the first data lines to the Nth data lines; and a controller that controls the scan driver and the data driver. The data driver includes: a first data latch to an Nth data latch; a first channel circuit to an (N+1)th channel circuit; a first multiplexer connected between the first data latches to the Nth data latch and the first channel circuit to the (N+1)th channel circuit; and a second multiplexer connected between the first channel circuit to the (N+1)th channel circuit and the first data line to the Nth data line. In the first time period, the first multiplexer connects the first data latch to the Nth data latch to the first channel circuit to the Nth channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the first channel circuit to the Nth channel circuit, respectively. During the second time period, the first multiplexer connects the first data latch to the Nth data latch to the second channel circuit to the N+1 channel circuit, respectively, and the second multiplexer connects the first data line to the Nth data line to the second channel circuit to the N+1 channel circuit, respectively.

17. The electronic device according to claim 16, wherein, During the first time period, the Kth channel circuit among the first channel circuit to the (N+1)th channel circuit outputs the data voltage to the Kth data line among the first data line to the Nth data line, where K is an integer greater than or equal to 1 and less than or equal to N. During the second time period, the K+1 channel circuit among the first channel circuit to the N+1 channel circuit outputs the data voltage to the Kth data line.

18. The electronic device according to claim 16, wherein, The Kth channel circuit among the first channel circuit to the (N+1)th channel circuit includes: A level shifter performs a level shift operation on image data received from the Kth data latch among the first data latch to the Nth data latch during the first time period, and performs a level shift operation on image data received from the (K-1)th data latch among the first data latch to the Nth data latch during the second time period. A digital-to-analog converter generates a data voltage by performing a digital-to-analog conversion operation on image data output from the level shifter; and An output buffer outputs the data voltage to the Kth data line among the first data lines to the Nth data line during the first time period, and outputs the data voltage to the (K-1)th data line among the first data lines to the Nth data line during the second time period. Where K is an integer greater than or equal to 2 and less than or equal to N.

19. The electronic device according to claim 16, wherein, The first multiplexer includes: Multiple first switches, in response to a first switch signal, respectively connect the first data latch to the Nth data latch to the first channel circuit to the Nth channel circuit; and Multiple second switches, in response to second switch signals, respectively connect the first data latch to the Nth data latch to the second channel circuit to the N+1th channel circuit, and The second multiplexer includes: Multiple third switches, in response to the first switch signal, respectively connect the first data line to the Nth data line to the first channel circuit to the Nth channel circuit; and Multiple fourth switches, in response to the second switch signal, respectively connect the first data line to the Nth data line to the second channel circuit to the N+1th channel circuit.

20. The electronic device according to claim 19, wherein, The data driver also includes: A switch signal generator generates a first switch signal with an effective level during a first time period and generates a second switch signal with an effective level during a second time period.

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