Ripple elimination circuit with self-zeroing function and chopper operational amplifier

Abstract

The invention provides a ripple elimination circuit with a self-zeroing function and a chopping operational amplifier, and relates to the technical field of analog integrated circuits, and the ripple elimination circuit comprises an input sampling unit, a post-stage chopping unit, an integral self-zeroing unit and a feedback unit. A first switch group is arranged in the input sampling unit, and a corresponding zero-setting switch group is arranged in the integral self-zero-setting unit. Through specific clock control, when the integral self-zeroing unit is in an offset voltage sampling phase, the first switch group is turned off, and an input sampling capacitor is physically isolated from a subsequent integral zeroing loop; and in a signal amplification phase, the first switch group is switched on, and a signal path is established. According to the design, the interference of external ripples on the offset voltage storage process at the sampling phase is effectively blocked, and the accuracy of the compensation current is remarkably improved in combination with optimized sequential control, so that an excellent ripple elimination effect and extremely low residual offset voltage are realized, and the method is suitable for an ultra-high-precision analog operational amplifier.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a ripple cancellation circuit with self-zeroing and a chopper operational amplifier. Background Technology

[0002] In chopper operational amplifiers, chopper modulation techniques are often used to eliminate the low-frequency offset and noise inherent in the operational amplifier itself in order to achieve high precision and low offset characteristics. However, this technique modulates the offset voltage to the chopper frequency, resulting in a significant ripple voltage at the output. To suppress this output ripple, a ripple cancellation circuit is typically introduced. Its core is an integral feedback loop used to detect the output ripple and generate a compensation current to counteract the offset of the main path.

[0003] To achieve better suppression, the offset voltage of the integrator itself usually needs to be dynamically eliminated. A common approach is to use a self-zeroing technique with input offset storage. In this technique, the integrator's operating cycle is divided into a sampling phase and an amplification phase. During the sampling phase, the operational amplifier in the integrator is configured as a buffer, and its offset voltage is sampled and stored in the zeroing capacitor at the input. During the amplification phase, the integrator resumes normal operation, and the stored voltage is used to compensate for the operational amplifier's offset.

[0004] like Figure 1 This is a schematic diagram of a common ripple suppression loop structure. Its principle is to sample the output ripple through a capacitor, integrate it using an integrator composed of amplifiers GM3 and Cint1 and Cint2, and finally convert it into a feedback current to compensate for offset through a transconductance amplifier, thereby suppressing the ripple. However, the offset voltage of the integrator will form a large residual ripple at the output through the detection capacitors Cs1 and Cs2, and therefore must be eliminated. To eliminate the residual ripple, one method is to add input offset storage to the integrator. The integrator constantly switches between a self-reset (AZ) state and a signal transmission (TS) state throughout its operation. When it is in the AZ state, as... Figure 2 The integrator output is its offset voltage. When it is in the signal transmission (TS) state, the integrator output is the voltage during normal ripple compensation, which is about several hundred millivolts. This transition will create new residual spikes at the output, affecting signal quality and must be eliminated. Traditional technology does not have a zero-adjustment switch in the input section of the ripple cancellation circuit. As a result, when the circuit enters the sampling phase, although the input capacitor is short-circuited to the common-mode level, switches S5 and S6 are equivalent to the resistance of the switch conduction. The external ripple signal can still be coupled to the integrator's integrating capacitor through the input capacitors Cs1 and Cs2, as well as Rs5 and Rs6. This causes the equivalent offset voltage of Caz1 and Caz2 to be affected by the input signal, resulting in a deviation in the compensation current, deteriorating the ripple cancellation effect, and resulting in a high residual offset voltage, which is not suitable for circuits with higher offset voltage requirements.

[0005] Therefore, existing ripple cancellation circuits of this type have an inherent drawback: as shown in the attached diagram. Figure 2 As shown, during the self-zeroing sampling phase, although the input capacitor is shorted to the common-mode level, the shorting switch itself has a finite on-resistance. Strong external output ripple signals can still leak to the integrator's zeroing and integrating capacitors through the coupling path formed by the input sampling capacitor and the switching resistor. This contaminates the accuracy of the stored offset voltage information, causing deviations in the compensation current generated by the subsequent amplified phase, thus worsening the final ripple cancellation effect and increasing the residual offset voltage, limiting its performance in ultra-low offset, high-precision applications. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a ripple cancellation circuit with self-zero adjustment and a chopper operational amplifier.

[0007] According to the present invention, a ripple cancellation circuit with self-zero adjustment and a chopper operational amplifier are provided, the solution of which is as follows: In a first aspect, a ripple cancellation circuit with self-zero adjustment is provided, applied to a chopper operational amplifier including a pre-stage chopper unit and a pre-stage transconductance amplification unit, comprising: The input sampling unit includes a differential sampling capacitor subunit and a first switch group; the input terminal of the differential sampling capacitor subunit is connected to the differential output terminal of the chopper operational amplifier, and the first switch group is used to control the on / off state of the differential sampling capacitor subunit with the common-mode level and subsequent circuits; The input terminal of the post-stage chopper unit is connected to the output terminal of the input sampling unit, and is used to chop the sampled signal. The self-zeroing integration unit includes an operational amplifier subunit, a zeroing subunit, an integrating capacitor subunit, and a second switch group; the input terminal of the operational amplifier subunit is connected to the output terminal of the subsequent chopper unit; the zeroing subunit is used to store the offset voltage of the operational amplifier subunit; the integrating capacitor subunit and the operational amplifier subunit cooperate to form an integrating structure; the second switch group is used to control the operating state and signal feedback path of the zeroing subunit. The feedback unit has its input connected to the output of the integral self-zeroing unit, and its output fed back to the pre-amplifier signal node of the chopper operational amplifier to inject a compensation signal to cancel the offset voltage and chopper ripple.

[0008] Preferably, the differential sampling capacitor subunit includes differential input capacitor Cs1 and capacitor Cs2; the first switch group includes switch S7, switch S8, switch S9 and switch S10. The first terminal of capacitor Cs1 is connected to the output terminal Vout- of the chopper operational amplifier, and the first terminal of capacitor Cs2 is connected to the output terminal Vout+ of the chopper operational amplifier. The second terminal of capacitor Cs1 is connected to the first terminal of switch S7 and the first terminal of switch S8. The second terminal of capacitor Cs2 is connected to the first terminal of switch S9 and the first terminal of switch S10. The second terminals of switch S7 and switch S9 are both connected to the common-mode level. The second terminals of switch S8 and switch S10 are connected to the input terminal of the subsequent chopper unit. Preferably, the subsequent chopper unit is a third chopper switch CH3, whose differential input terminal is connected to the second terminal of switches S8 and S10 in the first switch group, and whose differential output terminal is connected to the differential input terminal of the operational amplifier subunit.

[0009] Preferably, the operational amplifier subunit is a transconductance amplifier Gm3; The zero-adjustment subunit includes zero-adjustment capacitors Caz1 and Caz2, and zero-adjustment switches S3 and S4. Zero-adjustment capacitor Caz1 is differentially connected between the non-inverting input and output of transconductance amplifier Gm3, and zero-adjustment capacitor Caz2 is differentially connected between the inverting input and output of transconductance amplifier Gm3. The first terminal of zero-adjustment switch S3 is connected to the common node of zero-adjustment capacitor Caz1 and the non-inverting input of transconductance amplifier Gm3, and the first terminal of zero-adjustment switch S4 is connected to the common node of zero-adjustment capacitor Caz2 and the inverting input of transconductance amplifier Gm3. The second terminals of both zero-adjustment switches S3 and S4 are connected to a common-mode level. The integrating capacitor subunit includes integrating capacitor Cint1 and integrating capacitor Cint2. The integrating capacitor Cint1 is differentially connected between the non-inverting input terminal and the output terminal of the transconductance amplifier Gm3, and the integrating capacitor Cint2 is differentially connected between the inverting input terminal and the output terminal of the transconductance amplifier Gm3. The second switch group includes switch S1 and switch S2. The first end of switch S1 is connected to the non-inverting input of transconductance amplifier Gm3, and the first end of switch S2 is connected to the inverting input of transconductance amplifier Gm3.

[0010] Preferably, the feedback unit is a transconductance amplifier Gm4, whose differential input terminal is connected to the differential output terminal of the operational amplifier subunit, and whose differential output terminal is connected to the second terminals of switches S1 and S2 in the second switch group.

[0011] Preferably, the pre-amplifier signal node is the common connection node between the output terminal of the pre-amplifier chopper unit and the input terminal of the pre-amplifier transconductance amplifier unit in the chopper operational amplifier.

[0012] Preferably, switches S7, S8, S9, and S10 of the first switch group, switches S1 and S2 of the second switch group, and zero-adjustment switches S3 and S4 of the zero-adjustment subunit are all synchronously controlled by the same self-zeroing clock.

[0013] Preferably, the control clock of the pre-stage chopper unit of the chopper operational amplifier and the control clock of the third chopper switch CH3 are chopper clocks with the same frequency but different phases, and the period of the chopper clock is twice the period of the self-zeroing clock.

[0014] Secondly, a chopper operational amplifier is provided, comprising: The main signal amplification circuit is used to perform differential amplification of the input signal; A ripple elimination circuit with self-zero adjustment has its input terminal connected to the output terminal of the main signal amplification circuit; The transconductance amplification unit serves as the feedback unit of the ripple elimination circuit. Its input terminal is connected to the output terminal of the integral self-zeroing unit of the ripple elimination circuit, and its output terminal is connected to the signal node of the main signal amplification circuit to inject compensation current into the main signal amplification circuit, thereby achieving offset voltage suppression and ripple elimination.

[0015] Preferably, the transconductance amplification unit is a transconductance amplifier Gm4, which converts the feedback voltage output by the integral self-zeroing unit in the ripple cancellation circuit into a compensation current. The compensation current is injected into the node between the pre-stage chopper unit and the pre-stage transconductance amplification unit in the main signal amplification circuit to cancel the offset voltage and ripple interference of the main signal amplification circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention adds a controlled switch group between the input sampling capacitor and the subsequent circuit, physically isolating the input sampling network from the integral zero-adjustment circuit in the self-zeroing sampling phase (AZ phase). This effectively blocks external ripple signals from interfering with the storage process of the zero-adjustment capacitors (Caz1, Caz2) through capacitive coupling and the switching resistor path, ensuring the accuracy and purity of offset voltage sampling, and solving the key problem of the compensation current being easily interfered with in traditional structures from the source. 2. Based on the accurately stored offset voltage information, the integral feedback loop of this invention can generate a highly accurate compensation current in the amplification phase (TS phase). After this current is injected into the main signal path, it can efficiently cancel the main operational amplifier offset and chopper ripple. 3. By setting the chopping clock period to twice the self-zeroing clock period and enabling each switch group to operate in coordination under precise timing, this invention ensures seamless connection between ripple sampling, self-zeroing storage, and signal amplification phase. This design allows the compensation loop to operate continuously throughout the entire cycle, while avoiding additional transient interference or residual spikes that may be caused by state switching, thereby improving the overall circuit stability and signal quality.

[0017] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 The overall architecture of a chopper operational amplifier with ripple cancellation circuitry; Figure 2 The equivalent circuit diagram of the ripple elimination circuit when it operates in the AZ stage; Figure 3 This is the overall architecture of the ripple elimination circuit with self-zero adjustment in this invention; Figure 4 This is the timing diagram required in this invention. Detailed Implementation

[0019] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0020] This invention provides a ripple cancellation circuit with self-zero adjustment. Two sets of switches are added after the input capacitor of the ripple cancellation circuit. These switches are disconnected when the integrator is in the sampling phase, thereby ensuring that the compensation current is not interfered with by the ripple signal and improving the ripple cancellation effect. The new structure achieves optimal ripple cancellation effect and minimizes the influence of residual voltage drift under specific chopping and AZ phase and frequency relationships.

[0021] Reference Figure 3As shown, this circuit is applied in a chopper operational amplifier that includes a pre-stage chopper unit (such as CH1, CH2) and a pre-stage transconductance amplification unit (Gm1, Gm2). It is primarily used to eliminate output ripple caused by chopper modulation and operational amplifier offset in the main amplifier. The ripple elimination circuit mainly includes an input sampling unit, a post-stage chopper unit, an integral self-zeroing unit, and a feedback unit.

[0022] Specifically, the input sampling unit is used to sample the ripple signal from the output of the main amplifier. It includes a differential sampling capacitor subunit and a first switch group. The differential sampling capacitor subunit includes two sampling capacitors, Cs1 and Cs2. One end of capacitor Cs1 is connected to the inverting output Vout- of the chopper operational amplifier, and one end of capacitor Cs2 is connected to the non-inverting output Vout+. The first switch group includes four switches, S7, S8, S9, and S10. The other end of capacitor Cs1 is connected to one end of switch S7 and one end of switch S8. The other end of capacitor Cs2 is connected to one end of switch S9 and one end of switch S10. The other ends of switches S7 and S9 are connected to a fixed common-mode reference level Vcm. The other ends of switches S8 and S10 serve as the outputs of this unit and are connected to the input of the subsequent chopper unit.

[0023] The subsequent chopper unit, typically composed of a third chopper switch CH3, modulates the sampled ripple signal. Its differential input is connected to the outputs of switches S8 and S10 in the input sampling unit. Its differential output is then connected to the input of the subsequent self-zeroing integration unit.

[0024] The self-zeroing integrating unit is the core component, used to integrate the modulated ripple signal and dynamically eliminate the offset voltage of its own operational amplifier. It includes an operational amplifier subunit, a zeroing subunit, an integrating capacitor subunit, and a second switching group.

[0025] The operational amplifier subunit is typically implemented by a transconductance amplifier Gm3, with its differential input connected to the output of the subsequent chopper unit CH3. The zero-adjustment subunit stores the offset voltage of Gm3 at a specific phase. It includes two zero-adjustment capacitors, Caz1 and Caz2, and two zero-adjustment switches, S3 and S4. Zero-adjustment capacitor Caz1 is connected between the non-inverting input and output of Gm3, and zero-adjustment capacitor Caz2 is connected between the inverting input and output of Gm3. Switch S3 is connected between the non-inverting input of Gm3 and the common-mode level Vcm, and switch S4 is connected between the inverting input and the common-mode level Vcm. The integrating capacitor subunit includes two integrating capacitors, Cint1 and Cint2, connected in parallel with Caz1 and Caz2 respectively. Specifically, Cint1 is connected between the non-inverting input and output of Gm3, and Cint2 is connected between the inverting input and output of Gm3. The second switch group includes switches S1 and S2. Switch S1 is connected between the non-inverting input of Gm3 and the output of the feedback unit, and switch S2 is connected between the inverting input of Gm3 and the output of the feedback unit. Furthermore, the output of Gm3 is directly connected to the input of the feedback unit.

[0026] The feedback unit converts the integrated voltage into a compensation current. It is typically implemented by the transconductance amplifier Gm4. The differential input of Gm4 is connected to the output of Gm3 in the self-zeroing integration unit. The differential output of Gm4 is connected to the other end of the second switch group (S1, S2) and ultimately fed back to the pre-amplifier signal node of the main amplifier, specifically the common node between the output of the pre-amplifier chopper unit (e.g., CH1) and the input of the pre-amplifier transconductance amplifier unit (e.g., Gm1).

[0027] Working sequence and control logic, refer to Figure 4 As shown, the circuit is controlled by two main clocks: a chopper clock and a self-zeroing clock. The first switch group (S7, S8, S9, S10), the second switch group (S1, S2), and the switches (S3, S4) of the zeroing subunit are all synchronously controlled by the same self-zeroing clock signal (AZ_CLK) and its inverted signal. The pre-stage chopper units (CH1, CH2) in the main amplifier and the post-stage chopper unit (CH3) in the ripple cancellation circuit are controlled by a chopper clock (CHOP_CLK) with the same frequency and a specific phase relationship. Crucially, the period of the chopper clock (CHOP_CLK) is configured to be twice the period of the self-zeroing clock (AZ_CLK).

[0028] Working process phase description: A. Offset voltage sampling phase (AZ phase, self-zero clock valid); In this phase: Switch status: Switches S7, S9, S3, and S4 are on; switches S8, S10, S1, and S2 are off.

[0029] Input sampling unit: One end of sampling capacitors Cs1 and Cs2 is shorted to the common-mode level Vcm through the conducting S7 and S9, and the other end is physically disconnected from the subsequent circuit through the turned-off S8 and S10, thereby completely isolating the interference of external output ripple (Vout+ / Vout-) on the subsequent circuit.

[0030] Integrating self-zeroing unit: The input terminal of transconductance amplifier Gm3 is shorted to Vcm through conducting S3 and S4. Its output terminal is fed back to the input terminal through integrating capacitors Cint1 and Cint2 (and zeroing capacitors Caz1 and Caz2), forming a unity-gain buffer structure. At this time, the input offset voltage of Gm3 itself is sampled and stored in the zeroing capacitors Caz1 and Caz2.

[0031] Feedback loop: Since S1 and S2 are turned off, the output of the integral self-zeroing unit is disconnected from the input of the feedback unit Gm4, and the feedback loop does not work in this phase.

[0032] B. Signal amplification and ripple elimination phase (TS phase, self-zero clock is invalid). In this phase: Switch status: Switches S8, S10, S1, and S2 are on; switches S7, S9, S3, and S4 are off.

[0033] Input sampling unit: Sampling capacitors Cs1 and Cs2 are connected to the subsequent chopper unit CH3 through the conducting S8 and S10, effectively transmitting the ripple signal at the output of the main amplifier to the subsequent circuit.

[0034] Integral self-zeroing unit: With switches S3 and S4 off, the input terminal of Gm3 is disconnected from Vcm. The offset voltage stored in Caz1 and Caz2 cancels out the offset voltage of Gm3 itself. At this time, Gm3, together with integrating capacitors Cint1 and Cint2, forms an effective integrator to integrate and amplify the ripple signal transmitted from CH3.

[0035] Feedback Loop: Switches S1 and S2 are turned on, transferring the output voltage of the self-zeroing integral unit to the input of the feedback unit Gm4. Gm4 converts this voltage into a compensation current, which is injected into the node of the preamplifier stage (between CH1 and Gm1) through S1 and S2. This compensation current is used to offset the offset of the main path, thereby suppressing the output ripple.

[0036] Since the chopper clock cycle is twice that of the self-zeroing clock, a complete chopper cycle includes the aforementioned AZ and TS phases, thus working together to continuously and accurately eliminate the main path misalignment and ripple.

[0037] The invention will now be described in more detail with reference to the accompanying drawings.

[0038] Figure 1 The diagram illustrates a traditional ripple suppression loop structure. Its principle involves sampling the output ripple through a capacitor, integrating it using an integrator composed of amplifiers GM3, Cint1, and Cint2, and finally converting it into a feedback current through a transconductance amplifier Gm4 to compensate for offset, thereby suppressing the ripple. The integrator's offset voltage will generate a significant residual ripple at the output through the detection capacitors Cs1 and Cs2, and therefore must be eliminated. To eliminate the residual ripple, one method is to add input offset storage to the integrator. The integrator continuously switches between a self-reset (AZ) state and a signal transmission (TS) state throughout its operation. When it is in the AZ state (as shown in the attached diagram)... Figure 2 The integrator output is its offset voltage. When it is in the signal transmission (TS) state, the integrator output is the voltage during normal ripple compensation, which is about several hundred millivolts. This conversion will create new residual spikes in the output, affecting the signal quality, and must be eliminated.

[0039] Figure 2 The diagram shows the equivalent circuit diagram of the traditional technology in its self-reset (AZ) state, also known as the sampling phase. At this time, switches S3, S4, S5, and S6 are on, while S1 and S2 are off. Input capacitors Caz1 and Caz2 are short-circuited to the common-mode level through switches S5 and S6. The offset voltage of GM3 is stored in input capacitors Caz1 and Caz2. Switches S5 and S6 are equivalent to the resistance of the switching circuit. External ripple signals can still be coupled to the integrator's integrating capacitors through input capacitors Cs1 and Cs2, as well as Rs5 and Rs6. This causes the stored equivalent offset voltage of Caz1 and Caz2 to be affected by the input signal, resulting in a deviation in the compensation current, worsening the ripple cancellation effect, and leaving a high residual offset voltage, making it unsuitable for circuits with higher offset voltage requirements. During the signal transmission (TS) state and signal amplification stage, switches S3, S4, S5, and S6 are open, while switches S1 and S2 are open. The signal carries capacitors Caz1 and Caz2, which store the offset voltage of GM3. It passes through the integrator and then through GM4, and is converted into a compensation current that is injected into the main signal amplification circuit to achieve theoretical offset voltage elimination.

[0040] like Figure 3As shown, during the first half of the self-zeroing clock cycle, i.e., the sampling phase: switches S1, S2, S7, and S8 are off, while switches S3, S4, S5, S6, S9, and S10 are on. The input offset signal is converted into a compensation signal output through the input sampling capacitor, chopper switch, and integrator. At this time, the self-zeroing circuit of the integrator is in the amplification phase, and the offset voltage of the integrator is stored in Caz1 and Caz2. Due to the effect of the two sets of switches S7, S8, S9, and S10 added in this invention, the common-mode terminals of Cs1 and Cs2 are completely separated from Caz1 and Caz2, and the signal ripple will not couple to Caz1 and Caz2.

[0041] During the second half of the self-zeroing cycle, i.e., the amplification phase: switches S1, S2, S7, and S8 are turned on, while switches S3, S4, S5, S6, S9, and S10 are turned off. The signal, carrying capacitors Caz1 and Caz2 storing the GM3 offset voltage, passes through the integrator and then through GM4, where it is converted into a compensation current that is injected into the main signal amplification circuit, thus achieving the theoretical elimination of the GM3 offset voltage.

[0042] like Figure 4 As shown, in this invention, the chop clock period is twice the AZ clock period. AZ and TS states are applied during the positive and negative phases of the chopping phase, respectively, thereby achieving offset voltage cancellation and ripple cancellation for the entire operational amplifier circuit. The AZ state pulse width needs to satisfy the settling time of the entire ripple cancellation circuit.

[0043] This invention provides a ripple cancellation circuit with self-zero adjustment. Through a novel structural design, two sets of switches are added to the input of the ripple cancellation circuit. These switches are open during the self-zero sampling phase and closed during the amplification phase. Therefore, during the sampling phase, the integrator capacitor is more thoroughly isolated from external ripple signals, thereby eliminating ripple interference and allowing the integrator capacitor to continuously output accurate compensation current.

[0044] This invention uses a self-zeroing technique for storing input offset in the integrator. The self-zeroing circuit consists of a switch and a zeroing capacitor.

[0045] The switch opens after the input capacitor of the ripple cancellation circuit during sampling phase. Simultaneously, the operational amplifier is disconnected from the circuit, forming a buffer structure. At this time, the op-amp's offset voltage is stored on the zero-adjustment capacitor at its input. During amplification phase, both the op-amp and the input sampling capacitor are normally connected to the circuit. The op-amp's unity negative feedback is disconnected, forming an integrator structure with the integrating capacitor. The voltage on the zero-adjustment capacitor will then cancel out the op-amp's offset voltage.

[0046] In the amplification phase, the operational amplifier is connected to the circuit and forms an integrator with the integrating capacitor to convert the ripple current into voltage and feed it out. In the sampling phase, the operational amplifier is disconnected from the circuit, and one end of the integrating capacitor is also disconnected from the input terminal of the ripple elimination circuit. According to the principle of charge conservation, the integrating capacitor will continuously output the voltage information at the end of the previous phase, so that the ripple elimination circuit can work in the entire cycle.

[0047] This invention provides a ripple cancellation circuit with self-zero adjustment and a chopper operational amplifier. By adding two sets of zero-adjustment switches after the input capacitor of the ripple cancellation circuit, the ripple cancellation circuit is completely disconnected from the external ripple signal at the sampling phase, ensuring that the total charge on the integrating capacitor is not affected. This ensures the accuracy of the compensation current, improves the ripple cancellation effect, and reduces the residual offset voltage. This invention achieves a high-precision, low-offset operational amplifier with an offset voltage of less than 2uV under all voltage and full temperature conditions, which is far lower than that of similar operational amplifiers.

[0048] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0049] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A ripple elimination circuit with self-zero adjustment, characterized in that, Chopper operational amplifiers, including those comprising a pre-stage chopper unit and a pre-stage transconductance amplification unit, are used in the following applications: The input sampling unit includes a differential sampling capacitor subunit and a first switch group; the input terminal of the differential sampling capacitor subunit is connected to the differential output terminal of the chopper operational amplifier, and the first switch group is used to control the on / off state of the differential sampling capacitor subunit with the common-mode level and subsequent circuits; The input terminal of the post-stage chopper unit is connected to the output terminal of the input sampling unit, and is used to chop the sampled signal. The self-zeroing integration unit includes an operational amplifier subunit, a zeroing subunit, an integrating capacitor subunit, and a second switch group; the input terminal of the operational amplifier subunit is connected to the output terminal of the subsequent chopper unit; the zeroing subunit is used to store the offset voltage of the operational amplifier subunit; the integrating capacitor subunit and the operational amplifier subunit cooperate to form an integrating structure; the second switch group is used to control the operating state and signal feedback path of the zeroing subunit. The feedback unit has its input connected to the output of the integral self-zeroing unit, and its output fed back to the pre-amplifier signal node of the chopper operational amplifier to inject a compensation signal to cancel the offset voltage and chopper ripple.

2. The ripple elimination circuit with self-zero adjustment according to claim 1, characterized in that, The differential sampling capacitor subunit includes differential input capacitor Cs1 and capacitor Cs2; the first switch group includes switch S7, switch S8, switch S9 and switch S10. The first terminal of capacitor Cs1 is connected to the output terminal Vout- of the chopper operational amplifier, and the first terminal of capacitor Cs2 is connected to the output terminal Vout+ of the chopper operational amplifier. The second terminal of capacitor Cs1 is connected to the first terminal of switch S7 and the first terminal of switch S8. The second terminal of capacitor Cs2 is connected to the first terminal of switch S9 and the first terminal of switch S10. The second terminals of switch S7 and switch S9 are both connected to the common-mode level. The second terminals of switch S8 and switch S10 are connected to the input terminal of the subsequent chopper unit.

3. The ripple elimination circuit with self-zero adjustment according to claim 2, characterized in that, The subsequent chopper unit is the third chopper switch CH3, whose differential input terminal is connected to the second terminal of switches S8 and S10 in the first switch group, and its differential output terminal is connected to the differential input terminal of the operational amplifier subunit.

4. The ripple elimination circuit with self-zero adjustment according to claim 1, characterized in that, The operational amplifier subunit is a transconductance amplifier Gm3; The zero-adjustment subunit includes zero-adjustment capacitors Caz1 and Caz2, and zero-adjustment switches S3 and S4. Zero-adjustment capacitor Caz1 is differentially connected between the non-inverting input and output of transconductance amplifier Gm3, and zero-adjustment capacitor Caz2 is differentially connected between the inverting input and output of transconductance amplifier Gm3. The first terminal of zero-adjustment switch S3 is connected to the common node of zero-adjustment capacitor Caz1 and the non-inverting input of transconductance amplifier Gm3, and the first terminal of zero-adjustment switch S4 is connected to the common node of zero-adjustment capacitor Caz2 and the inverting input of transconductance amplifier Gm3. The second terminals of both zero-adjustment switches S3 and S4 are connected to a common-mode level. The integrating capacitor subunit includes integrating capacitor Cint1 and integrating capacitor Cint2. The integrating capacitor Cint1 is differentially connected between the non-inverting input terminal and the output terminal of the transconductance amplifier Gm3, and the integrating capacitor Cint2 is differentially connected between the inverting input terminal and the output terminal of the transconductance amplifier Gm3. The second switch group includes switch S1 and switch S2. The first end of switch S1 is connected to the non-inverting input of transconductance amplifier Gm3, and the first end of switch S2 is connected to the inverting input of transconductance amplifier Gm3.

5. The ripple elimination circuit with self-zero adjustment according to claim 4, characterized in that, The feedback unit is a transconductance amplifier Gm4, whose differential input terminal is connected to the differential output terminal of the operational amplifier subunit, and whose differential output terminal is connected to the second terminal of switches S1 and S2 in the second switch group.

6. The ripple elimination circuit with self-zero adjustment according to claim 1, characterized in that, The preceding signal node is the common connection node between the output terminal of the preceding chopper unit and the input terminal of the preceding transconductance amplifier unit in the chopper operational amplifier.

7. The ripple elimination circuit with self-zero adjustment according to claim 4, characterized in that, The switches S7, S8, S9, and S10 of the first switch group, the off group S1 and off group S2 of the second switch group, and the zero-adjustment switch S3 and zero-adjustment switch S4 of the zero-adjustment subunit are all controlled synchronously by the same self-zeroing clock.

8. The ripple elimination circuit with self-zero adjustment according to claim 3, characterized in that, The control clock of the pre-stage chopper unit of the chopper operational amplifier and the third chopper switch CH3 are chopper clocks with the same frequency but different phases, and the period of the chopper clock is twice the period of the self-zeroing clock.

9. A chopper operational amplifier, characterized in that, include: The main signal amplification circuit is used to perform differential amplification of the input signal; The ripple elimination circuit with self-zero adjustment according to any one of claims 1-8 has its input terminal connected to the output terminal of the main signal amplification circuit; The transconductance amplification unit serves as the feedback unit of the ripple elimination circuit. Its input terminal is connected to the output terminal of the integral self-zeroing unit of the ripple elimination circuit, and its output terminal is connected to the signal node of the main signal amplification circuit to inject compensation current into the main signal amplification circuit, thereby achieving offset voltage suppression and ripple elimination.

10. The chopper operational amplifier according to claim 9, characterized in that, The transconductance amplification unit is a transconductance amplifier Gm4. The transconductance amplifier Gm4 converts the feedback voltage output by the integral self-zeroing unit in the ripple elimination circuit into a compensation current. The compensation current is injected into the node between the front-stage chopper unit and the front-stage transconductance amplification unit in the main signal amplification circuit to cancel the offset voltage and ripple interference of the main signal amplification circuit.

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