Method of manufacturing integrated circuit device

Abstract

A method includes forming a base substrate having a semiconductor substrate having a first dopant concentration, a bottom epitaxial semiconductor layer having a second dopant concentration greater than the first dopant concentration, and a top epitaxial semiconductor layer having a third dopant concentration less than the second dopant concentration; forming a front end of line (FEOL) structure on the top epitaxial semiconductor layer; forming a first back end of line (BEOL) structure on the FEOL structure; removing the semiconductor substrate to expose the bottom epitaxial semiconductor layer; and forming a second BEOL structure to space the second BEOL structure from the first BEOL structure, with the FEOL structure between the second BEOL structure and the first BEOL structure by removing the bottom epitaxial semiconductor layer by wet etching to expose the top epitaxial semiconductor layer, and patterning the top epitaxial semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0141454, filed on October 16, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method of manufacturing an integrated circuit device, and more specifically, to a method of manufacturing an integrated circuit device including a back-side power delivery network (BSPDN) structure in which wiring structures are formed on the back side of a substrate. Background Technology

[0004] Due to advancements in electronic technology, integrated circuit devices have rapidly miniaturized. Therefore, research is underway to achieve higher integration density while ensuring the required functionality and operating speed of integrated circuit devices, focusing on the efficient design of wiring structures. Furthermore, there is a need to develop techniques that can improve the stability of integrated circuit manufacturing processes and / or, consequently, the reliability of the resulting integrated circuit devices, by providing uniform flatness of the back-side surface of the substrate used in the fabrication process of integrated circuit devices with BSPDN structures. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a method for manufacturing an integrated circuit device. When performing a thinning process for reducing the thickness of a substrate from the back side of the substrate and subsequent processes thereto in the manufacturing process of an integrated circuit device having a back-side power delivery network (BSPDN) structure, the method allows for improved stability of the manufacturing process of the integrated circuit device by providing uniform flatness without thickness deviations depending on the location in the substrate (e.g., relatively uniform flatness with thickness deviations below a certain value).

[0006] According to an exemplary embodiment of the present invention, a method for manufacturing an integrated circuit device is provided. The method includes: forming a substrate having a structure comprising a semiconductor substrate, a bottom epitaxial semiconductor layer, and a top epitaxial semiconductor layer; the semiconductor substrate having a first dopant concentration; the bottom epitaxial semiconductor layer being integrally connected to the semiconductor substrate and having a second dopant concentration greater than the first dopant concentration; and the top epitaxial semiconductor layer being integrally connected to the bottom epitaxial semiconductor layer and having a third dopant concentration less than the second dopant concentration, wherein the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer are sequentially stacked in a vertical direction; forming a front-end process (FEOL) structure on the front surface of the top epitaxial semiconductor layer; and forming a front-end process (FEOL) structure on the F... A first back-end process (BEOL) structure is formed on the EOL structure, such that the first BEOL structure is vertically spaced from the substrate, and the FEOL structure is located between the first BEOL structure and the substrate; a semiconductor substrate is removed from the substrate to expose a bottom epitaxial semiconductor layer; and a second BEOL structure is formed by performing a back-side process such that the second BEOL structure is vertically spaced from the first BEOL structure, and the FEOL structure is located between the second BEOL structure and the first BEOL structure, the back-side process including: removing the bottom epitaxial semiconductor layer by wet etching to expose a top epitaxial semiconductor layer and patterning the top epitaxial semiconductor layer.

[0007] According to an exemplary embodiment of the present invention, a method for manufacturing an integrated circuit device is provided. The method includes: forming a substrate having a structure including a semiconductor substrate, a bottom epitaxial semiconductor layer, and a top epitaxial semiconductor layer; the semiconductor substrate having a first dopant concentration, the bottom epitaxial semiconductor layer having a second dopant concentration greater than the first dopant concentration, and the top epitaxial semiconductor layer having a third dopant concentration less than the second dopant concentration; wherein the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer are sequentially stacked in a vertical direction; forming a fin-type active region by etching a portion of the top epitaxial semiconductor layer, the fin-type active region including another portion of the top epitaxial semiconductor layer; and forming a front-end process (FEOL) structure on the fin-type active region, the FEOL structure including a gate line and a source line. The fin / drain regions; forming a first back-end process (BEOL) structure on the FEOL structure such that the first BEOL structure is vertically spaced from the substrate, and the FEOL structure is located between the first BEOL structure and the substrate; removing a semiconductor substrate from the substrate to expose a bottom epitaxial semiconductor layer; and forming a second BEOL structure by performing a back-side process such that the second BEOL structure is vertically spaced from the first BEOL structure, and the FEOL structure is located between the second BEOL structure and the first BEOL structure, the back-side process including: removing the bottom epitaxial semiconductor layer by wet etching to expose the back-side surface of the fin active region, and etching at least a portion of the fin active region.

[0008] According to an exemplary embodiment of the present invention, a method for manufacturing an integrated circuit device is provided. The method includes: forming a substrate comprising a Si substrate having a first dopant concentration, a bottom epitaxial Si layer integrally connected to the Si substrate and having a second dopant concentration greater than the first dopant concentration, and a top epitaxial Si layer without germanium (Ge), the top epitaxial Si layer integrally connected to the bottom epitaxial Si layer and having a third dopant concentration less than the second dopant concentration; forming a fin-type active region by etching a portion of the top epitaxial Si layer, the fin-type active region including another portion of the top epitaxial Si layer; forming a front-end process (FEOL) structure on the fin-type active region, the FEOL structure including a gate line and a source / drain region; and forming a first back-end process (BEOL) structure on the FEOL structure such that the first BEOL... The OL structure is vertically spaced from the substrate, and the FEOL structure is located between the first BEOL structure and the substrate; a sustaining wafer is bonded to the first BEOL structure; while the first BEOL structure is bonded to the sustaining wafer, a Si substrate is removed from the substrate to expose a bottom epitaxial Si layer; and a second BEOL structure is formed by performing a back-side process to space the second BEOL structure from the first BEOL structure, and the FEOL structure is located between the second BEOL structure and the first BEOL structure, the back-side process including: while the first BEOL structure is bonded to the sustaining wafer, removing the bottom epitaxial Si layer by wet etching to expose the back-side surface of the fin active region and etching at least a portion of the fin active region. Attached Figure Description

[0009] The exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0010] In the attached image:

[0011] Figure 1 This is a flowchart illustrating a method for manufacturing an integrated circuit device according to an example embodiment;

[0012] Figures 2A to 2H These are cross-sectional views showing the process sequence of a method for manufacturing an integrated circuit device according to an example embodiment;

[0013] Figure 3 This is an example diagram illustrating the dopant concentration profile in a substrate used in a method for manufacturing an integrated circuit device according to an exemplary embodiment;

[0014] Figure 4 This is an example diagram illustrating the dopant concentration profile in a substrate used in a method for manufacturing an integrated circuit device according to an exemplary embodiment;

[0015] Figure 5A and Figure 5BThese are cross-sectional views illustrating, respectively, an example of the process sequence of bonding a first back-end process (BEOL) structure and a method for maintaining wafers bonded together according to an exemplary embodiment of a method for manufacturing an integrated circuit device;

[0016] Figure 6 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an example embodiment;

[0017] Figure 7 This is an example of a planar layout diagram of an integrated circuit device manufactured by a method of manufacturing an integrated circuit device according to an exemplary embodiment;

[0018] Figures 8 to 24 This is a cross-sectional view illustrating the process sequence of a method for manufacturing an integrated circuit device according to an example embodiment, and specifically, Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 These are shown separately according to the process sequence and along... Figure 7 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1', and Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B These are shown separately according to the process sequence and along... Figure 7 A cross-sectional view of the region corresponding to the section intercepted by line Y1-Y1'; and

[0019] Figures 25 to 29 These are cross-sectional views illustrating the process sequence of a method for manufacturing an integrated circuit device according to an example embodiment, and showing the process sequence and its progression along the process path. Figure 7 The cross-sectional structure of the region corresponding to the section intercepted by line X1-X1'. Detailed Implementation

[0020] Although the terms “same,” “equal,” or “equivalent” are used in the description of the example embodiments, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within the expected range of manufacturing or operational tolerances (e.g., ±10%).

[0021] When the terms “approximately,” “substantially,” or “roughly” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Furthermore, when the terms “approximately,” “substantially,” or “roughly” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but the degrees of freedom of the shape are within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “approximately” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0022] As used herein, when expressions such as “one of…”, “one or more of…”, “any one of…”, and “at least one of…” follow a list of elements, they modify the entire list of elements, not individual elements within that list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0023] In the following description, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same components are indicated by the same reference numerals throughout the specification, and repeated descriptions thereof are omitted.

[0024] Figure 1 This is a flowchart illustrating a method for manufacturing an integrated circuit device according to an example embodiment. Figures 2A to 2H These are cross-sectional views illustrating the process sequence of a method for manufacturing an integrated circuit device according to an example embodiment. (Refer to...) Figure 1 and Figures 2A to 2H A method for manufacturing an integrated circuit device according to an example embodiment is described.

[0025] Reference Figure 1 and Figure 2A In process P12, a substrate 110 is formed. The substrate 110 has a structure in which a semiconductor substrate 102 having a first dopant concentration, a bottom epitaxial semiconductor layer 103 having a second dopant concentration greater than the first dopant concentration, and a top epitaxial semiconductor layer 106 having a third dopant concentration less than the second dopant concentration are stacked in the vertical direction (Z direction) in the order stated.

[0026] The bottom epitaxial semiconductor layer 103 can be integrally connected to the semiconductor substrate 102, and the top epitaxial semiconductor layer 106 can be integrally connected to the bottom epitaxial semiconductor layer 103. The semiconductor substrate 102 can have a front surface 102F and a back surface 102B. The process of forming the substrate 110 can include a process of forming the bottom epitaxial semiconductor layer 103 by epitaxially growing a semiconductor layer doped with a second dopant concentration on the front surface 102F of the semiconductor substrate 102, and a process of forming the top epitaxial semiconductor layer 106 by epitaxially growing a semiconductor layer doped with a third dopant concentration on the front surface 103F of the bottom epitaxial semiconductor layer 103.

[0027] The substrate 110 may comprise only a semiconductor substrate 102, a bottom epitaxial semiconductor layer 103, and a top epitaxial semiconductor layer 106. In the substrate 110, each of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 may comprise silicon (Si) doped with p-type or n-type dopants. The substrate 110 may not include germanium (Ge). For example, the substrate 110 may not include a Ge layer and a SiGe layer. Each of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 in the substrate 110 may comprise silicon (Si), thereby eliminating the possibility of crystal defects due to lattice mismatch, which may occur when the Si layer is present in the substrate 110 along with another semiconductor material layer including germanium (Ge) (e.g., a SiGe layer or a Ge layer).

[0028] In the substrate 110, the semiconductor substrate 102 may include a Si substrate having a shape from approximately 1 × 10⁻⁶. 14 atoms / cm 3 Up to approximately 1×10 17 atoms / cm 3 The range of first dopant concentrations selected (e.g., approximately 1 × 10⁻⁶) 14 atoms / cm 3 Up to approximately 5×10 15 atoms / cm 3 The bottom epitaxial semiconductor layer 103 may include a Si layer having a concentration greater than that of the first dopant and ranging from approximately 1 × 10⁻⁶. 18 atoms / cm 3 Up to approximately 1×10 21 atoms / cm 3 The range of the second dopant concentration selected (e.g., approximately 1 × 10⁻⁶) 18 atoms / cm 3 Up to approximately 1×10 20 atoms / cm 3In this document, the bottom epitaxial semiconductor layer 103 may also be referred to as the bottom epitaxial Si layer. The top epitaxial semiconductor layer 106 may include a Si layer having a concentration less than that of the second dopant and ranging from approximately 1 × 10⁻⁶. 14 atoms / cm 3 Up to approximately 1×10 17 atoms / cm 3 The range of third dopant concentrations selected (e.g., approximately 1 × 10⁻⁶) 14 atoms / cm 3 Up to approximately 5×10 15 atoms / cm 3 In this paper, the top epitaxial semiconductor layer 106 may also be referred to as the top epitaxial Si layer.

[0029] In some example embodiments, the first dopant concentration of the semiconductor substrate 102 in the substrate 110 may be equal to or similar to the third dopant concentration of the top epitaxial semiconductor layer 106. In some example embodiments, the first dopant concentration of the semiconductor substrate 102 in the substrate 110 may be different from the third dopant concentration of the top epitaxial semiconductor layer 106. For example, the first dopant concentration may be less than or greater than the third dopant concentration.

[0030] In some example embodiments, each of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 in the substrate substrate 110 may comprise silicon (Si) doped with a p-type dopant. The p-type dopant may comprise boron (B), aluminum (Al), gallium (Ga), indium (In), or combinations thereof. For example, the p-type dopant may comprise boron (B).

[0031] In some example embodiments, each of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 in the substrate substrate 110 may comprise silicon (Si) doped with an n-type dopant. The n-type dopant may comprise nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. For example, the n-type dopant may comprise phosphorus (P).

[0032] In some example embodiments, when the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 in the substrate substrate 110 each comprise silicon (Si) doped with p-type or n-type dopants, at least one of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, or the top epitaxial semiconductor layer 106 may also comprise a neutral dopant, such as carbon (C) or hydrogen (H).

[0033] The thickness of each of the semiconductor substrate 102, the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 in the substrate substrate 110 can be determined differently as needed. In some example embodiments, the thickness of each of the bottom epitaxial semiconductor layer 103 and the top epitaxial semiconductor layer 106 in the vertical direction (Z direction) can be selected from approximately 1 / 10000 to approximately 1 / 100 of the thickness of the semiconductor substrate 102. For example, the thickness of the semiconductor substrate 102 in the vertical direction (Z direction) can be selected from approximately 700 μm to approximately 800 μm, and the thickness of each of the bottom epitaxial semiconductor layer 103 and the top epitaxial semiconductor layer 106 can be selected from approximately 0.5 μm to approximately 3.0 μm, but the inventive concept is not limited thereto. Thus, because the bottom epitaxial semiconductor layer 103, having a dopant concentration greater than that of each of the semiconductor substrate 102 and the top epitaxial semiconductor layer 106, is formed with a relatively small thickness, the volume occupied by the bottom epitaxial semiconductor layer 103 with a relatively high dopant concentration in the substrate 110 can be relatively small. Therefore, when the top epitaxial semiconductor layer 106 is grown on the front surface 103F of the bottom epitaxial semiconductor layer 103, problems caused by autodoping (the unintentional or undesirable diffusion of dopants in the bottom epitaxial semiconductor layer 103 into the top epitaxial semiconductor layer 106 through autodoping) can be reduced or prevented (e.g., problems of uniformity of dopant concentration depending on the position in the top epitaxial semiconductor layer 106, or problems of differences in dopant concentration between the central and edge portions of the top epitaxial semiconductor layer 106 in a cross section parallel to the front surface 106F of the top epitaxial semiconductor layer 106).

[0034] Figure 3 This is a diagram illustrating an example of the dopant concentration profile CP1 in the substrate 110.

[0035] Reference Figure 3 The second dopant concentration in the bottom epitaxial semiconductor layer 103 can have a concentration gradient, such that the second dopant concentration has a maximum value in the central portion of the bottom epitaxial semiconductor layer 103 based on the total thickness of the bottom epitaxial semiconductor layer 103 in the vertical direction (Z direction), and gradually decreases away from the central portion of the bottom epitaxial semiconductor layer 103 towards the edge portions of the bottom epitaxial semiconductor layer 103 adjacent to the semiconductor substrate 102 and the top epitaxial semiconductor layer 106, respectively. In the bottom epitaxial semiconductor layer 103, the thickness DMX of the central portion where the second dopant concentration has a maximum value in the vertical direction (Z direction) can be greater than the corresponding thicknesses D11 and D12 of the edge portions in the vertical direction (Z direction).

[0036] Figure 4This is a diagram illustrating another example of the dopant concentration profile CP2 in the substrate 110.

[0037] Reference Figure 4 The second dopant concentration in the bottom epitaxial semiconductor layer 103 can have a variable concentration gradient in the vertical direction (Z direction). The second dopant concentration can have a maximum value in the edge portion of the bottom epitaxial semiconductor layer 103 near the semiconductor substrate 102 in the vertical direction (Z direction), and the second dopant concentration can gradually decrease in the vertical direction (Z direction) from the edge portion of the bottom epitaxial semiconductor layer 103 near the semiconductor substrate 102 toward the top epitaxial semiconductor layer 106. In the bottom epitaxial semiconductor layer 103, the first distance D21 from the portion having the maximum value of the second dopant concentration to the top epitaxial semiconductor layer 106 can be larger in the vertical direction (Z direction) than the second distance D22 from the portion having the maximum value of the second dopant concentration to the semiconductor substrate 102.

[0038] Reference Figure 1 and Figure 2B In process P14, a front-end process (FEOL) structure FS can be formed on the front surface 106F of the epitaxial semiconductor layer 106 on top of the substrate 110. See below for further details. Figures 8 to 14 A specific example describing the process for forming the FEOL structure FS.

[0039] Reference Figure 1 and Figure 2C In process P16, a first back-end process (BEOL) structure BS1 can be formed on the FEOL structure FS, and the first back-end process (BEOL) structure BS1 is spaced apart from the substrate 110 in the vertical direction (Z direction), and the FEOL structure FS is located between the first back-end process (BEOL) structure BS1 and the substrate 110. See below for further details. Figure 15 A specific example of the process for forming the first BEOL structure BS1 is described.

[0040] Reference Figure 1 and Figure 2D In process P18, the sustaining wafer SW can be bonded to the first BEOL structure BS1. Next, the semiconductor substrate 102 can be positioned (e.g., flipped) with its vertical direction (Z direction) facing upwards.

[0041] In some example embodiments, the sustaining wafer SW may include a Si substrate. In some example embodiments, in order to bond the sustaining wafer SW to a first BEOL structure BS1, the first BEOL structure BS1 may be aligned to face the sustaining wafer SW, and subsequently, the first BEOL structure BS1 and the sustaining wafer SW may be bonded to each other.

[0042] In some example embodiments, in order to bond the first BEOL structure BS1 and the sustaining wafer SW to each other, the bonding target surfaces of the first BEOL structure BS1 and the sustaining wafer SW can each be first plasma cleaned, then the sustaining wafer SW is pressed against the first BEOL structure BS1 so that the bonding target surface of the sustaining wafer SW contacts the first BEOL structure BS1 and bonding is performed, and then an annealing process can be performed.

[0043] To perform plasma cleaning on the bonding target surfaces of the first BEOL structure BS1 and the maintenance wafer SW, plasma and deionized water can be supplied to the bonding target surfaces of the first BEOL structure BS1 and the maintenance wafer SW in a surface treatment chamber. The process gas used to generate the plasma can include nitrogen, oxygen, argon, helium, or combinations thereof. Deionized water and plasma can be supplied to the surface treatment chamber simultaneously, or sequentially or alternately. The plasma can be used to remove contaminants from the bonding target surfaces of the first BEOL structure BS1 and the maintenance wafer SW, and the deionized water can be used as a medium for chemical bonding. More specifically, the plasma can break the Si-O bonds in the exposed silicon oxide film at the bonding target surfaces of each of the first BEOL structure BS1 and the maintenance wafer SW under vacuum, exposing -Si groups at the bonding target surfaces. By supplying water (H2O) to the bonding target surfaces, the deionized water can cause -OH groups to form at the bonding target surfaces. Therefore, the -Si groups present on the surface of the bonding target can maintain their bond with the -OH groups.

[0044] The first BEOL structure BS1 and the sustaining wafer SW, which have undergone plasma cleaning as described above, can be dried to remove excess water present on the bonding target surface of each of the first BEOL structure BS1 and the sustaining wafer SW.

[0045] Figure 5A and Figure 5B It shows the basis respectively. Figure 1 The cross-sectional view of process P18 is an example of the process sequence of the first BEOL structure BS1, which has undergone plasma cleaning as described above, and the method of maintaining the wafer SW bonded to each other.

[0046] Reference Figure 5A In the bonding chamber maintained under vacuum, the holding wafer SW can be attracted (e.g., adsorbed) onto the lower surface of the upper chuck 410 included in the bonding apparatus 400, and the process structure WF1 can be attracted (e.g., adsorbed) onto the upper surface of the lower chuck 420. The process structure WF1 is structured as follows: Figure 2CAs shown, the FEOL structure FS and the first BEOL structure BS1 are formed sequentially on the substrate 110 in the order stated. The process structure WF1 can be attracted (e.g., adsorbed) onto the upper surface of the lower chuck 420 such that the substrate 110 faces the lower chuck 420 and the first BEOL structure BS1 faces the holding wafer SW.

[0047] Reference Figure 5B ,exist Figure 5A In the resulting product, the central portion of the holding wafer SW can be pushed downward in the direction of arrow AR using the pusher 430 of the bonding device 400, thereby bringing the central portion of the holding wafer SW into contact with the central portion of the process structure WF1. As a result, the central portion of the holding wafer SW and the central portion of the process structure WF1 can be bonded to each other by the intermolecular forces between the corresponding contacting surfaces of the central portions of the holding wafer SW and the process structure WF1.

[0048] After the bonding between the central portion of the sustaining wafer SW and the central portion of the process structure WF1 begins, as the bonding wave between the sustaining wafer SW and the process structure WF1 propagates radially outward from the central portion between the bonding target surfaces, the bonding target surface of the sustaining wafer SW can bond to the bonding target surface of the first BEOL structure BS1 of the process structure WF1. Here, the Si-OH groups present at the bonding target surface of the sustaining wafer SW can bond to the Si-OH groups present at the bonding target surface of the first BEOL structure BS1, and when van der Waals force bonding occurs between the -OH groups present at the bonding target surfaces of the sustaining wafer SW and the first BEOL structure BS1, water (H2O) can be separated from the corresponding bonding target surfaces of the sustaining wafer SW and the first BEOL structure BS1. As a result, the bonding target surfaces of the sustaining wafer SW and the first BEOL structure BS1 can be bonded to each other via Si-O-Si bonds. After the bonding process is completed, an annealing process can be performed in a relatively high temperature atmosphere, where water (H2O) separated from the respective bonding target surfaces of the holding wafer SW and the first BEOL structure BS1 can be removed.

[0049] Reference Figure 1 and Figure 2E In process P20, the BEOL structure BS1 is bonded to the sustaining wafer SW. Figure 2D In the resulting product, the semiconductor substrate 102 can be removed to expose the bottom epitaxial semiconductor layer 103 of the bonded substrate 110.

[0050] To remove the semiconductor substrate 102, a mechanical polishing process and a chemical mechanical polishing (CMP) process can be performed sequentially in the order stated. When the CMP process is performed to remove the semiconductor substrate 102, a portion of the bottom epitaxial semiconductor layer 103 may be consumed by the CMP process. As a result, in the product retained after the removal of the semiconductor substrate 102, the vertical (Z-direction) thickness of the bottom epitaxial semiconductor layer 103 retained on the back surface 106B of the top epitaxial semiconductor layer 106 can be smaller than that of the bottom epitaxial semiconductor layer 103 before the removal of the semiconductor substrate 102 (by...). Figure 2E The vertical (Z-direction) thickness is indicated by the dashed line in the figure.

[0051] After removing the semiconductor substrate 102, the dopant concentration in the bottom epitaxial semiconductor layer 103 remaining on the back surface 106B of the top epitaxial semiconductor layer 106 can be greater than the dopant concentration in the top epitaxial semiconductor layer 106. In some example embodiments, when the bottom epitaxial semiconductor layer 103 has Figure 4 When the dopant concentration profile CP2 is shown, the bottom epitaxial semiconductor layer 103 retained on the back surface 106B of the top epitaxial semiconductor layer 106 can have a dopant concentration that gradually increases in the vertical direction (Z direction) away from the top epitaxial semiconductor layer 106.

[0052] exist Figure 1 In process P22, a back-side process can be performed to form the second BEOL structure BS2 (see...). Figure 2H The second BEOL structure BS2 is spaced apart from the first BEOL structure BS1 in the vertical direction (Z direction), and the FEOL structure FS is located between the second BEOL structure BS2 and the first BEOL structure BS1. The back-side process includes a first process of removing the bottom epitaxial semiconductor layer 103 by wet etching to expose the back-side surface 106B of the top epitaxial semiconductor layer 106, and a second process of patterning the top epitaxial semiconductor layer 106.

[0053] A first process of removing the bottom epitaxial semiconductor layer 103 by wet etching can be performed by utilizing the difference in dopant concentration between the top epitaxial semiconductor layer 106, which has a relatively low dopant concentration, and the bottom epitaxial semiconductor layer 103, which has a relatively high dopant concentration. A second process of patterning the top epitaxial semiconductor layer 106 may include a process of removing at least a portion of the top epitaxial semiconductor layer 106 by etching.

[0054] In some example embodiments, in order to perform Figure 1 For process P22, the following reference can be performed. Figure 2F , Figure 2G and Figure 2H The described process.

[0055] Reference Figure 2F The bottom epitaxial semiconductor layer 103 can be removed from the resulting product by wet etching, thereby exposing the back surface 106B of the top epitaxial semiconductor layer 106. In the resulting product, the back surface 106B of the top epitaxial semiconductor layer 106 is exposed. Figure 2E According to the diagram Figure 1 The bottom epitaxial semiconductor layer 103 is retained after the semiconductor substrate 102 is removed by process P20.

[0056] The process of removing the bottom epitaxial semiconductor layer 103 by wet etching can be performed by utilizing the difference in dopant concentration between the top epitaxial semiconductor layer 106, which has a relatively low dopant concentration, and the bottom epitaxial semiconductor layer 103, which has a relatively high dopant concentration. In some example embodiments, an etching solution comprising a mixture of an acidic solution, an alkaline solution, and deionized water can be used to remove the bottom epitaxial semiconductor layer 103 by wet etching. For example, the etching solution may include, but is not limited to, an etching solution comprising approximately 1 vol% hydrofluoric acid (HF), approximately 3 vol% nitric acid (HNO3), approximately 2 vol% phosphoric acid (H3PO4), approximately 6 vol% acetic acid (CH3COOH), and approximately 88 vol% deionized water.

[0057] Because the dopant concentration in the bottom epitaxial semiconductor layer 103 is greater than that in the top epitaxial semiconductor layer 106, when the bottom epitaxial semiconductor layer 103 is removed by wet etching using the etching solution described above, the bottom epitaxial semiconductor layer 103 can be removed with relatively high etch selectivity relative to the top epitaxial semiconductor layer 106. Therefore, in the product obtained by removing the bottom epitaxial semiconductor layer 103 via wet etching, the bottom epitaxial semiconductor layer 103 can be removed smoothly without unintentionally or undesirably retaining it or unintentionally or undesirably consuming a portion of the top epitaxial semiconductor layer 106. As a result, after removing the bottom epitaxial semiconductor layer 103, the top epitaxial semiconductor layer 106 can be retained in the resulting product while having a relatively constant thickness depending on its location (e.g., relatively uniform flatness with a thickness deviation below a certain value).

[0058] In some example embodiments, when according to Figure 1When process P20 performs the process of removing semiconductor substrate 102, a portion of the bottom epitaxial semiconductor layer 103 may be consumed during the process of removing the portion of semiconductor substrate 102 adjacent to the bottom epitaxial semiconductor layer 103 by CMP process. Here, the amount of bottom epitaxial semiconductor layer 103 consumed may be non-uniform depending on its position in the bottom epitaxial semiconductor layer 103, and therefore, the thickness of the bottom epitaxial semiconductor layer 103 remaining on the back surface 106B of the top epitaxial semiconductor layer 106 after removing semiconductor substrate 102 may not be constant depending on its position (e.g., it may not have a relatively uniform flatness with a thickness deviation below a certain value). Here, when the bottom epitaxial semiconductor layer 103 has Figure 4 When the dopant concentration profile CP2 is shown, in the bottom epitaxial semiconductor layer 103 remaining on the back side surface 106B of the top epitaxial semiconductor layer 106 after removing the semiconductor substrate 102, the dopant concentration at the exposed surface of the portion with a relatively high height is greater than the dopant concentration at the exposed surface of the portion with a relatively low height. Therefore, when according to Figure 1 When the wet etching process P20 removes the bottom epitaxial semiconductor layer 103 retained on the back surface 106B of the top epitaxial semiconductor layer 106, the etching rate of the portion of the bottom epitaxial semiconductor layer 103 with a relatively high height can be greater than the etching rate of the portion of the bottom epitaxial semiconductor layer 103 with a relatively low height. As a result, even when the thickness of the bottom epitaxial semiconductor layer 103 retained on the back surface 106B of the top epitaxial semiconductor layer 106 is not constant depending on the position in the bottom epitaxial semiconductor layer 103 (e.g., relatively non-uniform flatness with a thickness deviation higher than a certain value), the bottom epitaxial semiconductor layer 103 can be smoothly removed at all locations in the bottom epitaxial semiconductor layer 103 without the problem of unintentional and / or partial retention of the bottom epitaxial semiconductor layer 103 while performing the wet etching process described above.

[0059] Reference Figure 2G In reference Figure 2F In the product described, a portion of the top epitaxial semiconductor layer 106 can be etched from the back surface 106B of the top epitaxial semiconductor layer 106 to form a plurality of holes 106H in the top epitaxial semiconductor layer 106 to expose portions of the FEOL structure FS.

[0060] Reference Figure 2H In reference Figure 2G The resulting product described can form a second BEOL structure BS2, which includes a contact structure CTS that fills each of the plurality of holes 106H in the top epitaxial semiconductor layer 106.

[0061] According to reference Figures 2A to 2HThe method for manufacturing an integrated circuit device described herein, as referenced Figure 2C After the formation of the first BEOL structure BS1 is described, as shown in the reference... Figure 2H Before the formation of the second BEOL structure BS2, refer to Figure 2E The description refers to the removal of the semiconductor substrate 102 to perform a thinning process for reducing the thickness of the substrate 110, followed by reference to... Figure 2F The bottom epitaxial semiconductor layer 103 is removed by wet etching using the difference in dopant concentration between a top epitaxial semiconductor layer 106 with a relatively low dopant concentration and a bottom epitaxial semiconductor layer 103 with a relatively high dopant concentration, thereby exposing the back surface 106B of the top epitaxial semiconductor layer 106. Therefore, the top epitaxial semiconductor layer 106 can have a back surface 106B that has improved flatness (e.g., relatively uniform flatness with a thickness deviation below a certain value) without differences in surface roughness depending on the location within the top epitaxial semiconductor layer 106. Therefore, in the manufacturing process of an integrated circuit device with a back-side power delivery network (BSPDN) structure, when a subsequent process of the thinning process is performed by using a top epitaxial semiconductor layer 106 retained in the resulting product after a thinning process for reducing the thickness of the substrate 110, the back-side surface 106B of the top epitaxial semiconductor layer 106 can provide a relatively uniform flatness across its entire surface without thickness deviations (e.g., thickness deviations below a specific value) depending on the location of the top epitaxial semiconductor layer 106 retained in the resulting product, thereby improving the stability of the manufacturing process of the integrated circuit device and / or improving the reliability of the resulting integrated circuit device.

[0062] Figure 6 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an example embodiment. As an implementation... Figure 1 Another example of process P22 can be performed as follows (refer to the following). Figure 6 The described process.

[0063] Reference Figure 6 , as in reference Figure 2EIn the described product, while the back surface 106B of the top epitaxial semiconductor layer 106 is covered by the bottom epitaxial semiconductor layer 103, a portion of each of the bottom epitaxial semiconductor layer 103 and the top epitaxial semiconductor layer 106 can be etched from the exposed surface of the bottom epitaxial semiconductor layer 103 using an etching mask including a spin-on hard mask (SOH) material, thereby forming a plurality of holes 106H in the top epitaxial semiconductor layer 106 to expose portions of the FEOL structure FS. After forming the plurality of holes 106H in the top epitaxial semiconductor layer 106, the back surface 106B of the top epitaxial semiconductor layer 106 can remain covered by the reserved portion of the bottom epitaxial semiconductor layer 103.

[0064] Next, with reference Figure 2F A similar method, as described, can be used to remove [something] via wet etching. Figure 6 The bottom epitaxial semiconductor layer 103 is retained in the resulting product to expose the back surface 106B of the top epitaxial semiconductor layer 106, and subsequently, with reference... Figure 2H In a similar manner, a second BEOL structure BS2 can be formed, comprising a contact structure CTS that fills each of the plurality of holes 106H in the top epitaxial semiconductor layer 106.

[0065] According to reference Figure 6 The method for manufacturing an integrated circuit device described herein, in accordance with reference to Figure 1 and Figures 2A to 2H The description is similar. After removing the semiconductor substrate 102 by a thinning process to reduce the thickness of the substrate 110, the method includes a process of exposing the back surface 106B of the top epitaxial semiconductor layer 106 by removing the bottom epitaxial semiconductor layer 103 via wet etching using the difference in dopant concentration between the top epitaxial semiconductor layer 106, which has a relatively low dopant concentration, and the bottom epitaxial semiconductor layer 103, which has a relatively high dopant concentration. For example, in reference to Figure 6In the described method for manufacturing an integrated circuit device, since the bottom epitaxial semiconductor layer 103 is removed by wet etching after performing a process of forming a plurality of holes 106H in the top epitaxial semiconductor layer 106, the back surface 106B of the top epitaxial semiconductor layer 106 can be protected by the bottom epitaxial semiconductor layer 103 while forming a plurality of holes 106H in the top epitaxial semiconductor layer 106. Therefore, the possibility of surface damage to the top epitaxial semiconductor layer 106 due to the etching process atmosphere during the formation of multiple holes 106H in the top epitaxial semiconductor layer 106 can be reduced or prevented by the bottom epitaxial semiconductor layer 103. After the formation of multiple holes 106H in the top epitaxial semiconductor layer 106, the top epitaxial semiconductor layer 106 can have a back surface 106B with improved flatness that does not depend on the difference in surface roughness (e.g., thickness deviation below a certain value) depending on the location in the top epitaxial semiconductor layer 106. Therefore, when subsequent processes are performed using a top epitaxial semiconductor layer 106 including a plurality of holes 106H, the back surface 106B of the top epitaxial semiconductor layer 106 can provide uniform flatness across its entire surface without thickness deviations (e.g., thickness deviations below a certain value) depending on the position of the top epitaxial semiconductor layer 106 retained in the resulting product, thereby improving the stability of the integrated circuit device manufacturing process and / or improving the reliability of the integrated circuit device obtained as a result.

[0066] Figure 7 This is an example of a planar layout diagram of an integrated circuit device 100 that can be manufactured by a method for manufacturing an integrated circuit device according to an example embodiment.

[0067] Reference Figure 7 The integrated circuit device 100 may include a plurality of nanosheet stacks NSS, a plurality of gate lines 160 surrounding the plurality of nanosheet stacks NSS, and a plurality of source / drain regions 130 arranged sequentially between two adjacent gate lines 160. In the integrated circuit device 100, the plurality of gate lines 160, the plurality of nanosheet stacks NSS, and the plurality of source / drain regions 130 may constitute a plurality of field-effect transistors TR, each having a gate-all-around (GAA) structure.

[0068] Multiple nanosheet stacks (NSS) can be arranged spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction) orthogonal to each other. Multiple gate lines 160 can be spaced apart from each other in the first horizontal direction (X direction) and can extend longitudinally in the second horizontal direction (Y direction). Front-side source / drain contacts CA can be connected to source / drain regions 130 selected from the plurality of source / drain regions 130. Back-side via contacts BCA can be connected to some other source / drain regions 130 selected from the plurality of source / drain regions 130.

[0069] Figures 8 to 24 It shows the manufacturing process. Figure 7 A cross-sectional view of the process sequence of the method of the integrated circuit device 100 shown, and more specifically, Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 These are shown separately according to the process sequence and along... Figure 7 A cross-sectional view of the region corresponding to the section intercepted by line X1-X1', and Figure 9B , Figure 10B , Figure 11B , Figure 12B and Figure 13B These are shown separately according to the process sequence and along... Figure 7 A cross-sectional view of the region corresponding to the section intercepted by line Y1-Y1'. Figures 8 to 24 In, with Figures 2A to 2H The same reference numerals in the figures denote the same components, and here, repeated descriptions are omitted.

[0070] Reference Figure 8 By reference Figure 1 and Figure 2A The process described in P12 is to form a substrate 110 including a semiconductor substrate 102, a bottom epitaxial semiconductor layer 103 and a top epitaxial semiconductor layer 106, and subsequently a stacked structure in which a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS are stacked alternately on the front surface 106F of the top epitaxial semiconductor layer 106.

[0071] In the stacked structure, each of the plurality of sacrificial semiconductor layers 104 and each of the plurality of nanosheet semiconductor layers NS may each comprise a semiconductor material with different etch selectivity. In some example embodiments, each of the plurality of nanosheet semiconductor layers NS may comprise a Si layer, and each of the plurality of sacrificial semiconductor layers 104 may comprise a SiGe layer. The SiGe layer constituting each of the plurality of sacrificial semiconductor layers 104 may have a constant Ge content selected from a range of about 5 at% to about 50 at% (e.g., about 10 at% to about 40 at%). In some example embodiments, each of the plurality of sacrificial semiconductor layers 104 may comprise a SiGe layer, and the corresponding Ge contents in the plurality of sacrificial semiconductor layers 104 may be equal to each other.

[0072] Reference Figure 9A and Figure 9B ,exist Figure 8 In the resulting product, each of the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the top epitaxial semiconductor layer 106 can be partially etched to form a plurality of fin-type active regions F1, each including a retained portion of the top epitaxial semiconductor layer 106. A plurality of trench regions T1 can be defined above the semiconductor substrate 102 by the plurality of fin-type active regions F1. The bottom epitaxial semiconductor layer 103 can be exposed at the lower surface of each of the plurality of trench regions T1. A portion of each of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS can be retained on or above the fin top surface FF of each of the plurality of fin-type active regions F1.

[0073] Next, the device isolation film 112 can be formed to fill a plurality of trench regions T1. The device isolation film 112 may include portions that respectively contact the sidewalls of the plurality of fin active regions F1 and portions that contact the front surface 103F of the bottom epitaxial semiconductor layer 103. The device isolation film 112 may include an oxide film, a nitride film, or a combination thereof. A plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS retained on or above the fin top surface FF of each of the plurality of fin active regions F1 may protrude upward from the upper surface of the device isolation film 112.

[0074] Reference Figure 10A and Figure 10B , can Figure 9A and Figure 9BMultiple dummy gate structures DGS are formed on the resulting product. Each of the multiple dummy gate structures DGS can be formed to extend longitudinally in a second horizontal direction (Y direction). Each of the multiple dummy gate structures DGS may include a dummy oxide film D122, a dummy gate layer D124, and a capping layer D126, which are stacked in the stated order on a stacked structure including multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NS. In some example embodiments, the dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride film.

[0075] Multiple insulating spacers 118 may be formed to respectively cover the two sidewalls of each of the multiple dummy gate structures DGS. The multiple insulating spacers 118 may each include silicon nitride, silicon oxide, SiOC, SiOCN, SiCN, SiBN, SiON, SiBCN, SiOF, SiOCH or combinations thereof.

[0076] A portion of each of the multiple sacrificial semiconductor layers 104 and the multiple nanosheet semiconductor layers NS, as well as a portion of the finned active region F1, can be etched using multiple dummy gate structures DGS and multiple insulating spacers 118 as an etching mask. This divides the multiple nanosheet semiconductor layers NS into multiple nanosheet stacks NSS, each comprising first to fourth nanosheets N1, N2, N3, and N4, and forms multiple recesses R1 in the upper portion of the finned active region F1. The width of each of the first to fourth nanosheets N1, N2, N3, and N4 in a first horizontal direction (X direction) can be defined by the multiple recesses R1. To form the multiple recesses R1, etching can be performed by dry etching, wet etching, or a combination thereof.

[0077] Reference Figure 11A and Figure 11BMultiple source / drain regions 130 can be formed by epitaxially growing semiconductor material on the respective surfaces of the fin-type active region F1 exposed by each recess R1, the first to fourth nanosheets N1, N2, N3, and N4, and the multiple sacrificial semiconductor layers 104. Each of the multiple source / drain regions 130 may include an epitaxially grown semiconductor layer. In some example embodiments, each of the multiple source / drain regions 130 may include a Si layer, a SiC layer, or a SiGe layer. In some example embodiments, when the source / drain regions 130 constitute an NMOS transistor, the source / drain regions 130 may include a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). In some example embodiments, when the source / drain regions 130 constitute a PMOS transistor, the source / drain regions 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and gallium (Ga).

[0078] The insulating pad 142 can be formed to cover the resulting product in which a plurality of source / drain regions 130 are formed, and an inter-gate dielectric 144 can be formed on the insulating pad 142. The insulating pad 142 may comprise silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof, and the inter-gate dielectric 144 may comprise a silicon oxide film, but the inventive concept is not limited thereto.

[0079] Next, a portion of each of the insulating pad 142 and the inter-gate dielectric 144 can be etched to expose multiple capping layers D126 (see [link]). Figure 10A and Figure 10B Next, the dummy gate layer D124 can be exposed by removing multiple capping layers D126, and the insulating pad 142 and the inter-gate dielectric 144 can be partially removed so that the upper surface of the inter-gate dielectric 144 and the upper surface of the dummy gate layer D124 are at approximately the same level.

[0080] Reference Figure 12A and Figure 12B It can be seen from Figure 11A and Figure 11B The resulting product is used to remove the dummy gate layer D124 and the dummy oxide film D122, thereby fabricating a gate space GS. Next, the gate space GS can be used to selectively remove the plurality of sacrificial semiconductor layers 104 retained above the fin active region F1, thereby extending the gate space GS to the space between each of the first to fourth nanosheets N1, N2, N3 and N4, and to the space between the fin top surface FF of the fin active region F1 and the first nanosheet N1.

[0081] Reference Figure 13A and Figure 13B ,exist Figure 12A and Figure 12B In the resulting product, the gate dielectric film 152 can be formed to cover the exposed surfaces of the fin-type active region F1 and the first to fourth nanosheets N1, N2, N3, and N4. The gate dielectric film 152 may include a stacked structure of an interface dielectric film and a high-k film. The interface dielectric film may include a low-k material film having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some example embodiments, the interface dielectric film may be omitted. The high-k film may include a material having a dielectric constant greater than that of the silicon oxide film. For example, the high-k film may have a dielectric constant of about 10 to about 25. The high-k film may include, but is not limited to, hafnium oxide.

[0082] Multiple gate lines 160 can be formed on the gate dielectric film 152 to fill the gate space GS (see Figure 12A and Figure 12B Each of the plurality of gate lines 160 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may include TiAlC. However, the materials constituting each of the plurality of gate lines 160 are not limited to the examples described above.

[0083] Each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118 can be partially removed from its upper surface to reduce its height, and a plurality of capping insulating patterns 168 can each be formed to cover the upper surface of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118. Each of the plurality of capping insulating patterns 168 may include a silicon nitride film.

[0084] Reference Figure 14 ,exist Figure 13A and Figure 13BIn the resulting product, a source / drain contact hole can be formed between two adjacent gate lines 160 among a plurality of gate lines 160 to expose a source / drain region 130. A front-side metal silicide film 172 is then formed on the surface of the source / drain region 130 through the source / drain contact hole. Subsequently, a front-side source / drain contact CA can be formed on the front-side metal silicide film 172 to fill the source / drain contact hole. The front-side metal silicide film 172 may include a metal comprising at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or PD. For example, the front-side metal silicide film 172 may include, but is not limited to, titanium silicide. In some example embodiments, the front-side source / drain contact CA may consist only of a metal plug comprising a single metal. In some example embodiments, the front source / drain contact CA may include a metal plug and a conductive barrier film surrounding the metal plug. The metal plug may include, but is not limited to, molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), combinations thereof, or alloys thereof. The conductive barrier film may include a metal or a conductive metal nitride. For example, the conductive barrier film may include, but is not limited to, Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof.

[0085] The etch stop film 182 and the upper insulating film 184 can be formed in the order stated above, such that the etch stop film 182 and the upper insulating film 184 cover the upper surfaces of each of the front source / drain contacts CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric 144, thereby forming an upper insulating structure 180. Next, a source / drain via contact VA that passes through the upper insulating structure 180 in the vertical direction (Z direction) to connect to the front source / drain contacts CA, and a gate contact (not shown) that passes through the upper insulating structure 180 and the capping insulating patterns 168 in the vertical direction (Z direction) to connect to the gate line 160.

[0086] The etch stop film 182 may comprise silicon carbide (SiC), SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The upper insulating film 184 may comprise an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant of about 2.2 to about 2.4, or combinations thereof. For example, the upper insulating film 184 may include, but is not limited to, a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) oxide film, a borosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or combinations thereof. Each of the source / drain via contact VA and the gate contact may comprise a contact plug comprising molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), combinations thereof, or alloys thereof. In some example embodiments, each of the source / drain via contact VA and the gate contact may further include a conductive barrier pattern surrounding the contact plug. The conductive barrier pattern may include a metal or a metal nitride. For example, the conductive barrier pattern may include, but is not limited to, Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof.

[0087] Next, an interlayer dielectric 186 covering the upper insulating structure 180 and a plurality of upper wiring layers M1 passing through the interlayer dielectric 186 can be formed. The material constituting the interlayer dielectric 186 is the same as or substantially similar to the material constituting the upper insulating film 184 described above. The upper wiring layers M1 can be connected to source / drain via contacts VA or gate contacts. The upper wiring layers M1 can be, but are not limited to, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), combinations thereof, or alloys thereof.

[0088] Reference Figure 15 A first BEOL structure BS1 can be formed on multiple upper wiring layers M1 and interlayer dielectric 186. The first BEOL structure BS1 may include a front-side wiring structure FWS, which includes wiring layers MN1, via contacts CT1, and an interlayer dielectric 194 covering the wiring layers MN1 and the via contacts CT1. The constituent material of each of the wiring layers MN1 and the via contacts CT1 is the same as or substantially similar to the constituent material of each of the multiple upper wiring layers M1. The constituent material of the interlayer dielectric 194 is the same as or substantially similar to the constituent material of the upper insulating film 184.

[0089] Reference Figure 16 It has already gone through the reference period Figure 15The first BEOL structure BS1 included in the product obtained from the described process can be bonded to the sustaining wafer SW (see...). Figure 2D To bond the first BEOL structure BS1 to the sustaining wafer SW, a process similar to that described above can be performed. Figure 2D , Figure 5A and Figure 5B The methods described are similar to those used in this study. Figures 16 to 24 In the text, the sustaining chip SW is omitted.

[0090] While bonding the first BEOL structure BS1 to the sustaining wafer SW, it is possible to use it with a reference Figure 2E Description Figure 1 In a similar manner to process P20, the semiconductor substrate 102 is removed to expose the bottom epitaxial semiconductor layer 103. See reference... Figure 2E As described, a portion of the bottom epitaxial semiconductor layer 103 can be consumed during the CMP process to remove the semiconductor substrate 102. Therefore, in the resulting product retained after the semiconductor substrate 102 removal process is completed, the vertical (Z-direction) thickness of the bottom epitaxial semiconductor layer 103 retained on the back surface 106B of the top epitaxial semiconductor layer 106 can be less than the vertical (Z-direction) thickness of the bottom epitaxial semiconductor layer 103 (indicated by the dashed line in the figure) before the semiconductor substrate 102 was removed.

[0091] Reference Figure 17 It can be compared with the reference Figure 2F The bottom epitaxial semiconductor layer 103 is removed by wet etching in the same manner described, thereby exposing the back surface 106B of the fin-type active region F1, which is part of the top epitaxial semiconductor layer 106.

[0092] Reference Figure 18 ,exist Figure 17 In the resulting product, a first back-side mask pattern BMP1 can be formed on the back-side surface 106B of the fin-type active region F1, which is part of the top epitaxial semiconductor layer 106. The first back-side mask pattern BMP1 may have a plurality of linear openings BH1 extending longitudinally in a second horizontal direction (Y direction). A portion of the device isolation film 112 and each of the plurality of fin-type active regions F1 may be exposed by the plurality of linear openings BH1 formed in the first back-side mask pattern BMP1. In some example embodiments, the first back-side mask pattern BMP1 may include, but is not limited to, a SOH material.

[0093] Reference Figure 19 ,exist Figure 18In the resulting product, multiple vertical vias VCH can be formed by etching a portion of the fin-type active region F1 using a first back-side mask pattern BMP1 as an etching mask, thereby exposing the gate dielectric film 152 through the multiple vertical vias VCH. Furthermore, multiple back-side body insulating films BBI can be formed to fill the multiple vertical vias VCH and multiple linear openings BH1 (see [link to product description]). Figure 18 In some example embodiments, atomic layer deposition (ALD) or CVD processes can be used to form multiple back-side body insulating films (BBIs), but the inventive concept is not limited thereto. After forming multiple back-side body insulating films (BBIs), a structure in which a portion of the top epitaxial semiconductor layer 106 is disposed between each of the multiple back-side body insulating films (BBIs) can be obtained.

[0094] Reference Figure 20 It can be seen from Figure 19 The resulting product has the first back-side mask pattern BMP1 removed. When the first back-side mask pattern BMP1 includes SOH material, an ashing process and a stripping process can be used to remove the first back-side mask pattern BMP1.

[0095] Reference Figure 21 It can be done in Figure 20 The resulting product is coated with an SOH material to form a planarized hard mask film, and a second back-side mask pattern BMP2 with holes exposing a portion of the top epitaxial semiconductor layer 106 can be formed by patterning the hard mask film. Next, the fin-type active region F1, which is part of the top epitaxial semiconductor layer 106, can be partially etched using the second back-side mask pattern BMP2 as an etch mask, thereby forming vias VH in the fin-type active region F1 to expose the source / drain region 130. When the via VH is formed, a portion of the source / drain region 130 can be etched, and therefore, the via VH can extend into the interior of the source / drain region 130.

[0096] Reference Figure 22 It can be seen from Figure 21 The resulting product has the second back-side mask pattern BMP2 removed. When the second back-side mask pattern BMP2 includes SOH material, an ashing process and a stripping process can be used to remove the second back-side mask pattern BMP2.

[0097] Reference Figure 23 ,exist Figure 22In the resulting product, a back-side metal silicide film 198 can be formed on the surface of the source / drain region 130 through a via VH. The constituent material of the back-side metal silicide film 198 is the same as or substantially similar to the constituent material of the aforementioned front-side metal silicide film 172. Next, conductive material can fill the space between the via VH and each of the plurality of back-side body insulating films BBI, thereby forming a back-side via contact BCA filling the via VH and a back-side power rail MPR integrally connected to the back-side via contact BCA. The back-side via contact BCA can be configured to be connected to the source / drain region 130 via the back-side metal silicide film 198. Hereinafter, the back-side via contact BCA may be referred to as a contact structure. The constituent material of each of the back-side via contact BCA and the back-side power rail MPR is the same as or substantially similar to the constituent material of the front-side source / drain contact CA.

[0098] Reference Figure 24 It can be formed with a back-side through-hole contact (BCA) and a back-side power rail (MPR). Figure 23 The resulting product forms a back-side wiring structure (BWS), which includes a wiring layer MN2, via contacts CT2, and an interlayer dielectric 196 covering the wiring layer MN2 and the via contacts CT2. The back-side via contacts BCA, the back-side power rails MPR, and the back-side wiring structure BWS can constitute a second BEOL structure BS2. The constituent material of each of the wiring layer MN2 and the via contacts CT2 is the same as or substantially similar to the constituent material of the upper wiring layer M1. The constituent material of the interlayer dielectric 196 is the same as or substantially similar to the constituent material of the upper insulating film 184.

[0099] According to reference Figures 8 to 24 The method for manufacturing an integrated circuit device described herein, as referenced Figure 15 After forming the first BEOL structure BS1 and before forming the second BEOL structure BS2, the semiconductor substrate 102 can be removed to reduce the thickness of the substrate 110, and then the semiconductor substrate 102 can be removed using the method described in reference [reference]. Figure 16The difference in dopant concentration described is removed by wet etching of the bottom epitaxial semiconductor layer 103, which has a relatively high dopant concentration, thereby exposing the back surface 106B of the fin active region F1, which is part of the top epitaxial semiconductor layer 106. Therefore, the fin active region F1 can have a back surface 106B that has improved flatness (e.g., relatively uniform flatness with a thickness deviation below a certain value) without differences in surface roughness depending on the location within the back surface 106B of the fin active region F1. Therefore, in the manufacturing process of an integrated circuit device with a BSPDN structure, when a subsequent thinning process for reducing the thickness of the substrate 110 is performed by using a fin-type active region F1, which is part of the top epitaxial semiconductor layer 106 retained in the resulting product after thinning, the back surface 106B of the top epitaxial semiconductor layer 106 can provide uniform flatness (e.g., relative uniform flatness with a thickness deviation below a certain value) across its entire surface without thickness deviation depending on the position of the top epitaxial semiconductor layer 106 retained in the resulting product, thereby improving the stability of the integrated circuit device manufacturing process and / or improving the reliability of the integrated circuit device as a result.

[0100] Figures 25 to 29 The manufacturing process is shown separately. Figure 7 A cross-sectional view of the process sequence of the method for the integrated circuit device 100 shown. Figures 25 to 29 Showing respectively with along Figure 7 The cross-sectional structure of the region corresponding to the section intercepted by line X1-X1'. Figures 25 to 29 In, with Figures 2A to 24 The same reference numerals in the figures denote the same components, and here, repeated descriptions are omitted.

[0101] Reference Figure 25 , can execute reference Figures 8 to 16 The described process. Next, after already undergoing... Figure 16 In the product obtained by the process, a first back-side mask pattern BMP1 can be formed on the bottom epitaxial semiconductor layer 103. Details and references to the process for forming the first back-side mask pattern BMP1 are provided. Figure 18 The descriptions are the same.

[0102] Reference Figure 26 ,exist Figure 25 The resulting products can be compared with the reference. Figure 19A similar manner is described, using a first back-side mask pattern BMP1 as an etching mask to etch a portion of each of the bottom epitaxial semiconductor layer 103 and the fin-type active region F1, thereby forming a plurality of vertical vias VCH extending in the vertical direction (Z direction) toward the gate line 160. In some example embodiments, after forming the plurality of vertical vias VCH, the gate dielectric film 152 can be exposed through each of the plurality of vertical vias VCH. Next, a plurality of back-side body insulating films BBI can be formed to fill the plurality of vertical vias VCH and the plurality of linear openings BH1.

[0103] Reference Figure 27 , in order to refer to Figure 20 A similar way of describing it can be seen from Figure 26 The resulting product has the first back-side mask pattern BMP1 removed. As a result, the bottom epitaxial semiconductor layer 103 can be exposed between each of the plurality of back-side body insulating films BBI.

[0104] Reference Figure 28 ,exist Figure 27 In the resulting product, the bottom epitaxial semiconductor layer 103 can be selectively removed by wet etching using the difference in dopant concentration between the top epitaxial semiconductor layer 106 with a relatively low dopant concentration and the bottom epitaxial semiconductor layer 103 with a relatively high dopant concentration, thereby exposing the back surface 106B of the top epitaxial semiconductor layer 106. Details and references are provided for the process of selectively removing the bottom epitaxial semiconductor layer 103 by wet etching. Figure 2F and Figure 17 The descriptions are the same.

[0105] Reference Figure 29 ,right Figure 28 The products obtained shall be subject to the reference Figures 21 to 24 The process described forms a second BEOL structure BS2, which includes a back-side via contact BCA, a back-side power rail MPR, and a back-side wiring structure BWS.

[0106] According to reference Figures 25 to 29 The method for manufacturing an integrated circuit device described herein, in accordance with reference to Figures 8 to 24 The description is similar; after removing the semiconductor substrate 102 to perform a thinning process for reducing the thickness of the substrate 110, the method includes a process of exposing the back surface 106B of the top epitaxial semiconductor layer 106 by wet etching to remove the bottom epitaxial semiconductor layer 103 using the difference in dopant concentration between a top epitaxial semiconductor layer 106 with a relatively low dopant concentration and a bottom epitaxial semiconductor layer 103 with a relatively high dopant concentration. For example, in reference to Figures 25 to 29In the described method of manufacturing an integrated circuit device, since the bottom epitaxial semiconductor layer 103 is removed by wet etching after performing processes to form a plurality of vertical vias VCH through a fin-type active region F1 including a portion of the top epitaxial semiconductor layer 106 and to form a plurality of back-side body insulating films BBI to respectively fill the plurality of vertical vias VCH, the back-side surface 106B of the top epitaxial semiconductor layer 106 can be protected by the bottom epitaxial semiconductor layer 103 while the plurality of vertical vias VCH are formed in the top epitaxial semiconductor layer 106. Therefore, the possibility of surface damage that the top epitaxial semiconductor layer 106 may suffer due to the etching process atmosphere during the formation of the plurality of vertical vias VCH in the top epitaxial semiconductor layer 106 can be reduced or prevented by the bottom epitaxial semiconductor layer 103, and the top epitaxial semiconductor layer 106 can have a back-side surface 106B that has improved flatness (e.g., relatively uniform flatness with a thickness deviation below a certain value) without differences in surface roughness depending on the location in the top epitaxial semiconductor layer 106. In the resulting product in which multiple back-side body insulating films BBI are formed, when subsequent processes are performed using the top epitaxial semiconductor layer 106, the back-side surface 106B of the top epitaxial semiconductor layer 106 can provide uniform flatness (e.g., relative uniform flatness with a thickness deviation below a certain value) across its entire surface without thickness deviation depending on the position of the top epitaxial semiconductor layer 106 retained in the resulting product, thereby improving the stability of the integrated circuit device manufacturing process and / or improving the reliability of the integrated circuit device obtained as a result.

[0107] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing an integrated circuit device, the method comprising: A substrate is formed, the substrate having a structure including the following: Semiconductor substrate having a first dopant concentration, A bottom epitaxial semiconductor layer, integrally connected to the semiconductor substrate, the bottom epitaxial semiconductor layer having a second dopant concentration greater than the first dopant concentration, and A top epitaxial semiconductor layer, which is integrally connected to the bottom epitaxial semiconductor layer and has a third dopant concentration less than the second dopant concentration, wherein the semiconductor substrate, the bottom epitaxial semiconductor layer and the top epitaxial semiconductor layer are stacked sequentially in the vertical direction; A front-end process structure is formed on the front surface of the top epitaxial semiconductor layer; A first back-end process structure is formed on the front-end process structure, such that the first back-end process structure is spaced apart from the substrate in the vertical direction, and the front-end process structure is located between the first back-end process structure and the substrate. Remove the semiconductor substrate from the substrate to expose the bottom epitaxial semiconductor layer; and A second back-end process structure is formed by performing a back-side process such that the second back-end process structure is spaced apart from the first back-end process structure in the vertical direction, and the front-end process structure is located between the second back-end process structure and the first back-end process structure. The back-side process includes: The bottom epitaxial semiconductor layer is removed by wet etching to expose the top epitaxial semiconductor layer, and Pattern the top epitaxial semiconductor layer.

2. The method according to claim 1, wherein, The substrate is formed by: The bottom epitaxial semiconductor layer is formed such that the concentration of the second dopant is: The bottom epitaxial semiconductor layer has a maximum value in the vertical direction near the edge portion of the semiconductor substrate, and The thickness gradually decreases from the edge portion of the bottom epitaxial semiconductor layer toward the top epitaxial semiconductor layer in the vertical direction.

3. The method according to claim 1, wherein, When forming the substrate, each of the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer comprises silicon (Si) doped with a p-type dopant.

4. The method according to claim 1, wherein, When forming the substrate, each of the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer comprises silicon (Si) doped with an n-type dopant.

5. The method according to claim 1, wherein, During the formation of the substrate Each of the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer comprises doped silicon (Si), and The substrate does not include germanium (Ge).

6. The method according to claim 1, wherein, The second back-end process structure includes: The bottom epitaxial semiconductor layer is removed by wet etching to expose the back surface of the top epitaxial semiconductor layer; Subsequently, by etching a portion of the top epitaxial semiconductor layer from its back surface, a plurality of holes are formed in the top epitaxial semiconductor layer to expose portions of the front-end process structure; and A contact structure is formed to fill each of the plurality of holes.

7. The method according to claim 1, wherein, The second back-end process structure includes: By etching a portion of each of the bottom epitaxial semiconductor layer and the top epitaxial semiconductor layer from the exposed surface of the bottom epitaxial semiconductor layer, a plurality of holes are formed in the top epitaxial semiconductor layer to expose portions of the front-end process structure, while the back surface of the top epitaxial semiconductor layer is covered by the bottom epitaxial semiconductor layer. The back surface of the top epitaxial semiconductor layer is exposed by removing the bottom epitaxial semiconductor layer retained on the top epitaxial semiconductor layer from the resulting product in which the plurality of holes are formed via wet etching; and Multiple contact structures are formed to fill the multiple holes respectively.

8. The method according to claim 1, further comprising: After the first back-end process structure is formed and before the semiconductor substrate is removed, the wafer is maintained bonded to the first back-end process structure. The semiconductor substrate is removed and the second back-end process structure is formed while the first back-end process structure is being bonded to the sustaining wafer.

9. The method according to claim 1, wherein, Forming the substrate includes forming the bottom epitaxial semiconductor layer, such that: The concentration of the second dopant in the bottom epitaxial semiconductor layer has a concentration gradient, which is based on the fact that the total thickness of the bottom epitaxial semiconductor layer in the vertical direction has a maximum value in the central portion of the bottom epitaxial semiconductor layer. The concentration of the second dopant in the edge portion of the bottom epitaxial semiconductor layer gradually decreases from the center of the bottom epitaxial semiconductor layer toward the edge portion, which is close to both the semiconductor substrate and the top epitaxial semiconductor layer. In the bottom epitaxial semiconductor layer, the central portion where the second dopant concentration has a maximum value has a thickness in the vertical direction that is greater than the thickness in the vertical direction of each of the edge portions.

10. The method according to claim 1, wherein, Forming the substrate includes forming the bottom epitaxial semiconductor layer such that the concentration of the second dopant in the bottom epitaxial semiconductor layer has a variable concentration gradient in the vertical direction, and In the bottom epitaxial semiconductor layer, a first distance in the vertical direction from the portion having the maximum value of the second dopant concentration to the top epitaxial semiconductor layer is greater than a second distance from the portion having the maximum value of the second dopant concentration to the semiconductor substrate.

11. The method according to claim 1, wherein, The formation of the aforementioned front-end process structure includes: A fin-shaped active region is formed by etching a portion of the top epitaxial semiconductor layer, the fin-shaped active region including another portion of the top epitaxial semiconductor layer, and Source / drain regions are formed on the fin-shaped active region, and The second back-end process structure includes: The bottom epitaxial semiconductor layer is removed by wet etching to expose the back surface of the fin-shaped active region. Subsequently, by etching a portion of the fin-shaped active region from its dorsal surface, a via is formed in the fin-shaped active region to expose a portion of the source / drain region. A contact structure is formed to fill the via, and the contact structure is connected to the source / drain region.

12. The method according to claim 1, wherein, The formation of the aforementioned front-end process structure includes: A fin-shaped active region is formed by etching a portion of the top epitaxial semiconductor layer, the fin-shaped active region including another portion of the top epitaxial semiconductor layer, and A gate line, a gate dielectric film surrounding the gate line, and source / drain regions are formed on or above the fin-shaped active region. The second back-end process structure includes: A vertical via is formed in the fin active region by etching a portion of the bottom epitaxial semiconductor layer and each of the fin active regions from the exposed surface of the bottom epitaxial semiconductor layer to extend toward the gate line in the vertical direction, while the back surface of the fin active region is covered by the bottom epitaxial semiconductor layer. A back-side insulating film is formed to fill the vertical holes, and The back surface of the fin active region is exposed by removing the bottom epitaxial semiconductor layer retained on the back surface of the fin active region from the resulting product in which the back body insulating film is formed via wet etching.

13. A method for manufacturing an integrated circuit device, the method comprising: A substrate is formed, the substrate having a structure including the following: Semiconductor substrate having a first dopant concentration, The bottom epitaxial semiconductor layer has a second dopant concentration greater than that of the first dopant concentration, and A top epitaxial semiconductor layer having a third dopant concentration less than the second dopant concentration, wherein the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer are stacked sequentially in the vertical direction; A fin-shaped active region is formed by etching a portion of the top epitaxial semiconductor layer, the fin-shaped active region including another portion of the top epitaxial semiconductor layer; A front-end process structure is formed on the fin-shaped active region, the front-end process structure including a gate line and a source / drain region; A first back-end process structure is formed on the front-end process structure, such that the first back-end process structure is spaced apart from the substrate in the vertical direction, and the front-end process structure is located between the first back-end process structure and the substrate. Remove the semiconductor substrate from the substrate to expose the bottom epitaxial semiconductor layer; and A second back-end process structure is formed by performing a back-side process, such that the second back-end process structure is spaced apart from the first back-end process structure in the vertical direction, and the front-end process structure is located between the second back-end process structure and the first back-end process structure. The back-side process includes: The bottom epitaxial semiconductor layer is removed by wet etching to expose the back surface of the fin-shaped active region, and Etch at least a portion of the fin-shaped active region.

14. The method according to claim 13, wherein, The substrate is formed by: The bottom epitaxial semiconductor layer is formed such that the concentration of the second dopant is: The bottom epitaxial semiconductor layer has a maximum value in the vertical direction near the edge portion of the semiconductor substrate, and The thickness gradually decreases from the edge portion of the bottom epitaxial semiconductor layer toward the top epitaxial semiconductor layer in the vertical direction.

15. The method according to claim 13, wherein, During the formation of the substrate Each of the semiconductor substrate, the bottom epitaxial semiconductor layer, and the top epitaxial semiconductor layer comprises doped silicon (Si), and The substrate does not include germanium (Ge).

16. The method of claim 13, further comprising: After the first back-end process structure is formed and before the semiconductor substrate is removed, the wafer is maintained bonded to the first back-end process structure. The semiconductor substrate is removed and the second back-end process structure is formed while the first back-end process structure is being bonded to the sustaining wafer.

17. The method according to claim 13, wherein, The second back-end process structure includes: After removing the bottom epitaxial semiconductor layer, a via is formed in the fin active region by etching a portion of the fin active region from the back surface of the fin active region to expose a portion of the source / drain region; and A contact structure is formed to fill the via, and the contact structure is connected to the source / drain region.

18. The method according to claim 13, wherein, The second back-end process structure includes: A vertical hole is formed in the fin active region to extend toward the gate line in the vertical direction by etching a portion of the bottom epitaxial semiconductor layer and each of the fin active regions from the exposed surface of the bottom epitaxial semiconductor layer, while the back surface of the fin active region is covered by the bottom epitaxial semiconductor layer. Forming a back-side insulating film to fill the vertical aperture; and The back surface of the fin active region is exposed by removing the bottom epitaxial semiconductor layer retained on the back surface of the fin active region from the resulting product in which the back body insulating film is formed via wet etching.

19. A method for manufacturing an integrated circuit device, the method comprising: Forming a substrate, the substrate comprising: A Si substrate having a first dopant concentration A bottom epitaxial Si layer, integrally connected to the Si substrate, and having a second dopant concentration greater than the first dopant concentration, and The top epitaxial Si layer has no germanium (Ge), the top epitaxial Si layer is integrally connected to the bottom epitaxial Si layer, and has a third dopant concentration that is less than the second dopant concentration; A fin-shaped active region is formed by etching a portion of the top epitaxial Si layer, the fin-shaped active region including another portion of the top epitaxial Si layer; A front-end process structure is formed on the fin-shaped active region, the front-end process structure including a gate line and a source / drain region; A first back-end process structure is formed on the front-end process structure, such that the first back-end process structure is spaced apart from the substrate in the vertical direction, and the front-end process structure is located between the first back-end process structure and the substrate. This will maintain the chip bonding to the first back-end process structure; While the first back-end process structure is bonded to the sustaining wafer, the Si substrate is removed from the substrate to expose the bottom epitaxial Si layer; and A second back-end process structure is formed by performing a back-side process to space the second back-end process structure from the first back-end process structure, and the front-end process structure is located between the second back-end process structure and the first back-end process structure. The back-side process includes performing the following steps while the first back-end process structure is bonded to the sustaining wafer: The bottom epitaxial Si layer is removed by wet etching to expose the back surface of the fin-shaped active region, and Etch at least a portion of the fin-shaped active region.

20. The method according to claim 19, wherein, Forming the substrate includes forming the bottom epitaxial Si layer such that the concentration of the second dopant is: The bottom epitaxial Si layer has a maximum value in the vertical direction near the edge of the Si substrate, and The thickness gradually decreases from the edge portion of the bottom epitaxial Si layer toward the top epitaxial Si layer in the vertical direction.

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