Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, a pixel circuit in the array substrate comprises a first transistor, a second transistor and a third transistor, the array substrate comprises a substrate, a first active layer, a first metal layer, a second metal layer, a plurality of first via holes, a second active layer and a plurality of second via holes which are stacked in sequence, a first active structure in the first active layer comprises a common doped region, a first channel region of a first transistor and a second channel region of a second transistor of the same pixel circuit are located in the same first active structure, and the first metal layer comprises a first grid electrode of the first transistor and a second grid electrode of the second transistor. The second metal layer comprises a common electrode of the first transistor and the second transistor, a first via hole is electrically connected with the common electrode and the common doped region, a second active structure in the second active layer comprises a first doped region and a third channel region corresponding to the third transistor, and a second via hole is electrically connected with the common electrode and the first doped region. The orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are at least partially overlapped, so that the layout space of the pixel circuit in the transverse direction and the longitudinal direction can be reduced, and higher pixel arrangement density can be realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of organic light-emitting diode (OLED) display panels is becoming more and more widespread, such as virtual reality (VR) and augmented reality (AR) display solutions, bringing users a brand-new visual experience.

[0003] However, existing OLED display panels suffer from low resolution, which cannot meet the application requirements of display solutions such as AR / VR. Summary of the Invention

[0004] Based on the above and other issues, embodiments of this application provide an array substrate and a display panel.

[0005] This application provides an array substrate comprising a plurality of pixel circuits, each pixel circuit including a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor have a common electrode. The first transistor includes a first gate and a first channel region, the second transistor includes a second gate and a second channel region, and the third transistor includes a third channel region. The array substrate comprises: Substrate; The first active layer is located on one side of the substrate and includes multiple first active structures. The first active structures include a common doped region, and the first channel region and the second channel region of the same pixel circuit are located in the same first active structure. The first metal layer, located on the side of the first active layer away from the substrate, includes a first gate and a second gate. The orthographic projection of the first gate onto the substrate overlaps with the orthographic projection of the first channel region onto the substrate, and the orthographic projection of the second gate onto the substrate overlaps with the orthographic projection of the second channel region onto the substrate. The second metal layer is located on the side of the first metal layer away from the first active layer and includes a common electrode; Multiple first vias are used, and the first vias are electrically connected to the common electrode and the common doped region; The second active layer is located on the side of the second metal layer away from the first metal layer and includes a plurality of second active structures. The second active structure includes a first doped region and a third channel region corresponding to the third transistor. Multiple second vias are provided, and the second vias are electrically connected to the common electrode and the first doped region. Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap.

[0006] In one embodiment, the first transistor further includes a first bottom gate, and the array substrate further includes: The bottom metal layer is located between the substrate and the first active layer, and includes a first bottom gate. The orthographic projection of the first bottom gate onto the substrate overlaps with the orthographic projection of the first channel region onto the substrate, and is located outside the orthographic projection of the second channel region onto the substrate. Preferably, the orthographic projection of the first bottom gate onto the substrate covers the orthographic projection of the first channel region onto the substrate.

[0007] In one embodiment, the pixel circuit further includes a first capacitor, and the first active structure further includes a second doped region and a third doped region. Along a first direction parallel to the substrate, the second doped region is located on the side of the second channel region away from the common doped region, and the common doped region is located on the side of the first channel region away from the third doped region. The second metal layer further includes a first electrode of a first transistor, the first electrode of the first transistor being configured with a first power supply voltage, and the first electrode of the first transistor being electrically connected to the third doped region. The array substrate further includes: The third metal layer is located on the side of the second metal layer away from the first metal layer, and includes the first electrode of the first capacitor. The first electrode of the first capacitor is electrically connected to the second doped region and the first bottom gate. Among them, the multiple pixel circuits include adjacent pixel circuits located on one side of the pixel circuit in the first direction, and the first electrode of the first transistor in the adjacent pixel circuit serves as the second electrode of the first capacitor. Preferably, the orthographic projection of the first electrode of the first transistor in the adjacent pixel circuit onto the substrate overlaps with the orthographic projection of the first electrode plate of the first capacitor onto the substrate.

[0008] In one embodiment, the third transistor further includes a third gate and a second bottom gate, and the array substrate further includes: The fourth metal layer, located between the third metal layer and the second active layer, includes a second bottom gate, the orthographic projection of the second bottom gate onto the substrate overlapping the orthographic projection of the third channel region onto the substrate; The fifth metal layer is located on the side of the second active layer away from the fourth metal layer, and includes a third gate, the orthographic projection of the third gate onto the substrate overlapping the orthographic projection of the third channel region onto the substrate; Wherein, the orthographic projection of the second bottom gate onto the substrate overlaps with the orthographic projection of the first electrode plate of the first capacitor onto the substrate; Preferably, the orthographic projection of the second bottom gate onto the substrate covers the orthographic projection of the third channel region onto the substrate.

[0009] In one embodiment, the second active structure further includes a fourth doped region, and the array substrate further includes a top metal layer located on the side of the fifth metal layer away from the second active layer. The top metal layer includes a first electrode and a second electrode of a third transistor. The first electrode of the third transistor is electrically connected to the first doped region, and the second electrode of the third transistor is electrically connected to the fourth doped region and configured with a reference voltage, wherein: The second electrode of the third transistor is electrically connected to the second bottom gate; or... The second bottom gate is configured with a first power supply voltage. The first capacitor includes a first sub-capacitor and a second sub-capacitor connected in parallel. The first sub-capacitor and the second sub-capacitor have a first common capacitor plate. The first plate of the first capacitor serves as the first common capacitor plate. The first electrode of the first transistor in the adjacent pixel circuit serves as the first sub-plate of the first sub-capacitor. The second bottom gate serves as the second plate of the second sub-capacitor.

[0010] In one embodiment, the array substrate further includes: Multiple third vias pass through the fourth doped region and are electrically connected to the second electrode and the second bottom gate of the third transistor.

[0011] In one embodiment, within the same pixel circuit: The orthographic projection of the third channel region onto the substrate overlaps with the orthographic projection of either the first channel region or the second channel region onto the substrate; and / or, The first channel area and the second channel area are arranged along the first direction, and the length of the first channel area is greater than the length of the second channel area along the first direction.

[0012] In one embodiment, the pixel circuit further includes a second capacitor, with the first gate serving as the first plate of the second capacitor, the first electrode of the first transistor serving as the second plate of the second capacitor, and the orthographic projection of the first gate onto the substrate overlapping the orthographic projection of the first electrode of the first transistor onto the substrate.

[0013] In one embodiment, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor connected in parallel, the third sub-capacitor and the fourth sub-capacitor having a second common capacitor plate, wherein: The first electrode of the first transistor serves as the second common capacitor plate; The first gate acts as the third sub-plate of the third sub-capacitor; The third metal layer also includes the fourth sub-plate of the fourth sub-capacitor, which is electrically connected to the first gate. The orthographic projection of the fourth sub-capacitor onto the substrate overlaps with the orthographic projection of the first electrode of the first transistor onto the substrate.

[0014] In one embodiment, the pixel circuit further includes a fourth transistor, which includes a fourth channel region, wherein: The second active layer also includes multiple third active structures, which include a fifth doped region and a fourth channel region. The fifth doped region is electrically connected to the fourth sub-plate of the fourth sub-capacitor.

[0015] In one embodiment, the fourth transistor further includes a fourth gate and a third bottom gate, and the array substrate further includes: A fourth metal layer, located between the third metal layer and the second active layer, includes a third bottom gate, which is configured with a first power supply voltage, and the orthographic projection of the third bottom gate onto the substrate overlaps with the orthographic projection of the fourth channel region onto the substrate. The fifth metal layer is located on the side of the second active layer away from the fourth metal layer, and includes the fourth gate, the orthographic projection of the fourth gate onto the substrate overlaps with the orthographic projection of the fourth channel region onto the substrate; Preferably, the second capacitor further includes a fifth sub-capacitor connected in parallel with the third and fourth sub-capacitors, the fourth and fifth sub-capacitors having a third common capacitor plate, wherein: The fourth sub-plate of the fourth sub-capacitor serves as the third common capacitor plate. The third bottom gate serves as the fifth sub-plate of the fifth sub-capacitor, and the orthographic projection of the fourth sub-capacitor onto the substrate overlaps with the orthographic projection of the third bottom gate onto the substrate. Preferably, the third active structure further includes a sixth doped region, which is located on the side of the fourth channel region away from the fifth doped region, and the array substrate further includes: The sixth metal layer is located on the side of the fifth metal layer away from the second active layer, and includes the first electrode of the fourth transistor, which is electrically connected to the sixth doped region. Preferably, the first electrode of the fourth transistor is configured with both data voltage and initial voltage in a time-division configuration.

[0016] In one embodiment, within the same pixel circuit: The orthographic projection of the third channel region onto the substrate overlaps with the orthographic projection of either the first or second channel region onto the substrate; the orthographic projection of the fourth channel region onto the substrate overlaps with the orthographic projection of either the first or second channel region onto the substrate.

[0017] In one embodiment, the second metal layer further includes a first electrode of the second transistor, wherein: The first electrode of the second transistor is electrically connected to the second doped region and the first bottom gate; The first plate of the first capacitor is electrically connected to the first electrode of the second transistor; Preferably, the array substrate further includes: Multiple fourth vias, the fourth vias passing through the second doped region and electrically connected to the first gate of the first transistor and the first electrode of the second transistor; and, Multiple fifth vias are provided, and the fifth vias are electrically connected to the first plate of the first capacitor and the first electrode of the second transistor. Preferably, the orthographic projection of the fourth via on the substrate does not overlap with the orthographic projection of the fifth via on the substrate.

[0018] In one embodiment, the array substrate further includes: The top metal layer is located on the side of the second active layer away from the second metal layer. The top metal layer includes the first electrode of the third transistor, and the first electrode of the third transistor is electrically connected to the first doped region. Multiple first electrodes are located on the side of the top metal layer away from the second active layer, and the first electrodes are electrically connected to the first electrode of the third transistor; Preferably, the material of the first active layer includes polycrystalline silicon, and / or the material of the second active layer includes indium gallium zinc oxide.

[0019] In one embodiment, the array substrate further includes a top metal layer located on the side of the second active layer away from the second metal layer. The top metal layer includes a first electrode of a third transistor, which is electrically connected to a first doped region. The second via contacts the common electrode, the first doped region, and the first electrode of the third transistor; or, The second via includes a first sub-via and a second sub-via. The array substrate further includes a sixth metal layer located between the third gate of the third transistor and the top metal layer. The sixth metal layer includes a bridging structure. The first sub-via contacts the common electrode, the first doped region, and the bridging structure; the second sub-via contacts the bridging structure and the first electrode of the third transistor. Alternatively, The second via includes a third sub-via and a fourth sub-via, wherein the third sub-via contacts the common electrode and the first doped region, and the fourth sub-via contacts the first doped region and the first electrode of the third transistor.

[0020] In one embodiment, the common electrode and the corresponding first via are an integral structure, wherein: The first electrode of the third transistor and the corresponding second via are an integral structure; or, The bridging structure and the corresponding first sub-hole are an integral structure, and the first electrode of the third transistor and the corresponding second sub-hole are an integral structure; or, The first electrode of the third transistor and the corresponding fourth sub-hole are integrated into one structure, and the second active structure and the corresponding third sub-hole are integrated into one structure.

[0021] In one embodiment, the second electrode of the third transistor and the corresponding third via are an integral structure.

[0022] In one embodiment, the first electrode of the second transistor and the corresponding fourth via are integral structures, and the first electrode plate of the first capacitor and the corresponding fifth via are integral structures.

[0023] In one embodiment, the third transistor further includes a third gate, the first transistor is a driving transistor, and the second gate and the third gate are configured with different scan signals; Preferably, the pixel circuit further includes a fourth transistor, which includes a fourth gate and a fourth channel region, wherein: The second active layer also includes multiple third active structures, including a fifth doped region, a sixth doped region and a fourth channel region, with the sixth doped region located on the side of the fourth channel region away from the fifth doped region. The fifth doped region is electrically connected to the first gate, the sixth doped region is configured with data voltage and initial voltage in a time-division manner, and the second, third and fourth gates are configured with different scan signals.

[0024] A second aspect of this application provides a display panel, the display panel comprising an array substrate in any possible embodiment of the first aspect.

[0025] This application provides an array substrate and a display panel. The pixel circuit in the array substrate includes a first transistor, a second transistor, and a third transistor. The array substrate includes a substrate, a first active layer, a first metal layer, a second metal layer, a plurality of first vias, a second active layer, and a plurality of second vias stacked sequentially. The first active structure in the first active layer includes a common doped region. The first channel region of the first transistor and the second channel region of the second transistor in the same pixel circuit are located in the same first active structure. The first metal layer includes the first gate of the first transistor and the second gate of the second transistor. The second metal layer includes the common electrode of the first transistor and the second transistor. The first vias are electrically connected to the common electrode and the common doped region. The second active structure in the second active layer includes a first doped region and a third channel region corresponding to the third transistor. The second vias are electrically connected to the common electrode and the first doped region. The orthographic projection of the first vias on the substrate and the orthographic projection of the second vias on the substrate at least partially overlap, which can reduce the layout space of the pixel circuit in the horizontal and vertical directions to achieve a higher pixel arrangement density. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1This is a schematic cross-sectional view of the array substrate in one embodiment; Figure 2 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment; Figure 3 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment; Figure 4 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment; Figure 5 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment; Figure 6 This is a partial layout diagram of the array substrate in one embodiment; Figure 7 This is a schematic diagram of a partial layout structure of the array substrate in another embodiment; Figure 8 This is a schematic diagram of a partial layout structure of the array substrate in another embodiment; Figure 9 This is an equivalent circuit diagram of the pixel circuit of the array substrate in one embodiment; Figure 10 This is a schematic diagram of the control timing corresponding to the pixel circuit in one embodiment; Figure 11 This is a schematic diagram of the structure of the display panel in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] With the continuous increase in shipments of VR (Virtual Reality) products in recent years, developing display panels with higher PPI (Pixel Per Inch) has become a major demand for current clients.

[0030] However, while mainstream silicon-based OLED (Organic Light Emitting Diode) solutions can achieve high PPI, their reliance on semiconductor silicon-based backplane technology results in high costs and limited screen size, becoming a major bottleneck for VR products. Compared to silicon-based OLED, glass-based OLED has lower costs, but as the PPI increases (not less than 800), the pixel area shrinks dramatically. Space constraints mean that fewer TFTs (Thin Film Transistors) and signal lines can be used to achieve the pixel circuit compensation effect.

[0031] Based on this, this application provides an array substrate design scheme suitable for high PPI pixel circuits, with the aim of achieving higher pixel density to at least meet the display requirements of VR devices.

[0032] Please see Figure 1 , Figure 6 and Figure 9 ,in, Figure 1 This is a schematic cross-sectional view of the array substrate 100 in one embodiment. Figure 6 This is a partial layout diagram of the array substrate 100 in one embodiment. Figure 9 This is an equivalent circuit diagram of the pixel circuit PX of the array substrate 100 in one embodiment.

[0033] In one exemplary embodiment, see Figure 1 , Figure 6 and Figure 9 The array substrate 100 provided in this application includes multiple pixel circuits PX. Each pixel circuit PX includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 and the second transistor T2 have a common electrode COM. The first transistor includes a first gate G1 and a first channel region CH1. The second transistor T2 includes a second gate G2 and a second channel region CH2. The third transistor T3 includes a third channel region CH3. Specifically, the array substrate 100 includes a substrate 10, a first active layer 20, a first metal layer M1, a second metal layer M2, multiple first vias 30, a second active layer 40, and multiple second vias 50.

[0034] The first active layer 20 is located on one side of the substrate 10 and includes a plurality of first active structures 21, wherein the first active structure 21 includes a common doped region 211, and the first channel region CH1 and the second channel region CH2 of the same pixel circuit PX are located in the same first active structure 21.

[0035] The first metal layer M1 is located on the side of the first active layer 20 away from the substrate 10, and includes a first gate G1 and a second gate G2. The orthographic projection of the first gate G1 on the substrate 10 overlaps with the orthographic projection of the first channel region CH1 on the substrate 10, and the orthographic projection of the second gate G2 on the substrate 10 overlaps with the orthographic projection of the second channel region CH2 on the substrate 10.

[0036] The second metal layer M2 is located on the side of the first metal layer M1 away from the first active layer 20, and includes the common electrode COM.

[0037] The first via 30 electrically connects the common electrode COM and the common doped region 211.

[0038] The second active layer 40 is located on the side of the second metal layer M2 away from the first metal layer M1, and includes a plurality of second active structures 41, wherein the second active structure 41 includes a first doped region 411 and a third channel region CH3 corresponding to the third transistor T3.

[0039] The second via 50 electrically connects the common electrode COM and the first doped region 411.

[0040] like Figure 1 and Figure 6 As shown, in the various embodiments provided in this application, the orthographic projection of the first via 30 on the substrate 10 and the orthographic projection of the second via 50 on the substrate 10 at least partially overlap.

[0041] It should be noted that, in order to meet the requirement of higher pixel density, as many pixel circuits PX and corresponding light-emitting devices as possible need to be set in the direction parallel to the substrate 10. Therefore, in this embodiment, at least two active layers are set in the direction perpendicular to the substrate 10. Figure 1 In the example, the first active layer 20 and the second active layer 40 are used, so that the multiple transistors constituting the pixel circuit PX ( Figure 1 In the example, the first transistor T1, the second transistor T2, and the third transistor T3 can be stacked in a direction perpendicular to the substrate 10, thereby reducing the layout space occupied by a single pixel circuit PX in a direction parallel to the substrate 10, and thus effectively improving the pixel density.

[0042] Furthermore, in this embodiment, since one of the source and drain terminals of the first transistor T1 needs to be electrically connected to one of the source and drain terminals of the second transistor T2, this embodiment sets the first channel region CH1 of the first transistor T1 and the second channel region CH2 of the second transistor T2 in the same pixel circuit PX in the same first active structure 21, and sets the common doped region 211 of the first transistor T1 and the second transistor T2 in the first active structure 21. As a result, the layout space occupied by a single pixel circuit PX in the direction parallel to the substrate 10 can be reduced.

[0043] Furthermore, in this embodiment, since the first doped region 411 of the third transistor T3 needs to be electrically connected to the common doped region 211 of the first transistor T1 and the second transistor T2, and the third transistor T3 is disposed on the side of the first transistor T1 and the second transistor T2 away from the substrate 10, at least one via is required to electrically connect the first doped region 411 and the common doped region 211.

[0044] It should be noted that in etching technology, as the etching depth increases, the etching process is prone to drilling effect, meaning that while the bottom of the via is etched normally, the top entrance of the via is also eroded laterally, ultimately resulting in a via that is wider at the top and narrower at the bottom. When the upper opening of the via becomes too large due to drilling, the originally designed upper metal pattern may not be able to completely cover this enlarged opening, ultimately leading to weak or even broken edge coverage of the via (often referred to as insufficient edge coverage).

[0045] Therefore, to avoid the aforementioned potential problems, this embodiment of the application provides a common electrode COM for the first transistor T1 and the second transistor T2 in the second metal layer M2. Furthermore, a first via 30 is provided to electrically connect the corresponding common electrode COM and the common doped region 211, and a second via 50 is provided to electrically connect the corresponding common electrode COM and the first doped region 411. Even further, as... Figure 1 and Figure 6 As shown, the orthographic projection of the first via 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second via 50 on the substrate 10.

[0046] In other words, in this embodiment, since one of the source and drain electrodes of the first transistor T1, one of the source and drain electrodes of the second transistor T2, and one of the source and drain electrodes of the third transistor T3 need to be electrically connected, and at least two of the first transistor T1, the second transistor T2, and the third transistor T3 are stacked in a direction perpendicular to the substrate 10, the first via 30 corresponding to the common electrode COM and the common doped region 211, and the second via 50 corresponding to the common electrode COM and the first doped region 411 are respectively set by two etching processes. At the same time, the orthographic projection of the first via 30 on the substrate 10 and the orthographic projection of the second via 50 on the substrate 10 at least partially overlap, which can not only avoid the above-mentioned drilling effect, but also reduce the layout space occupied by a single pixel circuit PX in the direction parallel to the substrate 10, thereby increasing the pixel density.

[0047] Please see Figure 2 and Figure 7 ,in, Figure 2 This is a schematic cross-sectional view of the array substrate 100 in another embodiment. Figure 7This is a partial layout diagram of the array substrate 100 in another embodiment.

[0048] In one exemplary embodiment, see Figure 2 and Figure 7 The array substrate 100 provided in this application also includes a bottom metal layer BSM, which is located between the substrate 10 and the first active layer 20. The bottom metal layer BSM includes a first bottom gate B1, the orthographic projection of the first bottom gate B1 on the substrate 10 overlaps with the orthographic projection of the first channel region CH1 on the substrate 10, and the orthographic projection of the first bottom gate B1 on the substrate 10 is outside the orthographic projection of the second channel region CH2 on the substrate 10.

[0049] It should be noted that in some embodiments of this application, the threshold voltage of the first transistor T1 needs to be adjusted by setting a first bottom gate B1 on the first transistor T1 and adjusting the voltage of the first bottom gate B1. Therefore, the orthographic projection of the first bottom gate B1 on the substrate 10 needs to overlap with the orthographic projection of the first channel region CH1 on the substrate 10. At the same time, in order to avoid the switching characteristics of the second transistor T2 being affected during the adjustment of the threshold voltage of the first transistor T1, the orthographic projection of the first bottom gate B1 on the substrate 10 needs to be located outside the orthographic projection of the second channel region CH2 on the substrate 10, so as to avoid the first bottom gate B1 affecting the switching characteristics of the second transistor T2.

[0050] In some embodiments, the orthographic projection of the first bottom gate B1 onto the substrate 10 covers the orthographic projection of the first channel region CH1 onto the substrate 10.

[0051] Next, please continue reading. Figure 2 Please refer to Figure 8 , Figure 8 This is a partial layout diagram of the array substrate 100 in another embodiment.

[0052] In one exemplary embodiment, such as Figure 2 and Figure 8 As shown, the pixel circuit PX provided in this application also includes a first capacitor C1, and the first active structure 21 also includes a second doped region 212 and a third doped region 213. The second doped region 212 serves as the doped region of the second transistor T2, and the third doped region 213 serves as the doped region of the first transistor T1. Along the first direction X parallel to the substrate 10, the second doped region 212 is located on the side of the second channel region CH2 away from the common doped region 211, and the common doped region 211 is located on the side of the first channel region CH1 away from the third doped region 213. The second metal layer M2 also includes the first electrode t11 of the first transistor T1. The first electrode t11 of the first transistor T1 is configured with a first power supply voltage VDD, and the first electrode t11 of the first transistor T1 is electrically connected to the third doped region 213.

[0053] Furthermore, the array substrate 100 also includes a third metal layer M3, which is located on the side of the second metal layer M2 away from the first metal layer M1. The third metal layer M3 includes a first electrode c11 of a first capacitor C1, which is electrically connected to the second doped region 212 and the first bottom gate B1. The plurality of pixel circuits include an adjacent pixel circuit PXa located on the side of the pixel circuit PX in the first direction X. The first electrode t11a of the first transistor T1a in the adjacent pixel circuit PXa serves as the second electrode c12 of the first capacitor C1 of the pixel circuit PX.

[0054] It should be noted that, please refer to Figure 9 In this embodiment, the first plate c11 of the first capacitor C1 is electrically connected to the second doped region 212, which serves as one of the source and drain terminals of the second transistor T2, and the first bottom gate B1 of the first transistor T1. The second plate c12 of the first capacitor C1 is configured with a first power supply voltage VDD. The first capacitor C1 is used to maintain the potential of the first bottom gate B1 of the first transistor T1. Specifically, before threshold voltage compensation is performed on the first transistor T1, the threshold voltage Vth1 of the first transistor T1 in each pixel circuit PX is not completely the same. When threshold voltage compensation of the first transistor T1 begins, the first transistor T1 is in the on state. During the threshold voltage compensation process of the first transistor T1, the first power supply voltage VDD passes sequentially through the first transistor T1 and the second transistor T2 (specifically, sequentially through the third doped region 213, the first channel region CH1, the common doped region 211, the second channel region CH2, the second doped region 212, and the first bottom gate B1). The first power supply voltage VDD gradually raises the voltage of the first bottom gate B1 until the potential of the first bottom gate B1 is VDD+Vth0. The voltage difference between the third doped region 213 and the first bottom gate B1 causes the first transistor T1 to turn off. At this time, the potential of the first bottom gate B1 of the first transistor T1 of each pixel circuit PX is written as VDD+Vth0, and Vth0 is stored in the corresponding first capacitor C1. Thus, in the subsequent light emission stage, since the potential of the first bottom gate B1 of the first transistor T1 of each pixel circuit PX is equal, the light emission uniformity of the corresponding light emission devices electrically connected to them is also guaranteed.

[0055] In this embodiment, on the one hand, setting the first capacitor C1 can ensure the stability of the first bottom gate B1 potential of the first transistor T1, thereby ensuring the uniformity of the display. On the other hand, by using the first electrode t11a of the first transistor T1a of the adjacent pixel circuit PXa located on the side of the pixel circuit PX in the first direction X as the second electrode c12 of the first capacitor C1 of the pixel circuit PX, the compactness of the pixel circuit PX in the first direction X can also be improved, thereby increasing the pixel density.

[0056] Specifically, the orthographic projection of the first electrode t11a of the first transistor T1a of the adjacent pixel circuit PXa onto the substrate 10 overlaps with the orthographic projection of the first electrode c11 of the first capacitor C1 onto the substrate 10.

[0057] In one exemplary embodiment, such as Figure 2 As shown, the third transistor T3 also includes a third gate G3 and a second bottom gate B2, and the array substrate 100 also includes a fourth metal layer M4 and a fifth metal layer M5.

[0058] The fourth metal layer M4 is located between the third metal layer M3 and the second active layer 40. The fourth metal layer M4 includes a second bottom gate B2, the orthographic projection of the second bottom gate B2 onto the substrate 10 overlaps with the orthographic projection of the third channel region CH3 onto the substrate 10. The fifth metal layer M5 is located on the side of the second active layer 40 away from the fourth metal layer M4. The fifth metal layer M5 includes a third gate G3, the orthographic projection of the third gate G3 onto the substrate 10 overlaps with the orthographic projection of the third channel region CH3 onto the substrate 10. The orthographic projection of the second bottom gate B2 onto the substrate 10 overlaps with the orthographic projection of the first electrode c11 of the first capacitor C1 onto the substrate 10.

[0059] It should be noted that, in order to further ensure the stability of the potential of the first bottom gate B1 of the first transistor T1, the potential of the first bottom gate B1 of the first transistor T1 can be better maintained by making the orthogonal projection of the second bottom gate B2 on the substrate 10 overlap with the orthogonal projection of the first plate c11 of the first capacitor C1 on the substrate 10 to form a storage capacitor.

[0060] Furthermore, in order to ensure that signals transmitted on other trace structures located on the side of the third channel region CH3 near the substrate 10 do not affect the switching characteristics of the third transistor T3, in some embodiments, the second bottom gate B2 can serve as a shielding layer between the third transistor T3 and the first transistor T1 and the second transistor T2 located below it. Specifically, the orthogonal projection of the second bottom gate B2 on the substrate 10 covers the orthogonal projection of the third channel region CH3 on the substrate 10.

[0061] For further information, please refer to [link / reference]. Figure 2 The second active structure 41 also includes a fourth doped region 412, and the array substrate 100 also includes a top metal layer M7. The top metal layer M7 is located on the side of the fifth metal layer M5 away from the second active layer 40. The top metal layer M7 includes a first electrode t31 and a second electrode t32 of the third transistor T3. The first electrode t31 of the third transistor T3 is electrically connected to the first doped region 411, and the second electrode t32 of the third transistor T3 is electrically connected to the fourth doped region 412 and is configured with a reference voltage VREF.

[0062] In some implementations, please refer to [the relevant documentation]. Figure 2 The second terminal t32 of the third transistor T3 is electrically connected to the second bottom gate B2. That is, based on the first capacitor C1, the potential of the first bottom gate B1 of the first transistor T1 is further maintained by the storage capacitor composed of the second bottom gate B2 configured with reference voltage VREF and the first plate c11 of the first capacitor C1 located in the third metal layer M3.

[0063] In some implementations, please refer to Figure 3 In another embodiment shown, a cross-sectional view of the array substrate 100 is provided. The second bottom gate B2 is configured with a first power supply voltage VDD. The first capacitor C1 includes a first sub-capacitor C1-1 and a second sub-capacitor C1-2 connected in parallel. The first sub-capacitor C1-1 and the second sub-capacitor C1-2 have a first common capacitor plate. The first plate c11 of the first capacitor C1 serves as the first common capacitor plate. Further, the first electrode t11a of the first transistor T1a in the adjacent pixel circuit PXa serves as the first sub-plate of the first sub-capacitor C1-1, and the second bottom gate B2 serves as the second sub-plate of the second sub-capacitor C1-2.

[0064] Specifically, in the embodiment where the second terminal t32 of the third transistor T3 is electrically connected to the second bottom gate B2, please refer to [the relevant documentation]. Figure 2 The array substrate 100 also includes a plurality of third vias 60, which pass through the fourth doped region 412 and are electrically connected to the second electrode t32 and the second bottom gate B2 of the third transistor T3.

[0065] Please continue reading. Figure 1 In some embodiments, the orthographic projection of the third channel region CH3 of the third transistor T3 in the same pixel circuit PX onto the substrate 10 overlaps with the orthographic projection of either the first channel region CH1 of the first transistor T1 or the second channel region CH2 of the second transistor T2 onto the substrate 10. This arrangement can further reduce the layout space occupied by a single pixel circuit PX in the direction parallel to the substrate 10, thereby effectively increasing pixel density. For example, as... Figure 1 As shown, in the same pixel circuit PX, the orthographic projection of the third channel region CH3 of the third transistor T3 onto the substrate 10 overlaps with the orthographic projection of the second channel region CH2 of the second transistor T2 onto the substrate 10. Alternatively, in other embodiments, in the same pixel circuit PX, the orthographic projection of the third channel region CH3 of the third transistor T3 onto the substrate 10 overlaps with the orthographic projection of the first channel region CH1 of the first transistor T1 onto the substrate 10.

[0066] For further information, please refer to [link / reference]. Figure 7In the embodiments of this application, the first channel region CH1 of the first transistor T1 and the second channel region CH2 of the second transistor T2 are arranged along the first direction X. Specifically, along the first direction X, the length of the first channel region CH1 is greater than the length of the second channel region CH2.

[0067] In some embodiments, the first transistor T1 is a driving transistor. As mentioned above, since the layout space occupied by a single pixel circuit PX in the direction parallel to the substrate 10 is compressed as much as possible by setting the common doped region 211 of the first transistor T1 and the second transistor T2 in the first active structure 21, the length of the first channel region CH1 of the first transistor T1 in the first embodiment of this application along the first direction X can be designed to be longer, thereby better ensuring the driving performance of the first transistor T1.

[0068] It should be noted that the data voltage DATA of the pixel circuit PX is typically written through the gate of the driving transistor (i.e., the first gate G1 of the first transistor T1) during the data writing phase. During the light-emitting phase, the data voltage DATA on the first gate G1 of the first transistor T1 needs to be maintained. Therefore, in this embodiment, the pixel circuit PX also includes a second capacitor C2, which is used to maintain the potential of the first gate G1 of the first transistor T1. For details, please refer to the following documentation. Figure 2 The first gate G1 of the first transistor T1 serves as the first plate of the second capacitor C2, and the first electrode t11 of the first transistor T1 serves as the second plate of the second capacitor C2. The orthogonal projection of the first gate G1 of the first transistor T1 onto the substrate 10 overlaps with the orthogonal projection of the first electrode t11 of the first transistor T1 onto the substrate 10.

[0069] For further information, please refer to [link / reference]. Figure 2 In some embodiments, the second capacitor C2 includes a third sub-capacitor C2-1 and a fourth sub-capacitor C2-2 connected in parallel. The third sub-capacitor C2-1 and the fourth sub-capacitor C2-2 have a second common capacitor plate. This arrangement can improve the storage performance of the second capacitor C2, thereby better maintaining the potential of the first gate G1 of the first transistor T1.

[0070] Specifically, the first electrode t11 of the first transistor T1 serves as the second common capacitor plate, and the first gate G1 of the first transistor T1 serves as the third sub-plate of the third sub-capacitor C2-1. The third metal layer M3 also includes the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2. Specifically, the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 is electrically connected to the first gate G1 of the first transistor T1, and the orthographic projection of the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 onto the substrate 10 overlaps with the orthographic projection of the first electrode t11 of the first transistor T1 onto the substrate 10.

[0071] In some implementations, such as Figure 2 As shown, the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 and the first plate c11 of the first capacitor C1 are both located in the third metal layer M3 and are formed by the same material in the same process.

[0072] It should be noted that, in the embodiment of the application, the second via 50 passes through the third metal layer M3. Since the orthographic projection of the first via 30 on the substrate 10 is at least partially the orthographic projection of the second via 50 on the substrate 10, the area of ​​the first electrode plate c11 of the first capacitor C1 and the fourth electrode plate C2-2a of the fourth sub-capacitor C2-2 located in the third metal layer M3 can be set to be larger, thereby improving the storage performance of the correspondingly formed first capacitor C1 and fourth sub-capacitor C2-2.

[0073] Furthermore, in some implementations, such as Figure 2 As shown, the pixel circuit PX also includes a fourth transistor T4 for controlling whether the data voltage DATA is written to the first gate G1 of the first transistor T1. The fourth transistor T4 includes a fourth channel region CH4. The second active layer 40 also includes a plurality of third active structures 42. The third active structures 42 include a fifth doped region 421 and the fourth channel region CH4 of the fourth transistor T4. The fifth doped region 421 serves as one of the source and drain electrodes of the fourth transistor T4 and is electrically connected to the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2.

[0074] It should be noted that, by setting the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 in the third metal layer M3, on the one hand, as mentioned above, the storage performance of the second capacitor C2 can be improved; on the other hand, by using a shallow hole penetrating from the second active layer 40 to the third metal layer M3 and a shallow hole penetrating from the third metal layer M3 to the first metal layer M1, the fifth doped region 421 can be indirectly electrically connected to the first gate G1 of the first transistor T1. This avoids the fifth doped region 421 being electrically connected to the first gate G1 of the first transistor T1 through a deep hole penetrating from the second active layer 40 to the first metal layer M1, thereby reducing the drilling depth, effectively avoiding the occurrence of drilling and etching effects, and ensuring that the doped regions in the second active structure 41 and the third active structure 42 in the second active layer 40 can be effectively conductive, thereby ensuring the device performance of the third transistor T3 and the fourth transistor T4.

[0075] For further information, please refer to [link / reference]. Figure 2In some embodiments, the fourth transistor T4 further includes a fourth gate G4 and a third bottom gate B3. In order to reduce the fabrication process and the overall thickness of the array substrate 100, the fourth gate G4 and the third bottom gate B3 of the fourth transistor T4 can be reused from the fourth metal layer M4 and the fifth metal layer M5 on which the third gate G3 and the second bottom gate B2 of the third transistor T3 are placed.

[0076] For details, please continue reading. Figure 2 The fourth metal layer M4 includes a third bottom gate B3, which is configured with a first power supply voltage VDD. The orthographic projection of the third bottom gate B3 onto the substrate 10 overlaps with the orthographic projection of the fourth channel region CH4 onto the substrate 10. The fifth metal layer M5 includes a fourth gate G4, the orthographic projection of the fourth gate G4 onto the substrate 10 overlaps with the orthographic projection of the fourth channel region CH4 onto the substrate 10.

[0077] It should be noted that the third bottom gate B3 is provided to ensure that signals transmitted on other trace structures on the side of the fourth channel region CH4 near the substrate 10 will not affect the switching characteristics of the fourth transistor T4. In some embodiments, the third bottom gate B3 can serve as a shielding layer between the fourth transistor T4 and the first transistor T1 and the second transistor T2 located below it.

[0078] Furthermore, the third bottom gate B3, in addition to serving as the aforementioned shielding layer, can further improve the storage performance of the second capacitor C2. Specifically, the second capacitor C2 also includes a fifth sub-capacitor C2-3 connected in parallel with the third sub-capacitor C2-1 and the fourth sub-capacitor C2-2. The fourth sub-capacitor C2-2 and the fifth sub-capacitor C2-3 have a third common capacitor plate, wherein the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 serves as the aforementioned third common capacitor plate, and the third bottom gate B3 serves as the fifth sub-plate of the fifth sub-capacitor C2-3. The orthographic projection of the fourth sub-plate C2-2a of the fourth sub-capacitor C2-2 onto the substrate 10 overlaps with the orthographic projection of the third bottom gate B3 onto the substrate 10.

[0079] For further information, please refer to [link / reference]. Figure 2 The third active structure 42 also includes a sixth doped region 422, which is located on the side of the fourth channel region CH4 away from the fifth doped region 421. Furthermore, the array substrate 100 also includes a sixth metal layer M6, which is located on the side of the fifth metal layer M5 away from the second active layer 40. The sixth metal layer M6 includes the first electrode t41 of the fourth transistor T4, which is electrically connected to the sixth doped region 422.

[0080] Specifically, in some embodiments of this application, the first terminal t41 of the fourth transistor T4 is configured with the data voltage DATA and the initial voltage Vini in a time-division configuration.

[0081] For further information, please refer to [link / reference]. Figure 2 In some embodiments, within the same pixel circuit PX, the orthographic projection of the third channel region CH3 of the third transistor T3 onto the substrate 10 overlaps with the orthographic projection of either the first channel region CH1 of the first transistor T1 or the second channel region CH2 of the second transistor T2 onto the substrate 10. Furthermore, the orthographic projection of the fourth channel region CH4 of the fourth transistor T4 onto the substrate 10 overlaps with the orthographic projection of the other of the first channel region CH1 of the first transistor T1 or the second channel region CH2 of the second transistor T2 onto the substrate 10. This arrangement can further reduce the layout space occupied by a single pixel circuit PX in the direction parallel to the substrate 10, thereby effectively increasing pixel density. For example, as... Figure 2 As shown, in the same pixel circuit PX, the orthographic projection of the third channel region CH3 of the third transistor T3 onto the substrate 10 overlaps with the orthographic projection of the second channel region CH2 of the second transistor T2 onto the substrate 10, and the orthographic projection of the fourth channel region CH4 of the fourth transistor T4 onto the substrate 10 overlaps with the orthographic projection of the first channel region CH1 of the first transistor T1 onto the substrate 10. Alternatively, in other embodiments not shown, the orthographic projection of the third channel region CH3 of the third transistor T3 onto the substrate 10 may overlap with the orthographic projection of the first channel region CH1 of the first transistor T1 onto the substrate 10, and the orthographic projection of the fourth channel region CH4 of the fourth transistor T4 onto the substrate 10 may overlap with the orthographic projection of the second channel region CH2 of the second transistor T2 onto the substrate 10.

[0082] For further information, please refer to [link / reference]. Figure 2 In some embodiments, the second metal layer M2 further includes a first electrode t21 of the second transistor T2, wherein the first electrode t21 of the second transistor T2 is electrically connected to the second doped region 212 and the first bottom gate B1, and the first plate c11 of the first capacitor C1 is electrically connected to the first electrode t21 of the second transistor T2.

[0083] Specifically, the array substrate 100 further includes a plurality of fourth vias 70 and a plurality of fifth vias 80. The fourth vias 70 pass through the second doped region 212 and are electrically connected to the first bottom gate B1 and the first electrode t21 of the second transistor T2. The fifth vias 80 are electrically connected to the first electrode c11 of the first capacitor C1 and the first electrode t21 of the second transistor T2. In some embodiments, the orthographic projection of the fourth via 70 onto the substrate 10 does not overlap with the orthographic projection of the fifth via 80 onto the substrate 10.

[0084] Specifically, in the above embodiment, the first electrode t21 of the second transistor T2 and the corresponding fourth via 70 are an integral structure, and the first electrode c11 of the first capacitor C1 and the corresponding fifth via 80 are an integral structure.

[0085] For further information, please refer to [link / reference]. Figure 2 In some embodiments, the array substrate 100 further includes a plurality of first electrodes 90 located on the side of the top metal layer M7 away from the second active layer 40, and the first electrodes 90 are electrically connected to the first electrode t31 of the third transistor T3. Specifically, for a top-emitting device, the first electrode 90 may be the anode of the light-emitting device, or for a bottom-emitting device, the first electrode 90 may be the cathode of the light-emitting device.

[0086] In some implementations, please refer to [the relevant documentation]. Figure 2 The second via 50 extends from the top metal layer M7 to the second metal layer M2, and the second via 50 contacts the common electrode COM, the first doped region 411, and the first electrode t31 of the third transistor T3.

[0087] Furthermore, in this embodiment, please continue to refer to... Figure 2 The first electrode t31 of the third transistor T3 and the corresponding second via 50 are an integral structure.

[0088] In other implementations, please refer to Figure 4 A cross-sectional structural diagram of the array substrate 100 in another embodiment is shown, wherein the second via 50 includes a first sub-via 51 and a second sub-via 52, and the sixth metal layer M6 of the array substrate includes a bridging structure P. Specifically, the first sub-via 51 extends from the sixth metal layer M6 to the second metal layer M2, and the first sub-via 51 contacts the common electrode COM, the first doped region 411 and the bridging structure P; the second sub-via 52 extends from the top metal layer M7 to the sixth metal layer M6, and the second sub-via 52 contacts the bridging structure P and the first electrode t31 of the third transistor T3.

[0089] Furthermore, in this embodiment, please continue to refer to... Figure 4 The bridging structure P and the corresponding first sub-hole 51 are an integral structure, and the first electrode t31 of the third transistor T3 and the corresponding second sub-hole 52 are an integral structure.

[0090] In other implementations, please refer to Figure 5 A cross-sectional structural diagram of the array substrate 100 in another embodiment is shown, wherein the second via 50 includes a third sub-via 53 and a fourth sub-via 54. Specifically, the third sub-via 53 extends from the second active layer 40 to the second metal layer M2, and contacts the common electrode COM and the first doped region 411. The fourth sub-via 54 extends from the top metal layer M7 to the second active layer 40, and contacts the first doped region 411 and the first electrode t31 of the third transistor T3.

[0091] Furthermore, in this embodiment, please continue to refer to... Figure 5 The first electrode t31 of the third transistor T3 and the corresponding fourth sub-hole 54 are integrated into one structure, and the second active structure 41 and the corresponding third sub-hole 53 are integrated into one structure.

[0092] For further information, please refer to [link / reference]. Figure 2 In some embodiments of the present invention, the common electrode COM and the corresponding first via 30 are integral structures, and / or, the second electrode t32 of the third transistor T3 and the corresponding third via 60 are integral structures.

[0093] It should be noted that in some embodiments, the first transistor T1 is a driving transistor. When the pixel circuit PX further includes a second transistor T2 and a third transistor T3, the second gate G2 of the second transistor T2 and the third gate G3 of the third transistor T3 are configured with different scan signals. When the pixel circuit PX further includes a fourth transistor T4, the second gate G2 of the second transistor T2, the third gate G3 of the third transistor T3, and the fourth gate G4 of the fourth transistor T4 are configured with different scan signals.

[0094] Next, combined Figure 9 The equivalent circuit diagram of the pixel circuit PX of the array substrate 100 shown in one embodiment is as follows: Figure 10 The diagram shown is a control timing diagram corresponding to the pixel circuit PX in one embodiment, which illustrates the driving method of the pixel circuit PX.

[0095] In some implementations, the pixel circuit PX includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2. The pixel circuit PX is used to drive the light-emitting device OLED to emit light. The common electrode COM of the first transistor T1 and the second transistor T2 and the first electrode t31 of the third transistor T3 are electrically connected to the light-emitting device OLED. Specifically, the first electrode 90 is electrically connected to the anode node of the light-emitting device OLED. Other specific connection methods of the above components have been described in detail above and will not be repeated here.

[0096] Specifically, the first transistor T1 is a driving transistor, the second transistor T2 is a threshold voltage regulating transistor, the third transistor T3 is a reset transistor, and the fourth transistor T4 is a data writing transistor. The first capacitor C1 is used to maintain the potential of the first bottom gate B1 of the first transistor T1, and the second capacitor C2 is used to maintain the potential of the first gate G1 of the first transistor T1. The second gate G2 of the second transistor T2 is configured with the first scan signal SCAN1, the third gate G3 of the third transistor T3 is configured with the second scan signal SCAN2, and the fourth gate G4 of the fourth transistor T4 is configured with the third scan signal SCAN3. The first terminal t11 of the first transistor T1 is configured with the first power supply voltage VDD, the second terminal t32 of the third transistor T3 is configured with the reference voltage VREF, and the first terminal t41 of the fourth transistor T4 is configured with the data voltage DATA and the initial voltage Vini in a time-division configuration.

[0097] Specifically, the operation of the pixel circuit PX mainly includes a reset phase S1, a threshold compensation phase S2, a data writing phase S3, and a light emission phase S4. Figure 9 and Figure 10 In the embodiment shown, the first transistor T1 and the second transistor T2 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors.

[0098] During the reset phase S1, the first scan signal SCAN1 is low, and the second scan signal SCAN2 and the third scan signal SCAN3 are high. The second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on. The first terminal t41 of the fourth transistor T4 is configured with an initial voltage Vini. This initial voltage Vini resets the first gate G1 of the first transistor T1 via the fourth transistor T4. Furthermore, the first gate G1 of the first transistor T1 is configured with the initial voltage Vini, and the first terminal t11 of the first transistor T1 is configured with the first power supply voltage VDD, causing the first transistor T1 to turn on. The second terminal t32 of the third transistor T3 is configured with a reference voltage VREF. This reference voltage VREF resets the anode node of the OLED via the third transistor T3 and further resets the first bottom gate B1 of the first transistor T1 via the second transistor T2.

[0099] During the threshold compensation phase S2, the second scan signal SCAN2 transitions to a low level, the first scan signal SCAN1 remains low, the third scan signal SCAN3 remains high, and the first terminal t41 of the fourth transistor T4 is maintained at the initial voltage Vini. The third transistor T3 is turned off, while the first transistor T1, the second transistor T2, and the fourth transistor T4 remain on. During the threshold voltage compensation process for the first transistor T1, the first power supply voltage VDD gradually increases the voltage of the first bottom gate B1 via the first transistor T1 and the second transistor T2 until the potential of the first bottom gate B1 is VDD+Vth0. At this point, the voltage difference between the first power supply voltage VDD and the corresponding potential VDD+Vth0 of the first bottom gate B1 at the first terminal t11 of the first transistor T1 turns off the first transistor T1. At this time, the potential of the first bottom gate B1 of the first transistor T1 in each pixel circuit PX is written as VDD+Vth0, and Vth0 is stored in the corresponding first capacitor C1.

[0100] During the data writing phase S3, the second scan signal SCAN2 remains low, while the first scan signal SCAN1 transitions to a high level. Consequently, the second transistor T2 is turned off, and the third transistor T3 remains off. At the initial moment of this phase, the third scan signal SCAN3 transitions to a low level and then sequentially transitions to a high level line by line. The first terminal t41 of the fourth transistor T4 is configured with the data voltage DATA. The data voltage DATA is written to the first gate G1 of the first transistor T1 via the fourth transistor T4 and stored in the corresponding second capacitor C2.

[0101] It should be noted that during the reset phase S1, threshold compensation phase S2, and data writing phase S3, the cathode node of the OLED light-emitting device maintains a high potential, and the OLED does not emit light.

[0102] During the light-emitting stage S4, the first scan signal SCAN1 remains at a high level, the second scan signal SCAN2 remains at a low level, and the third scan signal SCAN3 is at a low level. The cathode node of the light-emitting device OLED jumps to a low potential, which makes the driving path of the light-emitting device OLED and the first transistor T1 conduct, and emits light under the drive of the corresponding driving current.

[0103] In one specific embodiment, a method for fabricating an array substrate 100 is provided with a specific mask design, the method for fabricating the array substrate 100 including the steps described below.

[0104] PEP1: The first photomask is used to fabricate multiple first bottom gates B1 in the underlying metal layer BSM.

[0105] Specifically, the material of the bottom metal layer BSM may include molybdenum (chemical formula Mo). After the bottom metal layer BSM is formed, a buffer insulating layer (unlabeled, located between the bottom metal layer BSM and the first active layer 20) is formed. The material of the buffer insulating layer may include at least one of silicon nitride (SiNx) or silicon oxide (SiOx).

[0106] PEP2: The second photomask is used to fabricate multiple first active structures 21 in the first active layer 20.

[0107] Specifically, the first active layer 20 is a P-type LTPS semiconductor layer, and the material of the first active layer 20 can be low-temperature polycrystalline silicon (LTPS). After forming the first active layer 20, a full-surface gate insulating layer (unlabeled, located between the first active layer 20 and the first metal layer M1) is formed. The material of the gate insulating layer can include at least one of silicon nitride, silicon oxide, and silicon oxynitride (SiNxOy). The gate insulating layer can be a single layer or a stacked structure, and can be achieved by chemical vapor deposition. In addition, before fabricating the first active layer 20 on the substrate 10, at least one inorganic insulating layer can be prepared first to isolate water and oxygen.

[0108] PEP3: The third photomask is used to fabricate the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 in the first metal layer M1.

[0109] Specifically, the material of the first metal layer M1 may include Mo. After the first metal layer M1 is formed, an insulating layer (unlabeled, the material of which may include silicon nitride) is formed on the entire surface between the first metal layer M1 and the second metal layer M2.

[0110] PEP4: The fourth photomask is used to form a plurality of first vias 30, so that the common electrode COM in the subsequently formed second metal layer M2 is electrically connected to the common doped region 211 in the first active structure 21. Further, the aforementioned fourth photomask is also used to form corresponding vias, so that the first electrode t11 of the first transistor T1 in the subsequently formed second metal layer M2 is electrically connected to the third doped region 213 in the first active structure 21.

[0111] PEP5: The fifth photomask is used to prepare and form a plurality of fourth vias 70 so that the first terminal t21 of the second transistor T2 in the subsequently formed second metal layer M2 passes through the fourth vias 70 through the second doped region 212 and is electrically connected to the first bottom gate B1 in the bottom metal layer BSM.

[0112] PEP6: The sixth photomask is used to prepare and form the second metal layer M2, which includes the common electrode COM of the first transistor T1 and the second transistor T2, the first electrode t11 of the first transistor T1 and the first electrode t21 of the second transistor T2.

[0113] Specifically, the material of the second metal layer M2 may include Mo. After the second metal layer M2 is formed, an insulating layer (unlabeled, the material of which may include silicon nitride) is formed on the entire surface between the second metal layer M2 and the third metal layer M3.

[0114] PEP7: The seventh photomask is used to form multiple fifth vias 80, so that the first electrode c11 of the first capacitor C1 in the subsequently formed third metal layer M3 is electrically connected to the first electrode t21 of the second transistor T2 in the second metal layer M2. Further, the aforementioned fourth photomask is also used to form corresponding vias, so that the fourth electrode C2-2a of the fourth sub-capacitor C2-2 in the subsequently formed third metal layer M3 is electrically connected to the first gate G1 of the first transistor T1 in the first metal layer M1.

[0115] PEP8: The eighth photomask is used to prepare and form the third metal layer M3, which includes the first electrode C11 of the first capacitor C1 and the fourth sub-electrode C2-2a of the fourth sub-capacitor C2-2.

[0116] Specifically, the material of the third metal layer M3 may include Mo. After the third metal layer M3 is formed, an insulating layer (unlabeled, the material of which may include silicon nitride) is formed on the entire surface between the third metal layer M3 and the fourth metal layer M4.

[0117] PEP9: The ninth photomask is used to fabricate the fourth metal layer M4, which includes the second bottom gate B2 of the third transistor T3 and the third bottom gate B3 of the fourth transistor T4.

[0118] Specifically, the material of the fourth metal layer M4 may include Mo. After the fourth metal layer M4 is formed, an insulating layer (unlabeled, the material of which may include silicon nitride) is formed on the entire surface between the fourth metal layer M4 and the second active layer 40.

[0119] PEP10: The tenth photomask is used to prepare and form the corresponding via so that the fifth doped region 421 of the third active structure 42 in the subsequently formed second active layer 40 is electrically connected to the fourth sub-electrode C2-2a of the fourth sub-capacitor C2-2 in the third metal layer M3.

[0120] PEP11: The eleventh photomask is used to prepare and form the second active layer 40, which includes multiple second active structures 41 and multiple third active structures 42.

[0121] Specifically, the material of the second active layer 40 may include IGZO (Indium Gallium Zinc Oxide).

[0122] PEP12: The twelfth photomask is used to fabricate the fifth metal layer M5, which includes the third gate G3 of the third transistor T3 and the fourth gate G4 of the fourth transistor T4. Specifically, the material of the fifth metal layer M5 may include Mo.

[0123] PEP13: The thirteenth photomask is used to prepare and form the corresponding via so that the first electrode t41 of the fourth transistor T4 in the subsequently formed sixth metal layer M6 is electrically connected to the sixth doped region 422 of the third active structure 42 in the second active layer 40.

[0124] PEP14: The fourteenth photomask is used to fabricate the sixth metal layer M6, which includes the first electrode t41 of the fourth transistor T4. Specifically, the material of the sixth metal layer M6 may include a titanium / aluminum / titanium three-layer stacked structure (Ti / Al / Ti).

[0125] PEP15: The fifteenth photomask is used to fabricate vias that form partial structural electrical connections between the top metal layer M7 and the sixth metal layer M6 in the bezel area located outside the display area.

[0126] PEP16: The sixteenth photomask is used to prepare and form the corresponding via so that the second electrode t32 of the third transistor T3 in the subsequently formed top metal layer M7 is electrically connected to the fourth doped region 412 of the second active structure 41 in the second active layer 40 and the second bottom gate B2 of the third transistor T3 in the fourth metal layer M4.

[0127] Furthermore, the sixteenth photomask is also used to prepare and form a plurality of second vias 50 so that the common electrode COM of the second metal layer M2 and the first electrode t31 of the third transistor T3 in the subsequently formed top metal layer M7 are electrically connected.

[0128] PEP17: The seventeenth photomask is used to fabricate the top metal layer M7, which includes the first electrode t31 and the second electrode t32 of the third transistor T3. Specifically, the material of the top metal layer M7 may include a titanium / aluminum / titanium three-layer stacked structure (Ti / Al / Ti).

[0129] PEP18: The eighteenth photomask is used to prepare the corresponding via so that the subsequently formed lead structure can be electrically connected to the first electrode t31 of the third transistor T3.

[0130] PEP19: The nineteenth photomask is used to fabricate the lead structure, and the material of the lead structure may include ITO (indium tin oxide).

[0131] PEP20: The twentieth photomask is used to fabricate and form multiple first electrodes 90. The first electrodes 90 are electrically connected to corresponding lead structures. The material of the first electrodes 90 may include ITO / Ag / ITO.

[0132] PEP21: The twenty-first photomask is used to prepare the pixel definition layer, and the material of the pixel definition layer may include polyimide.

[0133] It should be noted that the first active layer 20 and the second active layer 40 are important film layers defining the conductive channel region of the transistor, and are actually semiconductor layers in a thin-film transistor. The first active layer 20 and the second active layer 40 can be made of different types of semiconductor materials, such as polysilicon, oxide semiconductor, or other semiconductor materials. They can be made of the same material or different materials, depending on the actual pixel circuit requirements. In this application, the material of the first active layer 20 includes polysilicon, and / or the material of the second active layer 20 includes indium gallium zinc oxide.

[0134] Specifically, when polysilicon is selected as the semiconductor material for the active layer, a high-temperature annealing process is required. Generally, the high-temperature annealing process will damage indium gallium zinc oxide. That is to say, in the embodiments of this application, there is a sequential order in the preparation of the stacked first active layer 20 and the second active layer 40. If the stacked first active layer 20 and the second active layer 40 need to use both polysilicon and indium gallium zinc oxide as semiconductor materials, the first active layer 20 prepared first should be made of polysilicon and the second active layer 40 prepared later should be made of indium gallium zinc oxide. Alternatively, the stacked first active layer 20 and the second active layer 40 can be made of polysilicon or indium gallium zinc oxide at the same time. Therefore, in some embodiments of this application, the material of the first active layer 20 includes polysilicon and the material of the second active layer 20 includes indium gallium zinc oxide; in some embodiments of this application, the material of the first active layer 20 includes polysilicon and the material of the second active layer 20 includes polysilicon; in some embodiments of this application, the material of the first active layer 20 includes indium gallium zinc oxide and the material of the second active layer 20 includes indium gallium zinc oxide.

[0135] In one exemplary embodiment, a display panel is also provided, including the array substrate of any of the above embodiments. Therefore, the display panel also has the same beneficial effects as the array substrate described in any of the above embodiments. The similarities can be understood with reference to the explanation of the array substrate above. Figure 11 This is a schematic diagram of the structure of a display panel 200 provided in an embodiment of this application. In this embodiment, the display panel 200 includes any of the array substrates 100 provided in the above embodiments.

[0136] In summary, this application provides an array substrate 100 and a display panel 200. The pixel circuit PX in the array substrate 100 includes a first transistor T1, a second transistor T2, and a third transistor T3. The array substrate 100 includes a substrate 10, a first active layer 20, a first metal layer M1, a second metal layer M2, a plurality of first vias 30, a second active layer 40, and a plurality of second vias 50 stacked sequentially. The first active structure 21 in the first active layer 20 includes a common doped region 211. The first channel region CH1 of the first transistor T1 and the second channel region CH2 of the second transistor T2 in the same pixel circuit PX are located in the same first active structure 21. The first metal layer M1 includes... The first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2, the second metal layer M2 includes the common electrode COM of the first transistor T1 and the second transistor T2, the first via 30 electrically connects the common electrode COM and the common doped region 211, the second active structure 41 in the second active layer 40 includes the first doped region 411 and the third channel region 412 corresponding to the third transistor T3, the second via 50 electrically connects the common electrode COM and the first doped region 411, the orthographic projection of the first via 30 on the substrate 10 and the orthographic projection of the second via 50 on the substrate 10 at least partially overlap, which can reduce the layout space of the pixel circuit PX in the horizontal and vertical directions to achieve a higher pixel arrangement density.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array includes multiple pixel circuits, each pixel circuit comprising a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor have a common electrode. The first transistor includes a first gate and a first channel region. The second transistor includes a second gate and a second channel region. The third transistor includes a third channel region. The array substrate includes: Substrate; The first active layer is located on one side of the substrate and includes a plurality of first active structures. The first active structures include a common doped region, and the first channel region and the second channel region of the same pixel circuit are located in the same first active structure. A first metal layer, located on the side of the first active layer away from the substrate, includes a first gate and a second gate, wherein the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second channel region on the substrate. The second metal layer is located on the side of the first metal layer away from the first active layer, and includes the common electrode; Multiple first vias, wherein the first vias are electrically connected to the common electrode and the common doped region; The second active layer is located on the side of the second metal layer away from the first metal layer and includes a plurality of second active structures, wherein the second active structure includes a first doped region and a third channel region corresponding to the third transistor. Multiple second vias, the second vias being electrically connected to the common electrode and the first doped region; Wherein, the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap.

2. The array substrate according to claim 1, characterized in that, The first transistor further includes a first bottom gate, and the array substrate further includes: The bottom metal layer, located between the substrate and the first active layer, includes the first bottom gate, the orthographic projection of the first bottom gate on the substrate overlaps with the orthographic projection of the first channel region on the substrate, and is located outside the orthographic projection of the second channel region on the substrate; Preferably, the orthographic projection of the first bottom gate on the substrate covers the orthographic projection of the first channel region on the substrate.

3. The array substrate according to claim 2, characterized in that, The pixel circuit further includes a first capacitor, and the first active structure further includes a second doped region and a third doped region. Along a first direction parallel to the substrate, the second doped region is located on the side of the second channel region away from the common doped region, and the common doped region is located on the side of the first channel region away from the third doped region. The second metal layer further includes a first electrode of the first transistor, the first electrode of the first transistor being configured with a first power supply voltage, and the first electrode of the first transistor being electrically connected to the third doped region. The array substrate further includes: The third metal layer is located on the side of the second metal layer away from the first metal layer, and includes the first electrode of the first capacitor. The first electrode of the first capacitor is electrically connected to the second doped region and the first bottom gate. The plurality of pixel circuits include adjacent pixel circuits located on one side of the pixel circuit in the first direction, wherein the first electrode of the first transistor in the adjacent pixel circuit serves as the second electrode of the first capacitor. Preferably, the orthographic projection of the first electrode of the first transistor in the adjacent pixel circuit onto the substrate overlaps with the orthographic projection of the first electrode of the first capacitor onto the substrate.

4. The array substrate according to claim 3, characterized in that, The third transistor further includes a third gate and a second bottom gate, and the array substrate further includes: A fourth metal layer, located between the third metal layer and the second active layer, includes the second bottom gate, wherein the orthographic projection of the second bottom gate on the substrate overlaps with the orthographic projection of the third channel region on the substrate; The fifth metal layer is located on the side of the second active layer away from the fourth metal layer, and includes the third gate, wherein the orthographic projection of the third gate on the substrate overlaps with the orthographic projection of the third channel region on the substrate; Wherein, the orthographic projection of the second bottom gate on the substrate overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate; Preferably, the orthographic projection of the second bottom gate on the substrate covers the orthographic projection of the third channel region on the substrate.

5. The array substrate according to claim 4, characterized in that, The second active structure further includes a fourth doped region, and the array substrate further includes a top metal layer located on the side of the fifth metal layer away from the second active layer. The top metal layer includes a first electrode and a second electrode of the third transistor. The first electrode of the third transistor is electrically connected to the first doped region, and the second electrode of the third transistor is electrically connected to the fourth doped region and configured with a reference voltage, wherein: The second electrode of the third transistor is electrically connected to the second bottom gate; or... The second bottom gate is configured with the first power supply voltage. The first capacitor includes a first sub-capacitor and a second sub-capacitor connected in parallel. The first sub-capacitor and the second sub-capacitor have a first common capacitor plate. The first plate of the first capacitor serves as the first common capacitor plate. The first electrode of the first transistor in the adjacent pixel circuit serves as the first sub-plate of the first sub-capacitor. The second bottom gate serves as the second plate of the second sub-capacitor.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes: Multiple third vias pass through the fourth doped region and are electrically connected to the second electrode and the second bottom gate of the third transistor.

7. The array substrate according to claim 1, characterized in that, In the same pixel circuit: The orthographic projection of the third channel region onto the substrate overlaps with the orthographic projection of either the first channel region or the second channel region onto the substrate; and / or, The first channel area and the second channel area are arranged along a first direction, and along the first direction, the length of the first channel area is greater than the length of the second channel area.

8. The array substrate according to claim 3, characterized in that, The pixel circuit further includes a second capacitor, with the first gate serving as the first plate of the second capacitor, the first electrode of the first transistor serving as the second plate of the second capacitor, and the orthographic projection of the first gate on the substrate overlapping the orthographic projection of the first electrode of the first transistor on the substrate.

9. The array substrate according to claim 8, characterized in that, The second capacitor includes a third sub-capacitor and a fourth sub-capacitor connected in parallel, the third sub-capacitor and the fourth sub-capacitor having a second common capacitor plate, wherein: The first electrode of the first transistor serves as the second common capacitor plate. The first gate serves as the third sub-plate of the third sub-capacitor; The third metal layer further includes a fourth sub-plate of the fourth sub-capacitor, the fourth sub-plate of the fourth sub-capacitor being electrically connected to the first gate, and the orthographic projection of the fourth sub-plate of the fourth sub-capacitor onto the substrate overlapping the orthographic projection of the first electrode of the first transistor onto the substrate.

10. The array substrate according to claim 9, characterized in that, The pixel circuit further includes a fourth transistor, the fourth transistor including a fourth channel region, wherein: The second active layer also includes a plurality of third active structures, wherein the third active structure includes a fifth doped region and the fourth channel region, and the fifth doped region is electrically connected to the fourth sub-plate of the fourth sub-capacitor.

11. The array substrate according to claim 10, characterized in that, The fourth transistor further includes a fourth gate and a third bottom gate, and the array substrate further includes: A fourth metal layer, located between the third metal layer and the second active layer, includes the third bottom gate, which is configured with the first power supply voltage, and the orthographic projection of the third bottom gate on the substrate overlaps with the orthographic projection of the fourth channel region on the substrate. The fifth metal layer is located on the side of the second active layer away from the fourth metal layer, and includes the fourth gate, wherein the orthographic projection of the fourth gate on the substrate overlaps with the orthographic projection of the fourth channel region on the substrate; Preferably, the second capacitor further includes a fifth sub-capacitor connected in parallel with the third and fourth sub-capacitors, wherein the fourth and fifth sub-capacitors have a third common capacitor plate, wherein: The fourth sub-plate of the fourth sub-capacitor serves as the third common capacitor plate; The third bottom gate serves as the fifth sub-plate of the fifth sub-capacitor, and the orthographic projection of the fourth sub-electrode of the fourth sub-capacitor onto the substrate overlaps with the orthographic projection of the third bottom gate onto the substrate. Preferably, the third active structure further includes a sixth doped region, the sixth doped region being located on the side of the fourth channel region away from the fifth doped region, and the array substrate further includes: A sixth metal layer, located on the side of the fifth metal layer away from the second active layer, includes the first electrode of the fourth transistor, the first electrode of the fourth transistor being electrically connected to the sixth doped region; Preferably, the first electrode of the fourth transistor is configured with a time-division multiplexing of the data voltage and the initial voltage.

12. The array substrate according to claim 10, characterized in that, In the same pixel circuit: The orthographic projection of the third channel region onto the substrate overlaps with the orthographic projection of either the first channel region or the second channel region onto the substrate. The orthographic projection of the fourth channel region onto the substrate overlaps with the orthographic projection of the other of the first channel region and the second channel region onto the substrate.

13. The array substrate according to claim 3, characterized in that, The second metal layer further includes a first electrode of the second transistor, wherein: The first electrode of the second transistor is electrically connected to the second doped region and the first bottom gate; The first plate of the first capacitor is electrically connected to the first electrode of the second transistor; Preferably, the array substrate further includes: Multiple fourth vias, the fourth vias passing through the second doped region and electrically connecting the first bottom gate and the first electrode of the second transistor; and, Multiple fifth vias, wherein the fifth vias are electrically connected to the first plate of the first capacitor and the first electrode of the second transistor; Preferably, the orthographic projection of the fourth via on the substrate does not overlap with the orthographic projection of the fifth via on the substrate.

14. The array substrate according to claim 1, characterized in that, The array substrate further includes: A top metal layer is located on the side of the second active layer away from the second metal layer. The top metal layer includes the first electrode of the third transistor, and the first electrode of the third transistor is electrically connected to the first doped region. Multiple first electrodes are located on the side of the top metal layer away from the second active layer, and the first electrodes are electrically connected to the first electrode of the third transistor; Preferably, the material of the first active layer includes polycrystalline silicon, and / or the material of the second active layer includes indium gallium zinc oxide.

15. The array substrate according to claim 1, characterized in that, The array substrate further includes a top metal layer located on the side of the second active layer away from the second metal layer. The top metal layer includes a first electrode of the third transistor, which is electrically connected to the first doped region. The second via contacts the common electrode, the first doped region, and the first electrode of the third transistor; or, The second via includes a first sub-via and a second sub-via. The array substrate further includes a sixth metal layer located between the third gate of the third transistor and the top metal layer. The sixth metal layer includes a bridging structure. The first sub-via contacts the common electrode, the first doped region, and the bridging structure; the second sub-via contacts the bridging structure and the first electrode of the third transistor. Alternatively, The second via includes a third sub-via and a fourth sub-via, wherein the third sub-via contacts the common electrode and the first doped region, and the fourth sub-via contacts the first doped region and the first electrode of the third transistor.

16. The array substrate according to claim 15, characterized in that, The common electrode and the corresponding first via are an integral structure, wherein: The first electrode of the third transistor and the corresponding second via are an integral structure; or, The bridging structure and the corresponding first sub-hole are an integral structure, and the first electrode of the third transistor and the corresponding second sub-hole are an integral structure; or... The first electrode of the third transistor and the corresponding fourth sub-hole are an integral structure, and the second active structure and the corresponding third sub-hole are an integral structure.

17. The array substrate according to claim 6, characterized in that, The second electrode of the third transistor and the corresponding third via are an integral structure.

18. The array substrate according to claim 3, characterized in that, The first electrode of the second transistor and the corresponding fourth via are integral structures, and the first electrode plate of the first capacitor and the corresponding fifth via are integral structures.

19. The array substrate according to claim 1, characterized in that, The third transistor further includes a third gate, the first transistor is a driving transistor, and the second gate and the third gate are configured with different scan signals; Preferably, the pixel circuit further includes a fourth transistor, the fourth transistor including a fourth gate and a fourth channel region, wherein: The second active layer also includes a plurality of third active structures, the third active structures including a fifth doped region, a sixth doped region and the fourth channel region, the sixth doped region being located on the side of the fourth channel region away from the fifth doped region; The fifth doped region is electrically connected to the first gate, the sixth doped region is configured with a data voltage and an initial voltage in a time-division manner, and the second gate, the third gate, and the fourth gate are configured with different scan signals.

20. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-19.

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