Micro structure for improving light efficiency and stability of micro LED matrix headlamp and preparation method thereof

Abstract

The application discloses a micro structure for improving light efficiency and stability of a Micro LED matrix headlamp and a preparation method thereof. The micro structure comprises an N-side ITO current expansion layer of a Micro LED chip unit, a conical hole structure arranged in a periodic misplacement manner is arranged in the N-side ITO current expansion layer, the etching depth is 50% of the total thickness of the ITO layer, and a continuous ITO conductive layer is reserved at the bottom; the surface of the ITO layer is entirely covered with a SiO2 passivation buffer layer; a three-dimensional current expansion network is formed through the misplacement hole structure, the current distribution is optimized, the total reflection is reduced by breaking the smooth interface, the step refractive index matching is realized in combination with the SiO2 layer, the light extraction efficiency is greatly improved, the surface roughness and the surface area are improved through the hole structure, the adhesion of the fluorescent powder is enhanced, the passivation protection is realized through the SiO2 layer, and the stability and the service life of the device in a vehicle-mounted wide-temperature vibration environment are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, specifically to a microstructure and its fabrication method for improving the luminous efficacy and stability of Micro LED matrix headlights. Background Technology

[0002] Micro LED, as a new generation of semiconductor display and light-emitting technology, has advantages such as high brightness, high contrast, fast response, long life and high reliability, and has broad application prospects in automotive matrix headlight systems. Automotive matrix headlights place stringent requirements on the light extraction efficiency, light emission uniformity, environmental stability and vibration resistance of Micro LED devices. Their operating temperature range covers -40℃ to 85℃, and they must withstand long-term vibration and temperature cycling shocks.

[0003] In current mainstream Micro LED manufacturing processes, a flat indium tin oxide (ITO) thin film is typically deposited on the surface of an N-type gallium nitride (GaN) layer as a current spreading layer. This structure has the following technical drawbacks in automotive applications:

[0004] 1. Low light emission efficiency: The refractive index of ITO is about 1.9-2.0, which is much higher than that of air (refractive index 1.0) or encapsulating epoxy resin / silicone (refractive index 1.4-1.5). When light shines from the ITO layer to the external medium, significant total internal reflection will occur on the smooth ITO surface, causing a large amount of light to be confined inside the LED chip and unable to be emitted effectively, thus reducing the luminous efficiency and brightness of the headlight.

[0005] 2. Uneven current distribution: Although a flat ITO film has a certain ability to spread lateral current, as the pixel size of Micro LED shrinks to below 10μm, the current congestion effect becomes particularly significant. This not only leads to uneven local brightness but also causes local overheating, accelerating device aging. In the wide temperature cycling environment of automotive applications, this unevenness will be further aggravated, seriously affecting the device lifespan.

[0006] 3. Poor phosphor adhesion: The white light output of automotive matrix headlights is usually achieved by exciting phosphors with blue Micro LEDs to achieve color conversion. However, the smooth ITO surface has weak adhesion to phosphor colloids. Under long-term vibration in the automotive environment, phosphor layer peeling and cracking are prone to occur, resulting in color deviation and brightness decay of the device.

[0007] 4. Insufficient device stability: In the wide temperature environment of automotive applications, the thermal expansion coefficients between the traditional ITO thin film and the GaN semiconductor layer are mismatched, which can easily lead to stress accumulation during temperature cycling, resulting in interface cracking and contact failure. At the same time, the smooth ITO surface lacks effective passivation protection, making the device susceptible to corrosion by moisture and oxygen, and its performance degrades over time.

[0008] To address the aforementioned shortcomings, existing technologies mostly employ a single microstructure design to improve luminous efficiency or a separate passivation layer to enhance stability. However, they cannot simultaneously achieve a synergistic improvement in luminous efficiency, current uniformity, phosphor adhesion, and long-term device stability, making it difficult to meet the stringent application requirements of automotive matrix headlights. Summary of the Invention

[0009] The purpose of this invention is to provide a microstructure and fabrication method for improving the light efficiency and stability of Micro LED matrix headlights. By combining a staggered arrangement of conical ITO hole structures with a SiO2 passivation buffer layer covering the entire surface, the light extraction efficiency, current spread uniformity, phosphor adhesion and device environmental stability are improved simultaneously, thus solving the technical pain points of existing automotive Micro LED matrix headlights.

[0010] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0011] A microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights is disclosed. The Micro LED matrix headlight comprises several arrayed Micro LED chip units. Each Micro LED chip unit, from bottom to top, is provided with a silicon-based CMOS driving substrate, a bonding metal layer, a P-type ITO layer, a P-type GaN layer, a multi-quantum-well light-emitting layer, an N-type GaN layer, and an N-side ITO current extension layer. The N-side ITO current extension layer contains periodically staggered conical hole structures. The etching depth of the conical hole structures is 50% of the total thickness of the N-side ITO current extension layer. A continuous ITO conductive layer is retained at the bottom of the N-side ITO current extension layer. The bottom width of the conical hole structure is 350 nm, the top width is 650 nm, and the spacing between adjacent conical hole structures is 1 μm. The entire surface of the N-side ITO current extension layer is covered with a SiO2 passivation buffer layer.

[0012] In a preferred embodiment, the adjacent conical hole structures are arranged in a honeycomb pattern with staggered positions of holes in adjacent rows, thus avoiding the formation of a regular periodic grating structure.

[0013] In a preferred embodiment, the conical hole structure increases the effective surface area of ​​the N-side ITO current extension layer by 40%-60% compared to a flat ITO layer.

[0014] In a preferred embodiment, the SiO2 passivation buffer layer has a refractive index of 1.46, which is used to form a stepped refractive index matching structure between the N-side ITO current extension layer and the external encapsulation medium, thereby reducing interface Fresnel reflection.

[0015] In a preferred embodiment, the total thickness of the N-side ITO current spreading layer is 600 nm, and the etching depth of the conical hole structure is 300 nm.

[0016] This invention also provides a method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix headlight, comprising the following steps:

[0017] S1, Fabrication of Micro LED chip substrate structure: Complete the eutectic bonding of silicon-based CMOS driving substrate and GaN epitaxial wafer, remove the substrate and thin the N-type GaN layer, and sequentially complete mesa etching, P-type ITO fabrication, bonding metal layer fabrication and isolation etching to obtain arrayed Micro LED chip units.

[0018] S2, Preparation of N-side ITO current spreading layer: On the surface of the N-type GaN layer obtained in step S1, an ITO thin film is deposited by electron beam evaporation to form an N-side ITO current spreading layer.

[0019] S3, Prepare a staggered conical hole structure: Spin-coat photoresist on the surface of the N-side ITO current spreading layer, transfer the staggered conical hole pattern to the photoresist layer through mask exposure and development process, etch the N-side ITO current spreading layer using ion beam etching process, and control the etching depth to 50% of the total thickness of the ITO film to form a periodically staggered conical hole structure. Remove the remaining photoresist after etching.

[0020] S4, Preparation of SiO2 passivation buffer layer: SiO2 thin film is grown on the entire surface of the etched N-side ITO current extension layer using chemical vapor deposition process to form SiO2 passivation buffer layer.

[0021] S5, Electrode fabrication and phosphor coating: The electrode area of ​​the chip is exposed by photolithography etching process to complete the N-polar metal mesh fabrication; the light-emitting surface of the chip is treated with oxygen plasma to increase the surface hydroxyl density, and then phosphor colloid is spin-coated to complete curing and thinning to obtain the Micro LED matrix headlight device.

[0022] In a preferred embodiment, in step S2, the evaporation thickness of the ITO thin film is 600 nm, and in step S3, the etching depth is controlled to be 300 nm.

[0023] In a preferred embodiment, in step S3, the mask pattern is a honeycomb pattern of staggered conical holes, with the holes in adjacent rows being staggered. The holes are designed with a bottom width of 350nm, a top width of 650nm, and a spacing of 1μm between adjacent holes.

[0024] In a preferred embodiment, in step S3, the ion beam etching process employs IBE etching, and the anisotropic etching precision is controlled during the etching process to ensure that the taper of the hole sidewall meets the design requirements, and a continuous ITO conductive layer is retained at the bottom of the N-side ITO current extension layer.

[0025] In a preferred embodiment, in step S4, the growth thickness of the SiO2 thin film is 50-200 nm. The SiO2 thin film serves as both a refractive index buffer layer and a passivation protection layer, achieving stepped refractive index matching and isolation from the device environment.

[0026] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0027] 1. Significantly Improved Light Extraction Efficiency: This invention breaks the smooth interface of the ITO surface through a staggered arrangement of conical holes, providing more escape cone angles for light and significantly reducing the probability of total internal reflection. As a two-dimensional scatterer, the hole structure causes light to undergo multiple reflections and refractions at the sidewalls, valleys, and peaks, increasing the chance of light escaping at angles less than the critical angle. At the same time, the SiO2 layer covering the entire surface forms a stepped refractive index matching structure of ITO (n=1.9-2.0) → SiO2 (n=1.46) → external medium (n=1.0-1.5), which significantly reduces Fresnel reflection at the interface, further improves light transmittance, and ultimately achieves a significant improvement in device luminous efficiency.

[0028] 2. Optimize current distribution and improve device reliability: The etching depth of the hole structure in this invention is 50% of the total thickness of the ITO layer. The bottom retains a continuous ITO layer to provide lateral current expansion, and the ITO area between the holes provides a vertical current path, forming a three-dimensional current expansion network. This effectively disperses the current density, significantly suppresses the current congestion effect under the micro LED miniaturized pixels, reduces the generation of local hot spots, avoids device aging caused by local overheating, and greatly improves the working life and reliability of the device in the wide temperature range of automotive environments.

[0029] 3. Significantly improved phosphor adhesion: The staggered conical hole structure increases the effective surface area of ​​ITO by 40%-60%, providing a large number of mechanical anchoring points for the phosphor colloid; at the same time, combined with oxygen plasma treatment, the hydroxyl density of the ITO surface is increased, enhancing the chemical bonding force with the phosphor silicone material. This solves the problem of phosphor layer peeling and cracking under vehicle vibration environment from both mechanical and chemical perspectives, ensuring the long-term stability of device color coordinates and brightness.

[0030] 4. Enhanced device environmental stability: The full-coverage SiO2 layer forms a dense passivation protective layer, effectively isolating external environmental corrosion such as water vapor and oxygen, fixing the chemical state of the device surface, and preventing device performance degradation over time. At the same time, the SiO2 layer alleviates the problem of thermal expansion coefficient mismatch between the ITO layer and the external packaging material, reduces the accumulation of interface stress under wide temperature cycling, avoids interface cracking and contact failure, and meets the wide temperature operation requirements of automotive applications from -40℃ to 85℃.

[0031] 5. Excellent light emission uniformity: The present invention adopts a staggered arrangement of conical holes, which, compared with the traditional regular periodic photonic crystal structure, effectively avoids the problem of light emission directionality caused by grating diffraction effect, and achieves uniform light emission distribution at all angles, meeting the requirements of vehicle matrix headlights for uniform light emission angle. Attached Figure Description

[0032] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the layered structure of a traditional Micro LED chip.

[0034] Figure 2 This is a schematic diagram of the Micro LED chip structure after ITO structure etching in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the Micro LED chip structure after the SiO2 passivation buffer layer is completed in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the Micro LED chip structure after phosphor coating in an embodiment of the present invention;

[0037] Figure 5 This is a 52° top-view SEM image of the ITO structured etching in an embodiment of the present invention;

[0038] Figure 6 This is a cross-sectional SEM image of the ITO structured etching in an embodiment of the present invention;

[0039] Figure 7 This is a 52° top-view SEM image of the SiO2 layer after being covered in an embodiment of the present invention;

[0040] Figure 8This is a cross-sectional SEM image of the SiO2-covered section in an embodiment of the present invention;

[0041] The components include: 1. Silicon-based CMOS driving substrate; 2. Bonding metal layer; 3. P-type ITO layer; 4. P-type GaN layer; 5. Multiple quantum well light-emitting layer; 6. N-type GaN layer; 7. N-side ITO current spreading layer; 8. Conical hole structure; 9. ITO conductive layer; 10. SiO2 passivation buffer layer; and 11. Phosphor. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0044] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0045] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0046] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0047] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] Example 1

[0049] Please see Figures 1-8 This invention relates to a microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights, and is applied to a Micro LED array device for automotive matrix headlights. It includes several arrayed Micro LED chip units, and the layered structure of each chip unit from bottom to top consists of: a silicon-based CMOS driving substrate 1, a bonding metal layer 2, a P-type ITO layer 3, a P-type GaN layer 4, a multi-quantum-well light-emitting layer 5, an N-type GaN layer 6, and an N-side ITO current spreading layer 7.

[0050] The N-side ITO current spreading layer 7 has a total thickness of 600 nm and contains periodically staggered, honeycomb-like conical aperture structures 8. The positions of adjacent rows of apertures are offset to avoid forming a regular, periodic grating structure. The bottom (near the N-type GaN layer 6) of the conical aperture structure 8 has a width of 350 nm, and the top (away from the N-type GaN layer 6) has a width of 650 nm. The center-to-center distance between adjacent conical apertures is 1 μm, and the etching depth is 300 nm, which is 50% of the total ITO layer thickness. A continuous ITO conductive layer 9 is retained at the bottom of the N-side ITO current spreading layer 7 to ensure that conductivity is not affected. This aperture structure increases the effective surface area of ​​the N-side ITO current spreading layer 7 by 40-60% compared to a flat ITO layer.

[0051] The entire surface of the N-side ITO current spreading layer 7 is covered with a 100nm thick SiO2 passivation buffer layer 10 with a refractive index of 1.46. A stepped refractive index matching structure is formed between the N-side ITO current spreading layer 7 and the external encapsulation silicone, while also serving as a passivation protection layer to isolate it from external environmental corrosion.

[0052] Example 2

[0053] This application provides a method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix headlight, specifically including the following steps:

[0054] S1, Fabrication of Micro LED chip substrate structure:

[0055] S11, Select a GaN epitaxial wafer on a sapphire substrate. The GaN epitaxial wafer consists of a sapphire substrate, an N-type GaN layer 6, a multi-quantum-well light-emitting layer 5, and a P-type GaN layer 4 from bottom to top. A 150 nm thick P-type ITO film is deposited on the surface of the P-type GaN layer 4 using an electron beam evaporation process. The film is then subjected to rapid thermal annealing in a nitrogen atmosphere at a temperature of 550 °C for 5 min.

[0056] S12, a Ti / Au bonding metal layer 2 is deposited on the P-type ITO surface of the annealed GaN epitaxial wafer and the surface of the silicon-based CMOS driving substrate 1, respectively, with a deposition thickness of 200nm; the silicon-based CMOS driving substrate 1 is placed below and the GaN epitaxial wafer is placed above, so that the bonding metal layers 2 are bonded together, and eutectic bonding is performed under the conditions of temperature 280℃ and pressure 5MPa for a bonding time of 20min;

[0057] S13, the sapphire substrate of the GaN epitaxial wafer is removed by laser lift-off process, and then the N-type GaN layer 6 is thinned by inductively coupled plasma (ICP) etching process until the remaining thickness is 1.2 μm;

[0058] S14. A 200nm thick SiO2 hard mask layer is grown on the surface of the thinned N-type GaN layer 6 using plasma-enhanced chemical vapor deposition (PECVD). After spin-coating photoresist, an array mesa pattern is fabricated through exposure and development processes. The mesa diameter is 60μm. The SiO2 layer, N-type GaN layer 6, multi-quantum-well light-emitting layer 5, P-type GaN layer 4 to P-type ITO layer 3 between the mesa are etched away using ICP etching to form an array of Micro LED chip units. The remaining SiO2 hard mask layer is removed using BOE etchant.

[0059] S15 uses PECVD to grow a 300nm thick SiO2 electron blocking layer on the chip surface. After spin coating with photoresist, the light-emitting surface of each chip unit is exposed by mask exposure and development process. ICP etching process is used to etch the SiO2 layer through the light-emitting surface area to the surface of the N-type GaN layer 6. The remaining photoresist is washed away to complete the fabrication of the chip substrate structure.

[0060] S2, Fabrication of the N-side ITO current-spreading layer 7:

[0061] On the surface of the N-type GaN layer 6 obtained in step S1, an ITO thin film with a thickness of 600 nm is deposited by electron beam evaporation to form the N-side ITO current spreading layer 7. During the evaporation process, the substrate temperature is controlled at 100℃ to ensure the crystal quality and conductivity of the ITO thin film.

[0062] S3, Preparation of a staggered conical hole structure 8:

[0063] S31, spin-coat negative photoresist on the surface of the N-side ITO current spreading layer 7, the photoresist thickness is 800nm, and pre-bake at 110℃ for 90s;

[0064] S32 uses a photomask with a honeycomb-shaped staggered arrangement of conical holes for ultraviolet exposure at an exposure dose of 120mJ / cm². After exposure, it is developed in a developer at 23°C for 60s to transfer the staggered arrangement of conical holes to the photoresist layer. The holes in the pattern are designed with a bottom width of 350nm and a top width of 650nm. The center-to-center distance between adjacent holes is 1μm, and the positions of the holes in adjacent rows are staggered.

[0065] S33, the N-side ITO current extension layer 7 is anisotropically etched using the IBE process. The etching process parameters are: accelerating voltage 800V, beam current density 0.5mA / cm², etching angle 90°, and etching depth controlled at 300nm, which is 50% of the total thickness of the ITO film, to ensure that a continuous ITO conductive layer 9 is retained at the bottom of the N-side ITO current extension layer 7.

[0066] S34, acetone and deionized water are used to clean and remove the remaining photoresist, thus completing the fabrication of the staggered conical hole structure 8.

[0067] S4, Preparation of SiO2 passivation buffer layer 10:

[0068] Using PECVD process, a 100nm thick SiO2 film is grown on the entire surface of the etched N-side ITO current extension layer 7 to form a SiO2 passivation buffer layer 10. The growth temperature is 200℃ to ensure the density and step coverage of the film.

[0069] S5, Electrode preparation and phosphor coating:

[0070] S51 spin-coates a 2.5μm thick negative photoresist onto the chip surface. After curing, it exposes the channel area between the mesa through mask exposure and development processes. It then uses electron beam evaporation to deposit a Cr / Al / Cr N-polar metal layer with a total thickness of 1.2μm. The photoresist and excess metal are removed through a stripping process to form an N-polar metal mesh between the mesa.

[0071] S52 uses photolithography, exposure, and development processes to expose the P and N electrode pad areas of the chip, and uses ICP etching process to etch away the SiO2 layer in the electrode area to complete the electrode lead-out.

[0072] S53 uses photolithography to expose the light-emitting surface area of ​​the chip, and performs oxygen plasma treatment on the light-emitting surface with a processing power of 200W and a processing time of 5min to increase the hydroxyl density on the ITO surface.

[0073] S54. Spin-coat phosphor 11 silicone colloid in the light-emitting area. The mass fraction of phosphor 11 in the colloid is 30%. Heat cure at 150℃ for 1 hour. Thin the phosphor 11 layer using chemical mechanical polishing process. After thinning to the target thickness, clean it to complete the fabrication of the Micro LED matrix headlight device. It can then be conventionally packaged to obtain the final product.

[0074] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights, the Micro LED matrix headlight comprising a plurality of arrayed Micro LED chip units, each Micro LED chip unit having, from bottom to top, a silicon-based CMOS driving substrate, a bonding metal layer, a P-type ITO layer, a P-type GaN layer, a multi-quantum-well light-emitting layer, an N-type GaN layer, and an N-side ITO current spreading layer, characterized in that, The N-side ITO current extension layer contains periodically staggered conical hole structures. Adjacent conical hole structures are arranged in a honeycomb pattern, with the positions of adjacent rows of holes offset from each other to avoid forming a regular periodic grating structure. The etching depth of the conical hole structure is 50% of the total thickness of the N-side ITO current extension layer. A continuous ITO conductive layer is retained at the bottom of the N-side ITO current extension layer. The bottom width of the conical hole structure is 350 nm, the top width is 650 nm, and the spacing between adjacent conical hole structures is 1 μm. The entire surface of the N-side ITO current extension layer is covered with a SiO2 passivation buffer layer.

2. The microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights according to claim 1, characterized in that, The conical hole structure increases the effective surface area of ​​the N-side ITO current extension layer by 40%-60% compared to a flat ITO layer.

3. The microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights according to claim 1, characterized in that, The SiO2 passivation buffer layer has a refractive index of 1.46 and is used to form a stepped refractive index matching structure between the N-side ITO current extension layer and the external encapsulation medium, thereby reducing interface Fresnel reflection.

4. The microstructure for improving the luminous efficacy and stability of Micro LED matrix headlights according to claim 1, characterized in that, The total thickness of the N-side ITO current spreading layer is 600 nm, and the etching depth of the conical hole structure is 300 nm.

5. A method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix headlight according to any one of claims 1-4, characterized in that, Includes the following steps: S1, Fabrication of Micro LED chip substrate structure: Complete the eutectic bonding of silicon-based CMOS driving substrate and GaN epitaxial wafer, remove the substrate and thin the N-type GaN layer, and sequentially complete mesa etching, P-type ITO fabrication, bonding metal layer fabrication and isolation etching to obtain arrayed Micro LED chip units. S2, Preparation of N-side ITO current spreading layer: On the surface of the N-type GaN layer obtained in step S1, an ITO thin film is deposited by electron beam evaporation to form an N-side ITO current spreading layer. S3, Prepare a staggered conical hole structure: Spin-coat photoresist on the surface of the N-side ITO current spreading layer, transfer the staggered conical hole pattern to the photoresist layer through mask exposure and development process, etch the N-side ITO current spreading layer using ion beam etching process, and control the etching depth to 50% of the total thickness of the ITO film to form a periodically staggered conical hole structure. Remove the remaining photoresist after etching. S4, Preparation of SiO2 passivation buffer layer: SiO2 thin film is grown on the entire surface of the etched N-side ITO current extension layer using chemical vapor deposition process to form SiO2 passivation buffer layer. S5, Electrode fabrication and phosphor coating: The electrode area of ​​the chip is exposed by photolithography etching process to complete the N-polar metal mesh fabrication; the light-emitting surface of the chip is treated with oxygen plasma to increase the surface hydroxyl density, and then phosphor colloid is spin-coated to complete curing and thinning to obtain the Micro LED matrix headlight device.

6. The method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix headlight according to claim 5, characterized in that, In step S2, the evaporation thickness of the ITO thin film is 600 nm, and in step S3, the etching depth is controlled to be 300 nm.

7. The method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix large light according to claim 5, characterized in that, In step S3, the mask pattern is a honeycomb pattern of staggered conical holes, with the holes in adjacent rows being staggered. The bottom width of the holes is 350nm, the top width is 650nm, and the spacing between adjacent holes is 1μm.

8. The method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix large light according to claim 5, characterized in that, In step S3, the ion beam etching process adopts IBE etching. During the etching process, the anisotropic etching accuracy is controlled to ensure that the taper of the hole sidewall meets the design requirements, and a continuous ITO conductive layer is retained at the bottom of the N-side ITO current extension layer.

9. The method for fabricating a microstructure to improve the luminous efficacy and stability of a Micro LED matrix headlight according to claim 5, characterized in that, In step S4, the growth thickness of the SiO2 film is 50-200 nm. The SiO2 film serves as both a refractive index buffer layer and a passivation protection layer, achieving stepped refractive index matching and isolation from the device environment.

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