Full-automatic detection method and system for gray scale of section edge of silicon wafer
By employing a fully automated detection method, pre-set fixtures and multi-operator algorithms are used to process silicon wafer images, screen target contours, and analyze multi-dimensional grayscale features. This solves the error and accuracy problems of silicon wafer edge grayscale detection in existing technologies, and achieves high-precision automated detection and process evaluation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HAC GENERAL SEMITECH CO LTD
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-24
AI Technical Summary
Existing technologies lack fully automated, high-precision, and highly accurate methods for detecting grayscale at the edges of silicon wafers. Manual detection has large errors, while semi-automatic detection is complex and has poor adaptability, failing to meet the accuracy requirements for grayscale detection in the edge areas of silicon wafers.
The silicon wafer is fixed by a preset fixture. After the original detection image is acquired, it is scaled and pixel reduced. The edge detection and morphological closure processing are performed by combining a multi-operator algorithm to select target contours that meet the size characteristics of the silicon wafer. The passivation effect of the silicon wafer cut edge is analyzed. The process status is judged by comparing multi-dimensional grayscale features with the database.
It enables efficient and accurate automatic detection of grayscale at the edge of silicon wafers, reduces identification errors, improves edge continuity and detection success rate, and provides accurate assessment of process and equipment conditions.
Smart Images
Figure CN121921484A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon wafer edge detection technology, and in particular to a fully automated method and system for detecting the grayscale of silicon wafer cross-section edges. Background Technology
[0002] In the photovoltaic industry, to increase module power, a single solar cell is often cut into two or more sub-cells using methods such as laser cutting, forming a shingled solar cell. However, laser cutting causes laser damage and edge defects. These defects reduce the number of surface-excited charge carriers, leading to power loss and significantly negatively impacting the electrical performance of the solar cell. Passivation coating technology was developed to address this issue and repair these defects at the edges.
[0003] Photoluminescence (PL) testing is a technique that analyzes the physical, chemical, or structural properties of materials through their photoluminescence effect. The principle involves irradiating a sample with light of a specific wavelength (such as a laser). When the material absorbs photons, electrons transition to higher energy levels. Upon returning to lower energy levels, these electrons release energy and emit light—a phenomenon known as photoluminescence. By detecting the wavelength and intensity of the emitted light, information such as the material's band structure, defects, and composition can be inferred. In the photovoltaic industry, PL testing is primarily used in solar cells for detecting microcracks and defects, material quality assessment, passivation layer quality inspection, and cell efficiency distribution analysis.
[0004] Currently, the detection of edge passivation effect mainly relies on PL detection. The specific principle is that when the solar cell is irradiated by laser, photogenerated charge carriers (electron-hole pairs) diffuse in the material. If the edge passivation is good, the recombination rate of charge carriers after reaching the edge is low, the PL signal intensity in the edge region is close to that in the center region, and the light emission is uniform. If the passivation effect is poor, the charge carriers recombine rapidly at the edge, the PL signal in the edge region is significantly weakened, the light emission intensity is significantly reduced, and it appears as a dark ring or dark band in the image.
[0005] Currently, there are two methods for detecting the edge passivation effect of solar cells using PL (Plastic Prototype) detection: manual inspection and semi-automatic inspection. However, manual grayscale detection tools are not only labor-intensive and slow, but also prone to significant errors. These tools typically use horizontal-vertical quadrilateral bounding boxes to select regions, and even small angles of tilt on the silicon wafer can introduce errors that affect the grayscale detection results. Manually selecting irregular areas further increases the risk of errors due to inaccurate visual point selection. Semi-automatic grayscale detection methods, such as Canny edge detection, rely on contours and gradient-based approaches. These methods require manual threshold adjustment, are complex to operate, and have poor adaptability to complex scenarios. The Sobel / Prewitt operator method is sensitive to noise, has poor edge continuity, and has a low success rate for detecting complete contours. Furthermore, conventional image recognition technologies do not have high requirements for edge accuracy and cannot meet the needs of grayscale detection in silicon wafer edge areas. Summary of the Invention
[0006] Based on this, the purpose of this invention is to provide a fully automated method and system for detecting the grayscale of silicon wafer edges, aiming to solve the problem of the lack of a fully automated, high-precision and high-accuracy method for detecting the grayscale of silicon wafer edges in the prior art.
[0007] A fully automated method for detecting the grayscale of a silicon wafer cross-section edge according to an embodiment of the present invention includes: The silicon wafer is fixed by a preset fixture and the original inspection image of the silicon wafer is obtained; The original detection image is scaled and pixel-reduced by a preset ratio to obtain a first image, and then the first image is preprocessed to obtain a second image; Edge detection is performed on the second image to determine the edge image, morphological closure processing is performed on the edge image, and then the morphologically closed image contour is extracted to select the target contour that conforms to the silicon wafer size characteristics. The target contour is inversely mapped based on the preset ratio and matched with the original detection image to determine the target detection area in the original detection image, and the passivation effect of the silicon wafer cut edge is analyzed based on the target detection area.
[0008] In addition, the fully automated method for detecting the grayscale of a silicon wafer cross-section edge according to the above embodiments of the present invention may also have the following additional technical features: Furthermore, the step of preprocessing the first image to obtain the second image includes: The first image is converted into a first grayscale image, and the first grayscale image is denoised using a preset mask formula. The mask edges are then repaired to determine the second grayscale image. The second grayscale image is traversed through a preset sliding window to determine the mean and variance of grayscale values for each window. The parameters of the preset Gaussian blur are determined based on the range of the grayscale value variance to perform Gaussian blur processing on the second grayscale image to determine the second image.
[0009] Furthermore, the step of performing edge detection on the second image to determine edge images, and then performing morphological closure processing on the edge images, includes: performing parallel detection on the second image using a multi-operator algorithm to determine multiple edge maps, wherein the multi-operator algorithm includes at least the Cannibal operator, the Sobel operator, and the Laplacian operator; A fused edge map is obtained by fusing multiple edge maps. Then, an opening operation, consisting of dilation followed by erosion, is performed on the fused edge map to eliminate residual fine noise edges.
[0010] Further steps, including extracting the morphologically closed image contours and selecting target contours that match the silicon wafer size characteristics, include: Extract the morphologically closed image contours and determine the roundness of each image contour, and determine the contour with roundness within a preset range as the first contour; The first contour is fitted with a least-squares ellipse to determine the corresponding ellipse equation, and the silicon wafer tilt angle is determined according to the ellipse equation. The second contour is determined by rotating the first contour using a rotation matrix based on the silicon wafer tilt angle. The second contour is compared with the standard silicon wafer contour to determine the degree of difference. When the degree of difference is greater than a preset difference threshold, the second contour is filled with gaps to determine the target contour.
[0011] Furthermore, the step of analyzing the passivation effect of the silicon wafer cross-section edge based on the target detection area includes: The silicon wafer image before coating and the target detection area are divided into a central area and an edge area. The left and right edges of the edge area are further divided into multiple sub-partitions. The edge area is a region with a preset pixel width around the edge of the silicon wafer. Multidimensional grayscale features are calculated for the central region, the edge region, and the sub-region, respectively. The grayscale features include at least the grayscale mean, grayscale variance, grayscale difference between the edge and the center, local minimum, and grayscale gradient change rate. The passivation effect of the silicon wafer cut edge is determined based on the difference between the pre-coating silicon wafer image and the multidimensional grayscale features of the target detection area.
[0012] Furthermore, after the step of analyzing the passivation effect of the silicon wafer cross-section edge based on the target detection area, the method further includes: Retrieve the average multidimensional grayscale features of silicon wafers of the same model and batch from the database for a previously preset quantity, and calculate the first deviation between the current multidimensional grayscale features of the silicon wafer and the average multidimensional grayscale features of the silicon wafers in the database. Calculate the second deviation value between the current multidimensional grayscale characteristics of the silicon wafer and the mean of the multidimensional grayscale characteristics of adjacent silicon wafers in the same tray; The current process status and equipment status of the silicon wafer are determined based on the first deviation value and the second deviation value.
[0013] Furthermore, the preset fixture includes a flat plate, on which multiple silicon wafer slots of different sizes are arranged in an overlapping manner. Assembly holes are provided on both sides of the silicon wafer slots, and the assembly holes are used to avoid silicon wafer transfer clamping components.
[0014] Another object of the present invention is a fully automated detection system for the grayscale of silicon wafer cut edges, the system comprising: The image acquisition module is used to fix the silicon wafer with a preset fixture and acquire the original detection image of the silicon wafer; The image processing module is used to scale and reduce the pixel count of the original detection image by a preset ratio to obtain a first image, and then preprocess the first image to obtain a second image; The contour extraction module is used to perform edge detection on the second image to determine the edge image, perform morphological closure processing on the edge image, extract the image contour after morphological closure, and filter out the target contour that conforms to the silicon wafer size characteristics. An evaluation module is used to perform an inverse proportional mapping of the target contour based on the preset ratio and match it with the original detection image to determine the target detection region in the original detection image, and to analyze the passivation effect of the silicon wafer cut edge based on the target detection region.
[0015] Another objective of this invention is to provide a storage medium storing a computer program that, when executed by a processor, implements the steps of the fully automated detection method for the grayscale of silicon wafer cross-section edges described above.
[0016] Another objective of this invention is to provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the fully automated detection method for the grayscale of the silicon wafer cross-section edge described above.
[0017] This invention uses a pre-set clamp to fix and support the silicon wafer, reducing image deviations caused by the wafer moving beyond the detection area or varying laser intensity due to different wafer positions. Furthermore, by reducing the pixel count and proportionally shrinking the image size of the original detection image, noise is significantly reduced. The image is pre-processed to obtain the desired image after noise reduction filtering. Then, the target contour is determined based on ease of detection and morphological closure. This contour is then inversely enlarged to select the target detection area within the original detection image, thus completing edge determination. This results in a precisely identified target region on the image. This effectively solves the problems of recognition errors and insufficient edge continuity, achieving a very high recognition success rate. Finally, the image within the target region is analyzed, enabling efficient and accurate automatic analysis and detection of silicon wafer edges. Therefore, this invention solves the problem of the lack of a fully automatic, high-precision, and high-accuracy grayscale detection method for silicon wafer edges in existing technologies. Attached Figure Description
[0018] Figure 1 This is a flowchart of a fully automated method for detecting the grayscale of a silicon wafer cross-section edge according to the first embodiment of the present invention; Figure 2This is a schematic diagram of the results of the fully automated detection system for the grayscale of the silicon wafer cross-section edge in the second embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the electronic device in the third embodiment of the present invention; The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation
[0019] To facilitate understanding of the present invention, it will now be described more fully with reference to the accompanying drawings, which illustrate several embodiments of the invention. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the invention more thorough and complete.
[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0021] Example 1 Please see Figure 1 The figure shows a fully automatic detection method for the grayscale of the silicon wafer cut edge in the first embodiment of the present invention, the method specifically including steps S01-S04.
[0022] S01, the silicon wafer is fixed by a preset fixture and the original inspection image of the silicon wafer is obtained; Specifically, the preset fixture includes a flat plate with multiple overlapping silicon wafer slots of different sizes. Assembly holes are provided on both sides of each wafer slot to avoid interference with the silicon wafer transfer clamping components. In practice, a matching wafer slot is selected based on the model of the silicon wafer to be tested. A flexible silicone pad is placed at the bottom of the tray to reduce impact and displacement during wafer placement. The tray is then installed into the wafer placement chamber of the PL detector, ensuring alignment between the tray and the center of the laser irradiation area. The operator uses the mounting holes on the tray, along with the clamping components or their fingers, to smoothly place the silicon wafer to be tested into the corresponding slot. The PL detector is then started, and the testing parameters are set. The laser vertically irradiates the surface of the silicon wafer, stimulating its photoluminescence effect. The detector's built-in camera captures a PL image of the silicon wafer and saves the original image as input data for subsequent software processing.
[0023] S02, the original detection image is scaled and pixel-reduced by a preset ratio to obtain a first image, and then the first image is preprocessed to obtain a second image; Specifically, the first image is converted into a first grayscale image, and the first grayscale image is denoised using a preset mask formula, and the mask edges are repaired to determine a second grayscale image. A preset sliding window is used to traverse the second grayscale image to determine the grayscale mean and variance of each window. Based on the range of the grayscale variance, a preset Gaussian blur parameter is determined to perform Gaussian blur processing on the second grayscale image to determine the second image. In a specific implementation, after converting the first image into a first grayscale image, the first grayscale image is denoised using a binary mask formula generated based on PL image noise features to obtain a noise-filtered grayscale image. Then, the noise-filtered grayscale image is repaired using neighborhood linear interpolation to obtain the second image, which is more convenient than repairing broken pixels using a mask. The neighborhood linear interpolation formula is: N represents the number of neighborhoods, and its value is not less than 2. A 5x5 sliding window is then used to traverse the second grayscale image to calculate the grayscale mean and variance for each window. The Gaussian kernel size and standard deviation are assigned according to the variance range. Specifically, the rules are: a Gaussian kernel size of 3x3 with a variance not less than 50 and a standard deviation of 1.2; a Gaussian kernel size of 4x4 with a variance between 50 and 30 and a standard deviation of 1; and a Gaussian kernel size of 5x5 with a standard deviation of 0.8 with a variance less than 30. Then, a two-dimensional Gaussian blur is applied to each window according to the assigned parameters to obtain a smoothed image, i.e., the second image. The corresponding formula is:
[0024]
[0025] in, denoted as standard deviation, and k is the high-speed kernel size.
[0026] S03, perform edge detection on the second image to determine the edge image, perform morphological closure processing on the edge image, extract the image contour after morphological closure, and filter out the target contour that conforms to the silicon wafer size characteristics. Specifically, the second image is subjected to parallel detection using a multi-operator algorithm to determine multiple edge maps. The multi-operator algorithm includes at least the Cannibal operator, the Sobel operator, and the Laplacian operator. These multiple edge maps are then fused to obtain a fused edge map. Finally, the fused edge map undergoes an opening operation involving dilation followed by erosion to eliminate residual fine noise edges. In practice, a majority voting rule is used to select valid edges, which are then fused to obtain the fused edge map.
[0027] Furthermore, the morphologically closed image contours are extracted, and the roundness of each contour is determined. Contours with roundness within a preset range are designated as the first contour. Least-squares ellipse fitting is performed on the first contour to determine the corresponding ellipse equation, which is then used to determine the silicon wafer tilt angle. The first contour is rotated using a rotation matrix based on the silicon wafer tilt angle to determine the second contour. The second contour is compared with a standard silicon wafer contour to determine the difference. When the difference exceeds a preset difference threshold, the second contour is filled with gaps to determine the target contour. In practice, due to slight tilting of the silicon wafer on the tray, the directly extracted edge will be a tilted shape. If subsequent region segmentation and grayscale calculations are performed based on this tilted contour, the results will be inaccurate and cannot truly reflect the passivation quality of the silicon wafer. Furthermore, in actual inspection, PL images may have broken or uneven edges due to noise, uneven illumination, and other factors. The fitting algorithm has smoothing and anti-interference characteristics, capable of ignoring local edge defects and generating a complete, continuous, and smooth contour, which is crucial for ensuring the stability of all subsequent analyses. Therefore, contour correction can effectively avoid this defect and situation.
[0028] S04, the target contour is inversely mapped based on the preset ratio and matched with the original detection image to determine the target detection area in the original detection image, and the passivation effect of the silicon wafer cut edge is analyzed based on the target detection area.
[0029] Specifically, the pre-coating silicon wafer image and the target detection area are divided into a central region and an edge region. The left and right edges of the edge region are further divided into multiple sub-regions, each edge region being a region with a preset pixel width around the silicon wafer edge. Multidimensional grayscale features are calculated for the central region, the edge region, and the sub-regions. These grayscale features include at least the grayscale mean, grayscale variance, grayscale difference between the edge and center, local minimum, and grayscale gradient change rate. The passivation effect of the silicon wafer edge is determined based on the differences in the multidimensional grayscale features between the pre-coating silicon wafer image and the target detection area. By dividing the detection area and extracting and evaluating features from each divided area, a dual evaluation of macroscopic and microscopic aspects is achieved. This avoids the problem that a single overall analysis cannot detect "poor passivation in a certain segment of the edge," ensuring that the evaluation covers all key areas of the silicon wafer edge. Furthermore, the edge region is the core focus of the passivation process; its separate division allows for focused evaluation of the process effect. The central region serves as a "defect-free reference benchmark," providing a comparative basis for the edge passivation effect and avoiding the one-sidedness of a single-dimensional judgment. Furthermore, the design of subdivided small zones can directly reflect the local performance of the coating equipment, providing precise targets for process adjustments. Additionally, the use of multi-dimensional features for complementary verification from different dimensions results in higher evaluation accuracy compared to single mean analysis. Specifically, the proportion of local minimum values can directly quantify the degree of "local missed coating / defects," the gradient change rate can reflect the uniformity of the passivation layer thickness, solving the problem that traditional solutions cannot identify "hidden passivation defects" (such as thickness fluctuations), and "high grayscale mean but large variance" can be judged as "good overall passivation but local unevenness." Moreover, by comparing the same silicon wafer and the same location before and after coating, the interference of differences in the silicon wafer material itself is eliminated, accurately reflecting the improvement effect of the coating process on edge passivation.
[0030] Furthermore, after step S04, the method includes retrieving the average multidimensional grayscale features of a preset number of silicon wafers of the same model and batch from the database, and calculating a first deviation value between the current silicon wafer's multidimensional grayscale features and the average multidimensional grayscale features of silicon wafers in the database; calculating a second deviation value between the current silicon wafer's multidimensional grayscale features and the average multidimensional grayscale features of adjacent silicon wafers in the same tray; and determining the current silicon wafer's process status and equipment status based on the first and second deviation values. In practical implementation, by comparing time and space dimensions, hidden anomalies such as process fluctuations and equipment deviations can be accurately identified, avoiding misjudgments or omissions caused by relying solely on single silicon wafer data. Moreover, in practical implementation, based on quantitative features and machine learning models, the method can automatically identify anomaly types and provide confidence levels, replacing subjective human judgment, clarifying the root cause of anomalies, and providing direction for rapid processing.
[0031] In summary, the fully automated silicon wafer edge grayscale detection method in the above embodiments of the present invention uses a preset fixture to fix and support the silicon wafer, reducing image deviations caused by the silicon wafer moving beyond the detection area or varying laser intensities due to different wafer positions. Furthermore, by reducing the pixel count of the original detection image and proportionally reducing its size, noise is significantly reduced. The image is preprocessed to obtain the desired image after noise reduction and filtering. Then, the target contour is determined through easy detection and morphological closure. The target contour is then inversely enlarged to select the target detection area in the original detection image, thus completing edge determination. This results in a precisely identified target area on the image. This method effectively solves the problems of recognition errors and insufficient edge continuity, achieving a very high recognition success rate. Finally, the image within the target area is analyzed, achieving efficient and accurate automatic analysis and detection of silicon wafer edges. Therefore, the present invention solves the problem of the lack of a fully automated, high-precision, and highly accurate silicon wafer edge grayscale detection method in the prior art.
[0032] Example 2 Please see Figure 2 The diagram shows a structural block diagram of a fully automated silicon wafer edge grayscale detection system proposed in the second embodiment of the present invention. This fully automated silicon wafer edge grayscale detection system 200 includes: an image acquisition module 21, an image processing module 22, a contour extraction module 23, and an evaluation module 24, wherein: Image acquisition module 21 is used to fix the silicon wafer with a preset fixture and acquire the original detection image of the silicon wafer; Image processing module 22 is used to scale and reduce the pixel count of the original detection image by a preset ratio to obtain a first image, and then preprocess the first image to obtain a second image; The contour extraction module 23 is used to perform edge detection on the second image to determine the edge image, perform morphological closure processing on the edge image, extract the image contour after morphological closure, and filter out the target contour that conforms to the silicon wafer size characteristics. Evaluation module 24 is used to perform inverse proportional mapping of the target contour based on the preset ratio and match it with the original detection image to determine the target detection area in the original detection image, and analyze the passivation effect of the silicon wafer cut edge based on the target detection area.
[0033] Example 3 In another aspect, the present invention also proposes an electronic device, please refer to [link to relevant documentation]. Figure 3The diagram shows an electronic device according to the third embodiment of the present invention, including a memory 20, a processor 10, and a computer program 30 stored in the memory and executable on the processor. When the processor 10 executes the computer program 30, it implements the fully automatic detection method for the grayscale of the silicon wafer cut edge as described above.
[0034] In some embodiments, the processor 10 may be a central processing unit (CPU), controller, microcontroller, microprocessor or other data processing chip, used to run program code stored in memory 20 or process data, such as executing access restriction programs.
[0035] The memory 20 includes at least one type of readable storage medium, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 20 can be an internal storage unit of an electronic device, such as the hard disk of the electronic device. In other embodiments, the memory 20 can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. Furthermore, the memory 20 can include both internal and external storage units of the electronic device. The memory 20 can be used not only to store application software and various types of data of the electronic device, but also to temporarily store data that has been output or will be output.
[0036] It should be pointed out that, Figure 3 The structure shown does not constitute a limitation on the electronic device. In other embodiments, the electronic device may include fewer or more components than shown, or combine certain components, or have different component arrangements.
[0037] This invention also proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the fully automated detection method for the grayscale of silicon wafer cross-section edges as described above.
[0038] Those skilled in the art will understand that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.
[0039] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.
[0040] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0041] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0042] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.
Claims
1. A fully automated method for detecting the grayscale of a silicon wafer's cut edge, characterized in that, The method includes: The silicon wafer is fixed by a preset fixture and the original inspection image of the silicon wafer is obtained; The original detection image is scaled and pixel-reduced by a preset ratio to obtain a first image, and then the first image is preprocessed to obtain a second image; Edge detection is performed on the second image to determine the edge image, morphological closure processing is performed on the edge image, and then the image contour after morphological closure is extracted to select the target contour that conforms to the silicon wafer size characteristics. The target contour is inversely mapped based on the preset ratio and matched with the original detection image to determine the target detection area in the original detection image, and the passivation effect of the silicon wafer cut edge is analyzed based on the target detection area.
2. The fully automated method for detecting the grayscale of a silicon wafer's cut edge according to claim 1, characterized in that, The steps for preprocessing the first image to obtain the second image include: The first image is converted into a first grayscale image, and the first grayscale image is denoised using a preset mask formula. The mask edges are then repaired to determine the second grayscale image. The second grayscale image is traversed through a preset sliding window to determine the mean and variance of grayscale values for each window. The parameters of the preset Gaussian blur are determined based on the range of the grayscale value variance to perform Gaussian blur processing on the second grayscale image to determine the second image.
3. The fully automated method for detecting the grayscale of a silicon wafer's cross-section edge according to claim 2, characterized in that, The step of performing edge detection on the second image to determine edge images, and then performing morphological closure processing on the edge images, includes: performing parallel detection on the second image using a multi-operator algorithm to determine multiple edge images, wherein the multi-operator algorithm includes at least the Cannibal operator, the Sobel operator, and the Laplacian operator; A fused edge map is obtained by fusing multiple edge maps. Then, an opening operation, consisting of dilation followed by erosion, is performed on the fused edge map to eliminate residual fine noise edges.
4. The fully automated method for detecting the grayscale of a silicon wafer's cross-section edge according to claim 3, characterized in that, The steps for extracting the morphologically closed image contours and selecting target contours that match the size characteristics of the silicon wafer include: Extract the morphologically closed image contours and determine the roundness of each image contour, and determine the contour with roundness within a preset range as the first contour; The first contour is fitted with a least-squares ellipse to determine the corresponding ellipse equation, and the silicon wafer tilt angle is determined according to the ellipse equation. The second contour is determined by rotating the first contour using a rotation matrix based on the silicon wafer tilt angle. The second contour is compared with the standard silicon wafer contour to determine the degree of difference. When the degree of difference is greater than a preset difference threshold, the second contour is filled with gaps to determine the target contour.
5. The fully automated method for detecting the grayscale of a silicon wafer's cut edge according to claim 1, characterized in that, The steps for analyzing the passivation effect of the silicon wafer cross-section edge based on the target detection area include: The silicon wafer image before coating and the target detection area are divided into a central area and an edge area. The left and right edges of the edge area are further divided into multiple sub-partitions. The edge area is a region with a preset pixel width around the edge of the silicon wafer. Multidimensional grayscale features are calculated for the central region, the edge region, and the sub-region, respectively. The grayscale features include at least the grayscale mean, grayscale variance, grayscale difference between the edge and the center, local minimum, and grayscale gradient change rate. The passivation effect of the silicon wafer cut edge is determined based on the difference between the pre-coating silicon wafer image and the multidimensional grayscale features of the target detection area.
6. The fully automated method for detecting the grayscale of a silicon wafer's cut edge according to claim 5, characterized in that, Following the step of analyzing the passivation effect of the silicon wafer cut edge based on the target detection area, the method further includes: Retrieve the average multidimensional grayscale features of silicon wafers of the same model and batch from the database for a previously preset quantity, and calculate the first deviation between the current multidimensional grayscale features of the silicon wafer and the average multidimensional grayscale features of the silicon wafers in the database. Calculate the second deviation value between the current multidimensional grayscale characteristics of the silicon wafer and the mean of the multidimensional grayscale characteristics of adjacent silicon wafers in the same tray; The current process status and equipment status of the silicon wafer are determined based on the first deviation value and the second deviation value.
7. The fully automated method for detecting the grayscale of a silicon wafer's cross-section edge according to claim 6, characterized in that, The preset fixture includes a flat plate with multiple overlapping silicon wafer slots of different sizes. The silicon wafer slots have assembly holes on both sides to avoid silicon wafer transfer clamping components.
8. A fully automated detection system for the grayscale of a silicon wafer's cut edge, characterized in that, The system is used to implement a fully automated method for detecting the grayscale of silicon wafer cross-section edges as described in any one of claims 1 to 7, the system comprising: The image acquisition module is used to fix the silicon wafer with a preset fixture and acquire the original detection image of the silicon wafer; The image processing module is used to scale and reduce the pixel count of the original detection image by a preset ratio to obtain a first image, and then preprocess the first image to obtain a second image; The contour extraction module is used to perform edge detection on the second image to determine the edge image, perform morphological closure processing on the edge image, extract the image contour after morphological closure, and filter out the target contour that conforms to the silicon wafer size characteristics. An evaluation module is used to perform an inverse proportional mapping of the target contour based on the preset ratio and match it with the original detection image to determine the target detection region in the original detection image, and to analyze the passivation effect of the silicon wafer cut edge based on the target detection region.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the fully automatic detection method for the grayscale of the silicon wafer cross-section edge as described in any one of claims 1 to 7.
10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a fully automated method for detecting the grayscale of a silicon wafer cross-section edge as described in any one of claims 1-7.