Driving circuit and display device

Abstract

The invention discloses a driving circuit and a display device. The display device includes: a display panel including pixels; a light emitting diode in the pixel and a plurality of transistors electrically connected to the light emitting diode; and a gate driving circuit including a stage outputting a gate signal to one of the plurality of transistors, in which the stage includes: a pull-up transistor and a pull-down transistor, a gate of the pull-up transistor and a gate of the pull-down transistor being connected to a Q node and a QB node, respectively; a transfer transistor connected between the Q node and the Q2 node; and a reset circuit connected to the Q node or the Q2 node, wherein the reset circuit includes: an N-type reset transistor receiving a gate high voltage; and a P-type auxiliary transistor connected between the N-type reset transistor and the Q node or the Q2 node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0146487, filed on October 24, 2024, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This invention relates to a driving circuit and a display device. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms, and in recent years, various flat panel display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), have been used.

[0005] The gate drive circuit of an organic light-emitting display device is equipped with a reset transistor for reset operations. However, off-leakage current may occur through the reset transistor.

[0006] If a cutoff leakage current occurs through the reset transistor, the voltage of the nodes in the gate drive circuit will not be maintained properly, which leads to a malfunction in the gate drive circuit. Summary of the Invention

[0007] The advantage of this invention is that it provides a driving circuit and a display device that can prevent the cutoff leakage current of the reset transistor of the gate driving circuit, thereby stably maintaining the voltage of the nodes in the gate driving circuit and thus preventing failure of the gate driving circuit.

[0008] Additional features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and obtained by means of the structures specifically pointed out in the written description, the claims, and the drawings.

[0009] To achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described herein, a display device includes: a display panel comprising pixels; light-emitting diodes in the pixels and a plurality of transistors electrically connected to the light-emitting diodes; and a gate driving circuit comprising a stage for outputting a gate signal to one of the plurality of transistors, wherein the stage includes: a pull-up transistor and a pull-down transistor, the gates of the pull-up transistor and the pull-down transistor being connected to a Q node and a QB node, respectively; a transfer transistor connected between the Q node and a Q2 node; and a reset circuit connected to the Q node or the Q2 node, wherein the reset circuit includes: an N-type reset transistor receiving a gate high voltage; and a P-type auxiliary transistor connected between the N-type reset transistor and the Q node or the Q2 node.

[0010] In another aspect, a driving circuit includes: a transistor having a source or drain connected to a node; and a reset circuit connected to the node, wherein the reset circuit includes: an N-type reset transistor receiving a gate high voltage; and a P-type auxiliary transistor connected between the N-type reset transistor and the node.

[0011] In another aspect, a driving circuit includes: an output section; and a control section configured to control the output operation of the output section, wherein the output section includes a pull-up transistor and a pull-down transistor, the gates of the pull-up transistor and the pull-down transistor being connected to a Q node and a QB node, respectively; wherein the control section includes a reset circuit, the reset circuit including: an N-type reset transistor configured to receive a gate high voltage; and a P-type auxiliary transistor connected between the N-type reset transistor and the Q node or Q2 node.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0014] Figure 1 This is a schematic view illustrating a display device according to a first embodiment of the present invention;

[0015] Figure 2 This is a circuit diagram schematically illustrating an example of a pixel according to a first embodiment of the present invention;

[0016] Figure 3 This is a view showing the configuration of the gate driving section of a display device according to a first embodiment of the present invention;

[0017] Figure 4 and Figure 5 This is a timing diagram schematically showing an example of a drive signal output from a gate drive unit according to a first embodiment of the present invention;

[0018] Figure 6 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first embodiment of the present invention;

[0019] Figure 7 This is a schematic view showing the structure of a reset circuit according to a first embodiment of the present invention;

[0020] Figure 8 and Figure 9 This is a schematic view illustrating the operation of the reset circuit according to a first embodiment of the present invention;

[0021] Figure 10 It is an illustrative representation of the application. Figure 7 A view illustrating the structure of a reset circuit's scan drive circuit;

[0022] Figure 11 This is a view schematically illustrating a structural example of a scan drive circuit employing a reset circuit according to a second embodiment of the present invention;

[0023] Figure 12 This is a view schematically illustrating a first example of the structure of a scan drive circuit employing a reset circuit according to a third embodiment of the present invention;

[0024] Figure 13 This is a view schematically illustrating a second example of the structure of a scan drive circuit employing a reset circuit according to a third embodiment of the present invention;

[0025] Figure 14 This is a view schematically illustrating a first example of the structure of a scan drive circuit employing a reset circuit according to a fourth embodiment of the present invention;

[0026] Figure 15 This is a view schematically illustrating a second example of the structure of a scan drive circuit employing a reset circuit according to a fourth embodiment of the present invention;

[0027] Figure 16 This is a view schematically illustrating a first example of the structure of a scan drive circuit employing a reset circuit according to a fifth embodiment of the present invention;

[0028] Figure 17 This is a view schematically illustrating a second example of the structure of a scan drive circuit employing a reset circuit according to a fifth embodiment of the present invention. Detailed Implementation

[0029] By referring to the following and appendix Figure 1 The advantages, features, and implementation methods of the present invention will become clear from the detailed description of the embodiments described below. However, the present invention is not limited to the embodiments described below, but can be implemented in various different forms. These embodiments are provided only to ensure the completeness of the scope of the present invention. The disclosure of the present invention is provided to fully convey the scope of the invention to those skilled in the art, and the invention may be defined by the scope of the claims.

[0030] The shapes, dimensions, proportions, angles, quantities, etc., disclosed in the accompanying drawings, which are used to explain embodiments of the present invention, are exemplary, and the present invention is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same components.

[0031] Furthermore, in describing this invention, detailed descriptions of relevant known technologies may be omitted if it is determined that such detailed descriptions would unnecessarily obscure the subject matter of the invention. Where terms such as "comprising," "having," "including," and "containing" are used in this invention, other parts may be added unless "only" is used. When a component is referred to in the singular, it includes the case where it comprises a plural, unless otherwise specified.

[0032] When interpreting components, even without a separate explicit description, components are interpreted as including a margin range.

[0033] When describing positional relationships, such as when the positional relationship between two parts is described as "on," "above," "upper," "lower," "next to," "below," etc., one or more other parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0034] In describing temporal relationships, such as when the chronological order is described as "after," "following," "before," etc., discontinuous situations may be included unless "directly" or "immediately" is used.

[0035] When describing the components of the present invention, terms such as first, second, etc., may be used. These terms are only used to distinguish the components from other components, and the substance, order, sequence, or number of the components are not limited by these terms.

[0036] The corresponding features of various embodiments of the present invention may be partially or completely connected or combined with each other, and may be technically interlocked and driven in various ways. The corresponding embodiments may be implemented independently of each other, or may be implemented together in an associated relationship.

[0037] In the following description, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in the following embodiments, the same and similar reference numerals are assigned to the same and similar components, and their detailed descriptions may be omitted.

[0038] <First Implementation>

[0039] Figure 1 This is a schematic view of a display device according to a first embodiment of the present invention. Figure 2 This is a circuit diagram schematically illustrating an example of a pixel according to a first embodiment of the present invention. Figure 3 This is a view showing the configuration of the gate driving section of a display device according to a first embodiment of the present invention. Figure 4 and Figure 5 This is a timing diagram schematically illustrating an example of a drive signal output from a gate drive unit according to a first embodiment of the present invention. Figure 4 The diagram shows the drive signal output during frame refresh in the VRR method of the first embodiment of the present invention. Figure 5 The driving signal output during frame skipping is shown in the VRR method of the first embodiment of the present invention.

[0040] Before going into detail, the display device 10 according to this embodiment may include a light-emitting display device equipped with light-emitting diodes. Furthermore, the display device 10 of this embodiment may include all types of display devices that apply the VRR (Variable Refresh Rate) method.

[0041] For ease of explanation, in this embodiment, the organic light-emitting display device is described as an example of the display device 10.

[0042] Reference Figures 1 to 5 The display device 10 of this embodiment may include a display panel 100 and a driving circuit section for driving the display panel 100.

[0043] Here, the driving circuit section may include, for example, a gate driving section (or gate driving circuit) 210, a data driving section (or data driving circuit) 220, and a timing control section (or timing control circuit) 240. Furthermore, the driving circuit section may include a power supply section (or power supply circuit) 280, which provides the power required to drive the display panel 100, the gate driving section 210, the data driving section 220, and the timing control section 240.

[0044] The display panel 100 may include a display area AA for displaying images and a non-display area NA arranged outside (or around) the display area AA.

[0045] In the display area AA, multiple pixels P can be arranged in a matrix along multiple horizontal lines (or row lines) and multiple vertical lines (or column lines).

[0046] Here, the multiple pixels P may include pixels that display different colors, such as red pixels, green pixels, and blue pixels that display red, green, and blue respectively, but are not limited to this.

[0047] In the display panel 100, various signal lines for transmitting drive signals for driving pixels P can be formed on the substrate.

[0048] In this regard, for example, multiple data lines DL that transmit data signals (or data voltages) as image signals can extend in the vertical direction and be connected to the corresponding vertical pixel P.

[0049] In addition, the gate line GL that transmits the gate signal (or gate voltage) can extend in the horizontal direction and be connected to the pixel P of the corresponding horizontal line.

[0050] In this embodiment, multiple gate signals can be used to drive each pixel P. For example, first scan signals SC1 to fourth scan signals SC4 and light emission control signal EM can be used. Therefore, multiple gate lines GL can be used to transmit multiple gate signals respectively. For example, first to fourth scan lines SCL1 to SCL4 and light emission control line EML can be used.

[0051] Thus, multiple pixels P can be defined by multiple intersecting data lines DL and gate lines GL.

[0052] Each pixel P may include: a light-emitting diode OD as a light-emitting element; and a plurality of transistors and at least one capacitor for driving the light-emitting diode OD.

[0053] In this embodiment, for ease of explanation, an 8T1C structure is used as an example, where pixel P is equipped with eight transistors T1 to T7 and DT, and a capacitor Cst, as shown below. Figure 2 As shown.

[0054] Reference Figure 2 Pixel P may include multiple switching transistors, such as first transistor T1 to seventh transistor T7, driving transistor DT, storage capacitor Cst, and light-emitting diode OD.

[0055] Each of the first transistor T1 through the seventh transistor T7 and the driving transistor DT may include a first electrode, a second electrode, and a gate. One of the first electrode and the second electrode may be a source, and the other of the first electrode and the second electrode may be a drain.

[0056] Each of the first transistor T1 through the seventh transistor T7 and the driving transistor DT can be a P-type or N-type transistor. Meanwhile, in Figure 2 In this configuration, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are configured as P-type transistors, the first transistor T1 and the seventh transistor T7 are configured as N-type transistors, and the driving transistor DT is configured as a P-type transistor, but is not limited thereto. Optionally, the driving transistor DT may be configured as an N-type transistor.

[0057] The first transistors T1 through T7 and the driving transistor DT may comprise semiconductors of the same material or semiconductors of different materials. For example, some of the first transistors T1 through T7 and the driving transistor DT may have a semiconductor layer selected from polycrystalline silicon, an oxide semiconductor layer, and an amorphous silicon layer, while others of the first transistors T1 through T7 and the driving transistor DT may have other semiconductor layers selected from polycrystalline silicon, oxide semiconductor, and amorphous silicon.

[0058] Meanwhile, since oxide semiconductors have excellent cutoff current characteristics and properties suitable for switching transistors, at least one of the first transistors T1 to the seventh transistor T7 may have an oxide semiconductor layer. Furthermore, since polysilicon has excellent mobility, the driving transistor DT may have a polysilicon layer. The first transistors T1 to the seventh transistor T7 and the driving transistor DT may be configured in other ways; for example, the driving transistor DT may have an oxide semiconductor layer.

[0059] Meanwhile, in this embodiment, the case in which the first transistor T1 and the seventh transistor T7 include an oxide semiconductor layer and the remaining transistors T2 to T6 and DT include a polysilicon layer is used as an example.

[0060] Provided to Figure 2The gate signal for the nth horizontal line (more specifically, at least one of the odd and even horizontal lines constituting the nth horizontal line) can be provided from the corresponding nth stage of the gate driving unit 210. For example, four scan signals can be provided, namely, the first to fourth scan signals (SC1 to SC4: SC1(n) to SC4(n)) and two light emission control signals, namely, the first and second light emission control signals (EM: EM1(n) and EM2(n)). In this case, in the display area AA, the first to fourth scan signals SC1(n) to SC4(n) and the first and second light emission control signals EM1(n) and EM2(n) can be connected to the nth stage and transmit to the first to fourth scan lines SCL1 to SCL4 and the first and second light emission control lines EML1 and EML2 of the pixel P. Optionally, the gate driving unit 210 can be configured to provide one light emission control signal instead of two light emission control signals EM1(n) and EM2(n).

[0061] The first transistor T1 can be used as a sampling transistor, the second transistor T2 can be used as a data providing transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, the fifth transistor T5 can be used as a bias transistor, the sixth transistor T6 can be used as a reset transistor (or the first initialization transistor), and the seventh transistor T7 can be used as an initialization transistor (or the second initialization transistor).

[0062] A light-emitting diode (LED) OD may include an anode and a cathode. The anode of the LED OD may be connected to the fifth node N5, and the cathode of the LED OD may be subjected to a low-potential drive voltage EVSS.

[0063] The driving transistor DT may include a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a gate connected to a first node N1. The driving transistor DT can provide a driving current to the light-emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0064] The first transistor T1 may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate for receiving a first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n), and a data voltage Vdata may be applied (or written or sampled) to the gate of the driving transistor DT.

[0065] The storage capacitor Cst can be connected between the first node N1 and the fourth node N4. The storage capacitor Cst can store or hold the high-potential drive voltage EVDD.

[0066] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate for receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and transmit the data voltage Vdata to the second node N2.

[0067] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) can be connected between the power supply line of the high-potential drive voltage EVDD and the light-emitting diode OD, and can form a current path along which the drive current generated by the drive transistor DT moves.

[0068] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving a high-potential drive voltage EVDD, a second electrode connected to the second node N2, and a gate receiving a first light-emitting control signal EM1(n).

[0069] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting diode OD), and a gate for receiving the second light-emitting control signal EM2(n).

[0070] The third transistor T3 and the fourth transistor T4 can be turned on in response to the first light emission control signal EM1(n) and the second light emission control signal EM2(n), and the driving current can be provided to the light emission diode OD, and the light emission diode OD can emit light with a brightness corresponding to the driving current.

[0071] The fifth transistor T5 may include a first electrode connected to the bias voltage line VobsL that transmits the bias voltage Vobs, a second electrode connected to the second node N2, and a gate that receives the third scan signal SC3(n).

[0072] The sixth transistor T6 may include a first electrode connected to a reset voltage line (or first initialization voltage line) VarL that transmits the anode reset voltage (or first initialization voltage) Var, a second electrode connected to the fifth node N5, and a gate that receives the third scan signal SC3(n).

[0073] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the third scan signal SC3(n), the bias voltage Vobs can be applied to the second node N2, and the anode reset voltage Var can be applied to the fifth node N5 (i.e., the anode of the light-emitting diode OD).

[0074] The seventh transistor T7 may include a first electrode connected to the initialization voltage line ViniL that transmits the initialization voltage Vini, a second electrode connected to the first node N1, and a gate that receives the fourth scan signal SC4(n).

[0075] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4(n), and an initialization voltage Vini can be applied to initialize the gate of the drive transistor DT. Due to the high-potential drive voltage EVDD applied to the storage capacitor Cst, unwanted charge may remain in the gate of the drive transistor DT. Therefore, by applying the initialization voltage Vini to the gate of the drive transistor DT via the seventh transistor T7, the residual charge can be initialized.

[0076] The 8T1C structure of pixel P described above is an example; pixel P in this embodiment can be configured with different structures.

[0077] Reference Figure 1 The timing control unit 240 processes the image data Do input from the host system to fit the size and resolution of the display panel 100, and provides it to the data driving unit 220. The timing control unit 240 can use synchronization signals input from the host system (e.g., dot clock signal CLK, data enable signal DE, horizontal synchronization signal HSY, and vertical synchronization signal VSY) to generate a gate control signal GCS and a data control signal DCS. By providing the gate control signal GCS and the data control signal DCS generated in this manner to the gate driving unit 210 and the data driving unit 220 respectively, the gate driving unit 210 and the data driving unit 220 can be controlled.

[0078] Depending on the device to be installed, the timing control unit 240 can be configured to be combined with various processors (e.g., microprocessors, mobile processors, application processors, etc.).

[0079] Meanwhile, the host system can be, for example, a driving system for an electronic device that drives the application display device 10. The electronic device can be, for example, a TV, a navigation system, a display, a mobile device, or a wearable device.

[0080] The gate driving unit 210 can receive the gate control signal GCS from the timing control unit 240, generate a gate signal, and sequentially apply the gate signal to the gate line GL. For example, the gate signal can be output sequentially from top to bottom in the vertical direction.

[0081] The gate driving portion 210 may be arranged on at least one side of, for example, the display area AA. In this embodiment, an example is adopted in which the gate driving portion 210 is configured to include a first gate driving portion 211 and a second gate driving portion 212 arranged on both sides of the display area AA (e.g., on the left and right sides of the display area AA).

[0082] The gate driving portion 210 can be formed directly in the non-display area NA on the substrate of the display panel 100, for example, according to a GIP (gate in panel) structure. In this case, the gate driving portion 210 can be formed during the process of forming the elements of the display panel 100.

[0083] The gate drive unit 210 configured with a GIP structure may include, for example, a first scan drive circuit that sequentially outputs a first scan signal SC1, a second scan drive circuit that sequentially outputs a second scan signal SC2, a third scan drive circuit that sequentially outputs a third scan signal SC3, a fourth scan drive circuit that sequentially outputs a fourth scan signal SC4, a first light-emitting drive circuit that sequentially outputs a first light-emitting control signal EM1, and a second light-emitting drive circuit that sequentially outputs a second light-emitting control signal EM2.

[0084] Each of the first to fourth scan drive circuits and the first and second light-emitting drive circuits may be configured with a shift register comprising multiple stages for outputting corresponding signals. The gate drive unit 210 may include a stage for outputting a gate signal to one of a plurality of transistors electrically connected to the light-emitting diode OD.

[0085] Further reference Figure 3 The gate drive section 210 is described. Figure 3 A portion of the gate driving section 210 is shown, and for ease of explanation, a portion of the gate driving section 210 is shown that drives the display area AA and has an nth horizontal line with an nth odd horizontal line (or a 2n-1th horizontal line) and an nth even horizontal line (or a 2nth horizontal line).

[0086] In the first gate driving section 211 of the gate driving section 210, for example, the following may be arranged: a first scan level SSC1(n), a third scan level SSC3(n), and a fourth scan level SSC4(n) that respectively constitute a first scan driving circuit, a third scan driving circuit, and a fourth scan driving circuit; a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) that respectively constitute a first light-emitting driving circuit and a second light-emitting driving circuit; and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute a second scan driving circuit.

[0087] Furthermore, in the second gate driving section 212 of the gate driving section 210, for example, the following may be arranged: a first scan level SSC1(n), a third scan level SSC3(n), and a fourth scan level SSC4(n) that respectively constitute the first scan driving circuit, the third scan driving circuit, and the fourth scan driving circuit; a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) that respectively constitute the first light-emitting driving circuit and the second light-emitting driving circuit; and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute the second scan driving circuit.

[0088] In the gate driving section 210, the odd-numbered second scan levels SSC2_O(n) and even-numbered second scan levels SSC2_E(n) constituting the second scan driving circuit can be arranged closest to the display area AA, and the second light-emitting level SEM2(n) can be arranged at the outermost part furthest from the display area AA. Furthermore, the first light-emitting level SEM1(n) can be arranged between the first to fourth scan levels SSC1(n) to SSC4(n).

[0089] Figure 3 The arrangement of the first scan level SSC1(n) to the fourth scan level SSC4(n), the first light-emitting level SEM1(n), and the second light-emitting level SEM2(n) shown is an example, and they can be arranged in various combinations in the first gate driving section 211 and the second gate driving section 212.

[0090] The first scan level SSC1(n) can generate a first scan signal SC1(n) and output it to the corresponding first scan line SCL1. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the first scan signal SC1(n).

[0091] The odd-numbered second scan level SSC2_O(n) generates an odd-numbered second scan signal SC2_O(n) and outputs it to the corresponding odd-numbered second scan line SCL2, while the even-numbered second scan level SSC2_E(n) generates an even-numbered second scan signal SC2_E(n) and outputs it to the corresponding even-numbered second scan line SCL2. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line can be given the odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) of the nth even-numbered horizontal line can be given the even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signals SC2_O(n) and SC2_E(n) can have different timing sequences. For example, the odd-numbered second scan signals SC2_O(n) and SC2_E(n) can be applied to the data write period of the nth odd-numbered horizontal line and the immediately following data write period of the nth even-numbered horizontal line, respectively.

[0092] The third scan level SSC3(n) generates a third scan signal SC3(n) and outputs it to the corresponding third scan line SCL3. Therefore, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can be jointly subjected to the third scan signal SC3(n).

[0093] The fourth scan level SSC4(n) generates the fourth scan signal SC4(n) and outputs it to the corresponding fourth scan line SCL4. Therefore, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can be jointly subjected to the fourth scan signal SC4(n).

[0094] The first luminous level SEM1(n) can generate a first luminous control signal EM1(n) and output it to the corresponding first luminous control line EML1. Therefore, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can be jointly subjected to the first luminous control signal EM1(n).

[0095] The second luminous level SEM2(n) can generate a second luminous control signal EM2(n) and output it to the corresponding second luminous control line EML2. Therefore, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can be jointly subjected to the second luminous control signal EM2(n).

[0096] At the same time, refer to Figure 3 The bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can be arranged between the gate driving section 210 and the display area AA.

[0097] The bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can respectively supply the bias voltage Vobs, the anode reset voltage Var, and the initialization voltage Vini from the power supply unit 280 to the pixel P in the display area AA.

[0098] exist Figure 3 In the diagram, each of the bias voltage line VobsL, reset voltage line VarL, and initialization voltage line ViniL is shown as being located only on the left or right side of the display area AA, but is not limited thereto. Each of the bias voltage line VobL, reset voltage line VarL, and initialization voltage line ViniL may be located on both sides, and even if located on one side, the position on the left or right is not restricted.

[0099] In addition, refer to Figure 3 One or more optical zones OA1 and OA2 can be set in the display zone AA.

[0100] One or more optical zones OA1 and OA2 may be arranged to overlap with one or more optoelectronic devices (e.g., imaging devices such as cameras (or image sensors) and / or detection sensors such as proximity sensors and illuminance sensors). For the operation of the optoelectronic devices, one or more optical zones OA1 and OA2 may have light-transmitting structures formed therein and may have a certain level or higher transmittance. In other words, the number of pixels P per unit area in one or more optical zones OA1 and OA2 may be less than the number of pixels P per unit area in the regular region of the display area AA, excluding the optical zones OA1 and OA2. That is, the resolution of one or more optical zones OA1 and OA2 may be lower than the resolution of the regular region within the display area AA.

[0101] Return to reference Figure 1 The data driving unit 220 can receive image data Do and data control signal DCS from the timing control unit 240, and in response to the data control signal DCS, the data driving unit 220 can convert the image data Do into analog image data, i.e., data voltage Vdata, and output it to the corresponding data line DL.

[0102] The power supply unit 280 can use, for example, a DC-DC converter to generate the DC power required to drive the pixel array and drive circuitry of the display panel 100. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc.

[0103] The power supply unit 280 can receive, for example, a power supply voltage Vcc from the host system as a driving voltage for driving the display device 10, and generate DC voltages, such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, high-level driving voltage EVDD, and low-level driving voltage EVSS. Gate low voltages VGL and VEL, as well as gate high voltages VGH and VEH, can be provided to the gate driving unit 210. The high-level driving voltage EVDD and the low-level driving voltage EVSS can be jointly provided to the pixels P in the display panel 100.

[0104] The VRR method, which can be adjusted according to the refresh cycle (or refresh rate), drives the display device 10 of this embodiment configured as described above with low power in order to reduce power consumption.

[0105] In this regard, in the normal driving mode, which is a high-speed driving mode, the display device 10 can operate to refresh (or update) the image of the display panel 100 (or the data voltage Vdata applied to each pixel P) according to frame FR. For example, in the high-speed driving mode, the display device 10 can be driven at a refresh rate of 120Hz, thereby performing a refresh operation of 120 frames FR per second. In this way, in the high-speed driving mode, all frames FR can be assigned as refresh frames FRr in which the data voltage Vdata is written.

[0106] When displaying still images, the display device 10 can be driven in a low-speed drive mode. In the low-speed drive mode, the refresh rate is reduced, resulting in a longer refresh cycle for the display panel 100. For example, in the case of low-speed drive with a refresh rate of 10Hz, one refresh frame FRr and 11 consecutive skip frames FRs can be repeated alternately. Thus, in the low-speed drive mode, the frame FR can be divided into a refresh frame FRr in which data voltage Vdata is written and skip frames FRs in which no data voltage Vdata is written and the writing is skipped.

[0107] Therefore, in low-speed drive mode, as the drive frequency decreases, the period of refresh frame FRr (or the interval between refresh frames FRr) becomes longer, and one or more skip frames FRs exist between refresh frames FRr.

[0108] During frame skipping (FRs), image refresh operations are stopped, thereby reducing power consumption.

[0109] In the refresh frame FRr for writing the data voltage Vdata, the first scan signal SC1 to the fourth scan signal SC4 (more specifically, their scan pulses) can be applied during the non-light-emitting period to write the data voltage Vdata to the corresponding pixel P.

[0110] Furthermore, in skip frames FRs where the data voltage Vdata is not written but is maintained, operations can be performed to apply a bias voltage Vobs to mitigate the hysteresis of the drive transistor DT and to apply an anode reset voltage Var to reset the anode of the light-emitting diode OD. For this purpose, a third scan signal SC3 (more specifically, its scan pulse) can be applied to provide the bias voltage Vobs and the anode reset voltage Var to the pixel P.

[0111] Further reference is available. Figure 4 and Figure 5 This describes the driver in the refresh frame FRr and skip frame FRs of the VRR method.

[0112] At the same time, Figure 4 and Figure 5For ease of explanation, the first light emission control signal EM1(n) and the second light emission control signal EM2(n) are not shown separately, but rather a single light emission control signal EM(n) representing them is shown as an example.

[0113] First, refer to Figure 4 This describes the driving mechanism in the refresh frame FRr. The refresh frame FRr can be divided into a non-emitting period Tne and an emitting period Te. The non-emitting period Tne of the refresh frame FRr can be referred to as the first non-emitting period Tne1, and the emitting period Te of the refresh frame FRr can be referred to as the first emitting period Te1.

[0114] The first non-emitting period Tne1 and the first emitting period Te1 can be defined by the emitting control signal EM(n) of the refresh frame FRr. In this regard, the high level (as a cutoff level) of the emitting control signal EM(n) corresponds to the first non-emitting period Tne1, and the low level (as a conduction level) of the emitting control signal EM(n) corresponds to the first emitting period Te1.

[0115] During the first non-light-emitting period Tne1 of the refresh frame FRr, the operation of applying and writing data voltage Vdata can be performed.

[0116] In this regard, for example, during the data writing period (or sampling period) Tw when a low-level (as an on-state) scan pulse is applied to each of the odd-numbered second scan signals SC2_O(n) and even-numbered second scan signals SC2_E(n), and more specifically, during the data writing period (or sampling period) Tw when a low-level (as an on-state) scan pulse is applied to each of the odd-numbered second scan signals SC2_O(n) and even-numbered second scan signals SC2_E(n), the data voltage Vdata of each of the odd-numbered pixels P_O(n) and even-numbered pixels P_E(n) can be applied and written to the gate of the driving transistor DT. Simultaneously, during the data writing period Tw, the threshold voltage of the driving transistor DT can be sampled and reflected in the gate of the driving transistor DT.

[0117] During the data writing period Tw, the first scan signal SC1(n) may have a high-level scan pulse as the turn-on level, so that the first transistor T1 may be in the turn-on state.

[0118] Simultaneously, at least one bias period (or anode reset period) Tobs when the bias voltage Vobs and the anode reset voltage Var are applied can be located within the first non-light-emitting period Tne1. In this embodiment, the case where the bias periods Tobs are set before and after the data writing period Tw is used as an example. In this case, for ease of explanation, the bias periods Tobs set before data writing can be referred to as the first bias period Tobs1, and the bias periods Tobs set after data writing can be referred to as the second bias period Tobs2.

[0119] In each of the first and second bias periods Tobs1 and Tobs2, the third scan signal SC3(n) may have a scan pulse at a low level as the on level.

[0120] In this scenario, the fifth transistor T5 can be turned on, allowing a bias voltage Vobs to be applied to the second node N2 and the third node N3. This enables the conduction bias stress operation used to drive the transistor DT.

[0121] Furthermore, the sixth transistor T6 can be turned on, allowing the anode reset voltage Var to be applied to the fifth node N5. This enables the anode reset operation for the anode of the light-emitting diode OD to be performed.

[0122] Simultaneously, the application of the initialization voltage Vini can be performed between the data writing period Tw and the first bias period Tobs1. During this initialization period Ti, the fourth scan signal SC4(n) can have a high-level scan pulse as the turn-on level. Therefore, the seventh transistor T7 can be turned on, allowing the initialization voltage Vini to be applied to the first node N1, i.e., the gate of the driving transistor DT. Thus, the initialization operation for driving transistor DT can be performed.

[0123] Next, refer to Figure 5 This describes the driving mechanism in frame skipping (FRs). Frame skipping (FRs) can be divided into a non-emitting period Tne and an emitting period Te. Here, the non-emitting period Tne of the frame skipping (FRs) can be referred to as the second non-emitting period Tne2, and the emitting period Te of the frame skipping (FRs) can be referred to as the second emitting period Te2.

[0124] The second non-emitting period Tne2 and the second emitting period Te2 can be defined by the emitting control signal EM(n) of the skipped frame FRs. In this regard, the high-level (as cutoff level) scanning pulse segment of the emitting control signal EM(n) can correspond to the second non-emitting period Tne2, and the low-level (as on level) segment of the emitting control signal EM(n) can correspond to the second emitting period Te2.

[0125] During the second non-light-emitting period Tne2 of the frame skipping FRs, the operation of writing data voltage Vdata is not performed, therefore the data writing period Tw is not set in the first non-light-emitting period Tne1 of the refresh frame FRr.

[0126] Therefore, during the second non-light-emitting period Tne2 of the frame skipping FRs, the first scan signal SC1(n) associated with the data write operation can be kept at a low level as the cutoff level, and the second scan signals SC2_O(n) and SC2_E(n) can be kept at a high level as the cutoff level.

[0127] Furthermore, during the second non-light-emitting period Tne2 of the frame skipping FRs, the initialization operation of applying the initialization voltage Vini is not performed, and therefore the initialization period Ti is not set in the first non-light-emitting period Tne1 of the refresh frame FRr.

[0128] Therefore, during the second non-light-emitting period Tne2 of the skip frame FRs, the fourth scan signal SC4(n) associated with the initialization operation can be kept at a low level as the cutoff level.

[0129] Meanwhile, in the second non-emitting period Tne2 of the frame skipping FRs, a bias period Tobs can be set when the bias voltage Vobs and the anode reset voltage Var are applied. Here, for ease of explanation, the bias period Tobs set in the second non-emitting period Tne2 can be referred to as the third bias period Tobs3.

[0130] During the third bias period Tobs3, the third scan signal SC3(n) can have a low-level scan pulse as the on-state. Therefore, on-bias stress operation for driving transistor DT and anode reset operation for the anode of light-emitting diode OD can be performed.

[0131] Further references are provided below. Figure 6 An example describing the cross-sectional structure of the display panel 100 of this embodiment. Figure 6 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first embodiment of the present invention.

[0132] exist Figure 6 For ease of explanation, two thin-film transistors (TFTs) TFT1 and TFT2 are shown in pixel P within the display area AA. Here, TFT1, positioned relatively lower and closer to the substrate 101, is referred to as the first thin-film transistor TFT1, and it may be a polycrystalline silicon thin-film transistor. TFT2, positioned relatively higher and further away from the substrate 101, is referred to as the second thin-film transistor TFT2, and it may be an oxide thin-film transistor.

[0133] Meanwhile, the first thin-film transistor TFT1 can be a driving transistor ( Figure 2 (DT), but not limited to this, and for ease of explanation, in Figure 6 The diagram shows a configuration where the first thin-film transistor TFT1 is connected to the light-emitting diode OD. Furthermore, the second thin-film transistor TFT2 can be one of the first to seventh transistors serving as switching thin-film transistors. Figure 2 One of the transistors T1 to T7, more specifically, the first transistor T1 connected to the storage capacitor Cst or the seventh transistor T7 connected to the gate of the driving transistor DT, but not limited thereto.

[0134] The substrate 101 may be configured as, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) to achieve the flexible characteristics of the display panel 100.

[0135] Here, when the substrate 101 is configured as a glass substrate, for example, the substrate 101 may have a thickness of about 0.2 mm.

[0136] Meanwhile, when the substrate 101 is configured as a plastic substrate, for example, the substrate 101 may include at least one polyimide layer. In this embodiment, a substrate 101 configured with two polyimide layers, serving as a first polyimide layer 101a and a second polyimide layer 101b, is used as an example.

[0137] The first thin-film transistor TFT1 may include: a first semiconductor layer 105 disposed on a substrate 101; a first gate 115 overlapping the semiconductor layer 105, with a first insulating layer 110 interposed therebetween; and a first source 151 and a first drain 152 located on a fourth insulating layer 145 above the first gate 115. Here, the first semiconductor layer 105 may be formed of polysilicon, but is not limited thereto.

[0138] The first semiconductor layer 105 may include a central channel region and source and drain regions on both sides thereof. The first source 151 and the first drain 152 may be connected to the source and drain regions of the first semiconductor layer 105 via a first contact hole 156 and a second contact hole 157 formed in insulating layers 110, 120, 125, 135 and 145 located below the first source 151 and the first drain 152.

[0139] The second insulating layer 120 may be formed on the first gate 115 of the first thin film transistor TFT1.

[0140] The first interlayer insulating layer 125 may be formed on the second insulating layer 120. The second thin-film transistor TFT2 may be formed on the first interlayer insulating layer 125.

[0141] The second thin-film transistor TFT2 may include: a second semiconductor layer 130 located on a first interlayer insulating layer 125; a second gate 140 overlapping the second semiconductor layer 130, with a third insulating layer 135 interposed therebetween; and a second source 153 and a second drain 154 located on a fourth insulating layer 145 above the second gate 140. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited thereto.

[0142] The second semiconductor layer 130 may include a central channel region and source and drain regions on both sides thereof. The second source 153 and the second drain 154 may be connected to the source and drain regions of the second semiconductor layer 130 via a third contact hole 158 and a fourth contact hole 159 formed in the insulating layers 135 and 145 located below the second source 153 and the second drain 154.

[0143] The second interlayer insulating layer (or the first planarization layer) 160 may be formed on the second thin-film transistor TFT2.

[0144] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135 and the fourth insulating layer 145 may be formed of inorganic insulating materials such as silicon nitride or silicon oxide, but are not limited thereto.

[0145] Furthermore, the first interlayer insulation layer 125 and the second interlayer insulation layer 160 may be formed of organic insulating materials such as photo acrylic or benzocyclobutene, but are not limited thereto.

[0146] The connection electrode 162 may be formed on the second interlayer insulating layer 160. The connection electrode 162 may be connected to the first drain electrode 152 through a contact hole 161 formed in the second interlayer insulating layer 160.

[0147] A third interlayer insulating layer (or a second planarization layer) 163 may be formed on the connecting electrode 162. The third interlayer insulating layer 163 may be formed of an organic insulating material such as optical acrylic or benzocyclobutene, but is not limited thereto.

[0148] The light-emitting diode OD and the dam 165 can be formed on the third interlayer insulating layer 163.

[0149] A light-emitting diode (OD) may include an anode (or first electrode) 171, a light-emitting layer 172, and a cathode (or second electrode) 173.

[0150] The anode 171 can be connected to the connecting electrode 162 through a contact hole 164 formed in the third interlayer insulating layer 163.

[0151] The embankment 165 may be disposed along the boundary of pixel P and may be formed to cover the edge of anode 171. The light-emitting layer 172 may be formed on anode 171 exposed through the opening of embankment 165.

[0152] The cathode 173 can be formed on the light-emitting layer 172 and can be driven by a low potential voltage. Figure 2 (EVSS).

[0153] Encapsulation layer 180 may be formed on cathode 173. Encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In this invention, a structure of encapsulation layer 180 in which a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are stacked sequentially is described as an example.

[0154] A first encapsulation layer 181 may be formed on a substrate 101 on which a cathode 173 is formed. A third encapsulation layer 183 may be formed on a substrate 101 on which a second encapsulation layer 182 is formed, and may be formed together with the first encapsulation layer 181 to surround the upper surface, lower surface, and side surface of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light-emitting diode (OD). The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0155] The second encapsulation layer 182 can act as a buffer to alleviate interlayer stress caused by bending of the display device 10 and can flatten the steps between layers. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed, but is not limited to, using a non-photosensitive organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC)) or a photosensitive organic insulating material (such as optical acrylic). When the second encapsulation layer 182 is formed by inkjet printing, a dam DAM can be placed in the non-display area NA to prevent the liquid form of the second encapsulation layer 182 from spreading to the edge of the substrate 101. The dam DAM can be set closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM prevents the second encapsulation layer 182 from spreading to the pad area located at the outermost edge of the substrate 101, where conductive pads are provided.

[0156] The dam DAM can be designed to prevent the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 is formed during the process to exceed the height of the dam DAM, the second encapsulation layer 182, as an organic layer, can be exposed to the outside, allowing moisture and the like to easily penetrate into the light-emitting element. To prevent this, 10 or more dam DAMs can be formed consecutively, but this is not a limitation.

[0157] The weir DAM can be formed simultaneously with the first interlayer insulation layer 125, the second interlayer insulation layer 160, and the third interlayer insulation layer 163. When the first interlayer insulation layer 125 is formed, it can be formed together as the lower layer of the weir DAM, and when the second interlayer insulation layer 160 and the third interlayer insulation layer 163 are formed, they can be formed together as the upper layer of the weir DAM, so that the weir DAM can be formed as a three-layer laminated structure. As another example, the weir DAM can be formed together with one or two of the first, second, and third interlayer insulation layers 125, 160, and 163.

[0158] Therefore, the weir DAM can be formed of the same material as the first interlayer insulation layer 125, the second interlayer insulation layer 160 and the third interlayer insulation layer 163, but is not limited thereto.

[0159] The dammed DAM can be formed to overlap with the low-potential drive voltage line VSSL. For example, the low-potential drive voltage line VSSL can be formed in the layer below the area where the dammed DAM is located in the non-display area NA.

[0160] A low-potential driving voltage line VSSL and a gate driving portion 210 configured as a GIP structure may be formed along the periphery of the display panel 100, and the low-potential driving voltage line VSSL may be located outside the gate driving portion 210. Furthermore, the low-potential driving voltage line VSSL may be connected to the cathode 173 to apply a low-potential driving voltage EVSS. The gate driving portion 210 is simply shown in planar and cross-sectional form in the figures, but may be configured with the same structure as the first thin-film transistor TFT1 and / or the second thin-film transistor TFT2 of the display area AA.

[0161] A touch layer (or touch element layer) 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 may be positioned between the touch sensor metal (which includes touch electrode connection lines 192, 194 and touch electrodes 195, 196) and the cathode 173 of the light-emitting diode OD.

[0162] The touch buffer layer 191 can prevent chemical solutions (developers, etchants, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 191 or moisture from the outside from penetrating into the light-emitting layer 172 containing organic materials. Therefore, the touch buffer layer 191 can prevent damage to the light-emitting layer 172, which is susceptible to chemical solutions or moisture.

[0163] According to the mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 can be disposed on the touch buffer layer 191, and touch electrodes 195 and 196 can be arranged to cross each other.

[0164] Touch electrode connecting lines 192 and 194 can electrically connect to touch electrodes 195 and 196. One of the touch electrode connecting lines 192 and 194, as well as touch electrodes 195 and 196, can be located on different layers, with a touch insulating layer 193 interposed therebetween. Alternatively, the other of the touch electrode connecting lines 192 and 194, as well as touch electrodes 195 and 196, can be located on the same layer as the touch insulating layer 193.

[0165] The touch electrode connecting lines 192 and 194 can be arranged to overlap with the embankment 165, thereby preventing a reduction in the aperture ratio, but are not limited thereto.

[0166] Meanwhile, a portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 may extend along the top and side surfaces of the encapsulation layer 180 and the top and side surfaces of the dam DAM, and be electrically connected to the touch driving circuit via touch pads 198 and 199.

[0167] A portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 can receive touch drive signals from touch drive circuitry (touch drive signals can be transmitted to touch electrodes 195 and 196), and can transmit touch sensing signals detected by touch electrodes 195 and 196 to touch drive circuitry.

[0168] In this regard, for example, the driver IC (e.g., data IC, etc.) of the data driver section 220 including the touch driver circuit can be configured in COF type and connected to the non-display area NA of the substrate 101 of the display panel 100. In this case, the ends of the touch pads 198 and 199 can be connected to the flexible circuit film on which the driver IC is mounted, so that signals can be transmitted.

[0169] Touch protection layer 197 may be disposed on touch electrodes 195 and 196. In the accompanying drawings, touch protection layer 197 is shown as being disposed only on touch electrodes 195 and 196, but is not limited thereto; touch protection layer 197 may extend before or after the dam DAM is disposed on touch electrode connection line 192.

[0170] In addition, a color filter may be disposed on the encapsulation layer 180. The color filter may be located on the touch layer 190, or between the encapsulation layer 180 and the touch layer 190.

[0171] Meanwhile, the gate driving unit 210 of this embodiment may be equipped with a reset circuit for implementing a reset operation.

[0172] In this regard, a reset circuit may be provided, for example, in each stage of the drive circuitry used to output the gate signal. During the blanking interval between frames FR, the reset circuit may output a gate high voltage VGH (the gate high voltage VGH is a reset voltage used to reset the output control node of the stage) to reset the Q node of the stage electrically connected to the reset circuit or the Q2 node of the stage electrically connected to the Q node. The drive circuitry including the reset circuit may also include transistors having a source or drain connected to the Q node or the Q2 node.

[0173] The reset circuit may include a reset transistor, which is a reset switch that receives a gate high voltage VGH and is turned on during the reset period to output a gate high voltage VGH.

[0174] The reset transistor can be formed as an N-type oxide transistor comprising an oxide semiconductor with excellent cutoff current characteristics. In this respect, oxide transistors have the advantage of lower cutoff leakage current compared to polycrystalline transistors comprising polycrystalline silicon due to their characteristics. Therefore, oxide transistors can be used as reset transistors in reset circuits for stable reset of the Q node.

[0175] However, if the source of the reset transistor is directly connected to the Q node or Q2 node, then the Q node or Q2 node can be electrically coupled to the gate clock used to output the gate signal. In this respect, the Q node or Q2 node can form a parasitic capacitance with the gate of the transistor, which is electrically connected to it and receives the gate clock, thus being electrically coupled to the gate clock.

[0176] Due to electrical coupling, the source voltage (Vsn) of the reset transistor can vary. Due to electrical coupling, the source voltage Vsn of the reset transistor in the off state can be lower than the gate low voltage VGL, and even the source voltage Vsn can be equal to or lower than (VGL-Vthn) (where Vthn is the threshold voltage of the reset transistor).

[0177] Therefore, when the source voltage Vsn of the reset transistor becomes equal to or lower than (VGL-Vthn) and thus the threshold voltage Vthn or more is reduced compared to the gate low voltage VGL (the gate low voltage VGL is the voltage (Vgn) of the gate of the reset transistor in the off state), the reset transistor turns on, which may cause leakage current, i.e., cutoff leakage current.

[0178] If such a cutoff leakage current occurs, the voltage of the Q node or Q2 node will not be maintained, but will fluctuate abnormally, which may cause stage failure and reduce the reliability of the output signal.

[0179] However, the reset circuit of this embodiment may be provided with an additional transistor connected to the reset transistor and perform the function of preventing unwanted cutoff leakage current of the reset transistor by allowing the source voltage Vsn to remain equal to or higher than the gate low voltage VGL in the off state.

[0180] The reset circuit of this embodiment is described in more detail below.

[0181] Figure 7 This is a schematic view showing the structure of a reset circuit according to a first embodiment of the present invention. Figure 8 and Figure 9 This is a schematic view illustrating the operation of a reset circuit according to a first embodiment of the present invention. Figure 8 The diagram schematically illustrates the state where the reset circuit is turned on and outputs a reset voltage. Figure 9 The diagram schematically illustrates the state where the reset circuit is off and no reset voltage is output. Figure 10 This is an illustrative representation of the application. Figure 7 A view illustrating the structure of the reset circuit and the scan drive circuit.

[0182] In this embodiment, for ease of explanation, a second scan drive circuit that generates a second scan signal is used as an example as the gate drive circuit applying the reset circuit RC. Meanwhile, the reset circuit RC of this embodiment can be applied to at least one of the first scan drive circuit, the third scan drive circuit, the fourth scan drive circuit, the first light-emitting drive circuit, and the second light-emitting drive circuit.

[0183] In addition, Figure 10 As an example, a second scan level SSC2(n) is shown in the second scan level SSC2 that constitutes the second scan drive circuit, arranged in the nth horizontal line.

[0184] and Figures 1 to 6 Refer to together Figure 7 and Figure 10 The reset circuit RC in this embodiment may include, for example, a reset transistor Trst and an auxiliary transistor Tb, wherein the auxiliary transistor Tb is connected in series with the reset transistor Trst and is used to prevent cutoff leakage current. Thus, the reset transistor Trst and the auxiliary transistor Tb can be connected in series and have a node NR between them.

[0185] The reset transistor Trst may comprise, for example, an oxide semiconductor with excellent cutoff current characteristics. The reset transistor Trst may be configured as an N-type transistor.

[0186] Therefore, the reset transistor Trst, which is an N-type transistor with oxide semiconductor, can be formed using the same structure as, for example, N-type transistors with oxide semiconductor in pixel P (e.g., T1 and T7).

[0187] The reset transistor Trst can output a high gate voltage VGH as a reset voltage in response to the reset signal RST.

[0188] In this regard, the reset transistor Trst may have a gate for receiving the reset signal RST, a drain as a second electrode for receiving the gate high voltage VGH, and a source as a first electrode connected to the auxiliary transistor Tb. The drain of the reset transistor Trst to which the gate high voltage VGH is input can be used as an input terminal of the reset circuit RC.

[0189] The auxiliary transistor Tb may include, for example, polycrystalline silicon with excellent mobility characteristics, but is not limited thereto. The auxiliary transistor Tb may be configured as a P-type transistor.

[0190] Therefore, the auxiliary transistor Tb, which is a P-type transistor with polysilicon, can be formed using the same structure as, for example, the P-type transistors with polysilicon in pixel P (e.g., T2 to T6 and DT).

[0191] During the reset period, in response to the continuously applied gate low voltage VGL, the auxiliary transistor Tb can output a gate high voltage VGH, which is the reset voltage output by the reset transistor Trst in the on state.

[0192] During the reset cutoff period between adjacent reset periods (i.e., the period between the current reset period and the next reset period) (e.g., during frame FR), the auxiliary transistor Tb can be operated such that, in response to a continuously applied gate low voltage VGL, the source voltage (Vsn) of the reset transistor Trst, which is in the off state, is higher than the gate low voltage VGL. For example, the auxiliary transistor Tb can be operated such that the node NR to which the reset transistor Trst is connected is applied a voltage that is |Vthp| or more (or at least |Vthp|) higher than the gate low voltage VGL, i.e., is applied equal to or higher than (VGL + |Vthp|) (where |Vthp| is the absolute value of the threshold voltage (Vthp) of the auxiliary transistor Tb).

[0193] In this regard, the auxiliary transistor Tb may have a gate that receives a low gate voltage VGL, a source that serves as the first electrode connected to the source of the reset transistor Trst (i.e., node NR), and a drain that serves as the output terminal of the reset circuit RC.

[0194] Further reference Figure 8 and Figure 9 The operation of the reset circuit RC, configured as described above, with reset transistor Trst and auxiliary transistor Tb, is described.

[0195] First, refer to Figure 8 This describes the reset operation that outputs a reset voltage during the reset period. During the reset period, the reset signal RST may be in a high state, i.e., a high gate voltage VGH.

[0196] Therefore, the N-type reset transistor Trst can be turned on. At this time, a voltage (VGH-Vthn) can be applied to the source of the reset transistor Trst (where Vthn is the threshold voltage of the reset transistor Trst).

[0197] Therefore, when the reset transistor Trst is turned on during the reset period, the source voltage Vsn (or the voltage of node NR) can be set to Vsn = (VGH - Vthn).

[0198] Meanwhile, during the reset period, the P-type auxiliary transistor Tb can be applied a low-state voltage (i.e., gate low voltage VGL), thus turning it on.

[0199] In this regard, the source voltage (Vsp) of the auxiliary transistor Tb can actually have the source voltage Vsn of the reset transistor Trst connected to it, so the source voltage Vsp of the auxiliary transistor Tb can be changed to Vsp = (VGH - Vthn).

[0200] In this case, if the source voltage Vsp of the auxiliary transistor Tb is higher than the sum of the absolute value |Vthp| of the gate low voltage VGL applied to its gate and the threshold voltage Vthp of the auxiliary transistor Tb, then the auxiliary transistor Tb can be turned on.

[0201] In other words, if (VGH-Vthn)>(VGL+│Vthp│), then the auxiliary transistor Tb can be turned on. That is, if (VGH-VGL)>(Vthn+│Vthp│), then the auxiliary transistor Tb can be turned on.

[0202] In this regard, during normal operation of the display device, (VGH-VGL) is a large value of 5V or greater, and (Vthn+│Vthp│) is relatively small in comparison.

[0203] Therefore, during the reset period, the auxiliary transistor Tb can conduct normally.

[0204] Therefore, during the reset period, the source voltage Vsp (=(VGH-Vthn)) of the auxiliary transistor Tb can be set to an absolute value (│Vthp│) greater than its threshold voltage compared to the low gate voltage VGL input to its gate, so the auxiliary transistor Tb can be turned on without problems.

[0205] Therefore, since the auxiliary transistor Tb is turned on, the reset current Ir can flow from the input terminal of the reset circuit RC to the output terminal through the reset transistor Trst and the auxiliary transistor Tb, so that the high-level reset voltage can be output to the output terminal of the reset circuit RC.

[0206] Next, refer to Figure 9 This describes a reset off operation, where the reset voltage is not output after the reset period. During the reset off period following the reset period, the reset signal RST may be in a low state, i.e., a low gate voltage VGL.

[0207] Therefore, the N-type reset transistor Trst can be turned off.

[0208] Meanwhile, during the reset off period, a low-state voltage (i.e., gate low voltage VGL) can be applied to the P-type auxiliary transistor Tb to turn it on.

[0209] Therefore, the source voltage Vsp of the auxiliary transistor Tb can be (VGL + |Vthp|) or higher.

[0210] Therefore, when the reset transistor Trst is in the off state, the auxiliary transistor Tb is in the on state, so that the source voltage Vsp of the auxiliary transistor Tb can be set to (VGL+│Vthp│) or higher.

[0211] As a result, during the reset cutoff period, the source voltage Vsn of the reset transistor Trst can actually have the source voltage Vsp of the auxiliary transistor Tb connected to it, so that the source voltage Vsn of the reset transistor Trst can be set to (VGL+│Vthp│) or higher.

[0212] Therefore, during the reset off period, the source voltage Vsn of the reset transistor Trst can be set to a gate low voltage VGL or higher, so that the reset transistor Trst can be stably kept off.

[0213] Regarding this, as mentioned above, during the reset off period of the N-type reset transistor Trst when the gate low voltage VGL is applied, if the source voltage Vsn of the reset transistor Trst becomes equal to or lower than (VGL-Vthn), the reset transistor Trst is unintentionally turned on, which may result in a cutoff leakage current Il.

[0214] However, the reset circuit RC in this embodiment may include a P-type auxiliary transistor Tb connected between the source of the reset transistor Trst and the output terminal of the reset circuit RC.

[0215] With the aid of auxiliary transistor Tb, during the off period of reset transistor Trst, the source voltage Vsn of reset transistor Trst can be set to the source voltage Vsp of auxiliary transistor Tb, and the source voltage Vsn of reset transistor Trst can be (VGL + |Vthp|) or greater.

[0216] Therefore, the source of the reset transistor Trst can stably have a voltage higher than the gate low voltage VGL, thereby stably ensuring the cut-off state of the reset transistor Trst.

[0217] Therefore, the cutoff leakage current Il flowing through the reset transistor Trst can be prevented, so that the voltage at the output terminal of the reset circuit RC is not affected by the cutoff leakage current I1.

[0218] This prevents abnormal voltage fluctuations at the Q node or Q2 node in the stage connected to the reset circuit RC due to the cutoff leakage current Il, thereby preventing stage failures caused by the cutoff leakage current Il and improving the reliability of the signal output from the stage.

[0219] As an example of a gate drive circuit using the aforementioned reset circuit RC, further refer to Figure 10 Describe the configuration of the second scan drive circuit that generates the second scan signal SC2.

[0220] The second scan drive circuit may include multiple second scan levels SSC2, which correspond to multiple second scan lines SCL2 arranged in the display area AA and output corresponding second scan signals SC2.

[0221] Regarding the configuration of the second scan level SSC2, taking the nth second scan level SCC2(n) as an example, the nth second scan level SCC2(n) may include an output unit OC and a control unit CCP that controls the output operation of the output unit OC.

[0222] In this regard, the output section OC may include, for example, a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, a Q capacitor CQ, and a QB capacitor CQB.

[0223] The control unit CCP may include, for example, a transfer transistor TA and multiple control transistors Ts3, Ts4 and Ts5. Here, the multiple control transistors Ts3, Ts4 and Ts5 may include, for example, a first, second and third control transistor (or an eighth, ninth and tenth transistor) Ts3, Ts4 and Ts5.

[0224] Furthermore, the control unit CCP may include a reset circuit RC. In this embodiment, the reset circuit RC is connected to node Q2 in the second scan level SSC2 as an example.

[0225] Apart from the reset circuit RC, each of the plurality of transistors Ts1 to Ts5 and TA constituting the second scan stage SSC2(n) can be a P-type transistor or an N-type transistor. Furthermore, each of the plurality of transistors Ts1 to Ts5 and TA constituting the second scan stage SSC2(n) can be a transistor using oxide semiconductors or a transistor using polysilicon.

[0226] In this embodiment, the following scenario is used as an example: among the plurality of transistors Ts1 to Ts5 and TA constituting the second scan level SSC2(n), the pull-up transistor Ts1, the pull-down transistor Ts2, the transfer transistor TA, and the first and second control transistors Ts3 and Ts4 are configured as P-type transistors including a polysilicon layer, and the third control transistor Ts5 is configured as an N-type transistor including an oxide semiconductor layer.

[0227] Here, the N-type transistor Ts5 with oxide semiconductor can be formed, for example, using the same structure as the N-type transistors with oxide semiconductor in pixel P (e.g., T1 and T7). For example, the P-type transistors Ts1 to Ts4 and TA with polysilicon can be formed using the same structure as the P-type transistors with polysilicon in pixel P (e.g., T2 to T6 and DT).

[0228] The pull-up transistor Ts1 of the output section OC can drive the output terminal N0 of the second scan stage SSC2(n) in response to a signal applied to its gate at the Q node. Furthermore, the pull-down transistor Ts2 can drive the output terminal NO in response to a signal applied to its gate at the QB node.

[0229] The P-type pull-up transistor Ts1 may, for example, have a second electrode (or drain) that receives a low gate voltage VGL and a first electrode (or source) that is connected to the output terminal N0 of the second scan stage SSC2(n).

[0230] In addition, the P-type pull-down transistor Ts2 may have, for example, a second electrode (or drain) connected to the output terminal NO and a first electrode (or source) provided with a gate high voltage VGH.

[0231] Simultaneously, the transfer transistor TA of the control unit CCP can transfer charge from the Q2 node to the Q node in response to a gate low voltage VGL applied to its gate. The P-type transfer transistor TA may have, for example, a gate to which a gate low voltage VGL is applied, a first electrode (or source) connected to the Q2 node, and a second electrode (or drain) connected to the Q node.

[0232] The first control transistor Ts3 can provide the previous second scan signal SC2(n-1) (which is the output signal of the previous second scan stage SSC2) to the Q2 node in response to its corresponding scan clock SCLK1. The P-type first control transistor Ts3 may have, for example, a gate to which the scan clock SCLK1 is applied, a first electrode (or source) to which the previous second scan signal SC2(n-1) is applied, and a second electrode (or drain) connected to the Q2 node. Here, the scan clock SCLK1 input to the nth second scan stage SSC2(n) may be referred to as the first scan clock SCLK1.

[0233] Here, the previous second scan signal SC2(n-1) applied to the first control transistor Ts3 can be used as a start signal (or carry signal). At the same time, when the second scan level SSC2(n) is the scan level of the first horizontal line, the start signal provided from the timing control unit 240 can be input to the first control transistor Ts3 to start its output operation.

[0234] Furthermore, the second control transistor Ts4 can transfer a gate high voltage VGH to the QB node in response to the voltage at the Q2 node. The P-type second control transistor Ts4 may have, for example, a gate connected to the Q2 node, a second electrode (or drain) connected to the QB node, and a first electrode (or source) to which the gate high voltage VGH is applied.

[0235] Furthermore, the third control transistor Ts5 can be connected in series with the second control transistor Ts4 (with the QB node interposed therebetween), and can transfer a gate low voltage VGL to the QB node in response to the voltage of the Q node. The N-type third control transistor Ts5 may, for example, have a gate connected to the Q node, a second electrode (or drain) connected to the QB node, and a first electrode (or source) to which the gate low voltage VGL is applied.

[0236] Simultaneously, the Q capacitor CQ can be connected between the Q node and the output terminal N0, and the QB capacitor CQB can be connected between the QB node and the line transmitting the high gate voltage VGH. Here, the capacitance of both the Q capacitor CQ and the QB capacitor CQB can be set to be greater than the capacitance of the storage capacitor Cst in pixel P.

[0237] The second scan level SSC2(n) configured as described above can shift the previous second scan signal SC2(n-1) according to the input scan clock SCLK1, and output the corresponding second scan signal SC2(n) to the corresponding second scan line SCL2.

[0238] Therefore, the second scan level SSC2(n) of the nth horizontal line can receive the scan clock SCLK1 to perform signal output operation.

[0239] Meanwhile, the second scan level SSC2 located in the (n-1)th and (n+1)th horizontal lines (before and after the nth horizontal line) can receive its corresponding scan clock, such as the second scan clock (which is different in phase from the scan clock SCLK1 input to the nth second scan level SSC2(n)) and perform the operation of outputting its corresponding second scan signal SC2.

[0240] The reset circuit RC can be connected to the Q2 node of the second scan stage SSC2 configured as described above.

[0241] Regarding this, as mentioned above, the reset circuit RC may be configured with: a reset transistor Trst, which is connected to the input terminal that receives the gate high voltage VGH as the reset voltage; and an auxiliary transistor Tb, which is connected in series with the reset transistor Trst and outputs the reset voltage.

[0242] Here, the auxiliary transistor Tb can be connected to the Q2 node of the second scan stage SSC2(n). More specifically, the drain of the auxiliary transistor Tb can be connected to the Q2 node of the second scan stage SSC2(n).

[0243] Therefore, the Q2 node can be reset by the reset circuit RC connected to the Q2 node, and consequently, the Q node connected to the Q2 node by the transfer transistor TA electrically short-circuiting can be reset.

[0244] For example, as described above, when a high-state (i.e., gate high voltage VGH) reset signal RST is applied to the reset circuit RC during the reset period, the reset transistor Trst and the auxiliary transistor Tb arranged in the reset circuit RC are both turned on, so that the gate high voltage VGH, which is the reset voltage, can be transmitted to the Q2 node.

[0245] Therefore, the reset voltage is transmitted from node Q2 to node Q, and node Q can be reset to a high state.

[0246] Furthermore, when nodes Q2 and Q are reset to the high state, the second control transistor Ts4 can be turned off, the third control transistor Ts5 can be turned on, and the gate low voltage VGL can be transmitted to node QB through the third control transistor Ts5, so that node QB can be reset to the low state.

[0247] During the reset cutoff period following the reset period, as described above, the reset signal RST is switched to a low state, i.e., the gate voltage VGL is low, the reset transistor Trst can be turned off, and the auxiliary transistor Tb can be turned on.

[0248] At this time, the source voltage Vsn of the reset transistor Trst can be set to (VGL+│Vthp│) or higher, so that the reset transistor Trst can be stably kept in the off state.

[0249] Therefore, the cutoff leakage current Il flowing through the reset transistor Trst can be prevented.

[0250] Therefore, the cutoff leakage current Il of the reset circuit RC can be prevented from flowing into node Q2, which is connected to the output terminal of the reset circuit RC. As a result, the cutoff leakage current Il can be prevented from flowing into node Q.

[0251] Regarding this point, as mentioned above, when the reset circuit RC is configured with only the reset transistor Trst and no auxiliary transistor Tb, node Q2 is electrically coupled to the scan clock SCLK1 input to the first control transistor Ts3 connected thereto, causing the source voltage of the reset transistor Trst to become (VGL - Vthn) or lower. In this case, the cutoff leakage current Il can be generated through the reset transistor Trst and flow into nodes Q2 and Q, causing abnormal fluctuations in the voltages of nodes Q2 and Q. Consequently, leakage current can be generated through the Q capacitor CQ and flow into nodes Q (and Q2), causing abnormal fluctuations in the voltages of nodes Q (and Q2).

[0252] On the other hand, in this embodiment, by adding an auxiliary transistor Tb to the reset circuit RC, the source of the reset transistor Trst can stably have a voltage higher than the gate low voltage VGL during the reset off period, thereby stably ensuring the off state of the reset transistor Trst.

[0253] Therefore, the cutoff leakage current of the reset circuit RC can be prevented, thus preventing leakage current from flowing into the Q2 node and Q node which are electrically connected to the output terminal of the reset circuit RC. Therefore, it is unaffected by leakage current.

[0254] Therefore, abnormal voltage fluctuations at the Q nodes and Q2 nodes of the second scan stage SSC2 due to leakage current can be prevented, thus preventing faults in the second scan stage SSC2 caused by leakage current and improving the reliability of the signal output from it.

[0255] <Second Implementation>

[0256] Figure 11 This is a schematic view illustrating an example of the structure of a scan drive circuit employing a reset circuit according to a second embodiment of the present invention.

[0257] In the following description, specific descriptions of configurations that are the same as or similar to those in the first embodiment described above may be omitted.

[0258] In this embodiment, the gate driving section may be provided with a reset circuit RC, wherein the P-type auxiliary transistor Tb is connected to the reset transistor Trst formed of N-type oxide semiconductor, thereby preventing the cutoff leakage current of the reset transistor Trst, which is similar to the first embodiment.

[0259] Meanwhile, unlike the first embodiment, the reset circuit RC in this embodiment can be connected to the Q node.

[0260] Regarding this point, refer to Figure 11 As an example of a gate drive circuit that applies a reset circuit RC, the configuration of a second scan drive circuit that generates the second scan signal SC2 is described.

[0261] The second scan level SSC2 can be configured similarly to the nth second scan level SSC2 in the first embodiment, and its detailed description can be omitted.

[0262] The reset circuit RC can be connected to the Q node of the second scan stage SSC2.

[0263] In this regard, the reset circuit RC may be configured with: a reset transistor Trst, which is connected to the input terminal that receives the gate high voltage VGH as the reset voltage; and an auxiliary transistor Tb, which is connected in series with the reset transistor Trst and outputs the reset voltage.

[0264] Here, the auxiliary transistor Tb can be connected to the Q node of the second scan stage SSC2(n). More specifically, the drain of the auxiliary transistor Tb can be connected to the Q node of the second scan stage SSC2(n).

[0265] Therefore, the Q node can be reset via the RC reset circuit connected to the Q node.

[0266] For example, similar to the first embodiment described above, when a high-state (i.e., gate high voltage VGH) reset signal RST is applied to the reset circuit RC during the reset period, the reset transistor Trst and the auxiliary transistor Tb arranged in the reset circuit RC can be turned on, thereby transmitting the gate high voltage VGH, which is the reset voltage, to the Q node.

[0267] Therefore, the reset voltage can be transmitted to node Q, and node Q can be reset to a high state. At this time, node Q2, which is electrically shorted to node Q by the transfer transistor TA, can also be reset to a high state.

[0268] When the Q node is reset to the high state, the second control transistor Ts4 can be turned off and the third control transistor Ts5 can be turned on, and the gate low voltage VGL can be transmitted to the QB node through the third control transistor Ts5, so that the QB node can be reset to the low state.

[0269] During the reset cutoff period following the reset period, as described above, the reset signal RST is switched to a low state, i.e., the gate voltage VGL is low, the reset transistor Trst can be turned off, and the auxiliary transistor Tb can be turned on.

[0270] At this time, the source voltage Vsn of the reset transistor Trst can be set to (VGL+│Vthp│) or higher, thereby stably maintaining the cut-off state of the reset transistor Trst.

[0271] Therefore, it can prevent the cutoff leakage current flowing through the reset transistor Trst.

[0272] As a result, the cutoff leakage current of the reset circuit RC is prevented from flowing into node Q, which is connected to the output terminal of the reset circuit RC. Furthermore, the cutoff leakage current is prevented from flowing into node Q2.

[0273] Therefore, in this embodiment, by adding the auxiliary transistor Tb to the reset circuit RC, the source of the reset transistor Trst can stably have a voltage higher than the gate low voltage VGL during the reset off period, thereby stably ensuring the off state of the reset transistor Trst.

[0274] Therefore, the cutoff leakage current of the reset circuit RC can be prevented, thereby preventing leakage current from flowing into the Q node (and Q2 node) connected to the output terminal of the reset circuit RC, and thus preventing the influence of leakage current.

[0275] This prevents abnormal voltage fluctuations at the Q nodes (and Q2 nodes) of the second scan stage SSC2 due to leakage current, thereby preventing faults in the second scan stage SSC2 caused by leakage current and improving the reliability of the signal output from it.

[0276] <Third Implementation Method>

[0277] Figure 12 This is a view schematically illustrating a first example of the structure of a scan drive circuit using a reset circuit according to a third embodiment of the present invention. Figure 13 This is a view schematically illustrating a second example of the structure of a scan drive circuit using a reset circuit according to a third embodiment of the present invention.

[0278] In the following description, specific descriptions of configurations that are the same as or similar to the first and second embodiments described above may be omitted.

[0279] In this embodiment, the gate driving section may be provided with a reset circuit RC, wherein the P-type auxiliary transistor Tb is connected to the reset transistor Trst formed by the N-type oxide semiconductor, thereby preventing the cutoff leakage current of the reset transistor Trst, which is similar to the first embodiment and the second embodiment.

[0280] Furthermore, regarding the node to which the reset circuit RC in this embodiment is connected, in Figure 12 In the first example, the reset circuit RC can be connected to node Q2 similarly to the first embodiment; in Figure 13 In the second example, the reset circuit RC can be connected to the Q node in a manner similar to the second embodiment.

[0281] Meanwhile, the gate drive circuit of this embodiment, which uses a reset circuit RC, can be configured with a structure different from that of the first and second embodiments.

[0282] Regarding this point, refer to Figure 12 and Figure 13 As an example of a gate drive circuit that applies a reset circuit RC, the configuration of a second scan drive circuit that generates the second scan signal SC2 is described.

[0283] The second scan drive circuit may include multiple second scan levels SSC2, which correspond to multiple second scan lines arranged in the display area and output corresponding second scan signals.

[0284] Regarding the configuration of the second scan level SSC2, the nth second scan level SCC2(n) is used as an example. The second scan level SCC2(n) may include an output unit OC and a control unit CCP that controls the output operation of the output unit OC.

[0285] In this regard, the output section OC may include, for example, a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, a Q capacitor CQ, and a QB capacitor CQB.

[0286] The control unit CCP may include, for example, a transfer transistor TA; multiple control transistors Ts3, Ts4, Ts5, and Ts6; and an on capacitor CON. Here, the multiple control transistors Ts3, Ts4, Ts5, and Ts6 may include, for example, a first, second, third, and fourth control transistor (or an eighth, ninth, tenth, and eleventh transistor) Ts3, Ts4, Ts5, and Ts6.

[0287] In addition, the control unit CCP may include a reset circuit RC.

[0288] As described above, in the first example of this embodiment, the reset circuit RC can be connected to node Q2 in the second scan level SSC2. In the second example of this embodiment, the reset circuit RC can be connected to node Q in the second scan level SSC2.

[0289] In addition, the control unit CCP may include a reset transistor Trst2 connected to the QB node and resetting the QB node.

[0290] Here, for ease of explanation, the reset transistor Trst, which is electrically connected to the Q node and resets the Q node, can be referred to as the first reset transistor Trst, and the reset transistor Trst2, which is connected to the QB node and resets the QB node, can be referred to as the second reset transistor Trst2.

[0291] In addition to the reset circuit RC and the second reset transistor Trst2, each of the plurality of transistors Ts1 to Ts6 and TA constituting the second scan stage SSC2(n) can be a P-type transistor or an N-type transistor. Furthermore, each of transistors Ts1 to Ts6 and TA can be a transistor using oxide semiconductor or a transistor using polysilicon.

[0292] In this embodiment, the case in which the transistors Ts1 to Ts6 and TA are configured as P-type transistors including a polysilicon layer is used as an example.

[0293] Meanwhile, in this embodiment, the second reset transistor Trst2 can be configured as a P-type transistor including a polysilicon layer.

[0294] The polysilicon P-type transistors Ts1 to Ts6, TA, and Trst2 can, for example, be used with pixels ( Figure 2 P-type transistors in polysilicon (e.g., P) Figure 2 The same structure is formed from T2 to T6 and DT.

[0295] The pull-up transistor Ts1 of the output section OC can drive the output terminal N0 of the second scan stage SSC2(n) in response to a signal applied to its gate at the Q node. Furthermore, the pull-down transistor Ts2 can drive the output terminal NO in response to a signal applied to its gate at the QB node.

[0296] The P-type pull-up transistor Ts1 may, for example, have a second electrode (or drain) that receives a low gate voltage VGL and a first electrode (or source) that is connected to the output terminal N0 of the second scan stage SSC2(n).

[0297] Furthermore, the P-type pull-down transistor Ts2 may, for example, have a second electrode (or drain) connected to the output terminal NO and a first electrode (or source) provided with a gate high voltage VGH.

[0298] Simultaneously, the transfer transistor TA of the control unit CCP can transfer charge from the Q2 node to the Q node in response to a gate low voltage VGL applied to its gate. The P-type transfer transistor TA may have, for example, a gate to which a gate low voltage VGL is applied, a first electrode (or source) connected to the Q2 node, and a second electrode (or drain) connected to the Q node.

[0299] The first control transistor Ts3 can provide the previous second scan signal SC2(n-1) (which is the output signal of the previous second scan stage SSC2) to the Q2 node in response to its corresponding scan clock SCLK1. The P-type first control transistor Ts3 may have, for example, a gate to which the scan clock SCLK1 is applied, a first electrode (or source) to which the previous second scan signal SC2(n-1) is applied, and a second electrode (or drain) connected to the Q2 node. Here, the scan clock SCLK1 input to the nth second scan stage SSC2(n) may be referred to as the first scan clock SCLK1.

[0300] Here, the previous second scan signal SC2(n-1) applied to the first control transistor Ts3 can be used as a start signal (or carry signal). At the same time, when the second scan level SSC2(n) is the scan level of the first horizontal line, the start signal provided from the timing control unit can be input to the first control transistor Ts3 to start its output operation.

[0301] Furthermore, the second control transistor Ts4 can transmit the gate high voltage VGH to the Q1 node in response to the previous second scan signal SC2(n-1). The second control transistor Ts4 may have, for example, a gate that receives the previous second scan signal SC2(n-1), a first electrode (or source) that receives the gate high voltage VGH, and a second electrode (or drain) connected to the Q1 node.

[0302] Furthermore, the third control transistor Ts5 can provide a scan clock SCLK1 as input to the QB node in response to the voltage of the Q1 node. The third control transistor Ts5 may have, for example, a gate connected to the Q1 node, a first electrode (or source) receiving the scan clock SCLK1, and a second electrode (or drain) connected to the QB node.

[0303] The fourth control transistor Ts6 can transfer a gate high voltage VGH to the QB node in response to the voltage at the Q2 node. The fourth control transistor Ts6 may have, for example, a gate connected to the Q2 node, a second electrode (or drain) connected to the QB node, and a first electrode (or source) to which the gate high voltage VGH is applied.

[0304] Simultaneously, the Q capacitor CQ can be connected between the Q node and the output terminal N0, and the QB capacitor CQB can be connected between the QB node and the line transmitting the gate high voltage VGH. The on-state capacitor CON can be connected between the input terminal of the scan clock SCLK1 and the Q1 node. Here, the capacitance of each of the Q capacitor CQ and the QB capacitor CQB can be set to be greater than the capacitance of the on-state capacitor CON. Furthermore, the capacitance of the on-state capacitor CON can be set to be greater than the capacitance of a pixel (…). Figure 2 Storage capacitors in P) Figure 2 The capacitor (Cst).

[0305] The second scan level SSC2(n) configured as described above can shift the previous second scan signal SC2(n-1) according to the input scan clock SCLK1, and output the corresponding second scan signal SC2(n) to the corresponding second scan line.

[0306] Therefore, the second scan level SSC2(n) of the nth horizontal line can receive the scan clock SCLK1 to perform signal output operation.

[0307] Regarding the second scan level SSC2 configured as described above, in the first example, the reset circuit RC can be connected to the Q2 node, and in the second example, the reset circuit RC can be connected to the Q node.

[0308] In this regard, the reset circuit RC may be configured with: a first reset transistor Trst connected to the input terminal of which receives a gate high voltage VGH as a reset voltage; and an auxiliary transistor Tb connected in series with the first reset transistor Trst and outputting a reset voltage.

[0309] Here, the auxiliary transistor Tb can be connected to node Q2 in the first example and to node Q in the second example.

[0310] The Q node and Q2 node can be reset through the reset circuit RC connected in this way.

[0311] For example, as described in the first and second embodiments, when a reset signal RST in a high state (i.e., gate high voltage VGH) is applied to the reset circuit RC during the reset period, both the first reset transistor Trst and the auxiliary transistor Tb arranged in the reset circuit RC can be turned on. Therefore, the gate high voltage VGH, which is the reset voltage, can be transmitted to node Q2 in the first example and to node Q in the second example.

[0312] Therefore, Q2 node and Q node can be reset to the high state.

[0313] During the reset cutoff period following the reset period, as described in the first and second embodiments, the reset signal RST can be switched to a low state, i.e., the gate low voltage VGL, the first reset transistor Trst can be turned off, and the auxiliary transistor Tb can be turned on.

[0314] At this time, the source voltage Vsn of the first reset transistor Trst can be set to (VGL+│Vthp│) or higher, thereby stably maintaining the cut-off state of the first reset transistor Trst.

[0315] Therefore, it can prevent the cutoff leakage current flowing through the first reset transistor Trst.

[0316] Therefore, the cutoff leakage current of the reset circuit RC can be prevented, thereby preventing leakage current from flowing into the Q2 node and Q node connected to the output terminal of the reset circuit RC, so that they are unaffected by leakage current.

[0317] Therefore, the voltage of the Q2 node and Q node of the second scan stage SSC2 can be prevented from fluctuating abnormally due to leakage current, thereby preventing the failure of the second scan stage SSC2 due to leakage current and improving the reliability of the signal output from it.

[0318] In this embodiment, as described above, a second reset transistor Trst2 for resetting the QB node may be additionally provided in the second scan level SSC2.

[0319] The second reset transistor Trst2 can transmit a low gate voltage VGL to the QB node in response to the input reset signal RSTB during the reset period, thereby resetting the QB node to a low state. Here, for ease of explanation, the reset signal RST input to the first reset transistor Trst can be referred to as the first reset signal RST, and the reset signal RSTB input to the second reset transistor Trst2 can be referred to as the second reset signal RSTB.

[0320] At this time, the second reset signal RSTB can be a signal with the opposite phase to the first reset signal RST. In this case, during the reset period, the first reset signal RST can be high and the second reset signal RSTB can be low, and during the reset cutoff period, the first reset signal RST can be low and the second reset signal RSTB can be high.

[0321] The second reset transistor Trst2 may have, for example, a gate that receives the second reset signal RSTB, a second electrode (or drain) that receives the gate low voltage VGL, and a first electrode (or source) connected to the QB node.

[0322] Therefore, during the reset period, when the second reset signal RSTB, which is in a low state (i.e., gate low voltage VGL), is applied to the second reset transistor Trst2, the second reset transistor Trst2 can be turned on, so that the gate low voltage VGL, which is the reset voltage, can be transmitted to the QB node.

[0323] Additionally, during the reset cutoff period following the reset period, the second reset signal RSTB can be switched to a high state, i.e., the gate voltage VGH is high, and the second reset transistor Trst2 can be turned off.

[0324] Therefore, in this embodiment, a second reset transistor Trst2 for resetting the QB node can be additionally provided.

[0325] In this regard, in the circuit configuration of the second scan level SSC2 in this embodiment, when the Q node is reset to a high state by the reset circuit RC, the reset of the QB node caused by the reset of the Q node is not performed.

[0326] However, in this embodiment, the second scan stage SSC2 may be separately provided with a second reset transistor Trst2 connected to the QB node, so that the QB node can be stably reset to a low state through the second reset transistor Trst2.

[0327] <Fourth Implementation Method>

[0328] Figure 14 This is a view schematically illustrating a first example of the structure of a scan drive circuit employing a reset circuit according to a fourth embodiment of the present invention. Figure 15 This is a view schematically illustrating a second example of the structure of a scan drive circuit employing a reset circuit according to a fourth embodiment of the present invention.

[0329] In the following description, specific descriptions of configurations that are the same as or similar to those in the first to third embodiments described above may be omitted.

[0330] In this embodiment, the gate driving section may be provided with a reset circuit RC, wherein the P-type auxiliary transistor Tb is connected to the reset transistor Trst formed by the N-type oxide semiconductor, thereby preventing the cutoff leakage current of the reset transistor Trst, which is similar to the first to third embodiments.

[0331] Furthermore, regarding the node to which the reset circuit RC is connected in this embodiment, in Figure 14 In the first example, the reset circuit RC can be connected to the Q2 node in a manner similar to the first examples of the first and third embodiments, and... Figure 15 In the second example, the reset circuit RC can be connected to the Q node in a manner similar to the second examples of the second and third embodiments.

[0332] Meanwhile, the gate drive circuit of this embodiment, which uses a reset circuit RC, can be configured with a structure different from that of the first to third embodiments.

[0333] Regarding this point, refer to Figure 14 and Figure 15 As an example of a gate drive circuit that applies a reset circuit RC, the configuration of a second scan drive circuit that generates the second scan signal SC2 is described.

[0334] The second scan drive circuit may include multiple second scan levels SSC2, which correspond to multiple second scan lines arranged in the display area and output corresponding second scan signals.

[0335] Regarding the configuration of the second scan level SSC2, the nth second scan level SCC2(n) is used as an example. The second scan level SCC2(n) may include an output unit OC and a control unit CCP that controls the output operation of the output unit OC.

[0336] In this regard, the output section OC may include, for example, a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, a Q capacitor CQ, and a QB capacitor CQB.

[0337] The control unit CCP may include, for example, a transfer transistor TA; a plurality of control transistors Ts3 to Ts10; and a Q3 capacitor C3. Here, the plurality of control transistors Ts3 to Ts10 may include, for example, the first to eighth control transistors (or the eighth to fifteenth transistors) Ts3 to Ts10.

[0338] In addition, the control unit CCP may include a reset circuit RC.

[0339] As described above, in the first example of this embodiment, the reset circuit RC can be connected to node Q2 in the second scan level SSC2. In the second example of this embodiment, the reset circuit RC can be connected to node Q in the second scan level SSC2.

[0340] In addition, the control unit CCP may include a reset transistor Trst2 connected to the QB node and used to reset the QB node.

[0341] Here, for ease of explanation, the reset transistor Trst, which is electrically connected to the Q node and resets the Q node, can be referred to as the first reset transistor Trst, and the reset transistor Trst2, which is connected to the QB node and resets the QB node, can be referred to as the second reset transistor Trst2.

[0342] In addition to the reset circuit RC and the second reset transistor Trst2, each of the plurality of transistors Ts1 to Ts10 and TA constituting the second scan stage SSC2(n) can be a P-type transistor or an N-type transistor. Furthermore, each of transistors Ts1 to Ts10 and TA can be a transistor using oxide semiconductor or a transistor using polysilicon.

[0343] In this embodiment, the case in which the transistors Ts1 to Ts10 and TA are configured as P-type transistors including a polysilicon layer is used as an example.

[0344] Meanwhile, in this embodiment, the second reset transistor Trst2 can be configured as a P-type transistor including a polysilicon layer.

[0345] The polysilicon P-type transistors Ts1 to Ts10, TA, and Trst2 can, for example, be used with pixels ( Figure 2 P-type transistors in polysilicon (e.g., P) Figure 2 The same structure is formed for T2 to T6 and DT.

[0346] The pull-up transistor Ts1 of the output section OC can drive the output terminal N0 of the second scan stage SSC2(n) in response to a signal applied to its gate at the Q node. Furthermore, the pull-down transistor Ts2 can drive the output terminal NO in response to a signal applied to its gate at the QB node.

[0347] Meanwhile, the transfer transistor TA of the control unit CCP can transfer the charge of the Q2 node to the Q node in response to the low gate voltage VGL applied to its gate.

[0348] The first control transistor Ts3 may, in response to the first scan clock SCLK1 (which is the scan clock corresponding to the first control transistor Ts3), provide the previous second scan signal SC2(n-1) (which is the output signal of the previous second scan stage SSC2) to the Q2 node. The P-type first control transistor Ts3 may have, for example, a gate to which the first scan clock SCLK1 is applied, a first electrode (or source) to which the previous second scan signal SC2(n-1) is applied, and a second electrode (or drain) connected to the Q2 node.

[0349] Here, the previous second scan signal SC2(n-1) applied to the first control transistor Ts3 can be used as a start signal (or carry signal). At the same time, when the second scan level SSC2(n) is the scan level of the first horizontal line, the start signal provided from the timing control unit can be input to the first control transistor Ts3 to start its output operation.

[0350] Additionally, the second control transistor Ts4 may have, for example, a gate connected to the Q node, a first electrode (or source) to which its corresponding first scan clock SCLK1 is applied, and a second electrode (or drain) connected to the QB node.

[0351] Furthermore, the third control transistor Ts5 may have, for example, a gate that receives its corresponding second scan clock SCLK2, a first electrode (or source) connected to the fourth control transistor Ts6, and a second electrode (or drain) connected to the QB node.

[0352] In addition, the fourth control transistor Ts6 may have, for example, a gate connected to the Q3 node, a first electrode (or source) receiving its corresponding second scan clock SCLK2, and a second electrode (or drain) connected to the third control transistor Ts5.

[0353] Furthermore, the fifth control transistor Ts7 may have, for example, a gate that receives its corresponding first scan clock SCLK1, a second electrode (or drain) to which a gate low voltage VGL is applied, and a first electrode (or source) connected to the sixth control transistor Ts8.

[0354] In addition, the sixth control transistor Ts8 may have, for example, a gate connected to the Q node, a first electrode (or source) receiving its corresponding first scan clock SCLK1, and a second electrode (or drain) connected to the fifth control transistor Ts7.

[0355] Furthermore, the seventh control transistor Ts9 may have, for example, a gate to which a gate low voltage VGL is applied, a first electrode (or source) connected to the node between the fifth control transistor Ts7 and the sixth control transistor Ts8, and a second electrode (or drain) connected to the Q3 node.

[0356] Furthermore, the eighth control transistor Ts10 may have, for example, a gate connected to the Q node, a first electrode (or source) receiving its corresponding second scan clock SCLK2, and a second electrode (or drain) connected to the Q capacitor CQ.

[0357] Simultaneously, the Q capacitor CQ can be connected between the Q node and the eighth control transistor Ts10, and the QB capacitor CQB can be connected between the QB node and the source of the pull-down transistor Ts2. The Q3 capacitor C3 can be connected between the Q3 node and the nodes between the third control transistor Ts5 and the fourth control transistor Ts6. Here, the capacitance of each of the Q capacitor CQ and the QB capacitor CQB can be set to be greater than the capacitance of the Q3 capacitor C3. Furthermore, the capacitance of the Q3 capacitor C3 can be set to be greater than the capacitance of a pixel ( Figure 2 Storage capacitors in P) Figure 2 The capacitor (Cst).

[0358] The second scan level SSC2(n) configured as described above can shift the previous second scan signal SC2(n-1) according to the input scan clocks SCLK1 and SCLK2, and output the corresponding second scan signal SC2(n) to the corresponding second scan line.

[0359] Therefore, the second scan level SSC2(n) of the nth horizontal line can receive scan clocks SCLK1 and SLCK2 to perform signal output operations.

[0360] Simultaneously, the positions of the first scan clock SCLK1 and the second scan clock SCLK2 input to the second scan level SSC2 located at the (n-1)th and (n+1)th horizontal lines (which are located before and after the nth horizontal line) can be reversed compared to the positions of the first scan clock SCLK1 and the second scan clock SCLK2 input to the second scan level SSC2(n) at the nth horizontal line. For example, the second scan clock SCLK2 can be input to the first control transistor Ts3 of each of the (n-1)th and (n+1)th second scan levels SSC2, and the first scan clock SCLK1 can be input to the third control transistor Ts5 of each of the (n-1)th and (n+1)th second scan levels SSC2.

[0361] Regarding the second scan level SSC2 configured as described above, in the first example, the reset circuit RC can be connected to the Q2 node, and in the second example, the reset circuit RC can be connected to the Q node.

[0362] In this regard, the reset circuit RC may be configured with: a first reset transistor Trst connected to the input terminal of which receives a gate high voltage VGH as a reset voltage; and an auxiliary transistor Tb connected in series with the first reset transistor Trst and outputting a reset voltage.

[0363] Here, the auxiliary transistor Tb can be connected to the Q2 node in the first example, and to the Q node in the second example.

[0364] The Q node and Q2 node can be reset through the reset circuit RC connected in this way.

[0365] For example, as described in the first to third embodiments, when a reset signal RST, which is in a high state (i.e., a gate high voltage VGH), is applied to the reset circuit RC during the reset period, both the first reset transistor Trst and the auxiliary transistor Tb arranged in the reset circuit RC can be turned on. Therefore, the gate high voltage VGH, which is the reset voltage, can be transmitted to node Q2 in the first example and to node Q in the second example.

[0366] Therefore, Q2 node and Q node can be reset to the high state.

[0367] During the reset cutoff period following the reset period, as described in the first to third embodiments, the reset signal RST can be switched to a low state, i.e., the gate low voltage VGL, the first reset transistor Trst can be turned off, and the auxiliary transistor Tb can be turned on.

[0368] At this time, since the source voltage Vsn of the first reset transistor Trst can be set to (VGL+│Vthp│) or greater, the first reset transistor Trst can be stably kept in the off state.

[0369] Therefore, it can prevent the cutoff leakage current flowing through the first reset transistor Trst.

[0370] Therefore, the cutoff leakage current of the reset circuit RC can be prevented, thereby preventing leakage current from flowing into the Q2 node and Q node connected to the output terminal of the reset circuit RC, and thus it is unaffected by leakage current.

[0371] Therefore, the voltage of the Q2 node and Q node of the second scan stage SSC2 can be prevented from fluctuating abnormally due to leakage current, thereby preventing the failure of the second scan stage SSC2 due to leakage current and improving the reliability of the signal output from it.

[0372] In this embodiment, as described above, a second reset transistor Trst2 for resetting the QB node may be additionally provided in the second scan level SSC2.

[0373] The second reset transistor Trst2 can transmit a low gate voltage VGL to the QB node in response to the input reset signal RSTB during the reset period, so that the QB node can be reset to a low state. Here, for ease of explanation, the reset signal RST input to the first reset transistor Trst can be referred to as the first reset signal RST, and the reset signal RSTB input to the second reset transistor Trst2 can be referred to as the second reset signal RSTB.

[0374] At this time, the second reset signal RSTB can be a signal with the opposite phase to the first reset signal RST. In this case, during the reset period, the first reset signal RST can be high and the second reset signal RSTB can be low, and during the reset cutoff period, the first reset signal RST can be low and the second reset signal RSTB can be high.

[0375] The second reset transistor Trst2 may have, for example, a gate that receives the second reset signal RSTB, a second electrode (or drain) that receives the gate low voltage VGL, and a first electrode (or source) connected to the QB node.

[0376] Therefore, during the reset period, when the second reset signal RSTB, which is in a low state (i.e., gate low voltage VGL), is applied to the second reset transistor Trst2, the second reset transistor Trst2 can be turned on, so that the gate low voltage VGL, which is the reset voltage, can be transmitted to the QB node.

[0377] Additionally, during the reset cutoff period following the reset period, the second reset signal RSTB can be switched to a high state, i.e., the gate high voltage VGH, and the second reset transistor Trst2 can be turned off.

[0378] Therefore, in this embodiment, a second reset transistor Trst2 for resetting the QB node may be additionally provided.

[0379] In this regard, in the circuit configuration of the second scan level SSC2 in this embodiment, similar to the third embodiment, when the Q node is reset to a high state by the reset circuit RC, the QB node will not be reset due to the reset of the Q node.

[0380] However, in this embodiment, the second scan stage SSC2 may be separately provided with a second reset transistor Trst2 connected to the QB node, so that the QB node can be stably reset to a low state through the second reset transistor Trst2.

[0381] <Fifth Implementation Method>

[0382] Figure 16This is a view schematically illustrating a first example of the structure of a scan drive circuit employing a reset circuit according to a fifth embodiment of the present invention. Figure 17 This is a view schematically illustrating a second example of the structure of a scan drive circuit employing a reset circuit according to a fifth embodiment of the present invention.

[0383] In the following description, specific descriptions of configurations that are the same as or similar to those in the first to fourth embodiments described above may be omitted.

[0384] In this embodiment, the gate driving section may be provided with a reset circuit RC, wherein the P-type auxiliary transistor Tb is connected to the reset transistor Trst formed by the N-type oxide semiconductor, thereby preventing the cutoff leakage current of the reset transistor Trst, which is similar to the first to fourth embodiments.

[0385] Furthermore, regarding the node to which the reset circuit RC is connected in this embodiment, in Figure 16 In the first example, the reset circuit RC can be connected to the Q2 node in a manner similar to the first example of the first embodiment, the first example of the third embodiment, and the first example of the fourth embodiment, and in... Figure 17 In the second example, the reset circuit RC may be connected to the Q node in a manner similar to the second example of the second embodiment, the second example of the third embodiment, and the second example of the fourth embodiment.

[0386] Meanwhile, the gate drive circuit of this embodiment, which uses a reset circuit RC, can be configured with a structure different from that of the first to fourth embodiments.

[0387] Regarding this point, refer to Figure 16 and Figure 17 As an example of a gate drive circuit that applies a reset circuit RC, the configuration of a second scan drive circuit that generates the second scan signal SC2 is described.

[0388] The second scan drive circuit may include multiple second scan levels SSC2, which correspond to multiple second scan lines arranged in the display area and output corresponding second scan signals.

[0389] Regarding the configuration of the second scan level SSC2, the nth second scan level SCC2(n) is used as an example. The second scan level SCC2(n) may include an output unit OC and a control unit CCP that controls the output operation of the output unit OC.

[0390] In this regard, the output section OC may include, for example, a pull-up transistor (or Q transistor) Ts1, a pull-down transistor (or QB transistor) Ts2, and a Q capacitor CQ.

[0391] The control unit CCP may include, for example, transfer transistors TA and TA2, multiple control transistors Ts3 to Ts10, and capacitor C3 (Q3). Here, the multiple control transistors Ts3 to Ts10 may include, for example, the first to eighth control transistors (or the eighth to fifteenth transistors) Ts3 to Ts10. For ease of explanation, transfer transistor TA may be referred to as the first transfer transistor TA, and transfer transistor TA2 may be referred to as the second transfer transistor TA2.

[0392] In addition, the control unit CCP may include a reset circuit RC.

[0393] As described above, in the first example of this embodiment, the reset circuit RC can be connected to node Q2 in the second scan level SSC2. In the second example of this embodiment, the reset circuit RC can be connected to node Q in the second scan level SSC2.

[0394] In addition, the control unit CCP may include a reset transistor Trst2 connected to the QB node and used to reset the QB node.

[0395] Here, for ease of explanation, the reset transistor Trst connected to the Q node and resetting the Q node in the reset circuit RC can be referred to as the first reset transistor Trst, and the reset transistor Trst2 connected to the QB node and resetting the QB node can be referred to as the second reset transistor Trst2.

[0396] In addition to the reset circuit RC and the second reset transistor Trst2, each of the plurality of transistors Ts1 to Ts10, TA and TA2 constituting the second scan stage SSC2(n) can be a P-type transistor or an N-type transistor. Furthermore, each of transistors Ts1 to Ts10, TA and TA2 can be a transistor using oxide semiconductor or a transistor using polysilicon.

[0397] In this embodiment, the case in which the transistors Ts1 to Ts10, TA and TA2 are configured as P-type transistors including a polysilicon layer is used as an example.

[0398] Meanwhile, in this embodiment, the second reset transistor Trst2 can be configured as a P-type transistor including a polysilicon layer.

[0399] The polysilicon P-type transistors Ts1 to Ts10, TA, TA2, and Trst2 can, for example, be used with pixels ( Figure 2 P-type transistors in polysilicon (e.g., P) Figure 2 The same structure is formed for T2 to T6 and DT.

[0400] The pull-up transistor Ts1 of the output section OC can drive the output terminal N0 of the second scan stage SSC2(n) in response to a signal applied to its gate at the Q node. Furthermore, the pull-down transistor Ts2 can drive the output terminal NO in response to a signal applied to its gate at the QB node.

[0401] Meanwhile, the first transfer transistor TA of the control unit CCP can transfer the charge of the Q2 node to the Q node in response to the low gate voltage VGL applied to its gate.

[0402] The first control transistor Ts3 can provide the previous second scan signal SC2(n-1) (which is the output signal of the previous second scan stage SSC2) to the Q2 node in response to its corresponding second scan clock SCLK2. The P-type first control transistor Ts3 may have, for example, a gate that receives the second scan clock SCLK2, a first electrode (or source) that receives the previous second scan signal SC2(n-1), and a second electrode (or drain) connected to the Q2 node.

[0403] Here, the previous second scan signal SC2(n-1) applied to the first control transistor Ts3 can be used as a start signal (or carry signal). At the same time, when the second scan level SSC2(n) is the scan level of the first horizontal line, the start signal provided from the timing control unit can be input to the first control transistor Ts3 to start its output operation.

[0404] Furthermore, the second control transistor Ts4 may have, for example, a gate connected to the Q2 node, a first electrode (or source) to which a gate high voltage VGH is applied, and a second electrode (or drain) connected to the QB node.

[0405] Furthermore, the third control transistor Ts5 may have, for example, a gate to which its corresponding first scan clock SCLK1 is applied, a first electrode (or source) connected to the fourth control transistor Ts6, and a second electrode (or drain) connected to the QB node.

[0406] Furthermore, the fourth control transistor Ts6 may have, for example, a gate connected to the Q3 node, a first electrode (or source) to which its corresponding first scan clock SCLK1 is applied, and a second electrode (or drain) connected to the third control transistor Ts5.

[0407] Furthermore, the fifth control transistor Ts7 may have, for example, a gate to which its corresponding second scan clock SCLK2 is applied, a second electrode (or drain) to which a gate low voltage VGL is applied, and a first electrode (or source) connected to the Q3 node.

[0408] Furthermore, the sixth control transistor Ts8 may have, for example, a gate connected to the Q2 node, a first electrode (or source) to which its corresponding second scan clock SCLK2 is applied, and a second electrode (or drain) connected to the second transfer transistor TA2.

[0409] In addition, the second transfer transistor TA2 may have, for example, a gate to which a low gate voltage VGL is applied, a first electrode (or source) connected to the sixth control transistor Ts8, and a second electrode (or drain) connected to the Q3 node.

[0410] In addition, the seventh control transistor Ts9 may have, for example, a gate connected to the Q3 node, a first electrode (or source) to which a gate high voltage VGH is applied, and a second electrode (or drain) connected to the Q capacitor CQ.

[0411] Furthermore, the eighth control transistor Ts10 may have, for example, a gate connected to the Q node, a first electrode (or source) receiving its corresponding first scan clock SCLK1, and a second electrode (or drain) connected to the Q capacitor CQ.

[0412] Simultaneously, capacitor CQ can be connected between the Q node and the nodes between the seventh control transistor Ts9 and the eighth control transistor Ts10. Capacitor C3 can be connected between the Q3 node and the nodes between the third control transistor Ts5 and the fourth control transistor Ts6. Here, the capacitance of capacitor CQ can be set to be greater than the capacitance of capacitor C3. Furthermore, the capacitance of capacitor C3 can be set to be greater than the capacitance of a pixel ( Figure 2 Storage capacitors in P) Figure 2 The capacitor (Cst).

[0413] The second scan level SSC2(n) configured as described above can shift the previous second scan signal SC2(n-1) according to the input scan clocks SCLK1 and SCLK2, and output the corresponding second scan signal SC2(n) to the corresponding second scan line.

[0414] Therefore, the second scan stage SSC2(n) of the nth horizontal line can receive scan clocks SCLK1 and SLCK2 to perform signal output operations.

[0415] Simultaneously, the positions of the first and second scan clocks SCLK1 and SCLK2 input to the second scan level SSC2 located at the (n-1)th and (n+1)th horizontal lines (which are located before and after the nth horizontal line) can be reversed with the positions of the first and second scan clocks SCLK1 and SCLK2 input to the second scan level SSC2(n) located at the nth horizontal line. For example, the first scan clock SCLK1 can be input to the first control transistor Ts3 of each of the (n-1)th and (n+1)th second scan levels SSC2, and the second scan clock SCLK2 can be input to the third control transistor Ts5 of each of the (n-1)th and (n+1)th second scan levels SSC2.

[0416] Regarding the second scan level SSC2 configured as described above, in the first example, the reset circuit RC can be connected to the Q2 node, and in the second example, the reset circuit RC can be connected to the Q node.

[0417] In this regard, the reset circuit RC may be configured with: a first reset transistor Trst connected to the input terminal of which receives a gate high voltage VGH as a reset voltage; and an auxiliary transistor Tb connected in series with the first reset transistor Trst and outputting a reset voltage.

[0418] Here, the auxiliary transistor Tb can be connected to node Q2 in the first example and to node Q in the second example.

[0419] The Q node and Q2 node can be reset through the reset circuit RC connected in this way.

[0420] For example, as described in the first to fourth embodiments, when a reset signal RST, which is in a high state (i.e., a gate high voltage VGH), is applied to the reset circuit RC during the reset period, both the first reset transistor Trst and the auxiliary transistor Tb arranged in the reset circuit RC can be turned on. Therefore, the gate high voltage VGH, which is the reset voltage, can be transferred to node Q2 in the first example and to node Q in the second example.

[0421] Therefore, nodes Q2 and Q can be reset to a high state.

[0422] During the reset cutoff period following the reset period, as described in the first to fourth embodiments, the reset signal RST can be switched to a low state, i.e., the gate low voltage VGL, the first reset transistor Trst can be turned off, and the auxiliary transistor Tb can be turned on.

[0423] At this time, the source voltage Vsn of the first reset transistor Trst can be set to (VGL+│Vthp│) or higher, thereby stably maintaining the cut-off state of the first reset transistor Trst.

[0424] Therefore, it can prevent the cutoff leakage current flowing through the first reset transistor Trst.

[0425] Therefore, the cutoff leakage current of the reset circuit RC can be prevented, thereby preventing leakage current from flowing into the Q2 node and Q node connected to the output terminal of the reset circuit RC, and thus it is unaffected by leakage current.

[0426] Therefore, the voltage of the Q2 node and Q node of the second scan stage SSC2 can be prevented from fluctuating abnormally due to leakage current, thereby preventing the failure of the second scan stage SSC2 due to leakage current and improving the reliability of the signal output from it.

[0427] In this embodiment, as described above, a second reset transistor Trst2 for resetting the QB node may be additionally provided in the second scan level SSC2.

[0428] This second reset transistor Trst2 can transmit a low gate voltage VGL to the QB node in response to the input reset signal RSTB during the reset period, so that the QB node can be reset to a low state. Here, for ease of explanation, the reset signal RST input to the first reset transistor Trst is referred to as the first reset signal RST, and the reset signal RSTB input to the second reset transistor Trst2 can be referred to as the second reset signal RSTB.

[0429] At this time, the second reset signal RSTB can be a signal with the opposite phase to the first reset signal RST. In this case, during the reset period, the first reset signal RST can be high and the second reset signal RSTB can be low, and during the reset cutoff period, the first reset signal RST can be low and the second reset signal RSTB can be high.

[0430] The second reset transistor Trst2 may have, for example, a gate that receives the second reset signal RSTB, a second electrode (or drain) that receives the gate low voltage VGL, and a first electrode (or source) connected to the QB node.

[0431] Therefore, during the reset period, when the second reset signal RSTB, which is in a low state (i.e., gate low voltage VGL), is applied to the second reset transistor Trst2, the second reset transistor Trst2 can be turned on, so that the gate low voltage VGL, which is the reset voltage, can be transmitted to the QB node.

[0432] Additionally, during the reset cutoff period following the reset period, the second reset signal RSTB can be switched to a high state, i.e., the gate high voltage VGH, and the second reset transistor Trst2 can be turned off.

[0433] Therefore, in this embodiment, a second reset transistor Trst2 for resetting the QB node may be additionally provided.

[0434] In this regard, in the circuit configuration of the second scan level SSC2 in this embodiment, similar to the third and fourth embodiments, when the Q node is reset to a high state by the reset circuit RC, the QB node will not be reset due to the reset of the Q node.

[0435] However, in this embodiment, the second scan stage SSC2 may be separately provided with a second reset transistor Trst2 connected to the QB node, so that the QB node can be stably reset to a low state through the second reset transistor Trst2.

[0436] Meanwhile, in the above embodiments, various scan drive circuits to which the reset circuit can be applied are given as examples. The reset circuit can be applied to various drive circuits that require reset.

[0437] As described above, in embodiments of the present invention, by adding an auxiliary transistor connected in series with the reset transistor to the reset circuit, the source of the reset transistor can stably have a voltage higher than the gate voltage during the reset off period, thereby stably ensuring the off state of the reset transistor.

[0438] Therefore, the cutoff leakage current of the reset circuit can be prevented, thereby preventing leakage current from flowing into the Q node connected to the output terminal of the reset circuit, and thus it is unaffected by leakage current.

[0439] Therefore, it can prevent the voltage of the Q node of the stage that outputs the gate signal from fluctuating abnormally due to leakage current, thereby preventing stage failures caused by leakage current and improving the reliability of the signal output from it.

[0440] Furthermore, in embodiments of the present invention, a reset transistor for resetting the QB node may be additionally provided. This reset transistor allows the QB node to be stably reset to a low state.

[0441] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from its spirit or scope. Therefore, this invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: Display panel including pixels; The pixel contains a light-emitting diode and a plurality of transistors electrically connected to the light-emitting diode; as well as A gate driving circuit, the gate driving circuit including a stage configured to output a gate signal to one of the plurality of transistors, The levels mentioned above include: Pull-up transistors and pull-down transistors, wherein the gates of the pull-up transistors and the pull-down transistors are respectively connected to the Q node and the QB node; The transfer transistor connected between the Q node and the Q2 node; and A reset circuit connected to the Q node or the Q2 node. The reset circuit includes: An N-type reset transistor configured to receive a high gate voltage; and A P-type auxiliary transistor is connected between the N-type reset transistor and the Q node or the Q2 node.

2. The display device of claim 1, wherein the reset transistor comprises an oxide semiconductor, and the gate of the reset transistor is configured to receive a reset signal.

3. The display device of claim 1, wherein the auxiliary transistor comprises polysilicon, and the gate of the auxiliary transistor is configured to receive a gate low voltage.

4. The display device of claim 1, wherein the stage further comprises a first control transistor connected to the Q2 node, configured to receive a carry signal and having a gate configured to receive a gate clock.

5. The display device of claim 4, wherein the Q2 node is electrically coupled to the gate clock.

6. The display device of claim 1, wherein the stage further comprises a P-type second reset transistor connected to the QB node and configured to receive a gate low voltage.

7. The display device of claim 6, wherein the reset transistor is subjected to a first reset signal, and the second reset transistor is subjected to a second reset signal, the second reset signal having an opposite phase to the first reset signal.

8. The display device according to claim 1, wherein the pull-up transistor, the pull-down transistor and the transfer transistor are P-type transistors comprising polysilicon.

9. The display device according to claim 4, wherein the stage further comprises: The P-type second control transistor has a gate connected to the Q2 node, a source configured to receive a high gate voltage, and a drain connected to the QB node. as well as The N-type third control transistor has a gate connected to the Q node, a source configured to receive a low gate voltage, and a drain connected to the QB node.

10. The display device of claim 1, wherein the stage further comprises a Q capacitor connected between the Q node and the source of the pull-up transistor.

11. The display device of claim 1, wherein the stage further comprises a QB capacitor connected between the QB node and the source of the pull-down transistor.

12. A driving circuit, comprising: A transistor having a source or drain connected to a node; as well as A reset circuit, the reset circuit being connected to the node, The reset circuit includes: An N-type reset transistor, configured to receive a gate high voltage; as well as A P-type auxiliary transistor is connected between the N-type reset transistor and the node.

13. The driving circuit of claim 12, wherein the reset transistor comprises an oxide semiconductor, and the gate of the reset transistor is configured to receive a reset signal.

14. The driving circuit of claim 12, wherein the auxiliary transistor comprises polysilicon, and the gate of the auxiliary transistor is configured to receive a gate low voltage.

15. The driving circuit of claim 12, further comprising a control transistor connected to the node and having a gate configured to receive a clock signal.

16. A driving circuit, comprising: Output section; as well as The control unit is configured to control the output operation of the output unit. The output section includes a pull-up transistor and a pull-down transistor, the gate of the pull-up transistor and the gate of the pull-down transistor being connected to the Q node and the QB node, respectively; The control unit includes a reset circuit, which includes an N-type reset transistor configured to receive a gate high voltage. And a P-type auxiliary transistor connected between the N-type reset transistor and the Q node or Q2 node.

17. The driving circuit of claim 16, wherein the control unit further includes a transfer transistor connected between the Q node and the Q2 node.

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