High-reliability network-on-chip circuit architecture

Abstract

The invention discloses a high-reliability network-on-chip circuit architecture which is composed of three layers of networks-on-chip, one layer of network-on-chip is used for normal data transmission, the other two layers of network-on-chip are used for timeout retransmission, and when a master device sends a request and does not receive a response at specified time, a timeout retransmission mechanism is triggered. And the data retransmitted overtime can automatically change an on-chip network path for data transmission. Each layer of network of the network-on-chip circuit adopts a 4 * 4 2D Mesh NoC topological structure, has good expansibility, and can well prevent deadlock in combination with a classical XY-dimensional sequence routing algorithm. The network-on-chip is composed of a router and an arbiter, four ports of the router are used for cascade connection, and one port of the router is connected with a local device. The three-layer network-on-chip carries out data interaction through the distribution arbiter, it is guaranteed that data of the three-layer network-on-chip can be arbitrated to one path to be provided for local equipment, data of the local equipment is distributed to the appointed network-on-chip, and it is guaranteed that the three-layer network-on-chip can share the same inter-chip bus.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and in particular to a high-reliability on-chip network circuit architecture. Background Technology

[0002] With the increasing operating frequency of integrated circuits and the improvement of manufacturing processes, on-chip network circuits are becoming increasingly sensitive to faults. To cope with the impact of complex environments, ensure the safety of core scenarios, and control costs throughout the entire lifecycle, it is crucial to address these challenges. Environments with strong radiation, high temperatures, and strong electromagnetic interference can easily affect the normal operation of on-chip network circuits, leading to transient or permanent failures in the network pathways. Furthermore, in fields such as automotive electronics, aerospace, and medical equipment, where the reliability requirements for integrated circuits are extremely high, chip failure or erroneous transmission can pose a fatal risk to the system. Therefore, fault-tolerant design of on-chip network circuits is necessary to improve their anti-interference capabilities. Summary of the Invention

[0003] The purpose of this invention is to provide a highly reliable on-chip network circuit architecture to solve the problems in the background art.

[0004] To address the aforementioned technical problems, this invention provides a high-reliability on-chip network architecture, consisting of three on-chip network layers: a zeroth network path, a first network path, and a second network path; the zeroth network path is used for normal data transmission, while the first and second network paths are used for timeout retransmission. The single-layer on-chip network comprises 16 routers, employing a 4x4 2D Mesh topology. These routers are designed based on a dimension-splitting router framework, dividing a functional router design into two single-dimensional routers. The router consists of three parts: a three-port X sub-router, a three-port Y sub-router, and an intermediate buffer unit connecting the two. When the router's local port sends data, it sends the data to the X sub-router and transmits it in the X-dimensional direction. When data needs to be transmitted through the Y sub-router in the Y-dimensional direction, it must enter the Y sub-router through the intermediate buffer unit, and the data is only transmitted in the Y-dimensional direction after entering the Y sub-router. When the data reaches the destination router node in the Y-dimensional direction, the Y sub-router sends it to the local node for output. The on-chip network (CNIC) transmits data using an event packet format that includes request and response event packets. Control information and data to be transmitted are encoded in a unified format to form a complete event packet. The CNIC circuit then segments the event packet into micro-chips and sends them sequentially. The transmission control and integrity of the event packets are managed by additional circuitry that parses and controls the data within the CNIC circuitry. The CNIC improves reliability through a combination of various fault-tolerance and error-detection mechanisms. Triple-modular redundancy is used for critical routing control information in the event packets to enhance anti-interference capabilities. Parity checking is used for the carried data information to ensure data transmission correctness. A timeout retransmission mechanism further enhances the CNIC's fault tolerance after a timeout retransmission.

[0005] In one implementation, the event packet is routed from the source router node to the destination router node, and after verification by the destination router node, a response event packet is returned to the source router node to indicate that the request has been approved. If the source router node does not receive a response packet from the destination router node within a specified time, it indicates that the request has failed. The source router node will perform a first timeout retransmission through the first on-chip network path. If it still does not receive a response packet within the specified time, the source router node will perform a second timeout retransmission through the second network path.

[0006] In one implementation, the microchip is defined as data transmitted on a data link in an on-chip network within one clock cycle. Each event packet consists of several microchips. All event packets include a header microchip marking the start position of the event packet, several individual microchips, and a tail microchip marking the end position of the event packet. The highest 6 bits of each microchip are used to store its tri-modal redundancy microchip type code.

[0007] In one implementation, the X sub-router has three input channels: a west input channel, an east input channel, and a local input channel; and three output channels: a west output channel, an east output channel, and a middle output channel. Each input channel consists of a channel buffer unit and a channel control unit. The channel buffer unit mainly performs temporary data storage and buffering, while the channel control unit mainly performs event packet distribution, sending the event packets to the designated output port according to the control information of the event packets. Each output channel consists of an arbitrator. Routers with the same address at each layer of the on-chip network interact with each other through the arbitrator. One end of the arbitrator is connected to the local input and output channels of the Layer 3 on-chip network router, and the other end is connected to the local device. The Y-sub-router also has three input channels: a south input channel, a north input channel, and a middle input channel; and three output channels: a south output channel, a north output channel, and a local output channel; the internal structure of each channel of the Y-sub-router is the same as that of the X-sub-router.

[0008] In one implementation, the arbitrator is used to allocate data to a designated on-chip network path according to control information, and to arbitrate data from three on-chip network paths into one path according to priority for provision to a local device.

[0009] In one implementation, the arbitrator employs a round-robin arbitration method to achieve the arbitration function, thereby ensuring the stability and fairness of the arbitration.

[0010] This invention provides a high-reliability on-chip network circuit architecture that improves the anti-interference capability of the on-chip network circuit by combining request-based timeout retransmission with error detection and correction mechanisms such as triple modulus redundancy, parity check, and timeout retransmission. It has good fault tolerance performance for single-event upsets, multiple-event upsets, and on-chip network link failures, greatly improving the reliability of the on-chip network circuit and reducing its total life cycle cost. Attached Figure Description

[0011] Figure 1 This is a structural diagram of the X sub-router; Figure 2 This is a structural diagram of the Y-sub router; Figure 3 This is a high-reliability on-chip network circuit architecture diagram; Figure 4 It is an event packet format diagram. Detailed Implementation

[0012] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the high-reliability on-chip network circuit architecture proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0013] The structure of the X sub-router is as follows: Figure 1 As shown, it internally has three input channels: a west input channel, an east input channel, and a local input channel; and three output channels: a west output channel, an east output channel, and a middle output channel. Each input channel consists of a channel buffer unit and a channel controller. The channel buffer unit mainly implements temporary data storage and buffering; the channel controller mainly implements event packet distribution, sending event packets to the designated output port according to the control information of the event packets. Each output channel consists of an arbitrator, using a round-robin arbitration method to ensure the stability and fairness of arbitration, realizing the arbitration output function of multi-port data. The internal architecture of the Y sub-router is as follows. Figure 2As shown, it also has three input channels: south input channel, north input channel, and middle input channel; and three output channels: south output channel, north output channel, and local output channel. The internal structure and function of each channel of the Y sub-router are the same as those of the X sub-router.

[0014] The high-reliability on-chip network circuit architecture provided by this invention is as follows: Figure 3 As shown, to avoid deadlock and improve the anti-interference capability of the on-chip network, the single-layer on-chip network is directly copied twice, creating three physical on-chip networks, forming the final three-layer on-chip network architecture. Each layer of the on-chip network adopts a 4*4 2D Mesh topology. One layer of the on-chip network is fixed for normal data transmission, while the other two layers are used for timeout retransmission. Routers with the same address in each layer of the on-chip network interact with each other through an arbitrator. One end of the arbitrator is connected to the local input and output channels of the routers with the same address in the three layers of the on-chip network, and the other end is connected to the local device. The arbitrator selects the on-chip network path based on the control information in the event packet, and then, based on the round-robin arbitration method, arbitrates the three data paths to one path according to the priority of the local output channel of the three layers of the on-chip network to provide to the local device.

[0015] Data is transmitted using an event packet format. Control information and data to be transmitted are encoded into a complete event packet using a unified format, thus offering good scalability and strong adaptability, making it suitable for systems with a large number of cores. The on-chip network circuit segments the event packet into micro-chips and sends them sequentially. The transmission control and integrity of the event packet (including request and response event packets) are managed and controlled by additional circuitry that parses and controls the data within the on-chip network circuitry. Figure 4 As shown, a chip is defined as the data transmitted on a data link in an on-chip network within one clock cycle. Each event packet consists of several chips. All event packets contain a header chip marking the start of the event packet, several individual chips, and a tail chip marking the end of the event packet. The highest 6 bits of each chip are used to store its tri-modal redundancy chip type code.

[0016] The header micro-chip stores control information for the current event packet (source router ID, destination router ID, on-chip network number, micro-chip type, etc.), while the body micro-chip carries the valid data payload. An event packet contains one header micro-chip, one tail micro-chip, and multiple body micro-chips.

[0017] The fault tolerance mechanism of the high-reliability on-chip network circuit architecture encodes request event packets and decodes response event packets on the local device connected to the source router; and encodes response event packets and decodes request event packets on the local device connected to the destination router. The specific workflow is as follows: (1) Local device of source router: The control information of the event packet is encoded with triple redundancy and the data information is grouped into packets by setting a parity bit for every 8 bits, and output to the local input port of source router. At the same time, the request event packet is cached in the retransmission buffer and the next request event packet is not sent before the retransmission buffer is released.

[0018] (2) Source router allocation arbitrator: Based on the corresponding network path information in the request event packet, the request event packet is allocated to the specified network path (network path 0, network path 1, network path 2) for routing transmission.

[0019] (3) On-chip network: The transmission of request event packets in the on-chip network follows the XY dimension routing method. That is, the routing is first performed in the X dimension of the on-chip network. When the X coordinate of the destination router address of the request event packet is the same as the X coordinate of the current routing node, the routing is switched to the Y dimension. After entering the Y dimension, it can no longer enter the X dimension routing, and finally arrives at the destination router node.

[0020] (4) The destination router’s allocation arbitrator: It uses a round-robin arbitration method to dynamically determine the output priority of request event packets from network path 0, network path 1 and network path 2, and outputs the data on the network path with the higher priority to its local device.

[0021] (5) The local device of the destination router: decodes the received request event packet. If the request event packet passes the verification, it returns a response event packet to the local device of the source router to notify it that the request was successful and the next transmission can proceed. The network path information of the response event packet is the same as that of the request event packet.

[0022] (6) Local device of the source router: If a valid response event packet is received before the retransmission timeout, the retransmission buffer is released and the next data transmission begins; if no response event packet is received after the retransmission timeout, the first retransmission is triggered, the cached request event packet is retrieved from the retransmission buffer and its network path information is changed, and then output to the local input port of the source router. After the first retransmission is triggered, if a valid response event packet is received before the retransmission timeout, the retransmission buffer is released and the next data transmission begins. If no response event packet is received after the first retransmission timeout, the second retransmission is triggered. The second retransmission still needs to change the network path information of the request event packet to achieve polling of the three network paths (network path 0, network path 1, and network path 2) until the retransmission is successful or both retransmissions fail, the retransmission buffer is released and the next data transmission begins.

[0023] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-reliability on-chip network circuit architecture, characterized in that, It consists of three on-chip networks: a zeroth network path, a first network path, and a second network path; the zeroth network path is used for normal data transmission, and the first and second network paths are used for timeout retransmission; The single-layer on-chip network comprises 16 routers, employing a 4x4 2D Mesh topology. These routers are designed based on a dimension-splitting router framework, dividing a functional router design into two single-dimensional routers. The router consists of three parts: a three-port X sub-router, a three-port Y sub-router, and an intermediate buffer unit connecting the two. When the router's local port sends data, it sends the data to the X sub-router and transmits it in the X-dimensional direction. When data needs to be transmitted through the Y sub-router in the Y-dimensional direction, it must enter the Y sub-router through the intermediate buffer unit, and the data is only transmitted in the Y-dimensional direction after entering the Y sub-router. When the data reaches the destination router node in the Y-dimensional direction, the Y sub-router sends it to the local node for output. The on-chip network (CNIC) transmits data using an event packet format that includes request and response event packets. Control information and data to be transmitted are encoded in a unified format to form a complete event packet. The CNIC circuit then segments the event packet into micro-chips and sends them sequentially. The transmission control and integrity of the event packets are managed by additional circuitry that parses and controls the data within the CNIC circuitry. The CNIC improves reliability through a combination of various fault-tolerance and error-detection mechanisms. Triple-modular redundancy is used for critical routing control information in the event packets to enhance anti-interference capabilities. Parity checking is used for the carried data information to ensure data transmission correctness. A timeout retransmission mechanism further enhances the CNIC's fault tolerance after a timeout retransmission.

2. The high-reliability on-chip network circuit architecture as described in claim 1, characterized in that, The event packet is routed from the source router node to the destination router node, and after verification by the destination router node, a response event packet is returned to the source router node to indicate that the request has been approved; If the source router node does not receive a response packet from the destination router node within the specified time, it means that the request failed. The source router node will perform a first timeout retransmission through the first on-chip network path. If it still does not receive a response packet within the specified time, the source router node will perform a second timeout retransmission through the second network path.

3. The high-reliability on-chip network circuit architecture as described in claim 2, characterized in that, The microchip is defined as the data transmitted on a data link in the on-chip network within one clock cycle. Each event packet consists of several microchips. All event packets contain a header microchip that marks the start position of the event packet, several individual microchips, and a tail microchip that marks the end position of the event packet. The highest 6 bits of each microchip are used to store its microchip type code after three-modal redundancy.

4. The high-reliability on-chip network circuit architecture as described in claim 1, characterized in that, The X-sub-router has three input channels: a west input channel, an east input channel, and a local input channel; and three output channels: a west output channel, an east output channel, and a middle output channel. Each input channel consists of a channel buffer unit and a channel control unit. The channel buffer unit mainly performs temporary data storage and buffering, while the channel control unit mainly performs event packet distribution, sending the event packets to the designated output port according to the control information of the event packets. Each output channel consists of an arbitrator. Routers with the same address at each layer of the on-chip network interact with each other through the arbitrator. One end of the arbitrator is connected to the local input and output channels of the Layer 3 on-chip network router, and the other end is connected to the local device. The Y-sub-router also has three input channels: a south input channel, a north input channel, and a middle input channel; and three output channels: a south output channel, a north output channel, and a local output channel; the internal structure of each channel of the Y-sub-router is the same as that of the X-sub-router.

5. The high-reliability on-chip network circuit architecture as described in claim 4, characterized in that, The arbitrator is used to allocate data to designated on-chip network paths according to control information, and to arbitrate data from three on-chip network paths into one path according to priority for provision to the local device.

6. The high-reliability on-chip network circuit architecture as described in claim 4, characterized in that, The arbitrator employs a round-robin arbitration method to achieve its arbitration function, thereby ensuring the stability and fairness of the arbitration process.

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