Super junction type power device

Abstract

The super junction type power device at least comprises a first cell and a second cell, and each of the first cell and the second cell comprises a substrate of a first doping type; the epitaxial layer of the first doping type is located on the substrate; the doping column of the second doping type is located in the epitaxial layer; the gate structure is located on the epitaxial layer, and the gate structure comprises a gate dielectric layer located on the epitaxial layer and a gate conductor located on the gate dielectric layer; the body region of the second doping type is located in the epitaxial layer and extends below the gate structure to form a channel; the source region of the first doping type is located in the body region; and a plurality of doped columns of a second doping type, wherein the doped columns extend from the bottom of the body region to the direction of the substrate. Wherein the first cell and the second cell have different threshold voltages.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a superjunction power device. Background Technology

[0002] Superjunction Trench MOS is an advanced semiconductor device that combines the features of superjunction technology and trench structure. It performs exceptionally well in high-voltage applications, exhibiting advantages such as low conduction losses, high current drive capability, and fast switching speed. It has broad application prospects in the field of power electronics.

[0003] EMI (Electromagnetic Interference) refers to the electromagnetic energy generated by electronic devices during operation. This energy may interfere with other electronic devices in the vicinity, thus affecting their normal operation. In applications, superjunction Trench MOSFETs, due to their extremely fast switching speed, generate large dv / dt and di / dt during switching. These rapidly changing voltages and currents excite surrounding electromagnetic fields, thus causing EMI problems. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a superjunction power device that reduces the switching speed of the superjunction trench and optimizes its EMI characteristics.

[0005] One aspect of this application provides a superjunction power device, comprising at least a first cell and a second cell, each comprising: a substrate of a first doping type; an epitaxial layer of the first doping type located on the substrate; doped pillars of the second doping type located in the epitaxial layer; a gate structure located on the epitaxial layer, the gate structure comprising a gate dielectric layer located on the epitaxial layer and a gate conductor located on the gate dielectric layer; a body region of the second doping type located in the epitaxial layer and extending below the gate structure to form a channel; a source region of the first doping type located in the body region; and a plurality of doped pillars of the second doping type extending from the bottom of the body region toward the substrate; wherein the first cell and the second cell have different threshold voltages. Attached Figure Description

[0006] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 A cross-sectional view of a superjunction power device according to an embodiment;

[0008] Figure 2a A top view of a superjunction power device according to a first embodiment of this application is shown;

[0009] Figure 2b It shows Figure 2a A cross-sectional view of the first cell in the middle;

[0010] Figure 2c It shows Figure 2a Cross-sectional view of the second cell in the middle;

[0011] Figure 3 A top view of the superjunction power device provided in the fourth embodiment of this application is shown;

[0012] Figure 4 A top view of the superjunction power device provided in the fifth embodiment of this application is shown;

[0013] Figure 5 A top view of the superjunction power device provided in the sixth embodiment of this application is shown;

[0014] Figure 6 A top view of the superjunction power device provided in the seventh embodiment of this application is shown. Detailed Implementation

[0015] In the following figures, the same elements are represented by similar reference numerals. For clarity, the parts in the figures are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0016] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0017] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0018] Unless otherwise specified below, the various parts of a semiconductor device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as metal layers, doped polysilicon layers, or stacked gate conductors including metal layers and doped polysilicon layers, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or a material with a dielectric constant greater than that of SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0019] Figure 1 This is a cross-sectional view of a superjunction power device according to an embodiment. Figure 1 As shown, the superjunction power device 100 includes a substrate 101, an epitaxial layer 111 on the substrate 101, a gate dielectric layer 113 on the epitaxial layer 111, a gate conductor 115 on the gate dielectric layer 113, a body region 116 in the epitaxial layer 111, a source region 119 in the body region 116, and a contact region 118 in the body region 116 and adjacent to the source region 119.

[0020] The superjunction power device 100 includes a plurality of doped pillars 120 located in an epitaxial layer 111. The plurality of doped pillars 120 are separated from each other and isolated from each other by the epitaxial layer 111. The epitaxial layer 111 between the doped pillars 120 and adjacent doped pillars 120 is arranged alternately in the horizontal direction. The doped pillars 120 extend from the bottom of the body region 116 in a direction away from the body region 116.

[0021] The superjunction trench MOSFET 100 includes an interlayer dielectric layer 117, a drain electrode 121, and a source electrode 122. The drain electrode 121 is located on the second surface of the substrate 101 and is electrically connected to the substrate 101. The source electrode 122 is located above the interlayer dielectric layer 117 and extends through the interlayer dielectric layer 117 to the surfaces of the contact region 118 and the source region 119, and is electrically connected to the contact region 118 and the source region 119. The second surface of the substrate 101 is opposite to the first surface of the substrate 101.

[0022] The switching speed of the superjunction power device 100 is too fast, and the changes in its dv / dt and di / dt are extremely rapid, making it a key source of electric and magnetic field coupling. In actual switching processes, this can trigger more severe voltage and current oscillations, and applications will face more severe EMI (Electromagnetic Interference) noise challenges.

[0023] Based on this, embodiments of this application provide a superjunction power device, which includes at least a first cell and a second cell, wherein the first cell and the second cell have different threshold voltages Vth, so that the cell with a smaller threshold voltage Vth is turned on first, while the cell with a larger threshold voltage Vth is turned on relatively later, avoiding all cells in the active region from being turned on at the same time, effectively reducing the transconductance Gf during the device turn-on process, and dynamically adjusting di / dt, which is beneficial to improving the EMI performance of the device.

[0024] Figure 2a A top view of a superjunction power device according to a first embodiment of this application is shown; Figure 2b It shows Figure 2a A cross-sectional view of the first cell in the middle; Figure 2c It shows Figure 2a A cross-sectional view of the second cell. (See diagram below.) Figures 2a to 2c As shown, the active region of the superjunction power device 200 includes a first region A and a second region B. A first cell 200a is formed in the first region A, and a second cell 200b is formed in the second region B. The first cell 200a and the second cell 200b have different threshold voltages Vth.

[0025] Each cell in the first cell 200a and the second cell 200b includes a substrate 201 and an epitaxial layer 211 located on the substrate 201. The substrate 201 serves as the drain region of the superjunction power device 100 and is of the first doping type. The epitaxial layer 211 is located on the substrate 201 and has the same first doping type as the substrate 201, but is lightly doped relative to the substrate 201. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. Implanting an N-type dopant, such as P or As, into the semiconductor layer can form an N-type semiconductor layer. Doping a P-type dopant, such as B, into the semiconductor layer can form a P-type semiconductor layer. In this embodiment, the first doping type is N-type doping, and the second doping type is P-type doping.

[0026] Each cell in the first cell 200a and the second cell 200b further includes a gate structure on the epitaxial layer 211, a plurality of doped pillars 220 in the epitaxial layer 211, and a body region 216 in the epitaxial layer 211. The gate structure includes a gate dielectric layer 213 on the epitaxial layer 211 and a gate conductor 215 on the gate dielectric layer 213. The body region 216 extends from the surface of the epitaxial layer 211 toward its interior and has a second doping type opposite to that of the epitaxial layer 211. The body region 216 includes a portion extending below the gate structure and a portion exposed on the surface of the epitaxial layer 211, and the portion of the body region 216 extending below the gate structure and opposite to the gate structure forms a channel of the device. Multiple doped pillars 220 are separated from each other, and adjacent doped pillars 220 are isolated by epitaxial layers 211. The doped pillars 220 and the epitaxial layers 211 between adjacent doped pillars 220 are arranged alternately in the horizontal direction. The alternating distribution of doped pillars 220 and epitaxial layers 211 can effectively disperse current, reduce overheating caused by excessive local current, and improve device stability. The doping type of the doped pillars 220 is opposite to that of the epitaxial layers 211, that is, the doped pillars 220 have a second doping type.

[0027] Each cell in the first cell 200a and the second cell 200b also includes a source region 219 of a first doped type and a contact region 218 of a second doped type. The source region 219 and the contact region 218 are located in the body region 216, wherein a portion of the source region 219 extends below the gate structure and another portion is exposed on the surface of the epitaxial layer 111, and the contact region 218 is adjacent to the source region 219 on the side of the source region 219 away from the gate structure.

[0028] Each cell in the first cell 200a and the second cell 200b further includes a dielectric layer 217, a drain electrode 221, and a source electrode 222. The dielectric layer 217 covers the surface of the epitaxial layer 211 away from the substrate 201 and covers the gate structure. The source electrode 222 is located on the surface of the dielectric layer 217 and penetrates the dielectric layer 217 to contact the contact region and the source region 219, thereby forming an electrical connection with the contact region and the source region 219. The drain electrode 221 is located on the second surface of the substrate 201 and is electrically connected to the substrate 201. The second surface of the substrate 201 is opposite to the first surface of the substrate 201.

[0029] Body region 216 is located below the gate structure, and the portion opposite the gate structure forms the device channel. In this embodiment, the length of the channel is adjusted so that the first cell 200a and the second cell 200b have different threshold voltages Vth. Figure 2b As shown, the channel length of the first cell 200a is L1, as... Figure 2cAs shown, the channel length of the second cell 200b is L2, and L1 is not equal to L2. In this embodiment, due to the influence of the thermal process during manufacturing, there will be differences in the concentration of channel regions with different channel lengths, resulting in different channel turn-on threshold voltages Vth for the first cell 200a and the second cell 200b. Furthermore, the method described in this embodiment for changing the threshold voltage Vth by adjusting the size (CD) of the mask used to fabricate the body region in the superjunction power device has the advantage of simple processing and does not increase the cost of additional mask components.

[0030] In the superjunction power device provided in the second embodiment of this application, the threshold voltage Vth of different cells is adjusted by changing the material of the gate conductor. Specifically, the gate conductor of the first cell 200a and the gate conductor of the second cell 200b are made of different materials, so that the gate conductors of the first cell 200a and the second cell 200b have different work functions, thereby making the first cell 200a and the second cell 200b have different threshold voltages Vth. For example, the gate conductor 215 of the first cell 200a is made of a first material, and the gate conductor 215 of the second cell 200b is made of a second material different from the first material; wherein the first material and the second material have different work functions.

[0031] In one embodiment, the gate conductor 215 of the first cell 200a is, for example, MoN (work function of 5.3), and the gate conductor 215 of the second cell 200a is, for example, Al (work function of 4.1). The threshold voltage Vth of the first cell 200a and the threshold voltage Vth of the second cell 200b are offset by 0.8V to 1.0V.

[0032] In the superjunction power device provided in the third embodiment of this application, the threshold voltage Vth of different cells is adjusted by adjusting the equivalent k-value of the gate dielectric layer. Furthermore, the gate dielectric layer of the first cell 200a and the gate dielectric layer of the second cell 200b have the same thickness, but the gate dielectric layer of the first cell 200a and the gate dielectric layer of the second cell 200b have different equivalent k-values. Therefore, the MIS capacitor (Metal-Insulator-Semiconductor Capacitor) formed by the gate conductor, gate dielectric layer, and epitaxial layer of the first cell 200a has a different capacitance value than the MIS capacitor formed by the gate conductor, gate dielectric layer, and epitaxial layer of the second cell 200b, and consequently, the threshold voltage Vth of the first cell 200a and the second cell 200b are different.

[0033] Specifically, the gate dielectric layer of at least one of the first and second cells comprises a high-k dielectric layer or a stack of high-k dielectric layers.

[0034] The gate dielectric layers of the first and second cells include composite dielectric layers, and at least one layer of the composite dielectric layer in the first cell and at least one layer of the composite dielectric layer in the second cell have different dielectric constants. If the first and second cells use the same high-k dielectric material or its stack, such as HfO2 and its stack with Al2O3, different K values ​​can be obtained by adjusting the annealing temperature and number of annealing cycles after dielectric deposition. Alternatively, the K value can also be adjusted by adjusting the relative ratio of the thicknesses of HfO2 and Al2O3 (e.g., thickness ratio HfO2:Al2O3 = 1:3 or 2:2).

[0035] Furthermore, in the high-k dielectric layer stack, a portion of the material can form a dipole layer at the interface between the gate dielectric layer and the channel after the stack is formed, such as a MoS2 and HfO2 stack. The dipole layer causes charge redistribution at the channel interface, achieving Vth drift.

[0036] In one embodiment, the gate dielectric layer 213a of the first cell 200a includes a silicon oxide (SiO2) layer, and the gate dielectric layer 213b of the second cell 200b includes a stack of one or more periods of high-k dielectric layers and a silicon oxide (SiO2) layer. The stack of one or more periods of high-k dielectric layers is located on the surface of the epitaxial layer 211, and the silicon oxide (SiO2) layer is located on the surface of the stack of one or more periods of high-k dielectric layers. In one embodiment, the stack of high-k dielectric layers includes a stack of hafnium dioxide (HfO2) and molybdenum disulfide (MoS2), wherein in each period of the stack of hafnium dioxide (HfO2) and molybdenum disulfide (MoS2), the thickness of molybdenum disulfide (MoS2) is, for example, 0.6 nm, and the thickness of hafnium dioxide (HfO2) is, for example, 1.2 nm.

[0037] In other embodiments, the first cell 200a and the second cell 200b comprise stacks of k dielectric layers with different periods. For example, the gate dielectric layer 213a of the first cell 200a comprises a stack of hafnium dioxide (HfO2) and molybdenum disulfide (MoS2) with one period, and the threshold voltage of the first cell 200a is, for example, 200mV; the gate dielectric layer 213b of the second cell 200b comprises a stack of hafnium dioxide (HfO2) and molybdenum disulfide (MoS2) with two periods, and the threshold voltage of the second cell 200b is, for example, 450mV.

[0038] In the superjunction power device provided in the fourth embodiment of this application, the first region A and the second region B are arranged in alternating stripes. Figure 3 A top view of the superjunction power device provided in the fourth embodiment of this application is shown, as follows: Figure 3 As shown, both the first region A and the second region B are in the first direction (e.g., Figure 3The strip shape extends along the X-axis direction, and the first region A and the second region B are alternately distributed in a second direction that intersects with the first direction.

[0039] In one specific embodiment, the first direction and the second direction are perpendicular to each other, and the first direction is, for example, Figure 3 The X-axis direction in the middle, the second direction is, for example, the X-axis direction. Figure 3 The Y-axis direction in the diagram.

[0040] In other embodiments, the shape of the first region A and / or the second region B may also be an N-sided polygon, where N is an integer greater than or equal to 3. For example, the shape of the first region A and / or the second region B may be a triangle, a rectangle, a pentagon, etc. Figure 4 A top view of the superjunction power device provided in the fifth embodiment of this application is shown, as follows. Figure 4 As shown, in the superjunction power device provided in the fifth embodiment of this application, multiple first regions A are separated from each other and are uniformly distributed, while second regions B are located between adjacent first regions A. For example, in Figure 4 In the embodiment shown, the first region A is rectangular in shape, and multiple first regions A are arranged in an array.

[0041] In other embodiments, the shapes of the first region A and / or the second region B may also be irregular shapes. Figure 5 A top view of the superjunction power device provided in the sixth embodiment of this application is shown, as follows. Figure 5 As shown, in the superjunction power device provided in the sixth embodiment of this application, the shape of the first region A is an irregular shape formed by connecting five octagons together. One of the five octagons is located in the center, and the other four octagons are respectively connected to the octagon located in the center.

[0042] Furthermore, the superjunction power device provided in the seventh embodiment of this application also includes other cells whose threshold voltages are different from those of the first cell and the second cell. Figure 6 A top view of the superjunction power device provided in the seventh embodiment of this application is shown, as follows. Figure 6 As shown, the active region of the superjunction power device 200 includes a first region A, a second region B, and a third region C. A first cell is formed in the first region A, a second cell is formed in the second region B, and a third cell is formed in the third region C. The first cell, the second cell, and the third cell have different threshold voltages Vth.

[0043] Furthermore, the di / dt change during device turn-on can be further adjusted by regulating the proportion and positional distribution of the first, second, and third cells in the active region. The proportion and positional distribution of the first, second, and third cells in the active region are not limited to... Figure 6 The distribution is shown below.

[0044] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A superjunction power device, characterized in that, The system comprises at least a first cell and a second cell, each comprising: a substrate of a first doping type; an epitaxial layer of the first doping type located on the substrate; doped pillars of the second doping type located in the epitaxial layer; a gate structure located on the epitaxial layer, the gate structure comprising a gate dielectric layer located on the epitaxial layer and a gate conductor located on the gate dielectric layer; a body region of the second doping type located in the epitaxial layer and extending below the gate structure to form a channel; a source region of the first doping type located in the body region; and a plurality of doped pillars of the second doping type extending from the bottom of the body region toward the substrate. The first cell and the second cell have different threshold voltages.

2. The superjunction power device according to claim 1, characterized in that, The channel length of the first cell is different from that of the second cell.

3. The superjunction power device according to claim 1, characterized in that, The gate conductor material of the first cell is different from that of the gate conductor material of the second cell, so that the gate conductors of the first cell and the gate conductors of the second cell have different work functions.

4. The superjunction power device according to claim 3, characterized in that, The gate conductor material of the first cell includes molybdenum nitride, and the gate conductor material of the second cell includes aluminum.

5. The superjunction power device according to claim 1, characterized in that, The equivalent dielectric constants of the gate dielectric layer of the first cell and the gate dielectric layer of the second cell are different.

6. The superjunction power device according to claim 5, characterized in that, The gate dielectric layer of at least one of the first cell and the second cell comprises a high-k dielectric layer or a stack of high-k dielectric layers.

7. The superjunction power device according to claim 6, characterized in that, The high-k dielectric layer includes hafnium dioxide, aluminum oxide, or molybdenum disulfide.

8. The superjunction power device according to claim 5, characterized in that, The gate dielectric layer of the first cell and the second cell includes a composite dielectric layer, and at least one layer of the composite dielectric layer of the first cell and at least one layer of the composite dielectric layer of the second cell have different dielectric constants.

9. The superjunction power device according to claim 1, characterized in that, It also includes other cells whose threshold voltages are different from both the first cell and the second cell.

10. The superjunction power device according to claim 1, characterized in that, Also includes: A dielectric layer covering the first surface of the epitaxial layer and the gate structure; The source electrode is located on the dielectric layer and is electrically connected to the source region and the contact region; as well as The drain electrode is located on the second surface of the substrate away from the epitaxial layer.

11. The superjunction power device according to claim 1, characterized in that, The first cell is located in the first region of the active region, and the second cell is located in the second region of the active region. The shape of the first region and / or the second region is one or more of the following: circle, strip, polygon, and irregular shape.

12. The superjunction power device according to claim 11, characterized in that, The first region is circular in shape, and the second region is an annular ring surrounding the first region.

13. The superjunction power device according to claim 11, characterized in that, The first region and the second region are stripes extending in a first direction, and the first region and the second region are alternately arranged in a second direction intersecting the first direction.

14. The superjunction power device according to claim 11, characterized in that, The first region is rectangular in shape, and multiple first regions are arranged in an array, with the second region located between adjacent first regions.

15. The superjunction power device according to claim 11, characterized in that, The first region is an irregular shape formed by connecting five octagons together. One of the five octagons is located in the center, and the other four octagons are connected to the octagon located in the center.

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