LED chip and light-emitting device

Abstract

The invention provides an LED chip and a light-emitting device, the LED chip comprises an insulating layer, the insulating layer at least covers a part of a light-emitting surface of the LED chip, the insulating layer comprises a first sub-layer and a second sub-layer which are stacked in sequence in the direction away from the light-emitting surface, and the refractive index of the first sub-layer is smaller than that of the second sub-layer. Due to the arrangement of the first sub-layer and the second sub-layer, the LED chip can be effectively protected, the phenomena of electric leakage and the like are prevented, and the LED chip is further prevented from losing efficacy due to high temperature and high humidity. And meanwhile, the light emitting brightness of the LED chip can be improved. The display device provided by the invention is provided with the LED chip, so that the display device also has higher brightness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor light-emitting materials technology, and in particular to an LED chip and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that directly converts electrical energy into light energy; it is a solid-state cold light source. The inherent physical characteristics of LEDs allow them to operate at low voltage / current, and they feature high luminous efficiency, small size, long lifespan, and energy saving. Therefore, LEDs have become core light-emitting devices in fields such as traffic displays, medical lighting, and military communications.

[0003] For vertical chips, the insulating protective layer in existing products typically uses SiN. x Its main function is insulation and protection, protecting the sidewalls from leakage, protecting the extension strip and light-emitting area, and preventing LED chips from failing due to high temperature and humidity. However, when the light-emitting area is covered with SiN... x The brightness of the LED chip decreased significantly. Even with optimization of SiN... x Coating process improves SiN x Even with variations in film quality, the brightness of LED chips can still decrease to some extent.

[0004] Therefore, how to improve the insulating protective layer to protect the LED chip without affecting its light output brightness has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an LED chip and a light-emitting device, which aims to improve the light output brightness of the LED chip while protecting it.

[0006] According to one embodiment of this application, an LED chip is provided, comprising at least:

[0007] A semiconductor epitaxial stack, the semiconductor epitaxial stack comprising at least a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially, the semiconductor epitaxial stack having a light-emitting surface and a back surface opposite to the light-emitting surface;

[0008] An insulating layer, at least partially covering the light-emitting surface, comprising a first sub-layer and a second sub-layer stacked sequentially in a direction away from the light-emitting surface, wherein the refractive index of the first sub-layer is less than the refractive index of the second sub-layer.

[0009] According to another embodiment of this application, a light-emitting device is provided, the light-emitting device comprising a circuit board and a light-emitting unit fixed on the circuit board, the light-emitting unit comprising the LED chip provided in this application.

[0010] Compared with the prior art, the LED chip and light-emitting device of this application have at least the following technical advantages:

[0011] The LED chip of this application includes an insulating layer that covers at least a portion of the light-emitting surface of the LED chip. In the direction away from the light-emitting surface, the insulating layer includes a first sub-layer and a second sub-layer stacked sequentially. The refractive index of the first sub-layer is lower than that of the second sub-layer. The aforementioned first and second sub-layers effectively protect the LED chip, preventing leakage and other issues, and further preventing LED chip failure due to high temperature and humidity. Simultaneously, it improves the light output brightness of the LED chip.

[0012] The display device of this application has the aforementioned LED chip, and therefore also has higher brightness. Attached Figure Description

[0013] Figures 1a to 1c The diagram shown is a schematic of a light-emitting diode in the prior art.

[0014] Figure 2 The diagram shown is a schematic diagram of the semiconductor epitaxial stack of an LED chip provided in Embodiment 1 of the present invention.

[0015] Figure 3 The diagram shown is a structural schematic of the LED chip provided in Embodiment 2 of the present invention.

[0016] Figure 4 The diagram shown is a structural schematic of an LED chip provided as an optional example of Embodiment 2.

[0017] Figure 5 The diagram shown is a structural schematic of the LED chip provided in Embodiment 3 of the present invention.

[0018] Figure 6 The diagram shown is a structural schematic of the LED chip provided in Embodiment 4 of the present invention.

[0019] Figure 7 The diagram shown is a structural schematic of the LED chip provided in Embodiment 5 of the present invention.

[0020] Figure 8 The diagram shown is a schematic diagram of the light-emitting device provided in Embodiment 3 of the present invention.

[0021] Component designation explanation

[0022] 11. Insulating protective layer; 12. Solder pad; 13. Extended electrode; 001. Light-emitting surface.

[0023] 110, Semiconductor epitaxial stack; 1101, Light-emitting surface; 1102, Back side; 111, First semiconductor layer; 112, Active layer; 1113, Second semiconductor layer; 120, Insulating layer; 121, First sublayer; 122, Second sublayer; 131, First electrode; 1311, Pad electrode; 1312, Extension strip; 1313, Metal adhesion layer; 132, Second electrode; 140, Substrate; 150, Ohmic contact layer; 160, Dielectric layer; 1600, Through-hole; 170, Adhesion layer; 180, Metal layer; 190, Bonding layer.

[0024] 500, Light-emitting device; 501, Circuit board; 502, Light-emitting unit. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] like Figures 1a to 1c As shown, in the prior art, an electrode structure is formed on one side of the light-emitting surface 001 of a light-emitting diode. This electrode structure includes a pad 12 and an extended electrode 13. The light-emitting diode also includes an insulating protective layer 11. Figure 1a As shown, the insulating protective layer 11 is formed on the sidewall of the light-emitting diode and the edge region of the light-emitting surface 001; or as shown... Figure 1b As shown, the insulating protective layer 11 is formed on the sidewall of the light-emitting diode and the edge region of the light-emitting surface 001, as well as on the sidewall of the pad 12, the sidewall of the extended electrode 13, and its surface; or as shown in the figure. Figure 1c As shown, the insulating protective layer 11 is formed on the sidewall of the light-emitting diode and the entire light-emitting surface 001, and is also formed on the sidewall of the pad 12, the sidewall of the extended electrode 13, and its surface. In the prior art, the above-mentioned products all exhibit varying degrees of brightness reduction due to the coverage of the insulating protective layer 11, especially... Figure 1c The product shown, with the light-emitting surface 001 covered by the insulating protective layer 11, has a brightness reduction of nearly 4%.

[0027] To address the issue of reduced light output brightness in light-emitting diodes (LEDs) due to the insulating protective layer, one aspect of this application provides an LED chip comprising at least a semiconductor epitaxial stack, wherein the semiconductor epitaxial stack comprises at least a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially, and the semiconductor epitaxial stack has a light-emitting surface and a back surface opposite to the light-emitting surface.

[0028] An insulating layer, at least covering the sidewall between the light-emitting surface and the back surface and a portion of the light-emitting surface, wherein, in a direction away from the light-emitting surface, the insulating layer comprises a first sub-layer and a second sub-layer stacked sequentially, wherein the refractive index of the first sub-layer is less than the refractive index of the second sub-layer.

[0029] As described above, in this invention, the insulating layer of the light-emitting diode at least covers a portion of the light-emitting surface of the LED chip. In the direction away from the light-emitting surface, the insulating layer includes a first sub-layer and a second sub-layer stacked sequentially, with the refractive index of the first sub-layer being lower than that of the second sub-layer. The aforementioned first and second sub-layers effectively protect the LED chip, preventing leakage and other phenomena, and further preventing LED chip failure due to high temperature and humidity. Simultaneously, it improves the light output brightness of the LED chip.

[0030] Optionally, the first sub-layer is an insulating oxide layer.

[0031] Optionally, the second sub-layer is a transparent insulating layer.

[0032] The first sublayer can be an insulating oxide layer such as SiO2, Al2O3, HfO2, ZrO2, or TiO2, with SiO2 being preferred. The second sublayer can be a transparent insulating layer such as Si3N4, SiO2, Al2O3, HfO2, ZrO2, or TiO2, with Si3N4 being preferred. The selection of materials for the first and second sublayers satisfies the requirement that the refractive index of the first sublayer is lower than that of the second sublayer, thus increasing the refraction of light and improving the light emission effect of the LED.

[0033] Optionally, the thickness of the first sublayer is between 20 Å and 300 Å.

[0034] Optionally, the thickness of the second sublayer is between 500 Å and 3000 Å.

[0035] Optionally, the thickness of the second sublayer is (1±10%)λ / (4n), where λ is the wavelength of the light radiated by the semiconductor epitaxial stack, and n is the refractive index of the second sublayer.

[0036] The insulating layer of this application includes a first sub-layer and a second sub-layer. The material selection and thickness design of the first sub-layer can passivate dangling bonds and other defects caused by etching on the sidewalls and surface of the semiconductor epitaxial stack, thereby improving the crystal quality of the semiconductor epitaxial stack and improving the light extraction efficiency. Simultaneously, it works synergistically with the material selection and thickness setting of the second sub-layer to improve the brightness of the light-emitting diode covered by the aforementioned insulating layer.

[0037] Optionally, the LED chip further includes:

[0038] A substrate is located on the back side of the semiconductor epitaxial stack;

[0039] A bonding layer is located between the substrate and the semiconductor epitaxial stack;

[0040] A metal reflector is located between the bonding layer and the semiconductor epitaxial stack;

[0041] The electrode structure includes a first electrode and a second electrode. The first electrode is located on the light-emitting surface side of the semiconductor epitaxial stack and is electrically connected to the first semiconductor layer. The second electrode is located on the side of the substrate opposite to the semiconductor epitaxial stack and is electrically connected to the second semiconductor layer.

[0042] Optionally, the first electrode includes a pad electrode and an extension strip, the first sub-layer covers the surface and sidewalls of the light-emitting surface and the extension strip, and the second sub-layer covers the edge region of the sidewalls and surface of the first sub-layer and the pad electrode.

[0043] Optionally, the first electrode includes a pad electrode and an extension strip, the first sub-layer covers the light-emitting surface, and the second sub-layer covers the surface and sidewalls of the first sub-layer and the extension strip, as well as the edge regions of the sidewalls and surface of the pad electrode. This arrangement of the insulating layer can further protect the light-emitting diode while improving its light-emitting brightness.

[0044] Optionally, the first electrode includes a pad electrode and an extension strip, the insulating layer covers the light-emitting surface, and there is a gap D between the insulating layer and the sidewall of the pad electrode and the sidewall of the extension strip, wherein 2μm≤D≤5μm.

[0045] The aforementioned spacing distance D ensures that the insulating layer does not directly contact the first electrode, overcoming the potential problem of poor adhesion between the two. This improves the stability between the insulating layer and the first electrode, thereby enhancing the stability and reliability of the light-emitting diode.

[0046] Optionally, the first electrode further includes a metal adhesion layer located on the surface and sidewalls of the extension strip, and on the edge region of the sidewalls and surface of the pad electrode covered by the first sublayer.

[0047] Optionally, the thickness of the metal adhesion layer does not exceed 1000 Å.

[0048] The metal adhesion layer enhances the adhesion between the insulating layer, especially the first sub-layer, and the first electrode, preventing the first sub-layer from detaching and ensuring the coverage and stability of the insulating layer. This, in turn, improves the stability of the LED chip. The thickness of the metal adhesion layer does not affect the overall structure of the first electrode, does not increase the projected area of ​​the first electrode, and therefore does not affect the light emission performance of the LED chip.

[0049] Optionally, except for the region where the first electrode is located, the light-emitting surface is formed as a roughened surface.

[0050] Setting the light-emitting surface to a roughened surface is beneficial for light extraction and improves the brightness of the emitted light.

[0051] Optionally, the insulating layer further includes a third sublayer formed on the side of the second sublayer away from the first sublayer.

[0052] Optionally, the third sub-layer is a silicon oxide layer or an aluminum oxide layer.

[0053] A third sublayer can be set above the second sublayer, and by selecting the third sublayer, the protection of the light-emitting diode by the insulating layer can be improved, while its light output brightness can be increased.

[0054] Another aspect of this application provides a light-emitting device, which includes a circuit board and a light-emitting unit fixed on the circuit board, the light-emitting unit including the LED chip described in this application.

[0055] Because it has the LED chip described in this application, the light-emitting device also has good light output brightness as well as high reliability and service life.

[0056] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0057] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0058] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides an LED chip, which includes at least one semiconductor epitaxial layer. Specifically, the semiconductor epitaxial layer can be any semiconductor epitaxial layer for light-emitting diodes, such as GaN, AlGaN, AlInP, AlGaInP, or AlGaAs, that can achieve photoelectric conversion under voltage. Figure 2 As shown, the semiconductor epitaxial stack 110 in the LED chip of this embodiment has a light-emitting surface 1101 and a back surface 1102 opposite to the light-emitting surface 1101. In the direction from the light-emitting surface 1101 to the back surface 1102, a first semiconductor layer 111, an active layer 112 and a second semiconductor layer 113 are stacked sequentially.

[0062] like Figure 2 As shown, the first semiconductor layer 111 comprises a multilayer structure containing N-type impurities (e.g., Si, Ge, Sn, Te), gradually moving away from the active layer 112 (i.e., Figure 2 In the direction from bottom to top, the first semiconductor layer 111 may include an N-type space layer, an N-type confinement layer, an N-type window layer, and an N-type ohmic contact layer stacked sequentially. The aforementioned N-type space layer, N-type confinement layer, and N-type window layer may be AlGaInP-based materials. In an optional embodiment, the N-type space layer is made of AlGaInP material with a thickness of less than 300 nm. This N-type space layer is an unintentionally doped layer, and its N-type doping concentration is negligible. The N-type confinement layer is made of AlInP material with a thickness between 100 nm and 900 nm, and its N-type doping concentration is less than 1+E19 atom / cm². 3 The N-type window layer is made of AlGaInP material, with a thickness between 1000 nm and 10000 nm, and an N-type doping concentration of less than 1 + E19 atom / cm. 3 The N-type ohmic contact layer is made of GaAs material, with a thickness between 10 nm and 200 nm and an N-type doping concentration greater than 1 + E18 atom / cm. 3.

[0063] Similarly, refer to Figure 2 The second semiconductor layer 130 is a multilayer structure including P-type impurities (e.g., Mg, C, Zn), and gradually moves away from the active layer 112 in the direction (i.e. Figure 2 In the top-to-bottom direction, the second semiconductor layer 113 in the semiconductor epitaxial stack 110 includes a P-type space layer, a P-type confinement layer, a P-type transition layer, a P-type window layer, and a P-type ohmic contact layer stacked sequentially. The P-type space layer and the P-type confinement layer are formed using AlGaInP-based materials. For example, the P-type space layer is formed using AlGaInP with a thickness of less than 500 nm; the P-type confinement layer is primarily formed using AlInP. The P-type window layer is formed using GaP, with a thickness between 300 nm and 10000 nm, and a P-type doping concentration of less than 1 + E19 atom / cm². 3 The P-type transition layer between the P-type window layer and the P-type confinement layer is formed by AlGaInP, with a thickness of less than 50 nm and a P-type doping concentration of less than 1+E19 atom / cm. 3 This P-type transition layer improves the lattice matching between the P-type window layer and the P-type confinement layer, ensuring the crystal growth quality of the semiconductor epitaxial stack 110. The P-type ohmic contact layer also uses GaP material, with a thickness between 10 nm and 100 nm and a P-type doping concentration greater than 5 + E19 atom / cm. 3 The P-type ohmic contact layer is beneficial for increasing ohmic contact with the subsequently formed conductive material, thereby improving the electrical performance of the light-emitting diode. In the second semiconductor layer 113, the aforementioned P-type confinement layer is the main P-type doped layer. Due to the diffusion effect of P-type impurities, a certain concentration of P-type impurities, i.e., unintentionally doped P-type impurities, will also exist in the P-type space layer. The doping element in the P-type confinement layer can be P-type impurities such as Mg, C, or Zn. In this embodiment, the doping concentration of P-type impurities in the P-type confinement layer is between 1.0E+16 atom / cm³. 3 ~1.0E+19atom / cm 3 Furthermore, less than 1.0E+18 atom / cm 3 The thickness of the p-type confinement layer 132 is 100 nm to 1000 nm, and further, between 300 nm and 600 nm. This doping concentration and thickness setting ensures that the p-type confinement layer can provide sufficient hole concentration for radiative recombination with electrons, while the p-type impurities therein will not cause excessive damage to the active layer 112 due to diffusion.

[0064] Refer again Figure 2The active layer 112 provides the region for electron-hole recombination and light radiation. Different materials can be selected depending on the emission wavelength. The active layer 112 can be a periodic structure of a single quantum well or multiple quantum wells. The active layer 112 includes a potential well layer and a barrier layer, wherein the barrier layer has a larger band gap than the potential well layer. By adjusting the composition ratio of the semiconductor material in the potential well layer of the active layer 112, it is desired to radiate light of different wavelengths. In this embodiment, the active layer 112 preferably radiates light in the 550nm~950nm wavelength range, such as red, yellow, yellow-green, orange, and infrared light. The active layer 112 is a material layer that provides electroluminescent radiation, such as AlGaInP or AlGaAs, more preferably AlGaInP, which can be a single quantum well or multiple quantum wells. In this embodiment, the active layer 112 may optionally be a multiple quantum well layer, which includes alternating AlGaInP potential well layers and AlGaInP barrier layers.

[0065] Similarly, Figure 2 As shown, the LED chip in this embodiment also includes an electrode structure and an insulating layer 120. The electrode structure includes a first electrode 131, which is located above the light-emitting surface 1101 of the semiconductor epitaxial stack 110 and electrically connected to the first semiconductor layer 111. Specifically, the first electrode 131 includes a pad electrode 1311 and an extension strip 1312 extending from the pad electrode 1311. The insulating layer 120 is formed on the light-emitting surface 1101 and the sidewalls of the semiconductor epitaxial stack 110. The insulating layer is not provided on the surface or sidewalls of the pad electrode 1311 and the extension strip 1312. To improve the light emission effect of the LED chip, the surface of the light-emitting surface 1101 side, except for the area covered by the electrode structure, is usually formed as a roughened surface. The insulating layer 120 covers the roughened light-emitting surface 1101 and the sidewalls of the semiconductor epitaxial stack 110. In an optional example, the insulating layer 120 is formed as a multilayer structure, such as... Figure 2 As shown, in the direction away from the light-emitting surface 1101, the insulating layer 120 includes a first sub-layer 121 and a second sub-layer 122 stacked in sequence, and the refractive index of the first sub-layer 121 is less than the refractive index of the second sub-layer 122.

[0066] In an optional example, the first sub-layer 121 is an insulating oxide layer, such as SiO2, Al2O3, HfO2, ZrO2, TiO2, etc., preferably a SiO2 layer; the second sub-layer 122 is a transparent insulating layer, such as Si3N4, SiO2, Al2O3, HfO2, ZrO2, TiO2, etc., preferably a Si3N4 layer. The material selection of the first and second sub-layers satisfies the requirement that the refractive index of the first sub-layer is less than that of the second sub-layer, thus increasing the refraction of light and improving the light emission effect of the light-emitting diode. As mentioned above, when the insulating layer 120 includes a silicon oxide layer, to avoid problems such as cracking due to poor adhesion between the silicon oxide layer and the metal material of the first electrode 131, such as... Figure 2 As shown, there is a gap D between the insulating layer 120 and the sidewalls of the pad electrode 1311 and the extension strip 1312 of the first electrode 131. This gap distance is between 1μm and 10μm, and more specifically, between 2μm and 5μm, 3μm and 8μm, or 3μm and 5μm. This gap distance ensures that the insulating layer 120, especially the silicon oxide layer therein, does not contact the first electrode 131, thus avoiding problems such as cracking and peeling of the insulating layer 120 due to poor adhesion between the two. This improves the stability of both and the reliability of the light-emitting diode.

[0067] Optionally, the thickness of the first sublayer 121 is between 20 Å and 300 Å, and more specifically, between 50 Å and 150 Å, 50 Å and 200 Å, 50 Å and 100 Å and 100 Å and 150 Å. The thickness of the second sublayer 122 is (1±10%)λ / (4n), where λ is the wavelength of light radiated by the semiconductor epitaxial stack 110, and n is the refractive index of the second sublayer 122. In this embodiment, λ is between 550 nm and 950 nm, and the refractive index of the silicon nitride layer is between 2 and 2.2. Furthermore, the thickness of the second sub-layer 122 is between 500 Å and 3000 Å, and more specifically, between 500 Å and 2500 Å, 600 Å and 3000 Å, 600 Å and 2000 Å, or 600 Å and 1500 Å; for example, 600 Å, 900 Å, 1100 Å, 1300 Å, etc. The first sub-layer 121 is a silicon oxide layer with a relatively small thickness, thus it can passivate and repair defects on the sidewalls and surface of the semiconductor epitaxial stack 110, improving the crystal quality of the semiconductor epitaxial stack 110, thereby improving the light extraction efficiency and the brightness of the LED chip. The second sub-layer 122 is a silicon nitride layer with a thickness greater than that of the first sub-layer 121, thus it can provide good insulation protection, especially preventing the semiconductor epitaxial stack 110 from being affected or damaged by external moisture, impurities, etc., improving the yield and reliability of the LED chip. Through actual testing and verification, the light-emitting diode with the above-mentioned insulating layer in this embodiment is relatively... Figure 1a and Figure 1b The existing light-emitting diodes shown have a brightness improvement of about 2%.

[0068] like Figure 2 As shown, in this embodiment, the LED chip is formed as a vertically oriented chip, which also includes a substrate 140, a bonding layer 190, a dielectric layer 160, and a metal layer 180. The semiconductor epitaxial stack 110 is bonded to the substrate 140 via the bonding layer 190. The dielectric layer 160 and the metal layer 180 are located between the semiconductor epitaxial stack 110 and the substrate 140. The dielectric layer 160 is located on the back side 1102 of the semiconductor epitaxial stack 110, and the metal layer 180 is located on the side of the dielectric layer 160 away from the back side 1102. The metal layer 180 is in contact with the bonding layer 190, and the interface between the two forms a metal bonding interface, which can increase the bonding strength. At the same time, the metal layer 180 may also include a metal reflective layer, which can reflect the incident light to the light-emitting surface for emission, thereby improving the light extraction efficiency. The substrate 140 may be an insulating substrate, a semiconductor substrate, a metal substrate, etc. In this embodiment, the substrate 140 is a silicon (Si) substrate, germanium (Ge) substrate, silicon carbide (SiC) substrate, gallium nitride (GaN) substrate, aluminum nitride (AlN) substrate, gallium phosphide (GaP) substrate, or copper-tungsten alloy (CuW) substrate, etc. Optionally, the bonding layer 190 is a metal bonding layer, such as Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, In, Pt, or W, etc.

[0069] The aforementioned dielectric layer 160 is typically configured as a multilayer structure, including, for example, an insulating dielectric layer and a reflective layer. The reflective layer may be, for example, a Bragg reflective layer comprising overlapping high-refractive-index material layers and low-refractive-index material layers. Here, "high-refractive-index" and "low-refractive-index" refer to the relative refractive indices of the overlapping material layers, not specific refractive index values. The high-refractive-index material layer and low-refractive-index material layer may be SiO2, SiN, or SiO2. x N y TiO x A dash breech-guided mirror (DBR) formed by repeatedly stacking two or more of the following materials: Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO2, TaO2, NbO2, or MgF2. For example, in this embodiment, the high refractive index material layer is TiO2. x Layers (e.g., TiO2, Ti2O3, or Ti3O5) or NbO yThe high-refractive-index material layer (e.g., NbO2 or Nb3O5) is a SiO2 layer, and the low-refractive-index material layer is a SiO2 layer. The total number of stacked layers of the high-refractive-index and low-refractive-index material layers is between 2 and 100 layers, further between 2 and 10 layers, and even further between 2 and 5 layers. The thickness of the high-refractive-index and low-refractive-index material layers is between 100 Å and 1000 Å, and even further between 200 Å and 800 Å, 500 Å and 1000 Å, and 500 Å and 800 Å. The thicknesses of the high-refractive-index and low-refractive-index material layers are usually different.

[0070] The aforementioned insulating dielectric layer can be, for example, SiO2, SiN, or SiO2. x N y TiO x The material can be any one of Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO2, TaO2, or MgF2. In an optional embodiment, the insulating dielectric layer and the low-refractive-index material layer in the reflective layer have the same material composition, for example, both being SiO2 layers. Having the same material composition for both the insulating dielectric layer and the low-refractive-index material layer allows them to serve as components of the reflective layer, increasing the reflective effect; furthermore, they can be formed using the same vapor deposition process as the reflective layer, which also helps to save costs.

[0071] An ohmic contact layer 150 is formed on the back side 1102 of the semiconductor epitaxial stack 110. The ohmic contact layer 150 is formed, for example, in a patterned structure and is covered and encapsulated by a dielectric layer 160. To achieve electrical connection between the metal layer 180 and the semiconductor epitaxial stack 110 (specifically, the second semiconductor layer 113 therein), a via 1600 is formed penetrating the dielectric layer 160. The bottom of the via 1600 exposes the ohmic contact 150. The metal layer 180 fills the via 1600 and is in direct contact with the ohmic contact layer 150, and is electrically connected to the second semiconductor layer 113 through the ohmic contact 150.

[0072] Optionally, Figure 2 As shown, to increase the adhesion between the metal layer 180 and the dielectric layer 160 and improve reliability, an adhesion layer 170 is also formed between the metal layer 180 and the dielectric layer 160. The adhesion layer 170 covers the surface of the dielectric layer 1609 and also covers the sidewalls and bottom of the via 1600. The adhesion layer 170 can be, for example, an ITO layer or an IZO layer.

[0073] Similarly, Figure 2As shown, the electrode structure of the LED chip also includes a second electrode 132 located on the back side of the substrate 140 (i.e., the side away from the semiconductor epitaxial stack 110). The extension strip 1312 of the first electrode 131 extends from the pad electrode 1311 to other areas on the light-emitting surface 1101 side to improve the current diffusion effect and uniformity on the first semiconductor layer 111 side. In an optional embodiment, the extension strip 1312 is formed as a finger-shaped extension strip 1312, and the first electrode 131 may include one or more of the aforementioned extension strips 1312. The first electrode 131 and the second electrode 132 can be metal electrodes, such as nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, and combinations thereof, but the embodiments disclosed herein are not limited thereto.

[0074] Example 2

[0075] This embodiment also provides an LED chip, such as... Figure 3 As shown, the LED chip also includes a semiconductor epitaxial stack 110, an electrode structure, an insulating layer 120, etc. The insulating layer 120 also includes a first sub-layer 121 and a second sub-layer 122 stacked sequentially, and the refractive index of the first sub-layer 121 is less than the refractive index of the second sub-layer 122. Similarities to other embodiments will not be repeated; the differences are as follows:

[0076] like Figure 3 As shown, the first sub-layer 121 in the insulating layer 120 only covers the sidewalls and light-emitting surface 1101 of the semiconductor epitaxial stack 110, and does not extend to cover the extension strip 1312 of the first electrode 131 and the pad electrode 1311, and also has a gap distance D between it and the pad electrode 1311 and the extension strip 1312. The second sub-layer 122 of the insulating layer 120 covers the first sub-layer 121, and the second sub-layer 122 fills to the gap distance D, thereby, for example, selecting the second sub-layer 122 of the silicon nitride layer to directly contact the first electrode 131, and the two have good adhesion, which can improve the stability between the insulating layer 120 and the first electrode 131. The second sub-layer 122 also extends to cover the surface and sidewalls of the extension strip 1312 of the first electrode 131, and the sidewalls of the pad electrode 1311, or further extends to cover the edge portion of the surface of the pad electrode 1311. The insulating layer 120 is also formed as a multilayer structure, for example, including a first sublayer 121 and a second sublayer 122. The other configurations of the first sublayer 121 and the second sublayer 122 are the same as those in the other embodiments, and will not be described again here.

[0077] like Figure 4As shown, in an optional example of this embodiment, the first sub-layer 121 only covers the light-emitting surface 1101 of the semiconductor epitaxial stack 110, and does not extend to cover the sidewalls of the semiconductor epitaxial stack 110, the extension strip 1312 of the first electrode 131, or the pad electrode 1311. The first sub-layer 121 also has a spacing distance D between itself and the pad electrode 1311 and the extension strip 1312. The second sub-layer 122 covers the first sub-layer 121 and fills the spacing distance D, while extending to cover the sidewalls of the semiconductor epitaxial stack 110, the surface and sidewalls of the extension strip 1312 of the first electrode 131, and the sidewalls of the pad electrode 1311, or further extends to cover the edge portion of the surface of the pad electrode 1311.

[0078] In this embodiment, the insulating layer 120 prevents the first sub-layer 121 from contacting the first electrode 131. When the first sub-layer 121 is a silicon oxide material layer, it avoids detachment or peeling due to poor adhesion between the silicon oxide material layer and the metal material. This ensures the adhesion and stability of the insulating layer 120 to the first electrode 131, thereby guaranteeing the stability of the LED chip. Simultaneously, the insulating layer 120 effectively improves the light extraction performance of the LED chip.

[0079] Example 3

[0080] This embodiment also provides an LED chip, such as... Figure 5 As shown, this LED chip also includes a semiconductor epitaxial layer 110, an electrode structure, an insulating layer 120, etc. The similarities to Embodiment 1 will not be repeated here; the differences are as follows:

[0081] like Figure 5 As shown, the insulating layer 120 not only covers the sidewalls and light-emitting surface 1101 of the semiconductor epitaxial stack 110, but also covers the sidewalls and surface of the extension strip 1312 of the first electrode 131, as well as the sidewalls of the pad electrode 1311, or further covers the edge portion of the surface of the pad electrode 1311. This insulating layer 120 is also formed as a multilayer structure, for example, including a first sublayer 121 and a second sublayer 122. The arrangement of the first sublayer 121 and the second sublayer 122 is the same as that in Embodiment 1, and will not be described again here.

[0082] In this embodiment, the insulating layer 120 is provided without affecting the light output brightness of the LED chip, and may even improve the light output brightness compared to existing LED chips. It further enhances the protection of the semiconductor epitaxial layer 110 of the LED chip, and also increases the protection of the first electrode 131. Through actual testing and verification, the light-emitting diode with the above-mentioned insulating layer in this embodiment, compared to… Figure 1c The existing light-emitting diodes shown have a brightness improvement of about 6%.

[0083] Example 4

[0084] This embodiment also provides an LED chip, such as... Figure 6 As shown, the LED chip also includes a semiconductor epitaxial stack 110, an electrode structure, an insulating layer 120, etc. The insulating layer 120 also includes a first sub-layer 121 and a second sub-layer 122 stacked sequentially, and the refractive index of the first sub-layer 121 is less than the refractive index of the second sub-layer 122. Similarities to other embodiments will not be repeated; the differences are as follows:

[0085] like Figure 6 As shown, the insulating layer 120 not only covers the sidewalls and light-emitting surface 1101 of the semiconductor epitaxial stack 110, but also covers the sidewalls and surface of the extension strip 1312 of the first electrode 131, and the sidewalls of the pad electrode 1311, or further covers the edge portion of the surface of the pad electrode 1311. That is, the first sub-layer 121 covers the sidewalls and light-emitting surface 1101 of the semiconductor epitaxial stack 110, and also covers the sidewalls and surface of the extension strip 1312 of the first electrode 131, and the sidewalls of the pad electrode 1311, and further covers the edge portion of the surface of the pad electrode 1311. The second sub-layer 122 covers the first sub-layer 121. The remaining configurations of the first sub-layer 121 and the second sub-layer 122 are the same as those in other embodiments, and will not be described again here.

[0086] In this embodiment, the first sub-layer 121 is a silicon oxide layer. To further increase the adhesion between the first sub-layer 121 and the first electrode 131, the first electrode 131 is also provided with a metal adhesion layer 1313. Specifically, the metal adhesion layer 1313 is located on the surface and sidewalls of the extension strip 1312 of the first electrode 131, as well as the edge region of the sidewalls and surface of the pad electrode 1311 covered by the first sub-layer 121. The metal adhesion layer 1313 can be, for example, a Ti layer. In order not to affect the overall structure of the first electrode 131, especially not to affect the area ratio of the first electrode 131 on the light-emitting surface 1101 side, the thickness of the metal adhesion layer 1313 does not exceed 1000 Å, further, less than or equal to 500 Å; even further, less than or equal to 100 Å, for example, between 10 Å and 80 Å, such as 10 Å, 30 Å, 40 Å, 50 Å, 70 Å, 80 Å, etc.

[0087] As described above, the insulating layer 120 in this embodiment can also increase the light extraction efficiency of the LED chip. Simultaneously, the metal adhesion layer increases the adhesion of the insulating layer 120, especially the first sub-layer 121, to the first electrode, preventing the first sub-layer 121 from detaching and ensuring the coverage and stability of the insulating layer 120, thereby improving the stability of the LED chip. Furthermore, the thickness of the metal adhesion layer 1313 is set so that it does not affect the overall structure of the first electrode 131 and does not increase the projected area of ​​the first electrode 131 on the light-emitting surface 1101 side, thus not affecting the light extraction effect of the LED chip. In addition, the metal adhesion layer 1313 is not provided at the welding position of the pad electrode 1312 of the first electrode 131, which helps ensure the stability of the welding position itself, as well as the stability and good conductivity of subsequent welding, thereby improving the electrical performance and reliability of the LED chip.

[0088] Example 5

[0089] This embodiment also provides an LED chip, which also includes a semiconductor epitaxial layer 110, an electrode structure, an insulating layer 120, etc. The similarities to other embodiments will not be repeated; the differences are as follows:

[0090] like Figure 7 As shown, in this embodiment, the insulating layer 120 has a multilayer structure. In addition to the first sub-layer 121 and the second sub-layer 122 described in other embodiments, the insulating layer 120 also includes a third sub-layer 123 formed on the side of the second sub-layer 122 away from the first sub-layer 121. This third sub-layer 123 can be a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, etc. Figure 7 As shown, in this embodiment, the insulating layer 120 covers the sidewalls and light-emitting surface 1101 of the semiconductor epitaxial stack 110, and also has a spacing distance D between it and the sidewalls of the pad electrode 1311 and the extension strip 1312 of the first electrode 131. This spacing distance D is the same as that in other embodiments, and will not be described again here. It is understood that the insulating layer 120 in this embodiment may also have the settings of other embodiments, and this embodiment is only exemplary and not intended to limit it. The thickness of the third sub-layer 123 is less than or equal to 1000 Å, and further, the thickness of the third sub-layer 123 is between 200 Å and 800 Å. The material selection and thickness setting of the third sub-layer 123 ensure that it does not affect the light emission brightness of the LED chip, while increasing the protection of the LED chip and further improving the reliability of the LED chip.

[0091] Example 6

[0092] This embodiment provides a light-emitting device, such as... Figure 8As shown, the light-emitting device 500 includes a circuit board 501 and light-emitting units 502 disposed on the circuit board 501. The light-emitting unit 502 may be one or more of the LED chips provided in other embodiments of this application, and multiple light-emitting units 502 may be arranged in an array on the circuit board 501.

[0093] It should be understood that the light-emitting device provided in this embodiment is based on the LED chip structure provided in any one or more of the other embodiments. Therefore, the light-emitting device provided in this embodiment also has high luminous efficiency and light output brightness.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LED chip, characterized in that, At least including: A semiconductor epitaxial stack, the semiconductor epitaxial stack comprising at least a first semiconductor layer, an active layer and a second semiconductor layer stacked sequentially, the semiconductor epitaxial stack having a light-emitting surface and a back surface opposite to the light-emitting surface; An insulating layer, at least covering the sidewall between the light-emitting surface and the back surface and a portion of the light-emitting surface, wherein, in a direction away from the light-emitting surface, the insulating layer comprises a first sub-layer and a second sub-layer stacked sequentially, wherein the refractive index of the first sub-layer is less than the refractive index of the second sub-layer.

2. The LED chip according to claim 1, characterized in that, The first sub-layer is an insulating oxide layer.

3. The LED chip according to claim 1, characterized in that, The second sub-layer is a transparent insulating layer.

4. The LED chip according to claim 1, characterized in that, The thickness of the first sublayer is between 20 Å and 300 Å.

5. The LED chip according to claim 1, characterized in that, The thickness of the second sublayer is between 500 Å and 3000 Å.

6. The LED chip according to claim 1, characterized in that, The thickness of the second sublayer is (1±10%)λ / (4n), where λ is the wavelength of the light radiated by the semiconductor epitaxial stack, and n is the refractive index of the second sublayer.

7. The LED chip according to claim 1, characterized in that, Also includes: A substrate is located on the back side of the semiconductor epitaxial stack; A bonding layer is located between the substrate and the semiconductor epitaxial stack; A metal reflector is located between the bonding layer and the semiconductor epitaxial stack; The electrode structure includes a first electrode and a second electrode. The first electrode is located on the light-emitting surface side of the semiconductor epitaxial stack and is electrically connected to the first semiconductor layer. The second electrode is located on the side of the substrate opposite to the semiconductor epitaxial stack and is electrically connected to the second semiconductor layer.

8. The LED chip according to claim 7, characterized in that, The first electrode includes a pad electrode and an extension strip. The first sub-layer covers the surface and sidewalls of the light-emitting surface and the extension strip. The second sub-layer covers the edge region of the sidewalls and surface of the first sub-layer and the pad electrode.

9. The LED chip according to claim 7, characterized in that, The first electrode includes a pad electrode and an extension strip. The first sub-layer covers the light-emitting surface, and the second sub-layer covers the surface and sidewalls of the first sub-layer and the extension strip, as well as the edge region of the sidewalls and surface of the pad electrode.

10. The LED chip according to claim 7, characterized in that, The first electrode includes a pad electrode and an extension strip. The insulating layer covers the light-emitting surface. There is a gap D between the insulating layer and the sidewall of the pad electrode and the sidewall of the extension strip, where 2μm≤D≤5μm.

11. The LED chip according to claim 8, characterized in that, The first electrode further includes a metal adhesion layer located on the surface and sidewalls of the extension strip, as well as the edge region of the sidewalls and surface of the pad electrode covered by the first sublayer.

12. The LED chip according to claim 11, characterized in that, The thickness of the metal adhesion layer does not exceed 1000 Å.

13. The LED chip according to claim 7, characterized in that, Except for the region where the first electrode is located, the light-emitting surface is formed as a roughened surface.

14. The LED chip according to claim 1, characterized in that, The insulating layer further includes a third sublayer formed on the side of the second sublayer away from the first sublayer.

15. The LED chip according to claim 14, characterized in that, The third sub-layer is a silicon oxide layer or an aluminum oxide layer.

16. A light-emitting device, characterized in that, The light-emitting device includes a circuit board and a light-emitting unit fixed on the circuit board, wherein the light-emitting unit includes an LED chip as described in any one of claims 1 to 15.

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