Display device, electronic device including the same, and method of manufacturing display device

Abstract

The invention provides a display device, an electronic apparatus including the display device, and a method of manufacturing the display device. The display device includes a semiconductor substrate; and a plurality of pixels in and on the semiconductor substrate, each of the plurality of pixels including: a light emitting element; a first transistor between the first power line and the light emitting element; and a second transistor between the data line and the first transistor. The first transistor includes a channel region, a source region adjacent a first side of the channel region, a drain region adjacent a second side of the channel region, and a gate on the channel region. The channel region of the first transistor includes a first channel region overlapping the gate of the first transistor and a second channel region not overlapping the gate of the first transistor.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0146891, filed on October 24, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a display device including a semiconductor substrate, an electronic device including a display device, and a method of manufacturing a display device. Background Technology

[0003] Electronic devices such as smartphones, laptops, navigation devices, and smart TVs provide images to users and may include display devices for displaying those images. Augmented reality devices, virtual reality devices, or video projection devices may include microdisplay devices. Microdisplay devices may include a silicon wafer and light-emitting elements disposed on the silicon wafer to drive and display high-brightness images with low power.

[0004] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] Embodiments of this disclosure may relate to a display device including a semiconductor substrate, an electronic device including the display device, and a method of manufacturing the display device.

[0006] According to one or more embodiments of this disclosure, a display device includes: a semiconductor substrate; and a plurality of pixels, in and on the semiconductor substrate, each of the plurality of pixels including: a light-emitting element; a first transistor between a first power line and the light-emitting element; and a second transistor between a data line and the first transistor. The first transistor includes a channel region, a source region adjacent to a first side of the channel region, a drain region adjacent to a second side of the channel region, and a gate on the channel region. The channel region of the first transistor includes a first channel region superimposed on the gate of the first transistor in a plan view and a second channel region not superimposed on the gate of the first transistor in a plan view.

[0007] In one embodiment, the first transistor may include a PMOS transistor.

[0008] In one embodiment, the source region of the first transistor may be electrically connected to a first power line.

[0009] In one embodiment, the first transistor may include an NMOS transistor.

[0010] In one embodiment, the source region of the first transistor may be electrically connected to the light-emitting element.

[0011] In this embodiment, at least a portion of the semiconductor substrate may be doped with a first impurity. The source region and drain region of the first transistor may be doped with a second impurity different from the first impurity.

[0012] In an embodiment, the gate and source regions of the first transistor may be spaced apart from each other in a plan view, and the gate and drain regions of the first transistor may be adjacent to each other in a plan view.

[0013] In an embodiment, the second transistor may include a channel region, a source region adjacent to a first side of the channel region of the second transistor, a drain region adjacent to a second side of the channel region of the second transistor, and a gate on the channel region of the second transistor. The channel region of the second transistor may be completely superimposed on the gate of the second transistor in a planar view.

[0014] In an embodiment, the gate and source regions of the second transistor may be adjacent to each other in a plan view, and the gate and drain regions of the second transistor may be adjacent to each other in a plan view.

[0015] In an embodiment, the first source length and the first drain length of the first transistor may be different from each other. The second source length and the second drain length of the second transistor may be the same as each other.

[0016] In one embodiment, the length of the gate of the first transistor may be greater than the length of the gate of the second transistor.

[0017] In an embodiment, the resistance of the second channel region may be higher than that of the first channel region.

[0018] According to one or more embodiments of this disclosure, a method of manufacturing a display device includes: preparing a preliminary semiconductor substrate doped with a first impurity; providing the semiconductor substrate by: forming a source region and a drain region by doping a first doped region and a second doped region of the preliminary semiconductor substrate with a second impurity via a first mask; forming a preliminary gate insulating layer on an upper surface of the semiconductor substrate; forming a preliminary gate on an upper surface of the preliminary gate insulating layer; and forming a gate insulating layer and a gate by etching the preliminary gate insulating layer and the preliminary gate via a second mask. The display device includes a first channel region superimposed on the gate in a plan view and a second channel region not superimposed on the gate in a plan view between the source region and the drain region.

[0019] In an embodiment, the display device may include a plurality of pixels disposed in and on a semiconductor substrate, each of the plurality of pixels including: a light-emitting element; a first transistor disposed between a first power line and the light-emitting element; and a second transistor disposed between a data line and the first transistor. The first transistor may include a source region, a drain region, and a gate.

[0020] In an embodiment, the gate and source regions of the first transistor may be spaced apart from each other in a plan view, and the gate and drain regions of the first transistor may be adjacent to each other in a plan view.

[0021] In an embodiment, the first mask may not be superimposed on the source and drain regions of the first transistor in a planar view.

[0022] In one embodiment, the second mask may be stacked in a plan view with the gate insulating layer and the gate of the first transistor.

[0023] In an embodiment, the first mask may be superimposed on the second channel region in a plan view, and the second mask may not be superimposed on the second channel region in a plan view.

[0024] In an embodiment, the resistance of the second channel region may be higher than that of the first channel region.

[0025] According to one or more embodiments of this disclosure, an electronic device includes: a display panel; a frame for housing the display panel; and a structure on which the frame is mounted. The display panel includes: a semiconductor substrate; and a plurality of pixels in and on the semiconductor substrate. Each of the plurality of pixels includes: a light-emitting element; a first transistor between a first power line and the light-emitting element; and a second transistor between a data line and the first transistor. The first transistor includes a channel region, a source region adjacent to a first side of the channel region, a drain region adjacent to a second side of the channel region, and a gate on the channel region. The channel region of the first transistor includes a first channel region superimposed on the gate of the first transistor in a plan view and a second channel region not superimposed on the gate of the first transistor in a plan view.

[0026] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the detailed description of the present invention with reference to the accompanying drawings, and may be apparent in part from thereto, or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0027] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments with reference to the accompanying drawings, in which: Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure; Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present disclosure; Figure 3A This is a plan view of the unit region according to an embodiment of the present disclosure; Figure 3B Is with Figure 3AA cross-sectional view of one of the three light-emitting regions: the first, the second, and the third light-emitting regions. Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure; Figure 5A This is a circuit diagram of a pixel according to an embodiment of the present disclosure; Figure 5B This is a circuit diagram of a pixel according to an embodiment of the present disclosure; Figure 5C This is a circuit diagram of a pixel according to an embodiment of the present disclosure; Figure 6 This is a block diagram of a first transistor according to an embodiment of the present disclosure; Figure 7 This is a block diagram of a second transistor according to an embodiment of the present disclosure; Figure 8 This is a plan view of a first transistor according to an embodiment of the present disclosure; Figure 9 This is a plan view of the second transistor according to an embodiment of the present disclosure; Figures 10A to 10F This is a cross-sectional view illustrating a method of manufacturing a first transistor according to an embodiment of the present disclosure; Figure 11 A block diagram of an electronic device according to embodiments of the present disclosure; and Figure 12 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0028] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout denote the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions may not be repeated.

[0029] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0030] Furthermore, as those skilled in the art will understand, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or in part or in whole with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0031] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature as shown in the drawings to another element(s). It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0032] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the drawings, but should be interpreted in light of variations in shape that may occur, for example, due to manufacturing processes. Thus, the shapes shown in the drawings may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0033] In the accompanying diagram, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0034] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, one component, one region, one layer, or one part from another element, another component, another region, another layer, or another part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first part described below may be referred to as a second element, second component, second region, second layer, or second part.

[0035] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be one or more intermediary elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element, with one or more intermediary layers, regions, or elements located between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0036] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements without modifying any individual elements in that list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0037] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” indicates “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0039] Figure 1 This is a perspective view of a display device according to an embodiment of the present disclosure.

[0040] Reference Figure 1 The display device DD may have a rectangular shape, comprising a long side parallel or substantially parallel to the first direction DR1 and a short side parallel or substantially parallel to the second direction DR2 intersecting the first direction DR1. However, this disclosure is not limited thereto, and the display device DD may have various suitable shapes such as a circular shape or a polygonal shape. Hereinafter, a direction perpendicular or substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. As used herein, the phrase "in a plan view" is defined as the state viewed from / on the third direction DR3.

[0041] The display device DD according to an embodiment can be activated in response to an electrical signal. The display device DD can be a display included in a television, monitor, billboard, tablet PC, car navigation unit or device, personal computer, laptop computer, personal digital terminal, game console, smartphone, camera, and / or wearable device. For example, wearable devices can include virtual reality devices, augmented reality devices, smartwatches, etc. Virtual reality devices and augmented reality devices can be devices in the form of wearable glasses. However, this disclosure is not limited to the examples of the above-described devices, and according to embodiments of this disclosure, the display device DD can display an image through a display area DA. A non-display area NDA can surround the display area DA (e.g., around the periphery of the display area DA). Figure 1As shown, the non-display area NDA can be set to be adjacent to one side of the display area DA (e.g., only one side), or it can be omitted as needed or desired.

[0042] Multiple pixels (PXs) can be arranged in the display area (DA). Pixels (PXs) can be arranged in a matrix. Each pixel (PX) can include pixel circuitry and a light-emitting diode (LED). Pixels (PXs) can produce light of the same color as each other. As another example, multiple pixels (PXs) that produce light of different colors (such as a first pixel (PX) that outputs a first color of light (e.g., red), a second pixel (PX) that outputs a second color of light (e.g., green), and a third pixel (PX) that outputs a third color of light (e.g., blue) can be arranged in the display area (DA).

[0043] Figure 2 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0044] Reference Figure 2 The display device DD may include a circuit layer CL, a light-emitting element layer EDL, a thin film encapsulation layer TFE, a color filter layer CFL, a lens layer LEL, a coating layer OCL, a window WD, and a polarizing layer POL.

[0045] The data drive 200 (for example, see Figure 4 ), gate driver 300 (e.g., see Figure 4 ), pixel circuit PXCa (for example, see Figure 5A Transistors, such as those for semiconductors, can be formed in a circuit layer CL. The circuit layer CL may include at least one insulating layer, a semiconductor pattern, a conductive pattern, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer can be formed by coating, deposition, etc., and thereafter, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned by multiple photolithography processes. As a result, semiconductor patterns, conductive patterns, and signal lines can be formed within the circuit layer CL.

[0046] The light-emitting element layer (EDL) can be disposed on the circuit layer (CL). The EDL may include a first electrode (AE), an emitting layer (EL), and a second electrode (CE). In this embodiment, the first electrode (AE) may be an anode, and the second electrode (CE) may be a cathode.

[0047] The first electrode AE ​​may include a transparent conductive oxide pattern. The first electrode AE ​​may be formed individually in each of the pixels PX. The transparent conductive oxide pattern may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO) to facilitate hole injection. x The first electrode AE ​​can have a single-layer or multi-layer structure. It can be indium oxide (In₂O₃) or aluminum-doped zinc oxide (AZO).

[0048] An emitting layer EL can be disposed on a first electrode AE. The emitting layer EL can have a monolithic shape and can be provided publicly to the pixel PX. When the emitting layer EL has a monolithic shape, it can provide blue light or white light. However, this disclosure is not limited thereto, and the emitting layer EL can be formed individually in each of the pixels PX. When the emitting layer EL is formed individually in each of the pixels PX, each emitting layer EL can emit at least one of a first color light, a second color light, and a third color light. The emitting layer EL can include organic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs.

[0049] The second electrode CE can be disposed on the emitter layer EL. The second electrode CE can have a monolithic shape and can be commonly disposed in multiple pixels PX. A common voltage can be provided to the second electrode CE, and the second electrode CE can be referred to as the common electrode.

[0050] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element layer (EDL). The TFE protects the EDL from moisture, oxygen, and foreign substances such as dust particles. The TFE may include at least one inorganic film (hereinafter, the inorganic encapsulation film). Furthermore, the TFE may also include at least one organic film (hereinafter, the organic encapsulation film). The TFE may include sequentially stacked inorganic, organic, and inorganic encapsulation layers, but the layers constituting the TFE are not limited to these.

[0051] A color filter layer (CFL) can be disposed on a thin-film encapsulation layer (TFE). The CFL can include multiple color filters CF1, CF2, and CF3. These multiple color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 can convert the color of light generated in the emitting layer (EL) (e.g., blue light) to a first color and can output light of the first color. The second color filter CF2 can convert the color of light generated in the emitting layer (EL) to a second color and can output light of the second color. The third color filter CF3 may not convert the color of light, but can transmit light of the color generated in the emitting layer (EL) and can output light of that color as a third color. In some embodiments, the CFL can also include a light-blocking pattern.

[0052] The lens layer (LEL) can be disposed on the color filter layer (CFL). The lens layer (LEL) can include multiple lens patterns. The lens patterns can be respectively disposed corresponding to the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), and can be spaced apart from each other.

[0053] An OCL (Optically Coated Layer) can be disposed on the lens layer (LEL). The OCL can be optically transparent. As a planarization layer, the OCL can include a flat or substantially flat upper surface.

[0054] The window WD can be mounted on the OCL (overlay layer). The window WD provides the outer surface of the display device DD.

[0055] A polarizing layer (POL) can be disposed on the window WD. The polarizing layer (POL) blocks external light incident on the display device DD. The polarizing layer (POL) blocks a portion of the external light. Furthermore, the polarizing layer (POL) reduces the amount of external light that can be emitted onto the display panel DP (e.g., see...). Figure 4 The reflected light generated at the point (e.g., the polarizing layer POL). In other words, the polarizing layer POL can be an anti-reflective layer. For example, when light incident from outside the display device DD onto the display panel DP (e.g., see...), the reflected light is reflected at the point (e.g., ... see...). Figure 4 In the case of light returning to its original position, the polarizing layer POL can block reflected light.

[0056] Figure 3A This is a plan view of the unit region according to an embodiment of the present disclosure.

[0057] Figure 3A It shows that it can be repeatedly set Figure 1 The display area DA contains a unit area LU. The unit area LU may include a first light-emitting area LA1, a second light-emitting area LA2, and a third light-emitting area LA3. The first light-emitting element of the first pixel, the second light-emitting element of the second pixel, and the third light-emitting element of the third pixel may be respectively disposed in the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3.

[0058] The first color light, the second color light, and the third color light can be output through the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3, respectively. The first light-emitting element, the second light-emitting element, and the third light-emitting element can be emitted from an integrally formed emitting layer EL (e.g., see...). Figure 2 ) produces light of the same color as each other (e.g., blue light). Color filters respectively disposed in the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 can emit light from the emitting layer EL (e.g., see...) which can be integrally formed. Figure 2 The generated colored light can be converted into a first colored light, a second colored light, and a third colored light, or it can transmit colored light generated from an emitting layer EL that can be integrally formed. In embodiments of this disclosure, light-emitting elements that generate light of different colors can be respectively disposed in a first light-emitting region LA1, a second light-emitting region LA2, and a third light-emitting region LA3.

[0059] Red light can be output through the first emitting area LA1, green light through the second emitting area LA2, and blue light through the third emitting area LA3. Figure 3A The arrangement of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3, the area ratio of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3, and the shapes of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 shown are examples, and this disclosure is not limited thereto.

[0060] Figure 3B Is with Figure 3A A cross-sectional view corresponding to one of the first, second, and third luminous regions.

[0061] Figure 3B Showing more details Figure 2 The cross-section of the display device DD shown depicts the circuit layer CL and the light-emitting element layer EDL. (Includes...) Figure 3B The components in the light-emitting element layer (EDL) shown can be included with the components referenced above. Figure 2 The components in the described light-emitting element layer (EDL) are the same or substantially the same (or similar), and therefore are represented by the same reference numerals or symbols. Thus, redundant descriptions need not be repeated.

[0062] The circuit layer CL may include a semiconductor substrate SS, at least one insulating layer IL1 to IL4, and at least one conductive pattern CP1 to CP4. In this embodiment, a circuit layer CL including four insulating layers IL1 to IL4 and four conductive patterns CP1 to CP4 is shown as an example.

[0063] The semiconductor substrate SS can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Multiple pixel PX (e.g., see...) Figure 4 The source region SA1 and drain region DRA1 can be formed in and on a semiconductor substrate SS. The semiconductor substrate SS may include a source region SA1 and a drain region DRA1. Both the source region SA1 and the drain region DRA1 may be doped regions. A pair of source regions SA1 and drain regions DRA1 may define a transistor having a gate GA1 as described in more detail below. Depending on the signal flow, the source region SA1 and the drain region DRA1 may be the source or the drain of a transistor. A shallow trench isolation (STI) region 10 may be further defined in the semiconductor substrate SS. The STI region 10 can prevent or substantially prevent leakage current by isolating the transistor. The STI region 10 may be configured differently depending on the design of the pixel circuit.

[0064] A gate insulating layer GIN1 and a gate GA1 are disposed on a semiconductor substrate SS. The gate GA1 may include metal. Each of the gates GA1 is disposed corresponding to a pair of source regions SA1 and drain regions DRA1. The gate insulating layer GIN1 may include an insulating pattern disposed corresponding to the gate GA1.

[0065] A first insulating layer IL1 can be disposed on a semiconductor substrate SS. The first insulating layer IL1 can be stacked with multiple pixels and can cover the gates GA1 of transistors T1 and T2. The first insulating layer IL1 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The first insulating layer IL1 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer IL1 can be a single-layer silicon oxide layer. Not only the first insulating layer IL1, but also the second insulating layers IL2 to the fourth insulating layers IL4, which will be described in more detail below, can be inorganic layers and / or organic layers, and can have a single-layer or multi-layer structure. The inorganic layer can include at least one of the above-described inorganic materials, but this disclosure is not limited thereto.

[0066] Contact holes CH1, CH2, CH3 and CO are respectively defined in insulating layers IL1 to IL4. The uppermost insulating layer among insulating layers IL1 to IL4 is defined as the fourth insulating layer IL4, and the opening formed in the fourth insulating layer IL4 is defined as the contact opening CO.

[0067] A first conductive pattern CP1 may be disposed in the first insulating layer IL1. The first conductive pattern CP1 may be connected to the source region SA1 and / or drain region DRA1 of transistors T1 and T2 through a first contact hole CH1. In this embodiment, the first conductive pattern CP1 is shown as being connected to the drain region DRA1 of the first transistor T1. Not only the first conductive pattern CP1, but also the second conductive pattern CP2, the third conductive pattern CP3, and the fourth conductive pattern CP4, which will be described in more detail below, may be defined as contact electrodes. The upper surfaces of conductive patterns CP1 to CP4 may define a flat surface that is the same as or substantially the same as the upper surfaces of insulating layers IL1 to IL4 (e.g., a surface continuous with the upper surfaces of insulating layers IL1 to IL4). Conductive patterns CP1 to CP4 may be formed by, for example, chemical / physical polishing processes (such as damascene processes). The materials of conductive patterns CP1 to CP4 are not particularly limited, as long as the material has high conductivity and high reflectivity. For example, conductive patterns CP1 to CP4 may include any of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and suitable alloys including at least one of them.

[0068] A second insulating layer IL2 can be disposed on the first insulating layer IL1 and can be stacked together with the pixel. The second insulating layer IL2 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. In this embodiment, the second insulating layer IL2 can be a single-layer silicon oxide layer. A second conductive pattern CP2 can be disposed in the second insulating layer IL2. The second conductive pattern CP2 can be connected to the first conductive pattern CP1 through a second contact hole CH2.

[0069] A third insulating layer IL3 can be disposed on the second insulating layer IL2 and can be stacked together with the pixel. The third insulating layer IL3 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. In this embodiment, the third insulating layer IL3 can be a single-layer silicon oxide layer. A third conductive pattern CP3 can be disposed in the third insulating layer IL3. The third conductive pattern CP3 can be connected to the second conductive pattern CP2 through a third contact hole CH3.

[0070] A fourth insulating layer IL4 can be disposed on the third insulating layer IL3 and can be stacked together with the pixel. The fourth insulating layer IL4 can be an inorganic layer and / or an organic layer, and can have a single-layer structure or a multi-layer structure. In this embodiment, the fourth insulating layer IL4 can be a single-layer silicon oxide layer. A fourth conductive pattern CP4 can be disposed in the fourth insulating layer IL4. The fourth conductive pattern CP4 can be connected to the third conductive pattern CP3 through contact opening CO.

[0071] The contact opening CO formed in the fourth insulating layer IL4 can be divided into two regions. The contact opening CO may include a first region CO1 and a second region CO2. The first region CO1 has a relatively large width, and the second region CO2 is continuous with the first region CO1, disposed below the first region CO1, and has a relatively small width. The width of the first region CO1 is not necessarily limited to being constant in the thickness direction, and the width of the second region CO2 is not necessarily limited to being constant in the thickness direction. The variation in width between the first region CO1 and the second region CO2 can be greater than the variation in width in the first region CO1 or the variation in width in the second region CO2.

[0072] A conductive pattern is disposed in the contact opening CO. The conductive pattern can be defined as a fourth conductive pattern CP4. The fourth conductive pattern CP4 can have the same or substantially the same shape as the contact opening CO. The portion of the fourth conductive pattern CP4 disposed in the first region CO1 has a larger width (or area in the plan view), and the portion of the fourth conductive pattern CP4 disposed in the second region CO2 has a smaller width (or area in the plan view).

[0073] In this embodiment, the contact opening CO is shown to be formed in an insulating layer IL4, but this disclosure is not limited thereto. In embodiments of this disclosure, the contact opening CO may be formed in two or more insulating layers.

[0074] The barrier layer BL can also be disposed on the inner surface of the defining contact opening CO of the fourth insulating layer IL4. In other words, the barrier layer BL can also be disposed between the fourth conductive pattern CP4 and the inner surface of the fourth insulating layer IL4. The barrier layer BL may not be disposed on the upper surface of the fourth insulating layer IL4.

[0075] The barrier layer BL may include a barrier metal layer and / or a nitride layer of the barrier metal. The barrier metal layer may be directly disposed on the inner surface of the fourth insulating layer IL4, and the nitride layer of the barrier metal may be disposed on the barrier metal layer.

[0076] The barrier metal layer improves the adhesion of the fourth conductive pattern CP4, and the nitride layer of the barrier metal prevents or substantially prevents the diffusion of atoms of the fourth conductive pattern CP4. The barrier metal layer may include titanium or tantalum. The nitride layer of the barrier metal may include a titanium nitride layer or a tantalum nitride layer. For example, the barrier layer BL may include a titanium layer and a titanium nitride layer disposed on the titanium layer. Alternatively, the barrier layer BL may include a tantalum layer and a tantalum nitride layer disposed on the tantalum layer.

[0077] The fourth conductive pattern CP4 electrically connects the third conductive pattern CP3 below the fourth conductive pattern CP4 and the first electrode AE ​​above the fourth conductive pattern CP4 to each other. Furthermore, the fourth conductive pattern CP4 serves as a reflective layer for the light-emitting element. Resonance can be utilized in the light-emitting element to improve the luminous efficiency of the light generated in the light-emitting unit. Two reflective layers are disposed on both sides (e.g., opposite sides) of the light-emitting unit to generate resonance. Between the two sides (e.g., opposite sides) of the light-emitting unit, a translucent reflective layer can be disposed on the side through which light passes, and an opaque reflective layer with high reflectivity can be disposed on the opposite side. The fourth conductive pattern CP4 can be used as an opaque reflective layer.

[0078] The light-emitting element layer (EDL) can be disposed on the fourth insulating layer (IL4). Figure 3B The light-emitting element layer (EDL) shown may further include a pixel-defining film (PDL). The pixel-defining film (PDL) may be an organic layer. In this embodiment, a single-layer pixel-defining film (PDL) is shown as an example, but this disclosure is not limited thereto. The opening OP that partially exposes the first electrode AE ​​is defined in the pixel-defining film (PDL).

[0079] Opening OP is basically limited Figure 3AThe corresponding luminescent regions are LA1, LA2, and LA3. An opening OP is positioned in the fourth conductive pattern CP4 in the planar view to align the luminescent region of the emitting layer EL with the reflective region of the fourth conductive pattern CP4. Light generated in the luminescent regions LA1, LA2, and LA3 can be sufficiently reflected at the fourth conductive pattern CP4, which has a larger area. The width of the opening OP can be smaller than the width of the fourth conductive pattern CP4.

[0080] Figure 4 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0081] Reference Figure 4 The display device DD may include a display panel DP and a panel driver PDD. As an example, the panel driver PDD may include a drive controller 100, a data driver 200, a gate driver 300, and a voltage generator 400.

[0082] The display panel DP may include a display area DA and a non-display area NDA surrounding at least a portion of the display area DA (e.g., around the periphery of at least a portion of the display area DA). The display panel DP may include a plurality of pixels PX disposed in the display area DA. The display panel DP may include write scan lines GWL1 to GWLi and data lines DL1 to DLj, wherein i and j may be integers (or natural numbers) equal to or greater than 1.

[0083] The drive controller 100 receives an image signal RGB and a control signal CTRL. The drive controller 100 generates image data I_DATA by converting the data format of the image signal RGB to conform to the specifications of the interface with the data driver 200. The drive controller 100 outputs a first drive control signal SCS and a second drive control signal DCS.

[0084] The data driver 200 receives a second drive control signal DCS and image data I_DATA from the drive controller 100. The data driver 200 converts the image data I_DATA into a data signal and outputs the data signal to data lines DL1 to DLj. The data signal can be an analog voltage corresponding to the grayscale value of the image data I_DATA.

[0085] The gate driver 300 can be located in the non-display area NDA of the display panel DP. The gate driver 300 receives a first drive control signal SCS from the drive controller 100. The gate driver 300 can be connected to write scan lines GWL1 to GWLi. In response to the first drive control signal SCS, the gate driver 300 can output write scan signals to write scan lines GWL1 to GWLi.

[0086] A voltage generator 400 (e.g., a power supply unit) generates voltages for the operation of the display panel DP. In this embodiment, the voltage generator 400 may generate a first drive voltage ELVDD and a second drive voltage ELVSS.

[0087] Multiple pixels (PX) may each include a light-emitting element (ED) (e.g., see...). Figure 5A ) and pixel circuits PXCa for controlling the light emission of the light-emitting element ED (e.g., see Figure 5A The pixel circuit PXCa may include at least one transistor and at least one capacitor. The gate driver 300 may include a capacitor that interacts with the pixel circuit PXCa (e.g., see...). Figure 5A Transistors formed using the same or substantially the same process.

[0088] Multiple pixels PX can be electrically connected to write scan lines GWL1 to GWLi and data lines DL1 to DLj. For example, a pixel in the i-th row can be connected to the i-th write scan line GWLi, and a pixel in the j-th column can be connected to the j-th data line DLj. However, this disclosure is not limited thereto, and multiple pixels PX can be connected to more than one scan line.

[0089] Multiple pixels PX can be connected to a first power line and a second power line. The first power line receives a first drive voltage ELVDD from the voltage generator 400, and the second power line receives a second drive voltage ELVSS from the voltage generator 400. However, this disclosure is not limited thereto, and multiple pixels PX can each receive a preliminary voltage and / or a reference voltage.

[0090] Figure 5A This is a circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 5B This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0091] As an example, Figure 5A A pixel PXa is shown, comprising a pixel circuit PXCa and a light-emitting element ED electrically connected to the pixel circuit PXCa. As an example, Figure 5B The diagram shows a pixel PXb comprising a pixel circuit PXCb and a light-emitting element ED electrically connected to the pixel circuit PXCb. Because besides... Figure 5A The pixel circuit PXCa and Figure 5B In addition to the first transistor T1 of the pixel circuit PXCb, which is a P-type transistor (e.g., PMOS) and an N-type transistor (e.g., NMOS), Figure 5A The pixel circuit PXCa and Figure 5B The pixel circuit PXCb comprises components that are similar to each other, and can therefore be described in more detail below. Figure 5A The pixel PXa, and can be used without repeating about Figure 5BRedundant description of pixel PXb.

[0092] In the embodiments, reference is made to Figure 5A The pixel circuit PXCa may include two transistors (e.g., a first transistor T1 and a second transistor T2) and a capacitor Cst. Both the first transistor T1 and the second transistor T2 may be transistors with a low-temperature polycrystalline silicon (LTPS) semiconductor layer. As an example, the first transistor T1 and the second transistor T2 may be P-type transistors.

[0093] Pixel PXa can be connected to the i-th write scan line GWLi among multiple write scan lines GWL1 to GWLi, and can be connected to the j-th data line DLj among multiple data lines DL1 to DLj (for example, see...). Figure 4 The i-th write scan line GWLi can transmit the i-th write scan signal GWi to pixel PXa, and the j-th data line DLj can transmit the j-th data signal DSj to pixel PXa. The j-th data signal DSj can have the same characteristics as the drive controller 100 (e.g., see [link]). Figure 4 The voltage level corresponding to the grayscale value of the output image data I_DATA.

[0094] Pixel PXa can be connected to a first power line PL1 that receives a first driving voltage ELVDD and a second power line PL2 that receives a second driving voltage ELVSS. The first driving voltage ELVDD can have a higher voltage level than the second driving voltage ELVSS.

[0095] The light-emitting element (ED) may include an anode and a cathode. If the ED is an organic light-emitting element, it may further include an organic layer disposed between the anode and the cathode. The anode of the ED may be connected to the pixel circuit PXCa. The cathode of the ED may be connected to the second power line PL2. The ED emits light in accordance with the amount of current flowing through the first transistor T1 of the pixel circuit PXCa.

[0096] A first transistor T1 is connected between the anode of the light-emitting element ED and the first power line PL1, which receives the first driving voltage ELVDD. The first transistor T1 can be referred to as a driving transistor. The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The gate electrode may be connected to a first node N1, the first electrode may be electrically connected to the first power line PL1, and the second electrode may be connected to the anode of the light-emitting element ED. The first electrode may be referred to as the source region SA1 of the first transistor T1, and the second electrode may be referred to as the drain region DRA1 of the first transistor T1. According to the switching operation of the second transistor T2, the first transistor T1 can receive the j-th data signal DSj transmitted by the j-th data line DLj and can supply a driving current Id to the light-emitting element ED.

[0097] Figure 5A This illustrates the case where the first transistor T1 is a P-type transistor. Therefore, the source region SA1 of the first transistor T1 is electrically connected to the first power line PL1, and the drain region DRA1 of the first transistor T1 is electrically connected to the anode of the light-emitting element ED. However, as... Figure 5B As shown, when the first transistor T1 is an N-type transistor, the source region SA1 of the first transistor T1 can be electrically connected to the anode of the light-emitting element ED, and the drain region DRA1 of the first transistor T1 can be electrically connected to the first power line PL1.

[0098] However, this disclosure is not limited thereto, and as follows Figure 5C As shown, when the first transistor T1 is a P-type transistor, a third transistor T3 for controlling light emission may be additionally disposed between the source region SA1 of the first transistor T1 and the first electric field line PL1. Furthermore, in some embodiments, when the first transistor T1 is an N-type transistor, a transistor for controlling light emission may be additionally disposed between the source region SA1 of the first transistor T1 and the anode of the light-emitting element ED.

[0099] According to embodiments of this disclosure, when the first transistor T1 is a P-type transistor, the source region SA1 and the first electric field line PL1 of the first transistor T1 can be directly connected to each other without any additional transistors between them, or only a transistor for controlling light emission can be provided (e.g., Figure 5CThe third transistor T3), and a transistor that can be used as a resistor may not be provided between the source region SA1 of the first transistor T1 and the first electric field line PL1. Similarly, when the first transistor T1 is an N-type transistor, the source region SA1 of the first transistor T1 and the anode of the light-emitting element ED may be directly connected to each other without an additional transistor between them, or only a transistor for controlling light emission may be provided between the source region SA1 of the first transistor T1 and the anode of the light-emitting element ED, and a transistor that can be used as a resistor may not be provided. Therefore, a display device DD in which the number of transistors can be reduced can be provided (for example, see Figure 4 ).

[0100] A second transistor T2 is connected between the j-th data line DLj and the first node N1, and receives the i-th write scan signal GWi. The second transistor T2 can be referred to as a switching transistor. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a gate electrode connected to the i-th write scan line GWLi. The second transistor T2 can be turned on by the i-th write scan signal GWi received through the i-th write scan line GWLi, and can transmit the j-th data signal DSj transmitted from the j-th data line DLj to the first node N1.

[0101] A capacitor Cst may be connected between a first power line PL1, which provides the first drive voltage ELVDD, and a first node N1. The capacitor Cst may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. The capacitor Cst may store the voltage difference between the first power line PL1 and the first node N1.

[0102] Figure 5C This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0103] As an example, Figure 5CA pixel PXc is illustrated, comprising a pixel circuit PXCc and a light-emitting element ED electrically connected to the pixel circuit PXCc. In this embodiment, the pixel circuit PXCc may include four transistors (e.g., first transistor T1, second transistor T2, third transistor T3, and fourth transistor T4) and three capacitors (e.g., first capacitor C1, second capacitor C2, and third capacitor C3). Each of the first transistors T1 to the fourth transistor T4 may be a transistor having an LTPS semiconductor layer. As an example, some of the first transistors T1 to the fourth transistor T4 may be P-type transistors, and the others may be N-type transistors. For example, among the first transistors T1 to the fourth transistor T4, the first transistors T1 to the third transistor T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor including an oxide semiconductor as its semiconductor layer. As another example, all of the first transistors T1 to the fourth transistor T4 may be P-type transistors, or all of the first transistors T1 to the fourth transistor T4 may be N-type transistors.

[0104] A first transistor T1 is connected between a first power line PL1 receiving a first driving voltage ELVDD and the anode of a light-emitting element ED. The first transistor T1 can be referred to as a driving transistor. The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The gate electrode may be connected to a first node N1, the first electrode may be connected to a second node N2, and the second electrode may be connected to the anode of the light-emitting element ED. The first electrode may be referred to as the source of the first transistor T1, and the second electrode may be referred to as the drain of the first transistor T1. According to the switching operation of the second transistor T2, the first transistor T1 can receive the j-th data signal DSj transmitted by the j-th data line DLj, and can supply a driving current Id to the light-emitting element ED.

[0105] A second transistor T2 is connected between the j-th data line DLj and the first node N1, and receives the i-th write scan signal GWi. The second transistor T2 can be referred to as a switching transistor. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a gate electrode connected to the i-th write scan line GWLi. The second transistor T2 can be turned on by the i-th write scan signal GWi received through the i-th write scan line GWLi, and can transmit the j-th data signal DSj transmitted from the j-th data line DLj to the first node N1.

[0106] The third transistor T3 is connected between the first power line PL1 and the second node N2, and receives the i-th light-emitting control signal EMi. The third transistor T3 can be turned on according to the i-th light-emitting control signal EMi received through the light-emitting control line EMi. The first driving voltage ELVDD applied through the turned-on third transistor T3 can be transmitted to the light-emitting element ED through the first transistor T1.

[0107] The fourth transistor T4 can be connected between the first voltage line VL1, which provides the initialization voltage VINT, and the anode of the light-emitting element ED, and can receive the i-th reset scan signal GRi. The fourth transistor T4 can be turned on by the i-th reset scan signal GRi received through the i-th reset scan line GRLi, and can transmit the initialization voltage VINT to the anode of the light-emitting element ED.

[0108] As an example, each of the first transistor T1 to the fourth transistor T4 may further include a third electrode. The third electrode of each of the first transistor T1 to the fourth transistor T4 may be connected to a substrate (e.g., Figure 6 The semiconductor substrate (SS) allows the substrate to have a constant or substantially constant voltage. For example... Figure 5C As shown, the third electrode of each of the first transistors T1 to the third transistor T3 can receive the first drive voltage ELVDD, and the third electrode of the fourth transistor T4 can receive the ground voltage GND.

[0109] A first capacitor C1 can be connected between the first node N1 and the second node N2. The first capacitor C1 can store the voltage difference between the first node N1 and the second node N2.

[0110] The second capacitor C2 can be connected between the first node N1 and the second voltage line VL2, which provides the reference voltage VREF. The second capacitor C2 can store the voltage difference between the first node N1 and the second voltage line VL2.

[0111] A third capacitor C3 can be connected between the first node N1 and the first voltage line VL1, which provides the initialization voltage VINT. The third capacitor C3 can store the voltage difference between the first node N1 and the first voltage line VL1.

[0112] However, this disclosure is not limited thereto. In addition to the above references... Figure 5A , Figure 5B and Figure 5C Aside from the configuration of the pixel circuits PXCa, PXCb, and PXCc described, the number of transistors or capacitors can be modified in various ways according to the desired design of the pixel circuits.

[0113] Figure 6 This is a block diagram of a first transistor according to an embodiment of the present disclosure. Figure 7 This is a block diagram of a second transistor according to an embodiment of the present disclosure.

[0114] Reference Figure 6 A first transistor T1 can be formed in and on a semiconductor substrate SS. The first transistor T1 may include a channel region CHA1, a source region SA1 adjacent to a first side of the channel region CHA1, a drain region DRA1 adjacent to a second side of the channel region CHA1, a gate insulating layer GIN1 disposed on the channel region CHA1, and a gate GA1 disposed on the gate insulating layer GIN1.

[0115] The semiconductor substrate SS can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. At least a portion of the semiconductor substrate SS can be doped with a first type of impurity. Each of the source region SA1 and the drain region DRA1 can be a region doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. For example, if the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. As another example, if the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0116] The gate GA1 of the first transistor T1 can be disposed correspondingly to the source region SA1 and the drain region DRA1. The source region SA1 and the drain region DRA1 can be formed asymmetrically with respect to the gate GA1. In other words, the source region SA1 of the first transistor T1 can be spaced apart from the gate GA1 in a planar view, and the drain region DRA1 of the first transistor T1 can be adjacent to the gate GA1 in a planar view.

[0117] The region between the source region SA1 and the drain region DRA1 can be referred to as the channel region CHA1. When a voltage is applied to the gate GA1, the channel region CHA1 can be formed at the semiconductor substrate SS due to the field effect, and current can flow through the channel region CHA1. In this embodiment, when a voltage is applied to the gate GA1 of the first transistor T1, current can flow from the source region SA1 through the channel region CHA1 to the drain region DRA1.

[0118] The channel region CHA1 may include a first channel region CHA1-1 and a second channel region CHA1-2. The first channel region CHA1-1 may be the area of ​​the channel region CHA1 that is superimposed on the gate GA1 in the plan view, and the second channel region CHA1-2 may be the area of ​​the channel region CHA1 that is not superimposed on the gate GA1 in the plan view. The drain region DRA1 may be adjacent to the first channel region CHA1-1 and may be superimposed on the gate GA1 in the plan view. The source region SA1 may be adjacent to the second channel region CHA1-2 and may be spaced apart from the gate GA1 in the plan view.

[0119] In the planar view, the second channel region CHA1-2 may not be superimposed on the gate GA1. Therefore, when a voltage is applied to the gate GA1 of the first transistor T1 and current flows from the source region SA1 to the drain region DRA1, fewer charge carriers (e.g., holes or charges) may accumulate in the second channel region CHA1-2 than in the first channel region CHA1-1. Thus, the second channel region CHA1-2 can have a higher resistance than the first channel region CHA1-1. In other words, the second channel region CHA1-2 can operate as a resistor. Therefore, the source region SA1 can be spaced apart from the gate GA1 in the planar view and can operate as a resistor (e.g., a predetermined resistor) connected to the source region SA1 of the first transistor T1. When the transistor is formed on the semiconductor substrate SS, even a small change in the gate voltage can significantly alter the drive current. Therefore, even a small voltage change can significantly produce differences in pixel brightness between adjacent pixels, resulting in uneven brightness. According to this embodiment, because a resistor can be added to the source region SA1 of the first transistor T1, the source voltage is affected when the drive current changes, and the change in current is slowed down by the feedback effect. Therefore, abrupt changes in current can be prevented or substantially prevented, thereby providing a display device with uniform brightness.

[0120] Reference Figure 7 A second transistor T2 can be formed in and on a semiconductor substrate SS. The second transistor T2 may include a channel region CHA2, a source region SA2 adjacent to a first side of the channel region CHA2, a drain region DRA2 adjacent to a second side of the channel region CHA2, a gate insulating layer GIN2 disposed on the channel region CHA2, and a gate GA2 disposed on the gate insulating layer GIN2.

[0121] The gate GA2 of the second transistor T2 can be disposed correspondingly to the source region SA2 and the drain region DRA2. The source region SA2 and the drain region DRA2 of the second transistor T2 can be formed symmetrically with respect to the gate GA2. In other words, the source region SA2 of the second transistor T2 can be adjacent to the gate GA2 in a planar view, and the drain region DRA2 of the second transistor T2 can be adjacent to the gate GA2 in a planar view.

[0122] The source region SA2 may include a first low-concentration impurity region LDD1 adjacent to the channel region CHA2, and the drain region DRA2 may include a second low-concentration impurity region LDD2 adjacent to the channel region CHA2. The first low-concentration impurity region LDD1 may be a region with a low impurity concentration in the source region SA2. The second low-concentration impurity region LDD2 may be a region with a low impurity concentration in the drain region DRA2. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA2 and the drain region DRA2 can be increased. Therefore, because the length of the channel region CHA2 of the second transistor T2 can be increased, breakdown and hot carrier phenomena caused by a shorter channel can be prevented or substantially prevented.

[0123] Figure 8 This is a plan view of a first transistor according to an embodiment of the present disclosure. Figure 9 This is a plan view of the second transistor according to an embodiment of the present disclosure.

[0124] Reference Figure 8 and Figure 9 The first transistor T1 and the second transistor T2 may respectively include a channel region CHA1 between the source region SA1 and the drain region DRA1 and a channel region CHA2 between the source region SA2 and the drain region DRA2. The channel region CHA1 of the first transistor T1 may include a first channel region CHA1-1 superimposed on the gate GA1 and a second channel region CHA1-2 not superimposed on the gate GA1. The channel region CHA2 of the second transistor T2 may be completely superimposed on the gate GA2. The source region SA1 and drain region DRA1 of the first transistor T1 and the source region SA2 and drain region DRA2 of the second transistor T2 can be electrically connected to the light-emitting element ED above them (e.g., see [link to related document]). Figure 5A ).

[0125] A first source length SL1 and a first drain length DRL1 can be defined in the first transistor T1. The first source length SL1 is the sum of the length of the source region SA1 in the first direction DR1 and the length of the second channel region CHA1-2. The first drain length DRL1 is the length of the drain region DRA1 that is not superimposed on the gate GA1 in the first direction DR1. Because the first source length SL1 includes the length of the second channel region CHA1-2, the first source length SL1 can be greater than the first drain length DRL1.

[0126] A second source length SL2 and a second drain length DRL2 can be defined in the second transistor T2. The second source length SL2 is the length of the region of the source region SA2 that is not superimposed on the gate GA2 in the first direction DR1. The second drain length DRL2 is the length of the region of the drain region DRA2 that is not superimposed on the gate GA2 in the first direction DR1. The second source length SL2 can be the same as or substantially the same as the second drain length DRL2. As an example, the first drain length DRL1, the second drain length DRL2, and the second source length SL2 can be the same as or substantially the same as each other.

[0127] The gate GA1 of the first transistor T1 can have a first length L1, and the gate GA2 of the second transistor T2 can have a second length L2. As an example, the first length L1 can be greater than the second length L2. In other words, the length of the channel region CHA1 of the first transistor T1 can be greater than the length of the channel region CHA2 of the second transistor T2. Because the channel region CHA1 is longer, when a voltage is applied to the gate GA1, the field effect can be distributed throughout the longer channel region CHA1. Therefore, abrupt changes in the drive current, even caused by small voltage variations, can be prevented or substantially prevented, thereby providing a display device with uniform brightness.

[0128] Figures 10A to 10F This is a cross-sectional view illustrating a method of manufacturing a first transistor according to an embodiment of the present disclosure.

[0129] Reference Figure 10A A preliminary semiconductor substrate (PSS) doped with a first type of impurity can be prepared. The entire region of the preliminary semiconductor substrate PSS can be doped with the first type of impurity. The preliminary semiconductor substrate PSS may include a first doped region AR1 and a second doped region AR2. The preliminary semiconductor substrate PSS can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first doped region AR1 and the second doped region AR2 can be doped with a second impurity using a first mask MK1. In a planar view, the first mask MK1 may not be superimposed on the first doped region AR1 and the second doped region AR2.

[0130] Reference Figure 10BThe semiconductor substrate SS may include a source region SA1 and a drain region DRA1. The source region SA1 and drain region DRA1 may be formed by doping a first doped region AR1 and a second doped region AR2 of the preliminary semiconductor substrate PSS, respectively. The source region SA1 and drain region DRA1 may be doped with impurities different from those in the preliminary semiconductor substrate PSS. In other words, the semiconductor substrate SS can be provided by doping the first doped region AR1 and the second doped region AR2 in the preliminary semiconductor substrate PSS with a second impurity and doping the remaining region of the preliminary semiconductor substrate PSS with a first type of impurity to form the source region SA1 and drain region DRA1. The source region SA1 and drain region DRA1 may be formed to be spaced apart from each other in a planar view.

[0131] Reference Figure 10C A preliminary gate insulating layer (PGIN) can be formed on the upper surface of a semiconductor substrate (SS). The preliminary gate insulating layer (PGIN) may include silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and / or titanium dioxide (TiO2).

[0132] Reference Figure 10D A preliminary gate PGA can be formed on the upper surface of the preliminary gate insulating layer PGIN. The preliminary gate PGA may include polysilicon, titanium nitride (TiN), tungsten (W), molybdenum (Mo), and / or aluminum (Al).

[0133] Reference Figure 10E The initial gate insulating layer PGIN and the initial gate PGA can be etched using a second mask MK2. The second mask MK2 can be stacked with the gate insulating layer GIN1 and the gate GA1 to form... Figure 10F The gate insulating layer GIN1 and gate GA1 are shown. The second mask MK2 may be spaced apart from the source region SA1 in a planar view and may be partially stacked with the drain region DRA1 in a planar view. However, this disclosure is not limited thereto, and the second mask MK2 may not be stacked with the drain region DRA1 in a planar view. As an example, the first mask MK1 may be stacked with the second channel region CHA1-2 (e.g., see...). Figure 6 The second mask MK2 may not be stacked with the second channel region CHA1-2. Therefore, in the process of forming the first transistor T1, the channel region CHA1 between the source region SA1 and the drain region DRA1 (for example, see...) Figure 6 The first mask MK1 can be used to define the second channel region CHA1, which is not superimposed on the gate GA1. The second channel region CHA1-2 of the channel region CHA1 can be used to define the second mask MK2.

[0134] Reference Figure 10FGate insulating layers GIN1 and GA1 can be formed by etching preliminary gate insulating layers PGIN and preliminary gate PGA. Gate insulating layers GIN1 and GA1 can be spaced apart from the source region SA1 in a planar view and can be partially stacked with the drain region DRA1 in a planar view. However, this disclosure is not limited thereto, and gate insulating layers GIN1 and GA1 may not be stacked with the drain region DRA1 in a planar view.

[0135] Figure 11 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0136] Reference Figure 11 The electronic device 601 outputs various information through the display module 640 in the operating system. When the processor 610 executes the application stored in the memory 620, the display module 640 provides application information to the user through the display panel 641.

[0137] The processor 610 receives external input via the input module 630 or the sensor module 661 and executes the application corresponding to the external input. For example, when a user selects the camera icon displayed on the display panel 641, the processor 610 receives user input via the input sensor 661-2 and activates the camera module 671. The processor 610 sends image data corresponding to the captured image obtained by the camera module 671 to the display module 640. The display module 640 can display the image corresponding to the captured image via the display panel 641.

[0138] As another example, when personal information authentication is performed in display module 640, fingerprint sensor 661-1 obtains the input fingerprint information as input data. Processor 610 compares the input data obtained by fingerprint sensor 661-1 with the authentication data stored in memory 620 and executes the application based on the comparison result. Display module 640 can display the information executed according to the application logic via display panel 641.

[0139] As another example, when the music stream icon displayed on the display module 640 is selected, the processor 610 obtains user input through the input sensor 661-2 and activates the music stream application stored in the memory 620. When a music execution command is entered in the music stream application, the processor 610 activates the sound output module 663 and provides the user with sound information corresponding to the music execution command.

[0140] The operation of electronic device 601 has been briefly described above. The configuration of electronic device 601 is described in more detail below. Some components of electronic device 601, which will be described in more detail below, can be integrated with each other and configured as a single component, and a single component can be divided into two or more components.

[0141] Reference Figure 11 Electronic device 601 can communicate with external electronic device 602 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to embodiments, electronic device 601 may include a processor 610, a memory 620, an input module 630, a display module 640, a power module 650, an internal module 660, and an external module 670. According to embodiments, at least one of the aforementioned components may be omitted from electronic device 601 as needed or desired, or one or more other components may be added. According to embodiments, some components (e.g., sensor module 661, antenna module 662, or audio output module 663) may be integrated into another component (e.g., display module 640).

[0142] The processor 610 can execute software to control at least one other component (e.g., a hardware or software component) of the electronic device 601 connected to the processor 610, and can perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, the processor 610 can store data or commands received from another component (e.g., input module 630, sensor module 661, or communication module 673) in volatile memory 621, and can process the data or commands stored in volatile memory 621, so that the resulting data can be stored in non-volatile memory 622.

[0143] Processor 610 may include a main processor 611 and an auxiliary processor 612. Main processor 611 may include one or more of a central processing unit (CPU) 611-1 and / or an application processor (AP). Main processor 611 may also include one or more of a graphics processing unit (GPU) 611-2, a communication processor (CP), and / or an image signal processor (ISP). Main processor 611 may also include a neural processing unit (NPU) 611-3. The neural processing unit may be a processor specifically designed for processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but this disclosure is not limited thereto. In addition to hardware architecture, the artificial intelligence model may also include software architecture, or the artificial intelligence model may include software architecture instead of hardware architecture. At least two of the aforementioned processing units and / or processors may be implemented as an integrated component (e.g., a single chip) or may each be implemented as an independent component (e.g., multiple chips).

[0144] The auxiliary processor 612 may include a drive controller 612-1. The drive controller 612-1 may include an interface conversion circuit and a timing control circuit. The drive controller 612-1 receives image signals from the main processor 611, converts the data format of the image signals to conform to the specifications of the interface with the display module 640, and outputs the image data. The drive controller 612-1 can output various control signals for driving the display module 640. Because the configuration of the drive controller 612-1 can be compared with the above... Figure 4 The configuration of the drive controller 100 described is the same or substantially the same (or similar), so its redundant description need not be repeated.

[0145] The auxiliary processor 612 may also include a data conversion circuit 612-2, a gamma correction circuit 612-3, and / or a rendering circuit 612-4. The data conversion circuit 612-2 can receive image data from the drive controller 612-1 and can compensate the image data to display the image at the desired brightness according to the characteristics of the electronic device 601, user settings, etc., or can convert the image data to reduce power consumption, compensate for image retention, etc. The gamma correction circuit 612-3 can convert image data, gamma reference voltage, etc., so that the image displayed on the electronic device 601 has the desired gamma characteristics. The rendering circuit 612-4 can receive image data from the drive controller 612-1 and can render the image data considering the pixel arrangement of the display panel 641 of the electronic device 601, etc. At least one of the data conversion circuit 612-2, gamma correction circuit 612-3, and rendering circuit 612-4 can be integrated into another component (e.g., the main processor 611 or the drive controller 612-1). At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 can be integrated into the data driver 643, which will be described in more detail below.

[0146] The memory 620 may store various data used by at least one component of the electronic device 601 (e.g., processor 610 or sensor module 661), and may output or input data about commands associated therewith. The memory 620 may include at least one of volatile memory 621 and non-volatile memory 622.

[0147] The input module 630 can receive data or commands from outside the electronic device 601 (e.g., from a user or external electronic device 602) that will be used in components of the electronic device 601 (e.g., processor 610, sensor module 661, or sound output module 663).

[0148] Input module 630 may include a first input module 631 for inputting commands or data from a user and a second input module 632 for inputting commands or data from an external electronic device 602. The first input module 631 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 632 may support a specified protocol for wired or wireless connection to the external electronic device 602. According to embodiments, the second input module 632 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 632 may include a connector for physical connection to the external electronic device 602 (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)).

[0149] Display module 640 visually provides information to the user. Display module 640 may include a display panel 641, a gate driver 642, and a data driver 643. Display module 640 may also include a rack, support, and window for protecting the display panel 641. Display module 640 may also include a light-emitting driver, a voltage generator, etc. The voltage generator can output various voltages for driving the display panel 641 (e.g., ...). Figure 4 The first drive voltage ELVDD and the second drive voltage ELVSS). Because the configuration of the display panel 641, gate driver 642, data driver 643 and voltage generator is the same as described above. Figure 4 The configurations of the described display panel DP, gate driver 300, and data driver 200 are the same or substantially the same (or similar), so their redundant descriptions need not be repeated.

[0150] Power module 650 supplies power to components of electronic device 601. Power module 650 may include a battery that is charged to a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 650 may include a power management integrated circuit (PMIC). The PMIC provides optimized power to each of the modules described above and those described in more detail below. Power module 650 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0151] The electronic device 601 may also include an internal module 660 and an external module 670. The internal module 660 may include a sensor module 661, an antenna module 662, and a sound output module 663. The external module 670 may include a camera module 671, an optical module 672, and a communication module 673.

[0152] The sensor module 661 can sense input from the user's body or from the pen in the first input module 631, and can generate data values ​​or electrical signals corresponding to the input. The sensor module 661 may include at least one of a fingerprint sensor 661-1, an input sensor 661-2, and a digitizer 661-3.

[0153] The fingerprint sensor 661-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 661-1 may include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0154] Input sensor 661-2 can generate data values ​​corresponding to coordinate information about input from the user's body or from a pen. Input sensor 661-2 generates the amount of capacitance change caused by the input as a data value. Input sensor 661-2 can sense input from a passive pen or send data to / receive data from an active pen.

[0155] Input sensor 661-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a part of a user's body is in contact with the sensor layer or sensor panel and remains stationary for a certain period of time, input sensor 661-2 can sense biosignals based on changes in the electric field caused by the part of the user's body and output the information desired by the user to display module 640.

[0156] The digitizer 661-3 can generate data values ​​corresponding to coordinate information about input from a pen. The digitizer 661-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 661-3 can sense input from a passive pen or send / receive data to / from an active pen.

[0157] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be implemented as a sensor layer formed on the display panel 641 by a continuous process. The fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be disposed above the display panel 641, and any one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 (such as the digitizer 661-3) can be disposed below the display panel 641.

[0158] At least two of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 can be integrated into a single sensing panel using the same process. When at least two of the fingerprint sensor 661-1, input sensor 661-2, and digitizer 661-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel 641 and a window positioned above the display panel 641. According to an embodiment, the sensing panel can be positioned on the window, and the position of the sensing panel is not particularly limited.

[0159] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be integrated into the display panel 641. In other words, at least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 can be formed concurrently (e.g., simultaneously or substantially simultaneously) by the process of forming elements (e.g., light-emitting elements and / or transistors, etc.) included in the display panel 641.

[0160] Furthermore, sensor module 661 can generate data values ​​or electrical signals corresponding to the internal or external states of electronic device 601. Sensor module 661 may also include, for example, gesture sensors, gyroscope sensors, atmospheric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0161] Antenna module 662 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to an embodiment, communication module 673 may transmit or receive signals from an external electronic device via an antenna suitable for a communication method. The antenna pattern of antenna module 662 may be integrated into a component of display module 640 (e.g., display panel 641), input sensors 661-2, etc.

[0162] The sound output module 663 can be a device for outputting sound signals to the outside of the electronic device 601, and may include, for example, a speaker for general purposes such as playing multimedia or playing recordings, and a receiver for receiving calls only. According to embodiments, the receiver may be integrated with the speaker or formed separately from the speaker. The sound output mode of the sound output module 663 may be integrated into the display module 640.

[0163] Camera module 671 can capture still images and moving images. According to embodiments, camera module 671 may include one or more lenses, image sensors, or image signal processors. Camera module 671 may also include an infrared camera capable of measuring the presence / absence of a user, the user's position, the user's gaze, etc.

[0164] The optical module 672 can provide light. The optical module 672 may include a light-emitting diode or a xenon lamp. The optical module 672 may operate in conjunction with the camera module 671 or independently.

[0165] Communication module 673 can support the establishment of a wired or wireless communication channel between electronic device 601 and external electronic device 602, and perform communication via the established communication channel. Communication module 673 may include any one or both of a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 673 can communicate with external electronic device 602 via a short-range communication network (such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA)) or a long-range communication network (such as a cellular network, the Internet, or a computer network (e.g., a LAN or a WAN)). The various communication modules 673 described above can be implemented as a single chip, or each can be implemented as a separate chip.

[0166] The input module 630, sensor module 661, camera module 671, etc., can be used to control the operation of the display module 640 in association with the processor 610.

[0167] The processor 610 outputs commands or data to the display module 640, sound output module 663, camera module 671, or optical module 672 based on the input data received from the input module 630. For example, the processor 610 can generate image data corresponding to input data applied via a mouse, active pen, etc., and output the image data to the display module 640; or it can generate command data corresponding to the input data and output the command data to the camera module 671 or optical module 672. When no input data is received from the input module 630 within a certain time period, the processor 610 can change the operating mode of the electronic device 601 to a low-power mode or sleep mode, thereby reducing the power consumption of the electronic device 601.

[0168] The processor 610 outputs commands or data to the display module 640, the sound output module 663, the camera module 671, or the optical module 672 based on the sensing data received from the sensor module 661. For example, the processor 610 can compare the authentication data applied by the fingerprint sensor 661-1 with the authentication data stored in the memory 620, and then execute the application based on the comparison result. The processor 610 can execute commands or output corresponding image data to the display module 640 based on the sensing data sensed by the input sensor 661-2 or the digitizer 661-3. If the sensor module 661 includes a temperature sensor, the processor 610 can receive temperature data about the measured temperature from the sensor module 661, and can also perform brightness correction on image data, etc., based on the temperature data.

[0169] Processor 610 can receive measurement data from camera module 671 regarding the presence / absence of a user, the user's position, and / or the user's gaze. Processor 610 can also perform brightness correction on image data, etc., based on the measurement data. For example, processor 610 determines the presence / absence of a user from input from camera module 671, and can then output image data with brightness corrected by data conversion circuit 612-2 or gamma correction circuit 612-3 to display module 640.

[0170] Some of the aforementioned components can be connected to each other via communication methods such as peripheral devices (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or hyperpath interconnect (UPI) links) and can exchange signals (e.g., commands or data). The processor 610 can communicate with the display module 640 via a mutual recognition interface, and for example, any of the aforementioned communication methods can be used, but not limited to them.

[0171] Electronic device 601 according to various embodiments can be a variety of suitable forms of device. For example, electronic device 601 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. Electronic device 601 is not limited to the devices described above.

[0172] Figure 12 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0173] Figure 12 An augmented reality (AR) glasses example of a wearable device is shown. The electronic device ELD may include glasses GR and a frame FR mounted on the glasses GR. The frame FR may accommodate the above reference. Figure 11The described display panel 641, or one that can accommodate the above reference, Figure 11 Other modules described. The light guide LG that guides the image generated at display panel 641 can be mounted on frame FR.

[0174] The glasses GR can be worn on the user's head. In this embodiment, since augmented reality (AR) glasses are described as an example of a wearable device, the structure with the frame FR is described as glasses. This structure can vary depending on the type of wearable device. Furthermore, this structure can be omitted depending on the type of electronic device ELD.

[0175] According to some embodiments of this disclosure, a region that operates like a resistor can be added by arranging the gate and source regions of the driving transistor to be spaced apart from each other in a planar view. By adding a resistor to the source region of the driving transistor, abrupt changes in the drive current can be prevented or substantially prevented.

[0176] Furthermore, according to some embodiments of this disclosure, the length of the gate of the driving transistor can be greater than the length of the gate of the switching transistor. In this case, the channel of the driving transistor can be formed to have a greater length, thereby preventing or substantially preventing abrupt changes in the drive current.

[0177] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise stated, the description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless explicitly stated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various variations of the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: Semiconductor substrate; as well as A plurality of pixels, in and on the semiconductor substrate, each of the plurality of pixels comprising: Light-emitting elements; A first transistor is located between the first power line and the light-emitting element; and The second transistor is located between the data line and the first transistor. The first transistor includes a channel region, a source region adjacent to a first side of the channel region, a drain region adjacent to a second side of the channel region, and a gate region on the channel region. The channel region of the first transistor includes a first channel region that is superimposed on the gate of the first transistor in a plan view and a second channel region that is not superimposed on the gate of the first transistor in a plan view.

2. The display device according to claim 1, wherein, The first transistor includes a PMOS transistor.

3. The display device according to claim 2, wherein, The source region of the first transistor is electrically connected to the first power line.

4. The display device according to claim 1, wherein, The first transistor includes an NMOS transistor.

5. The display device according to claim 4, wherein, The source region of the first transistor is electrically connected to the light-emitting element.

6. The display device according to claim 1, wherein, At least a portion of the semiconductor substrate is doped with a first impurity, and The source region and the drain region of the first transistor are doped with a second impurity that is different from the first impurity.

7. The display device according to claim 1, wherein, The gate and the source region of the first transistor are spaced apart from each other in a plan view, and the gate and the drain region of the first transistor are adjacent to each other in a plan view.

8. The display device according to claim 1, wherein, The second transistor includes a channel region, a source region adjacent to a first side of the channel region of the second transistor, a drain region adjacent to a second side of the channel region of the second transistor, and a gate on the channel region of the second transistor. In the plan view, the channel region of the second transistor is completely superimposed on the gate of the second transistor.

9. The display device according to claim 8, wherein, The gate and source regions of the second transistor are adjacent to each other in the plan view, and the gate and drain regions of the second transistor are adjacent to each other in the plan view.

10. The display device according to claim 8, wherein, The first source length and the first drain length of the first transistor are different from each other, and In this transistor, the second source length and the second drain length are the same.

11. The display device according to claim 8, wherein, The length of the gate of the first transistor is greater than the length of the gate of the second transistor.

12. The display device according to claim 1, wherein, The resistance of the second channel region is higher than that of the first channel region.

13. A method of manufacturing a display device, the method comprising: Prepare a preliminary semiconductor substrate doped with a first impurity; The semiconductor substrate is provided by forming a source region and a drain region by doping a first doped region and a second doped region of the preliminary semiconductor substrate with a second impurity using a first mask; A preliminary gate insulating layer is formed on the upper surface of the semiconductor substrate; A preliminary gate is formed on the upper surface of the preliminary gate insulating layer; as well as The gate insulating layer and the gate are formed by etching the initial gate insulating layer and the initial gate using a second mask. The display device includes a first channel region that is superimposed on the gate in a plan view and a second channel region that is not superimposed on the gate in a plan view between the source region and the drain region.

14. The method according to claim 13, wherein, The display device includes a plurality of pixels disposed in and on the semiconductor substrate, each of the plurality of pixels comprising: Light-emitting elements; A first transistor is disposed between a first power line and the light-emitting element; and The second transistor is disposed between the data line and the first transistor, and The first transistor includes the source region, the drain region, and the gate.

15. The method according to claim 14, wherein, The gate and the source region of the first transistor are spaced apart from each other in a plan view, and the gate and the drain region of the first transistor are adjacent to each other in a plan view.

16. The method of claim 14, wherein, The first mask is not superimposed on the source region and the drain region of the first transistor in the plan view.

17. The method according to claim 14, wherein, The second mask is superimposed on the gate insulating layer and the gate of the first transistor in the plan view.

18. The method according to claim 13, wherein, The first mask is superimposed on the second channel region in the plan view, and the second mask is not superimposed on the second channel region in the plan view.

19. The method according to claim 13, wherein, The resistance of the second channel region is higher than that of the first channel region.

20. An electronic device, the electronic device comprising: Display panel; A frame that houses the display panel; as well as The structure, on which the frame is mounted, The display panel includes: Semiconductor substrate; and Multiple pixels, in and on the semiconductor substrate, Each of the plurality of pixels includes: Light-emitting elements; A first transistor is located between the first power line and the light-emitting element; and The second transistor is located between the data line and the first transistor. The first transistor includes a channel region, a source region adjacent to a first side of the channel region, a drain region adjacent to a second side of the channel region, and a gate region on the channel region. The channel region of the first transistor includes a first channel region that is superimposed on the gate of the first transistor in a plan view and a second channel region that is not superimposed on the gate of the first transistor in a plan view.

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