Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a substrate including a display area and a non-display area surrounding the display area, the display area including a light emitting area and a non-light emitting area; a light emitting element on the light emitting region; a side passivation layer on the light emitting element in a direction toward the non-light emitting region; a side reflective metal on the side passivation layer in a direction toward the non-emission region; a pixel defining layer on the non-emission area and defining an opening; a microlens on the light emitting element; and a support metal on the non-display area and surrounding the display area, in which the support metal overlaps the side passivation layer and the side reflective metal in a direction parallel to the substrate, and the pixel defining layer is in contact with and covers the side passivation layer, the side reflective metal, and the support metal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0144535, filed on October 22, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of embodiments of this disclosure relate to a display device and an electronic device including the display device. Background Technology

[0003] With the development of the information society, consumer demand for display devices for displaying images is increasing in various forms. For example, display devices can be used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, or organic light-emitting diode (OLED) displays. In flat panel displays, the light-emitting display element can include a light-emitting element in which each pixel of the display panel can emit light by itself, thereby displaying images without a backlight unit that provides light to the display panel.

[0004] For example, display devices can be applied to eyeglasses to provide virtual reality and augmented reality. To apply a display device to eyeglasses, it can be implemented in a very small size, typically two inches or less, but can also have a high pixel density for high resolution. For example, the display device can have a high pixel density of 1000 pixels per inch (PPI) or greater.

[0005] As mentioned above, when a display device is implemented in a very small size but has a high pixel integration, the area of ​​the light-emitting region where the light-emitting element is located is relatively reduced, making it difficult to use a mask process to implement light-emitting elements that are separate for each light-emitting region.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section need not constitute prior art. Summary of the Invention

[0007] Some aspects of the embodiments disclosed herein can relatively improve the optical efficiency and reliability of display devices applied to ultra-high resolution products.

[0008] However, the aspects of the embodiments of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description of embodiments according to the disclosure.

[0009] Details of other embodiments are included in the detailed description and accompanying drawings.

[0010] According to some embodiments of this disclosure, a display device includes: a substrate including a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; a light-emitting element located on the light-emitting area of ​​the substrate; a side passivation layer located on the light-emitting element in a direction toward the non-light-emitting area; a side reflective metal located on the side passivation layer in a direction toward the non-light-emitting area; a pixel defining layer located on the non-light-emitting area of ​​the substrate and defining an opening; a microlens located on the light-emitting element; and a support metal located on the non-display area of ​​the substrate and positioned to surround the display area, wherein the support metal is positioned to overlap the side passivation layer and the side reflective metal in a direction parallel to the substrate, and the pixel defining layer contacts and covers the side passivation layer, the side reflective metal, and the support metal.

[0011] According to some embodiments, the side passivation layer and the side reflective metal can be stacked with the light-emitting region, but may not be stacked with the opening.

[0012] According to some embodiments, the support metal may not be stacked with the display area, and the support metal is positioned to be stacked with the light-emitting element in a direction parallel to the substrate.

[0013] According to some embodiments, the supporting metal may include: a first layer facing the display area; a second layer located on the first layer in a direction toward the outermost portion of the substrate and comprising a material different from that of the first layer; and a third layer located on the second layer in a direction toward the outermost portion of the substrate and comprising the same material as the first layer.

[0014] According to some embodiments, the side passivation layer may include: a first layer in contact with the light-emitting element; a second layer located on the first layer and comprising a material different from that of the first layer; and a third layer located on the second layer and in contact with the side-reflective metal.

[0015] According to some embodiments, the light-emitting element includes an anode electrode, a light-emitting layer, and a cathode electrode, and the first layer contacts and covers the non-light-emitting side surface of the anode electrode and the non-light-emitting side surface of the light-emitting layer.

[0016] According to some embodiments, the first layer does not contact the upper surface of the light-emitting layer facing the cathode electrode.

[0017] According to some embodiments, the light-emitting element further includes a connecting electrode positioned toward the substrate and a reflective electrode located between the connecting electrode and the anode electrode, and the first layer contacts and covers the non-light-emitting side surface of the connecting electrode and the non-light-emitting side surface of the reflective electrode.

[0018] According to some embodiments, the side passivation layer and the side reflective metal are spaced apart from the cathode electrode in a direction perpendicular to the substrate, and the pixel defining layer is disposed between the side passivation layer and the side reflective metal and the cathode electrode.

[0019] According to some embodiments, in a plan view, the side passivation layer completely surrounds the light-emitting layer, and in a plan view, the side reflective metal completely surrounds the side passivation layer.

[0020] According to some embodiments, the display device may further include a passivation layer located on a pixel defining layer in a portion overlapping with the light-emitting and non-light-emitting regions; and a lens passivation layer located on a microlens.

[0021] According to some embodiments, the passivation layer may include: a first layer in contact with the light-emitting element; a second layer located on the first layer and comprising a material different from that of the first layer; and a third layer located on the second layer in contact with the microlens and comprising the same material as the first layer.

[0022] According to some embodiments, the first, second, and third layers of the passivation layer may be stacked with the side passivation layer and the side reflective metal in a direction perpendicular to the substrate.

[0023] According to some embodiments of this disclosure, an electronic device includes at least one display device, the display device comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; a light-emitting element located on the light-emitting area of ​​the substrate; a side passivation layer located on the light-emitting element in a direction toward the non-light-emitting area; a side reflective metal located on the side passivation layer in a direction toward the non-light-emitting area; a pixel defining layer located on the non-light-emitting area of ​​the substrate and defining an opening; a microlens located on the light-emitting element; and a support metal located on the non-display area of ​​the substrate and positioned to surround the display area, wherein the support metal is positioned to overlap the side passivation layer and the side reflective metal in a direction parallel to the substrate, and the pixel defining layer contacts and covers the side passivation layer, the side reflective metal, and the support metal.

[0024] According to some embodiments, the display device can prevent or reduce the penetration of contaminants such as oxygen or moisture by including a protective layer covering the side and top surfaces of the light-emitting elements and the top surface of the microlens, thereby relatively improving the reliability of the display device.

[0025] Furthermore, according to some embodiments, the display device can relatively improve light efficiency by including a side-reflective metal covering the side surface of the light-emitting element, thereby relatively improving the reliability of the display device.

[0026] Furthermore, according to some embodiments, the display device can protect pixels from physical impacts caused during the manufacturing process by including a supporting metal surrounding the display area, thereby relatively improving the reliability of the display device.

[0027] However, the features of the embodiments according to this disclosure are not limited to those specifically set forth herein. Some of the above and other features of the embodiments will become more apparent to those skilled in the art to which the disclosed embodiments pertain by referring to the claims and their equivalents. Attached Figure Description

[0028] The above and other aspects and features of embodiments of the present disclosure will become more apparent from the accompanying drawings, which describe aspects of some embodiments of the present disclosure in more detail, in which: Figure 1 This is a perspective view showing a head-mounted electronic device according to some embodiments; Figure 2 It is shown Figure 1 Exploded perspective view of a head-mounted electronic device; Figure 3 This is a perspective view showing a head-mounted electronic device according to some embodiments; Figure 4 This is an exploded perspective view showing a display device according to some embodiments; Figure 5 yes Figure 4 A floor plan of the display panel; Figure 6 It is shown Figure 5 A plan view showing the arrangement of the light-emitting areas in the display area; Figure 7 It is along Figure 6 A schematic cross-sectional view of the display panel taken by line D-D' in the figure; Figure 8 It is positioned as... Figure 7 An enlarged cross-sectional view of the light-emitting element layer and optical layer stacked in the first light-emitting region; Figure 9 yes Figure 8 An enlarged sectional view of region A; Figure 10 It is shown Figure 9 A plan view showing the arrangement of the first light-emitting layer, the side passivation layer, and the side reflective metal in the image. Figure 11 It is according to some embodiments along Figure 6 A schematic cross-sectional view of the display panel taken by line D-D' in the figure; Figure 12 It is a comparison Figure 7 The display panel and Figure 11 A graph showing the reflectivity of the display panel; Figure 13 It is along Figure 5 A schematic cross-sectional view of the display panel taken by line N-N' in the diagram; Figure 14 This is a block diagram of an electronic device according to an embodiment of the present disclosure; and Figure 15 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0029] The invention will now be described more fully herein with reference to the accompanying drawings, in which some embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0030] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or one or more intervening layers may be present. Throughout the specification, the same reference numerals refer to the same components.

[0031] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and not in an idealized or overly formalized sense, unless expressly defined herein.

[0033] In the following, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0034] Figure 1 This is a perspective view showing a head-mounted electronic device 1 according to some embodiments. Figure 2 It is shown Figure 1Exploded perspective view of the head-mounted electronic device 1.

[0035] Reference Figure 1 and Figure 2 According to some embodiments, the head-mounted electronic device 1 may include a display device 10, a display device housing portion 110, a housing portion cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, a middle frame 160, a first optical component 151, a second optical component 152, and a control circuit board 170.

[0036] Display device 10 may include a first display device 10_1 and a second display device 10_2. The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. (See below for further details.) Figure 4 and Figure 5 A more detailed description of the display device 10 follows.

[0037] The first optical component 151 may be located between the first display device 10_1 and the first eyepiece 131, and the second optical component 152 may be located between the second display device 10_2 and the second eyepiece 132. Each of the first optical component 151 and the second optical component 152 may include at least one convex lens.

[0038] The intermediate frame 160 can be positioned between the first display device 10_1 and the control circuit board 170, and can also be located between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0039] The control circuit board 170 can be located between the intermediate frame 160 and the display device housing portion 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 170 can convert externally input image sources into digital video data, and can transmit the digital video data to the first display device 10_1 and the second display device 10_2 via connectors.

[0040] The control circuit board 170 can transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Optionally, the control circuit board 170 can transmit the same digital video data to both the first display device 10_1 and the second display device 10_2.

[0041] The display device receiving portion 110 is used to receive the display device 10, the intermediate frame 160, the first optical component 151, the second optical component 152, and the control circuit board 170. The receiving portion cover 120 is arranged to cover an open surface of the display device receiving portion 110. The receiving portion cover 120 may include a first eyepiece 131 positioned for the user's left eye and a second eyepiece 132 positioned for the user's right eye. Figure 1 and Figure 2 The first eyepiece 131 and the second eyepiece 132 are shown to be arranged separately, but the embodiments of this disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 can be integrated into one.

[0042] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical component 152. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 151 through the first eyepiece 131, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 152 through the second eyepiece 132.

[0043] A headband 140 is used to secure the display device housing 110 to a user's head, such that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are positioned over the user's left and right eyes, respectively. When the display device housing 110 is implemented in a lightweight and small size, the head-mounted electronic device 1 may include, for example... Figure 3 The eyeglasses frame shown is used in place of the headband 140.

[0044] Additionally, the head-mounted electronic device 1 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0045] Figure 3 This is a perspective view showing a head-mounted electronic device 1_1 according to some embodiments.

[0046] Reference Figure 3According to some embodiments, the head-mounted electronic device 1_1 may be an eyeglass-type electronic device in which the display device housing portion 120_1 is implemented in a lightweight and small size. According to some embodiments, the head-mounted electronic device 1_1 may include a display device 10, a left eye lens 311, a right eye lens 312, a support frame 350, eyeglass frame temples 341 and 342, an optical component 320, an optical path conversion component 330, and the display device housing portion 120_1.

[0047] Figure 3 The display device 10 shown may include a third display device 10_3. The third display device 10_3 may be connected with... Figure 2 The first display device 10_1 and the second display device 10_2 shown are the same (or substantially the same). See below for further details. Figure 4 and Figure 5 Description of display device 10.

[0048] The display device housing portion 120_1 can accommodate the display device 10, the optical component 320, and the light path conversion component 330. When the image displayed on the display device 10 is magnified by the optical component 320 and its light path is converted by the light path conversion component 330, the image can be provided to the user's right eye through the right eye lens 312. Therefore, the user can view an augmented reality image, which is a combination of the virtual image displayed on the display device 10 and the real image viewed through the right eye lens 312, through their right eye.

[0049] exist Figure 3 The illustration shows the display device receiving portion 120_1 positioned at the right end of the support frame 350, but the embodiments of this disclosure are not limited thereto. For example, the display device receiving portion 120_1 may be located at the left end of the support frame 350, and in this case, the image of the display device 10 can be provided to the user's left eye. Alternatively, the display device receiving portion 120_1 may be located at both the left and right ends of the support frame 350. In this case, the user can view the image displayed on the display device 10 through both the user's left and right eyes.

[0050] Figure 4 This is an exploded perspective view of a display device 10 according to some embodiments.

[0051] Reference Figure 4According to some embodiments, the display device 10 is a device for displaying moving or still images. The display device 10 according to some embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 can be applied to smartwatches, watch phones, and head-mounted displays (HMDs) for implementing virtual reality and augmented reality.

[0052] The display device 10 according to some embodiments includes a display panel 410, a heat dissipation layer 420, a circuit board 430, a driving circuit 440, and a power supply circuit 450.

[0053] The display panel 410 can be formed in a planar shape similar to a quadrilateral. For example, the display panel 410 can have a planar shape similar to a quadrilateral having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). In the display panel 410, the corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect each other can be formed at right angles, or can be formed in a rounded (or circular) shape to have curvature (e.g., a set or predetermined curvature). The planar shape of the display panel 410 is not limited to a quadrilateral, and can be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device 10 can follow the planar shape of the display panel 410, but the embodiments of this disclosure are not limited thereto.

[0054] The heat dissipation layer 420 may be stacked on the display panel 410 in a third direction (Z-axis direction) that is the thickness direction of the display panel 410. The heat dissipation layer 420 may be located on one surface of the display panel 410 (e.g., the rear surface of the display panel 410). The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include graphite or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al) with high thermal conductivity.

[0055] Circuit board 430 can be positioned on the non-display area NDA of display panel 410 using a conductive adhesive material such as anisotropic conductive film (see Figure 5 On. Circuit board 430 can be a flexible printed circuit board or flexible film made of flexible material. Figure 4The circuit board 430 is shown unfolded, but it can be bent. In this case, one end of the circuit board 430 can be located on the rear surface of the display panel 410. This one end of the circuit board 430 can be the opposite end of one of the other ends of a plurality of pads of the circuit board 430 that are connected to the pad (or "solder pad") area of ​​the display panel 410 by means of conductive adhesive members.

[0056] The driving circuit 440 can receive digital video data and timing signals from the outside. The driving circuit 440 can generate scanning timing control signals, transmission timing control signals and data timing control signals for controlling the display panel 410 according to the timing signals.

[0057] The power supply circuit 450 can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, the power supply circuit 450 can generate a first driving voltage (e.g., VSS), a second driving voltage (e.g., VDD), and a third driving voltage (e.g., VINT), and supply the generated driving voltages to the display panel 410.

[0058] The drive circuit 440 and the power supply circuit 450 can each be formed as an integrated circuit (IC) and attached to a surface of the circuit board 430.

[0059] Figure 5 yes Figure 4 A plan view of the display panel 410, and Figure 6 It is shown Figure 5 A plan view showing the arrangement of the light-emitting areas EA in the display area DA.

[0060] Reference Figure 5 and Figure 6 According to some embodiments, the display panel 410 may include a display area DA, a non-display area NDA, and a pad area PDA.

[0061] The display area DA can be located at the center of the display panel 410 and can occupy most of the area of ​​the display panel 410. The display area DA can include a light-emitting area EA and a non-light-emitting area NLA. The light-emitting area EA can be the part that emits light, and the non-light-emitting area NLA can be the part that helps to prevent or reduce the mixing of light emitted from each light-emitting area EA.

[0062] The display area DA can include multiple pixel groups (PXGs). Each pixel group (PXG) can be separate from each other. A pixel group (PXG) can be the smallest unit that emits white light.

[0063] A pixel group PXG may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, each containing a different light-emitting region EA. For example, the first sub-pixel SP1 may include a first light-emitting region EA1, the second sub-pixel SP2 may include a second light-emitting region EA2, and the third sub-pixel SP3 may include a third light-emitting region EA3. The accompanying drawings illustrate a pixel group PXG including a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3; however, embodiments of this disclosure are not limited thereto. According to some embodiments, the pixel group PXG may also include four different sub-pixels.

[0064] The first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 can emit light of different colors. As an example, the first emitting region EA1 emits light of a first color, the second emitting region EA2 emits light of a second color, and the third emitting region EA3 emits light of a third color. Here, the first color of light can be light in the red band, the second color of light can be light in the green band, and the third color of light can be light in the blue band.

[0065] The first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent to each other in the first direction (X-axis direction), and the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent to each other in the first direction (X-axis direction). In addition, the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent to each other in the second direction (Y-axis direction), but the embodiments of this disclosure are not limited thereto.

[0066] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a quadrilateral planar shape formed by four straight lines, but the embodiments of this disclosure are not limited to this. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a planar shape other than a quadrilateral, such as a polygon, a circle, an ellipse, or an irregular shape. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different.

[0067] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a ninth via VA9. This will be described in detail later.

[0068] The pad area PDA can be positioned below one side of the display area DA in the second direction (Y-axis direction). Multiple pad PDs arranged in the first direction (X-axis direction) can be positioned within the pad area PDA. Figure 4 The circuit board described in the document ( Figure 4 The 430 pad can be attached to multiple pad PDs. Multiple pad PDs can be electrically connected to the 430 board.

[0069] The non-display area NDA can be positioned around the display area DA and the pad area PDA. The non-display area NDA can refer to the edge area of ​​the display panel 410. Multiple lines electrically connecting the pad PD and the pixel PX, and the supporting metal SM can be located in the portion superimposed on the non-display area NDA.

[0070] According to some embodiments, the support metal SM can be positioned around the outer side of the display area DA. In other words, the support metal SM can be positioned around the edge of the display panel 410.

[0071] During the manufacturing process, a display device 10, according to some embodiments, can be formed on a silicon wafer. The display device 10 can be formed as multiple pieces on the silicon wafer and then separated into the shapes shown by a dicing process, which is the process of separating the individual display devices 10. The dicing process can be performed by applying physical force along the unit dicing line CCL, which is the outermost part of the display panel 410.

[0072] During the cutting process, the support metal SM can relatively reduce the impact applied to the multiple pixels PX located in the display area DA. Additionally, the support metal SM can protect the multiple pixels PX located in the display area DA from moisture and oxygen that infiltrate from the outside. The detailed structure of the support metal SM will be described later.

[0073] Figure 7 It is along Figure 6 A schematic cross-sectional view of the display panel 410 taken by line D-D'.

[0074] Reference Figure 7 The display panel 410 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, an optical layer OPL, a cover layer CVL, and an optical film POL.

[0075] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs).

[0076] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Optionally, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0077] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be located on either the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0078] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DRA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DRA.

[0079] Each of the source region SA and drain region DRA can be a region doped with a first type of impurity. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA in the third direction (Z-axis direction). The channel region CH can be stacked with the gate electrode GE in the third direction (Z-axis direction). The source region SA can be located on one side of the gate electrode GE, and the drain region DRA can be located on the other side of the gate electrode GE. Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DRA. The lower insulating film BINS can be disposed between the gate electrode GE and the well region WA. The side insulating film SINS can be disposed on the side surface of the gate electrode GE.

[0080] The first semiconductor insulating film SINS1 can be located on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed as an inorganic film of the silicon carbide or silicon oxide series, but the embodiments disclosed herein are not limited thereto.

[0081] The second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed as an inorganic film of the silicon oxide series, but the embodiments of this disclosure are not limited thereto.

[0082] Multiple contact terminals (CTEs) may be located on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to at least one of the gate electrode (GE), source region (SA), and drain region (DRA) of each of the multiple pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0083] The third semiconductor insulating film SINS3 may be located on the side surface of each of the plurality of contact terminals CTEs. The upper surface of each of the plurality of contact terminals CTEs may be exposed and not covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed as an inorganic film of the silicon oxide series, but the embodiments of this disclosure are not limited thereto.

[0084] The backplane EBP for the light-emitting element includes a first metal layer ML1 to an eighth metal layer ML8 and a plurality of vias VA1 to VA9. Additionally, the backplane EBP also includes a plurality of second interlayer insulating films INS2 to INS8 positioned between the first metal layer ML1 to the eighth metal layer ML8, a first interlayer insulating film INS1 positioned below the second interlayer insulating film INS2, and a ninth interlayer insulating film INS9 positioned on the eighth interlayer insulating film INS8.

[0085] The first metal layers ML1 to the eighth metal layers ML8 are used to implement the circuitry for sub-pixels SP1, SP2 and SP3 by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP.

[0086] The first interlayer insulating film INS1 may be located on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating film INS1 and connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be positioned on the first interlayer insulating film INS1 and may connect to the first via VA1.

[0087] The second interlayer insulating film INS2 can be located on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 can be connected to the exposed first metal layer ML1 by penetrating the second interlayer insulating film INS2. Each of the second metal layers ML2 can be positioned on the second interlayer insulating film INS2 and can be connected to the second via VA2.

[0088] The third interlayer insulating film INS3 can be located on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 can be connected to the exposed second metal layer ML2 by penetrating the third interlayer insulating film INS3. Each of the third metal layers ML3 can be positioned on the third interlayer insulating film INS3 and can be connected to the third via VA3.

[0089] The fourth interlayer insulating film INS4 can be located on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 can be connected to the exposed third metal layer ML3 by penetrating the fourth interlayer insulating film INS4. Each of the fourth metal layers ML4 can be positioned on the fourth interlayer insulating film INS4 and can be connected to the fourth via VA4.

[0090] The fifth interlayer insulating film INS5 can be located on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 can be connected to the exposed fourth metal layer ML4 by penetrating the fifth interlayer insulating film INS5. Each of the fifth metal layers ML5 can be positioned on the fifth interlayer insulating film INS5 and can be connected to the fifth via VA5.

[0091] The sixth interlayer insulating film INS6 can be located on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 can be connected to the exposed fifth metal layer ML5 by penetrating the sixth interlayer insulating film INS6. Each of the sixth metal layers ML6 can be positioned on the sixth interlayer insulating film INS6 and can be connected to the sixth via VA6.

[0092] The seventh interlayer insulating film INS7 can be located on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can be connected to the exposed sixth metal layer ML6 by penetrating the seventh interlayer insulating film INS7. Each of the seventh metal layers ML7 can be positioned on the seventh interlayer insulating film INS7 and can be connected to the seventh via VA7.

[0093] The eighth interlayer insulating film INS8 can be located on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 can be connected to the exposed seventh metal layer ML7 by penetrating the eighth interlayer insulating film INS8. Each of the eighth metal layers ML8 can be positioned on the eighth interlayer insulating film INS8 and can be connected to the eighth via VA8.

[0094] The first metal layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of the same (or substantially the same) material. The first metal layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. The first vias VA1 to VA8 can be formed of the same (or substantially the same) material. The first interlayer insulating films INS1 to INS8 can be formed as inorganic films of the silicon oxide series, but the embodiments of this disclosure are not limited thereto.

[0095] The thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can each be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. Each of the following thicknesses can be greater than the thickness of the first metal layer ML1: ML2, ML3, ML4, ML5, and ML6: ML2, ML3, ML4, ML5, and ML6. The thicknesses of the second metal layer ML2, ML3, ML4, ML5, and ML6 can be the same (or substantially the same).

[0096] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can each be greater than the thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can each be greater than the thickness of the seventh via VA7 and the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 can each be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can be the same (or substantially the same).

[0097] The ninth interlayer insulating film INS9 can be located on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 can be formed as an inorganic film of the silicon oxide series, but the embodiments of this disclosure are not limited thereto.

[0098] Each of the ninth vias VA9 can be connected to the exposed eighth metal layer ML8 by penetrating the ninth interlayer insulating film INS9. The ninth via VA9 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0099] The light-emitting element layer (EML) can be located on the light-emitting element backplane (EBP). The EML may include the light-emitting element (ED), the side passivation layer (SPL), the side reflective metal (SRM), and the passivation layer (PVL).

[0100] According to some embodiments, the light-emitting element ED can be located on the ninth interlayer insulating film INS9 in the portion superimposed with the light-emitting region EA. The light-emitting element ED may include a first light-emitting element ED1 located in the first light-emitting region EA1, a second light-emitting element ED2 located in the second light-emitting region EA2, and a third light-emitting element ED3 located in the third light-emitting region EA3. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be spaced apart from each other.

[0101] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit light of different colors. For example, the first light-emitting element ED1 can emit red light, the second light-emitting element ED2 can emit green light, and the third light-emitting element ED3 can emit blue light.

[0102] A light-emitting element (ED) may include a connecting electrode (ANC), a reflecting electrode (RL), an anode electrode (AND), a light-emitting layer (EL), and a cathode electrode (CE). Each of the first light-emitting element (ED1), the second light-emitting element (ED2), and the third light-emitting element (ED3) can be distinguished by including a first light-emitting layer (EL1), a second light-emitting layer (EL2), and a third light-emitting layer (EL3) that emits light of different colors. As an example, the first light-emitting element (ED1) may include a connecting electrode (ANC), a reflecting electrode (RL), an anode electrode (AND), a first light-emitting layer (EL1), and a cathode electrode (CE); the second light-emitting element (ED2) may include a connecting electrode (ANC), a reflecting electrode (RL), an anode electrode (AND), a second light-emitting layer (EL2), and a cathode electrode (CE); and the third light-emitting element (ED3) may include a connecting electrode (ANC), a reflecting electrode (RL), an anode electrode (AND), a third light-emitting layer (EL3), and a cathode electrode (CE).

[0103] According to some embodiments, the connection electrode ANC can be located on the ninth interlayer insulating film INS9. The connection electrode ANC can electrically connect the anode electrode AND and the eighth metal layer ML8. The connection electrodes ANC located in each of the overlapping portions of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other, and the pixel defining layer PDL is placed therebetween.

[0104] The connecting electrode ANC can be formed from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy or compound thereof, or a transparent conductive oxide. For example, the connecting electrode ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments disclosed herein are not limited thereto.

[0105] According to some embodiments, the reflective electrode RL can be located on the connecting electrode ANC. The reflective electrode RL can reflect light emitted from the light-emitting layer EL or light incident from the outside. The reflective electrodes RL located in the portions overlapping each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other, and the pixel defining layer PDL is placed therebetween.

[0106] The reflective electrode RL can be formed from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them. For example, each of the reflective electrodes RL may include aluminum (Al) which has high reflectivity.

[0107] According to some embodiments, the anode electrode AND can be located on the reflective electrode RL. The anode electrode AND can be connected to the drain region DRA or source region SA of the pixel transistor PTR via the reflective electrode RL, the connecting electrode ANC, the first via VA1 to the ninth via VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The anode electrodes AND located in the portions overlapping with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other, with the pixel defining layer PDL disposed therebetween.

[0108] The anode electrode AND can be formed from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy or compound thereof, or a transparent conductive oxide. For example, the anode electrode AND may include titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments disclosed herein are not limited thereto.

[0109] According to some embodiments, the light-emitting layer EL can be located on the anode electrode AND. The light-emitting layer EL can be an organic light-emitting layer made of organic material. The light-emitting layer EL can be in contact with the anode electrode AND at the portion overlapping with the opening OP.

[0110] The light-emitting layer EL may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3. The first light-emitting layer EL1 may be located in the portion superimposed with the first light-emitting region EA1, the second light-emitting layer EL2 may be located in the portion superimposed with the second light-emitting region EA2, and the third light-emitting layer EL3 may be located in the portion superimposed with the third light-emitting region EA3.

[0111] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can emit light of different colors. As an example, the first light-emitting layer EL1 can emit red light, the second light-emitting layer EL2 can emit green light, and the third light-emitting layer EL3 can emit blue light, but this disclosure is not limited thereto.

[0112] According to some embodiments, the side passivation layer SPL can be located on the ninth interlayer insulating film INS9 in the portion superimposed with the light-emitting region EA. The side passivation layer SPL can be located on the light-emitting element ED in a direction toward the non-light-emitting region NLA. The side passivation layer SPL can expose the opening OP and surround the light-emitting element ED. The side passivation layers SPL located in the portions superimposed with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other, and the pixel defining layer PDL is placed therebetween.

[0113] The side passivation layer SPL can cover the connecting electrode ANC, the reflective electrode RL, the anode electrode AND, and the light-emitting layer EL included in the light-emitting element ED in the direction toward the non-light-emitting region NLA. Additionally, the side passivation layer SPL can be in contact with the connecting electrode ANC, the reflective electrode RL, the anode electrode AND, and the light-emitting layer EL.

[0114] The side passivation layer (SPL) protects the light-emitting element (ED) from moisture penetration from the outside. Therefore, the display panel 410 according to some embodiments can provide a display device with relatively improved moisture penetration reliability. The detailed structure of the side passivation layer (SPL) will be described later.

[0115] According to some embodiments, the side-reflective metal SRM can be located on the ninth interlayer insulating film INS9 in the portion superimposed with the light-emitting region EA. The side-reflective metal SRM can be located on the side passivation layer SPL in the direction toward the non-light-emitting region NLA. In addition, the side-reflective metal SRM can expose the opening OP and surround the light-emitting element ED. The side-reflective metal SRMs located in the portions superimposed with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other, and the pixel defining layer PDL is placed therebetween.

[0116] The side-reflective metal SRM can cover the connecting electrode ANC, the reflective electrode RL, the anode electrode AND, and the light-emitting layer EL, which are included in the light-emitting element ED, in the direction toward the non-light-emitting area NLA.

[0117] The side-reflective metal SRM can reflect light emitted from the light-emitting element ED, so that no light is lost. Therefore, the display panel 410 according to some embodiments can provide a display device with relatively improved light efficiency. The detailed structure of the side-reflective metal SRM will be described later.

[0118] According to some embodiments, the pixel defining layer PDL can be located on the ninth interlayer insulating film INS9 in the portion superimposed with the non-emitting region NLA. The pixel defining layer PDL can separate the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3. The pixel defining layer PDL can define the opening OP and be positioned around the opening OP. The pixel defining layer PDL can expose the emitting layer EL in the portion superimposed with the opening OP.

[0119] The pixel-defining layer (PDL) can completely cover the side passivation layer (SPL) and the side reflective metal (SRM) in the portion not superimposed with the opening (OP). Therefore, the side reflective metals (SRMs) located in the portions superimposed with each of the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) can be insulated from each other. Furthermore, the side reflective metals (SRMs) and the cathode electrode (CE) located in the portions superimposed with each of the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) can be insulated from each other.

[0120] The pixel defining layer (PDL) may include an inorganic insulating material. As an example, the pixel defining layer (PDL) may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The pixel defining layer (PDL) may be formed as a single layer or as multiple layers.

[0121] According to some embodiments, the cathode electrode CE can be located on the light-emitting layer EL. The cathode electrode CE can be a common electrode. Therefore, the cathode electrode CE can completely cover each of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. In other words, the cathode electrode CE can completely cover the light-emitting layer EL and the pixel defining layer PDL in the portion superimposed with the light-emitting region EA and the non-light-emitting region NLA.

[0122] The cathode electrode CE can receive either a common voltage or a low potential voltage. For example, when the anode electrode AND receives a voltage corresponding to the data voltage and the cathode electrode CE receives a low potential voltage, the light-emitting layer EL can emit light because a potential difference is formed between the anode electrode AND and the cathode electrode CE.

[0123] The cathode electrode CE may include a transparent conductive material. As an example, the cathode electrode CE may include a layer of material with a low work function, such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, their compounds or mixtures (e.g., mixtures of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. The cathode electrode CE may also include a transparent metal oxide layer positioned on the material layer with the low work function.

[0124] According to some embodiments, a passivation layer PVL may be located on the cathode electrode CE. The passivation layer PVL may completely cover the cathode electrode CE in the portion overlapping with the light-emitting region EA and the non-light-emitting region NLA. The passivation layer PVL may include at least one inorganic insulating material to protect the light-emitting element ED from moisture and oxygen entering from the outside. A detailed structure of the passivation layer PVL will be described later.

[0125] According to some embodiments, the optical layer OPL may be located on the light-emitting element layer EML. The optical layer OPL may include a plurality of microlenses LNS and a lens passivation layer LPL covering each microlens LNS.

[0126] According to some embodiments, microlenses LNS can be located on the passivation layer PVL in the portion superimposed with the light-emitting region EA. The individual microlenses LNS located in the portions superimposed with the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be spaced apart from each other. The microlenses LNS located in the portions superimposed with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be aligned and positioned with each of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.

[0127] According to some embodiments, the lens passivation layer LPL can be located on the microlens LNS and can completely cover the microlens LNS. The lens passivation layer LPL may include at least one inorganic insulating material to protect the light-emitting element layer EML from moisture and oxygen entering from the outside. The detailed structure of the lens passivation layer LPL will be described later.

[0128] According to some embodiments, a filler layer (FIL) may be located on the optical layer (OPL). The filler layer (FIL) can flatten the steps between the multiple microlenses (LNS) and the passivation layer (PVL). The filler layer (FIL) may have a refractive index (e.g., a set or predetermined refractive index) to minimize or reduce light loss.

[0129] The filler layer (FIL) may include organic materials. As examples, the filler layer (FIL) may include acrylic resin, epoxy resin, phenolic resin, and polyamide resin.

[0130] According to some embodiments, the cover layer CVL may be located on the filler layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate, and when it is a polymer resin, an adhesive layer may be added between the cover layer CVL and the filler layer FIL. According to some embodiments, the cover layer CVL may be omitted.

[0131] According to some embodiments, the optical film POL can be located on the CVL cover layer. The optical film POL can be a structure used to prevent or reduce visibility degradation due to reflection of external light. The optical film POL can include a linear polarizer and a phase retardation film. As an example, the phase retardation film can be a λ / 4 (quarter-wave) plate, but the embodiments of this disclosure are not limited thereto.

[0132] Figure 8 It is positioned as... Figure 7 An enlarged cross-sectional view of the light-emitting element layer EML and optical layer OPL stacked in the first light-emitting region EA1. Figure 9 yes Figure 8 An enlarged sectional view of region A.

[0133] Reference Figure 8 and Figure 9 In the portion superimposed with the first light-emitting region EA1, the light-emitting element layer EML may include the first light-emitting element ED1, the side passivation layer SPL, the side reflective metal SRM, and the passivation layer PVL, and the optical layer OPL may include the microlens LNS and the lens passivation layer LPL.

[0134] In the portion superimposed with the first light-emitting region EA1, the first light-emitting element ED1 may include a connecting electrode ANC, a reflecting electrode RL, an anode electrode AND, a first light-emitting layer EL1, and a cathode electrode CE. The connecting electrode ANC, the reflecting electrode RL, the anode electrode AND, the first light-emitting layer EL1, and the cathode electrode CE may be sequentially stacked in the portion superimposed with the opening OP.

[0135] According to some embodiments, the side passivation layer SPL can be located on the side surface of the first light-emitting element ED1. For example, the side passivation layer SPL can contact and cover the side surface c1 of the connecting electrode ANC, the side surface r1 of the reflecting electrode RL, the side surface d1 of the anode electrode AND, and the side surface e1 of the first light-emitting layer EL1. The side passivation layer SPL may not contact the upper surface e3 of the first light-emitting layer EL1. In other words, the side passivation layer SPL may not be stacked with the opening OP.

[0136] The side passivation layer SPL may include multiple layers. For example, the side passivation layer SPL may include a first layer S1, a second layer S2, and a third layer S3. The first layer S1 of the side passivation layer SPL may be positioned facing the opening OP and in contact with the first light-emitting element ED1. The third layer S3 of the side passivation layer SPL may be spaced apart from the first layer S1 in a first direction (X-axis direction) and in contact with the side reflective metal SRM. The second layer S2 of the side passivation layer SPL may be located between the first layer S1 and the third layer S3 and in contact with the first layer S1 and the third layer S3.

[0137] The side passivation layer SPL may include an inorganic insulating material. However, the first layer S1 and the third layer S3 may include the same material, and the second layer S2 may include a material different from the first layer S1 and the third layer S3. As an example, the first layer S1 and the third layer S3 of the side passivation layer SPL may include silicon oxide, and the second layer S2 of the side passivation layer SPL may include aluminum oxide.

[0138] The first layer S1, the second layer S2, and the third layer S3 of the side passivation layer SPL can be formed continuously in the same process during manufacturing. As an example, the first layer S1, the second layer S2, and the third layer S3 can be formed using an atomic layer deposition (ALD) apparatus. Therefore, while the first layer S1, the second layer S2, and the third layer S3 are shown as separate layers in the figures, they can also be chemically bonded layers. That is, the side passivation layer SPL can have a multilayer structure in which silicon oxide-alumina oxide-silicon oxide are chemically bonded.

[0139] According to some embodiments, the side-reflecting metal SRM can be located on the side-passivation layer SPL. The side-reflecting metal SRM can be positioned to be in complete contact with the third layer S3 of the side-passivation layer SPL. The side-reflecting metal SRM can be spaced apart from and cover the side surface c1 of the connecting electrode ANC, the side surface r1 of the reflecting electrode RL, the side surface d1 of the anode electrode AND, and the side surface e1 of the first light-emitting layer EL1.

[0140] Side-reflective metal SRMs can include metals with reflective properties and good adhesion to inorganic insulating materials. As examples, side-reflective metal SRMs can include titanium, platinum, chromium, aluminum, silver, gold, and copper.

[0141] The side-reflective metal SRM can relatively reduce the loss of light emitted from the first light-emitting element ED1 by reflecting light incident on the pixel-defining layer PDL from the light emitted from the first light-emitting element ED1. Therefore, the side-reflective metal SRM can increase the light efficiency of the display panel 410.

[0142] According to some embodiments, the pixel defining layer (PDL) can completely cover the side passivation layer (SPL) and the side reflective metal (SRM) in the portion not overlapping with the opening (OP). Therefore, the pixel defining layer (PDL) can insulate the side passivation layer (SPL) and the side reflective metal (SRM) from the cathode electrode (CE). In other words, according to some embodiments, the cathode electrode (CE) can be spaced apart from the side passivation layer (SPL) and the side reflective metal (SRM) in a third direction (Z-axis direction), with a space (SPA) placed therebetween. The space (SPA) formed between the side passivation layer (SPL) and the side reflective metal (SRM) and the cathode electrode (CE) can be filled by the pixel defining layer (PDL).

[0143] According to some embodiments, the passivation layer PVL can contact and cover the cathode electrode CE. The passivation layer PVL may include a first layer P1, a second layer P2, and a third layer P3 stacked sequentially. The first layer P1 of the passivation layer PVL can contact the cathode electrode CE, the third layer P3 of the passivation layer PVL can be spaced apart from the first layer P1 in the third direction (Z-axis direction) and contact the microlens LNS, and the second layer P2 of the passivation layer PVL can be located between the first layer P1 and the third layer P3 and contact the first layer P1 and the third layer P3.

[0144] The passivation layer PVL may include the same material composition as the side passivation layer SPL. That is, the passivation layer PVL may include an inorganic insulating material. However, the first layer P1 and the third layer P3 may include the same material, while the second layer P2 may include a material different from the first layer P1 and the third layer P3. As an example, the first layer P1 and the third layer P3 of the passivation layer PVL may include silicon oxide, and the second layer P2 of the passivation layer PVL may include aluminum oxide.

[0145] The first layer P1, the second layer P2, and the third layer P3 of the passivation layer PVL can be formed continuously in the same process during manufacturing. As an example, the first layer P1, the second layer P2, and the third layer P3 can be formed using an ALD deposition apparatus. Therefore, the first layer P1, the second layer P2, and the third layer P3 are shown as separate layers in the figures; however, the first layer P1, the second layer P2, and the third layer P3 can be chemically bonded layers. That is, the passivation layer PVL can have a multilayer structure in which silicon oxide-alumina oxide-silicon oxide are chemically bonded.

[0146] According to some embodiments, the microlens LNS can be positioned in contact with the third layer P3 of the passivation layer PVL. The microlens LNS can have a profile shape that convexes in the upward direction, but is not limited thereto.

[0147] The microlens LNS can be a structure that relatively improves the efficiency of light emitted from the first light-emitting element ED1. In other words, the microlens LNS can be a structure used to increase the proportion of light guided towards the front of the display panel 410.

[0148] According to some embodiments, the lens passivation layer LPL can contact and cover the microlens LNS. In portions not overlapping with the microlens LNS, the lens passivation layer LPL can contact the passivation layer PVL.

[0149] The lens passivation layer LPL may include a first layer L1, a second layer L2, and a third layer L3 stacked sequentially. The first layer L1 of the lens passivation layer LPL may contact the microlens LNS, the third layer L3 of the lens passivation layer LPL may be spaced apart from the first layer L1 in the third direction (Z-axis direction), and the second layer L2 of the lens passivation layer LPL may be located between the first layer L1 and the third layer L3 and contact the first layer L1 and the third layer L3.

[0150] The lens passivation layer LPL may include the same material composition as the side passivation layer SPL and the passivation layer PVL. That is, the lens passivation layer LPL may include an inorganic insulating material. The first layer L1 and the third layer L3 may include the same material, and the second layer L2 may include a material different from the first layer L1 and the third layer L3. As an example, the first layer L1 and the third layer L3 of the lens passivation layer LPL may include silicon oxide, and the second layer L2 of the lens passivation layer LPL may include aluminum oxide.

[0151] The first layer L1, the second layer L2, and the third layer L3 of the lens passivation layer LPL can be formed continuously in the same process during manufacturing. As an example, the first layer L1, the second layer L2, and the third layer L3 can be formed using an ALD deposition apparatus. Therefore, while the first layer L1, the second layer L2, and the third layer L3 are shown as separate layers in the figures, they can also be chemically bonded layers. That is, the lens passivation layer LPL can have a multilayer structure in which silicon oxide-alumina oxide-silicon oxide are chemically bonded.

[0152] Since the display panel 410 according to some embodiments includes a side passivation layer SPL, a passivation layer PVL, and a lens passivation layer LPL protecting the first light-emitting element ED1, the first light-emitting element ED1 can be protected from the effects of moisture and oxygen entering from the outside. Therefore, the display panel 410 according to some embodiments can relatively improve reliability.

[0153] In addition, since the display panel 410 according to some embodiments includes a microlens LNS and a side-reflecting metal SRM that reflects light emitted from the first light-emitting element ED1, the light efficiency of the display panel 410 can be improved relatively.

[0154] For ease of explanation, a light-emitting element layer EML and an optical layer OPL superimposed on the first light-emitting region EA1 are shown and then described. However, a light-emitting element layer and an optical layer positioned superimposed on the second light-emitting region EA2 and the third light-emitting region EA3 may also have the same structure and characteristics as the structure superimposed on the first light-emitting region EA1.

[0155] Figure 10 It is shown Figure 9 A plan view showing the arrangement of the first light-emitting layer EL1, the side passivation layer SPL, and the side reflective metal SRM.

[0156] Reference Figure 10 The side passivation layer SPL can be positioned around the opening OP in a planar view. In the planar view, the side passivation layer SPL can expose the first light-emitting layer EL1 in the portion overlapping with the opening OP, and can be positioned around the edge of the first light-emitting layer EL1. In other words, in the planar view, the first light-emitting layer EL1 can be completely surrounded by the side passivation layer SPL.

[0157] In a planar view, the side-reflecting metal SRM can completely surround the side-passivation layer SPL. In other words, in a planar view, the side-reflecting metal SRM can expose the side-passivation layer SPL and the first light-emitting layer EL1, and can be positioned around the edge of the side-passivation layer SPL.

[0158] Figure 11 It is according to some embodiments along Figure 6 A schematic cross-sectional view of the display panel 410s taken by line D-D'. Figure 12 It is a comparison Figure 7 Display panel 410 and Figure 11 A graph showing the reflectivity of the 410s display panel.

[0159] Reference Figure 11 and Figure 12 The difference between display panel 410s and display panel 410 is that display panel 410s does not include the side-reflective metal SRM included in display panel 410. Other structures included in display panel 410s may be the same as other structures in display panel 410. Redundant descriptions will be omitted.

[0160] Figure 12 The graph shown can represent the difference between the reflectivity of display panel 410s and display panel 410. The reflectivity of display panel 410s and display panel 410 shown in the graph can be presented as data that only includes the differences depending on the presence or absence of the side reflective metal SRM.

[0161] The X-axis of the graph represents the wavelength in the visible light range, and the Y-axis represents the relative reflectivity when total internal reflection is defined as 1.

[0162] The display panel 410s, represented by the dashed line, has an average reflectance of 8% (or approximately 8%) in the visible light range, while the display panel 410, represented by the solid line, has an average reflectance of 88% (or approximately 88%) in the visible light range. In other words, the reflectance of display panel 410 can be 80% (or approximately 80%) higher than that of display panel 410s.

[0163] In other words, since the display panel 410 includes a cover for the light-emitting element ( Figure 7 Side reflective metal on the side surface of the ED (in the middle) Figure 7 The light efficiency of the display panel 410 is increased by reflecting light emitted from the light-emitting element ED (SRM) in the light source (ED). Redundant descriptions will be omitted.

[0164] Figure 13 It is along Figure 5 A schematic cross-sectional view of the display panel 410 taken by line N-N'.

[0165] Reference Figure 13 According to some embodiments, the support metal SM may be located in the portion superimposed with the non-display area NDA. The structure of the semiconductor backplane SBP and the light-emitting element backplane EBP superimposed with the non-display area NDA is merely an example and is not limited to the form shown.

[0166] The support metal SM can be located on the ninth interlayer insulating film INS9 in the portion superimposed with the non-display area NDA. The support metal SM can be aligned with the light-emitting element ED in the first direction (X-axis direction). In other words, the support metal SM can be aligned with the side passivation layer SPL and the side reflective metal SRM in the first direction (X-axis direction), and can be spaced apart from the side passivation layer SPL and the side reflective metal SRM in the first direction (X-axis direction). Being aligned with the same line can mean being on the same layer or being positioned to be superimposed in the first direction (X-axis direction).

[0167] The supporting metal SM can be completely covered by the pixel-defining layer PDL in the portion overlapping with the non-display area NDA. In other words, the supporting metal SM can be completely surrounded by the pixel-defining layer PDL and the ninth interlayer insulating film INS9. Therefore, the supporting metal SM can be insulated from the cathode electrode CE.

[0168] The supporting metal SM may include multiple layers. For example, the supporting metal SM may include a first layer M1, a second layer M2, and a third layer M3. The first layer M1 of the supporting metal SM may be a portion positioned toward the display area DA and facing the side passivation layer SPL and the side reflective metal SRM. The third layer M3 of the supporting metal SM may be a portion positioned toward the cell cut line CCL and spaced apart from the first layer M1 in a first direction (X-axis direction). The second layer M2 of the supporting metal SM may be a portion located between the first layer M1 and the third layer M3 and in contact with the first layer M1 and the third layer M3.

[0169] The first layer M1 and the third layer M3 supporting the metal SM may include materials different from the second layer M2.

[0170] The first layer M1 and the third layer M3 supporting the metal SM can be metals or compounds thereof with barrier properties. As an example, the first layer M1 and the third layer M3 can include either titanium nitride or tungsten nitride.

[0171] In addition, the second layer M2 supporting the metal SM can be a metal pillar and can include either titanium or tungsten.

[0172] As described above, when a cutting process is performed during manufacturing, the support metal SM can relatively reduce the impact applied to the structure superimposed on the display area DA. Additionally, the support metal SM can protect the multiple light-emitting elements ED located in the display area DA from moisture and oxygen that infiltrates from the outside. Therefore, the display panel 410 according to some embodiments can provide a display device with relatively improved mechanical reliability and relatively improved moisture penetration reliability. Redundant descriptions of other structures superimposed on the display area DA are omitted.

[0173] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. The electronic device according to one embodiment of the present disclosure includes the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device.

[0174] Figure 14 This is a block diagram of an electronic device 1 according to an embodiment of the present disclosure.

[0175] Reference Figure 14 An electronic device 1 according to an embodiment of the present disclosure may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0176] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0177] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, which can process the received signals and output image information through the display screen.

[0178] The power module 14 may include a power module (such as a power adapter or battery) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1.

[0179] At least one of the components of an electronic device 1 according to an embodiment of the present disclosure may be included in a display device 10 according to an embodiment of the present disclosure. Additionally, some modules functionally included in the electronic device 1 may be included in the display device 10, and other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 11, and a processor 12, a memory 13, and a power module 14 may be disposed within the electronic device 1 as other devices besides the display device 10.

[0180] Figure 15 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0181] Reference Figure 15 Various electronic devices employing the display device 10 according to embodiments of the present disclosure may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices 10_3a (such as CIDs (central information displays) and interior mirror displays arranged on the central dashboard and instrument panel of a car) that include display modules.

[0182] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the disclosure may be embodied in other specific forms without departing from the spirit and essential characteristics of the technology. Therefore, the above embodiments are to be considered illustrative and non-limiting in all respects.

[0183] The embodiments of this disclosure have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that various modifications and changes can be made without departing from the technical spirit or essential features of this disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

[0184] The features of the various disclosed embodiments can be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically feasible. Furthermore, the various embodiments can be practiced individually or in combination.

[0185] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the described embodiments without departing from the spirit and scope of the embodiments according to this disclosure. Therefore, the disclosed embodiments of the invention are intended for a general and descriptive sense, and not for limiting purposes.

Claims

1. A display device, the display device comprising: A substrate includes a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; A light-emitting element, located on the light-emitting region of the substrate; A side passivation layer is provided on the light-emitting element in a direction toward the non-light-emitting region; Side-reflective metal, on the side passivation layer in the direction toward the non-light-emitting region; A pixel defining layer is provided on the non-light-emitting area of ​​the substrate and defines an opening. Microlenses are located on the light-emitting element; as well as A supporting metal is placed on and around the non-display area of ​​the substrate. The supporting metal is stacked with the side passivation layer and the side reflective metal in a direction parallel to the substrate, and The pixel defining layer contacts and covers the side passivation layer, the side reflective metal, and the support metal.

2. The display device according to claim 1, wherein, The side passivation layer and the side reflective metal are stacked with the light-emitting area, but not with the opening, and Wherein, the supporting metal does not overlap with the display area, and The supporting metal is stacked with the light-emitting element in a direction parallel to the substrate.

3. The display device according to claim 2, wherein, The supporting metal includes: The first layer faces the display area; The second layer, situated on the first layer in the direction toward the outermost portion of the substrate, and comprising a material different from that of the first layer; and The third layer is on top of the second layer in the direction toward the outermost portion of the substrate and comprises the same material as the first layer.

4. The display device according to claim 1, wherein, The side passivation layer includes: The first layer is in contact with the light-emitting element; The second layer, on top of the first layer and comprising a material different from that of the first layer; and The third layer is on top of the second layer and is in contact with the side-reflective metal.

5. The display device according to claim 4, wherein, The light-emitting element includes an anode electrode, a light-emitting layer, and a cathode electrode, and The first layer contacts and covers the side surface of the anode electrode facing the non-light-emitting region and the side surface of the light-emitting layer facing the non-light-emitting region, and The first layer does not contact the upper surface of the light-emitting layer facing the cathode electrode.

6. The display device according to claim 5, wherein, The light-emitting element further includes a connecting electrode positioned toward the substrate and a reflective electrode located between the connecting electrode and the anode electrode, and The first layer contacts and covers the side surface of the connecting electrode facing the non-light-emitting area and the side surface of the reflecting electrode facing the non-light-emitting area.

7. The display device according to claim 5, wherein, The side passivation layer and the side reflective metal are spaced apart from the cathode electrode in a direction perpendicular to the substrate, and the pixel defining layer is disposed between the side passivation layer and the side reflective metal and the cathode electrode.

8. The display device according to claim 5, wherein, In the plan view, the side passivation layer completely surrounds the light-emitting layer, and In the plan view, the side-reflective metal completely surrounds the side passivation layer.

9. The display device according to claim 1, further comprising: A passivation layer is provided on the pixel defining layer in the portion of the region overlapping the light-emitting region and the non-light-emitting region. as well as Lens passivation layer, on the microlens, The passivation layer comprises: a first layer contacting the light-emitting element; a second layer on the first layer comprising a material different from that of the first layer; and a third layer on the second layer contacting the microlens and comprising the same material as the first layer. The first, second, and third layers of the passivation layer are stacked with the side passivation layer and the side reflective metal in a direction perpendicular to the substrate.

10. An electronic device comprising at least one display device, the display device comprising: A substrate includes a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; A light-emitting element, located on the light-emitting region of the substrate; A side passivation layer is provided on the light-emitting element in a direction toward the non-light-emitting region; Side-reflective metal, on the side passivation layer in the direction toward the non-light-emitting region; A pixel defining layer is provided on the non-light-emitting area of ​​the substrate and defines an opening. Microlenses are located on the light-emitting element; as well as A supporting metal is placed on the non-display area of ​​the substrate and positioned to surround the display area. The supporting metal is stacked with the side passivation layer and the side reflective metal in a direction parallel to the substrate, and The pixel defining layer contacts and covers the side passivation layer, the side reflective metal, and the support metal.

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