Display panel, preparation method thereof and display device
By combining the partition structure with the first electrode layer, the etching CD loss problem in the etching process of high PPI display panels is solved, achieving high PPI and low cost display effects, simplifying the manufacturing process, and improving the stability and display effect of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KUNSHAN GO VISIONOX OPTO ELECTRONICS CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-24
AI Technical Summary
Existing high PPI display panels suffer from problems in etching processes, such as large etching CD loss, which affects the size between pixels, and the need to change materials in dry etching processes, which leads to a decrease in reflectivity.
The design combines a partition structure with the first electrode layer. Multiple spaced first electrodes are formed through the partition structure. Combined with the blocking part and the pixel limiting layer, the disconnection and continuity of the electrode layer are controlled, avoiding etching limitations and achieving high PPI.
It achieves high PPI display effect, simplifies the manufacturing process, reduces the manufacturing cycle, lowers the cost, and improves the structural stability and display effect of the display panel.
Smart Images
Figure CN121924980A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology
[0002] Organic light-emitting diode (OLED) display technology is considered one of the most promising next-generation display technologies. Compared to liquid crystal displays, OLED displays offer advantages such as lower energy consumption, lower cost, self-emissiveness, wide viewing angles, and faster response times.
[0003] However, high PPI display panels still have some problems that need to be solved. Summary of the Invention
[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a display panel, which includes: a substrate, a partition structure located on one side of the substrate, a first electrode layer and a pixel defining layer.
[0005] The partition structure defines multiple partition openings. The first electrode layer includes multiple spaced-apart first electrodes, which are correspondingly disposed within the multiple partition openings. The pixel defining layer is located on the side of the partition structure away from the substrate, and defines multiple pixel openings, which are correspondingly disposed and connected to the partition openings, and expose at least a portion of the first electrodes.
[0006] In some embodiments of this application, the first electrode layer further includes a blocking portion located on the side of the partition structure away from the substrate, the blocking portion being located between the partition structure and the pixel defining layer.
[0007] In some embodiments of this application, the distance between the surface of the partition structure away from the substrate and the substrate is greater than the distance between the surface of the first electrode away from the substrate and the substrate, and the distance between the surface of the blocking portion away from the substrate and the substrate is greater than the distance between the surface of the partition structure away from the substrate and the substrate.
[0008] In some embodiments of this application, the orthographic projection of the blocking portion on the substrate completely overlaps with the orthographic projection of the partition structure on the substrate.
[0009] In some embodiments of this application, the orthogonal projection of the blocking portion on the substrate covers at least part of the edge of the orthogonal projection of the partition structure on the substrate.
[0010] In some embodiments of this application, the side surface of the pixel defining layer away from the substrate has a protrusion, and the orthogonal projection of the protrusion on the substrate covers the orthogonal projection of the blocking portion on the substrate.
[0011] In some embodiments of this application, the orthographic projection of the partition structure on the substrate is located within the orthographic projection of the pixel limiting layer on the substrate.
[0012] In some embodiments of this application, the pixel defining layer covers a portion of the first electrode, and the orthographic projection of the pixel defining layer on the substrate overlaps with the periphery of the orthographic projection of the first electrode on the substrate.
[0013] In some embodiments of this application, the display panel further includes a light-emitting device, at least a portion of which is located within a pixel opening. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked along a direction away from the substrate. At least a portion of the light-emitting layer is located within the pixel opening, and the second electrode is located on the side of the light-emitting layer and the pixel defining layer away from the substrate.
[0014] In some embodiments of this application, the orthographic projection of the light-emitting layer on the substrate and the orthographic projection of the pixel-defining layer on the substrate partially overlap, and both the orthographic projection of the light-emitting layer on the substrate and the orthographic projection of the pixel-defining layer on the substrate are located within the orthographic projection of the second electrode on the substrate.
[0015] In some embodiments of this application, the ratio of the size of the partition structure to the size of the first electrode along the thickness direction of the substrate is not less than 1.5.
[0016] In some embodiments of this application, the ratio of the size of the partition structure to the size of the first electrode along the thickness direction of the substrate is 1.5-2.
[0017] In some embodiments of this application, the size of the partition structure between two adjacent first electrodes is 1-2 μm along a direction parallel to the substrate.
[0018] In some embodiments of this application, the angle between the sidewall of the partition structure and the surface of the substrate is greater than 60 degrees.
[0019] In some embodiments of this application, the angle between the sidewall of the partition structure and the surface of the substrate is less than or equal to 90 degrees.
[0020] This application also provides a method for manufacturing a display panel, comprising:
[0021] A partition structure is fabricated on a substrate, the partition structure defining multiple partition openings.
[0022] A first electrode layer is prepared on the side of the partition structure away from the substrate, with at least a portion of the first electrode layer located within the partition opening, forming a plurality of spaced-apart first electrodes.
[0023] A pixel defining layer is prepared on the side of the first electrode layer away from the substrate. The pixel defining layer defines a plurality of pixel openings, and the pixel openings expose at least a portion of the first electrode.
[0024] In some embodiments of this application, after the first electrode layer is formed on the side of the partition structure away from the substrate and before the pixel defining layer is formed on the side of the first electrode layer away from the substrate, the method further includes: removing at least a portion of the first electrode layer on the side of the partition structure away from the substrate.
[0025] In some embodiments of this application, the first electrode layer located in the middle portion of the partition structure on the side away from the substrate is removed to form a blocking portion.
[0026] In some embodiments of this application, before removing at least a portion of the first electrode layer on the side of the partition structure away from the substrate, a protective structure is provided on the side of the first electrode within the partition opening away from the substrate.
[0027] In some embodiments of this application, during the process of preparing the pixel defining layer on the side of the first electrode layer away from the substrate, the method further includes: forming a pixel defining layer on the side of the partition structure away from the substrate, wherein the orthogonal projection of the partition structure on the substrate is located within the orthogonal projection of the pixel defining layer on the substrate.
[0028] In some embodiments of this application, a blocking portion is provided on the edge of the partition structure away from the substrate. After a pixel limiting layer is formed on the side of the partition structure away from the substrate, the pixel limiting layer has a protrusion. The orthogonal projection of the protrusion on the substrate covers the orthogonal projection of the blocking portion on the substrate.
[0029] In some embodiments of this application, after the first electrode layer is formed on the side of the partition structure away from the substrate and before the pixel defining layer is formed on the side of the first electrode layer away from the substrate, the method further includes: removing the partition structure and the first electrode layer located on the side of the partition structure away from the substrate.
[0030] Compared with the prior art, this application has the following beneficial effects:
[0031] This application provides a display panel, its fabrication method, and a display device. Multiple first electrodes are formed through a partition structure. Compared to traditional etching processes for forming first electrodes, the partition method is not limited by etching, and the distance between two first electrodes formed by the partition can be smaller, achieving a high PPI and thus improving the display effect of the display panel. By limiting the height difference between the partition structure and the first electrodes and the morphology of the partition structure, it is helpful to improve the separation of the first electrode layer at the partition structure, thereby ensuring the formation of multiple individual first electrodes. The process used in this application is simple and has a shorter cycle time compared to etching processes, which helps to reduce the fabrication cycle and lower costs. Attached Figure Description
[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;
[0034] Figure 2 This is a schematic cross-sectional view of the display panel provided in an embodiment of this application;
[0035] Figure 3 This is a schematic diagram of the film layer of the array functional layer provided in the embodiments of this application;
[0036] Figure 4 An equivalent circuit diagram of the pixel driving circuit provided in the embodiments of this application;
[0037] Figure 5 This is a schematic diagram of the cross-sectional structure of the partition structure provided in the embodiments of this application;
[0038] Figure 6 A cross-sectional structural diagram of the first electrode layer and the partition structure provided in the embodiments of this application;
[0039] Figure 7 A cross-sectional structural diagram of the first electrode layer and the partition structure provided in the embodiments of this application;
[0040] Figure 8 for Figure 7 A magnified view of a portion of point R in the middle;
[0041] Figure 9 This is a cross-sectional structural diagram of the pixel limiting layer and the partition structure provided in the embodiments of this application;
[0042] Figure 10 A cross-sectional structural diagram of the first electrode layer and the partition structure provided in the embodiments of this application;
[0043] Figure 11 This is a cross-sectional structural diagram of the pixel limiting layer and the partition structure provided in the embodiments of this application;
[0044] Figure 12 This is a schematic diagram of the light-emitting structure provided in the embodiments of this application;
[0045] Figure 13 This is a schematic diagram of the packaging structure provided in the embodiments of this application;
[0046] Figure 14A schematic flowchart illustrating the method for manufacturing a display panel according to an embodiment of this application;
[0047] Figure 15 This is a schematic diagram of the cross-sectional structure of the blocking part provided in an embodiment of this application;
[0048] Figure 16 A schematic diagram of the cross-sectional structure of the protective structure provided in the embodiments of this application;
[0049] Figure 17 This is a cross-sectional structural diagram of the pixel limiting layer and the partition structure provided in the embodiments of this application;
[0050] Figure 18 A schematic cross-sectional view of the pixel limiting layer and the first electrode provided in an embodiment of this application;
[0051] Figure 19 This is a schematic diagram of a display device provided in an embodiment of this application.
[0052] Reference numerals: 10-Display panel; 11-Substrate; 12-Partition structure; 121-Partition opening; 1211-First partition opening; 1212-Second partition opening; 1213-Third partition opening; 13-Light-emitting device; 132-Light-emitting structure; 133-First light-emitting device; 134-Second light-emitting device; 135-Third light-emitting device; 14-First electrode layer; 141-First electrode; 143-Blocking portion; 145-Protective structure; 151-Second electrode; 161-First encapsulation layer; 162-Second encapsulation layer; 163-Third encapsulation layer; 17-Pixel limiting layer; 171-Pixel opening; 173-Protrusion; 19-Planarization layer; 100-Display device. Detailed Implementation
[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0054] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0055] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.
[0056] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.
[0057] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.
[0058] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.
[0059] The display panel in the related technology includes a substrate, a first electrode located on one side of the substrate, a pixel defining layer, and light-emitting units located within the pixel openings formed by the pixel defining layer. The first electrode in a conventional display panel is mainly formed by a wet etching process. Wet etching is isotropic etching, resulting in a large etching CD loss (Critical Dimension Loss), which can be understood as a significant reduction in etching area. When fabricating high-PPI display panels, the large etching CD loss severely affects the size of the pixel defining layer between pixels. However, since the first electrode is generally made of ITO / Ag / ITO, dry etching is not suitable for etching existing first electrodes. If dry etching is used to etch the first electrode, the material of the first electrode needs to be changed. Known alternative materials are TI / AL / TI / ITO, but the reflectivity of the first electrode made from this material is low, leading to a decrease in the efficiency of the OLED device.
[0060] To address the aforementioned technical problems, the following innovative technical solutions are designed. The specific implementation schemes of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below should be considered contributions made to this application during the invention process, and should not be construed as technical content known to those skilled in the art.
[0061] Figure 1 This is a schematic diagram of the structure of a display panel 10 according to one embodiment of this application. The display panel 10 may be an organic light-emitting diode (OLED) display panel or a quantum dot (QLED) display panel. The display panel 10 includes a display area AA with display function and a non-display area NA.
[0062] The display area AA of the display panel 10 can be rectangular, square, circular, oval, or other shapes.
[0063] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.
[0064] Sub-pixels (SPX) include pixel circuits and light-emitting devices (13) driven by the pixel circuits to emit light of the corresponding color. First sub-pixel SPX1 includes a first light-emitting device (133), second sub-pixel SPX2 includes a second light-emitting device (134), and third sub-pixel SPX3 includes a third light-emitting device (135). One pixel circuit drives at least one light-emitting device (13) to emit light. For example, display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel circuit drives one light-emitting device (13) to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices (13) to emit light.
[0065] In one implementation, Figure 2 It shows Figure 1 A schematic diagram of a partial cross-sectional structure of the film layer in the BB direction of a local area of the display panel 10. (Reference) Figure 2 The display panel 10 includes a substrate 11 and a plurality of light-emitting devices 13.
[0066] refer to Figure 3 The substrate 11 includes a pixel circuit layer and a planarization layer 19. The pixel circuit layer includes pixel circuits for driving the light-emitting device 13 to emit light. Figure 3 A transistor 18 in a pixel circuit is shown. A via is provided in the planarization layer 19, and a first electrode 141 is electrically connected to the transistor 18 in the pixel circuit layer through the via. Furthermore, the pixel circuit layer includes at least one insulating layer, which may include at least one of an inorganic layer and an organic layer. Additionally, the substrate 11 includes scan lines providing the scan signal Scan and data lines providing the data signal Data to the pixel circuit.
[0067] refer to Figure 4 The pixel circuit includes a driving transistor T1 and a data transistor T2. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light-emitting device 13. Figure 4 This is one implementation of a pixel circuit; the pixel circuit described in this application is not limited to... Figure 4 The 2T1C pixel circuit shown can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.
[0068] refer to Figure 5 The display panel 10 includes a partition structure 12 located on one side of the substrate 11. Specifically, the partition structure 12 is located on the side of the planarization layer 19 away from the substrate 11, and the partition structure 12 defines a plurality of partition openings 121. In some embodiments of this application, the partition structure 12 is a mesh structure. The partition structure 12 is an organic material or an inorganic material; organic materials include organic adhesives, and inorganic materials include silicides, oxysilicides, and a-Si.
[0069] refer to Figure 6 and Figure 7The display panel 10 also includes a first electrode layer 14, which includes a plurality of spaced-apart first electrodes 141. The first electrodes 141 are located within the partition openings 121. That is, in this application, a plurality of spaced-apart first electrodes 141 are formed by the partition structure 12, and the plurality of first electrodes 141 are correspondingly arranged with the plurality of partition openings 121. In some embodiments of this application, the first electrodes 141 and partition openings 121 are arranged in a one-to-one correspondence. It can be understood that the first electrode layer 14 is interrupted at the partition structure 12, and the structure located within the partition openings 121 is the first electrode 141.
[0070] To ensure that the first electrode layer 14 is disconnected at the partition structure 12, the height of the partition structure 12 must be greater than that of the first electrode 141. The distance between the surface of the partition structure 12 away from the substrate 11 and the substrate 11 is greater than the distance between the surface of the first electrode 141 away from the substrate 11 and the substrate 11. That is, taking one surface of the substrate 11 as a reference, the height of the surface of the partition structure 12 away from the substrate 11 is greater than the height of the surface of the first electrode 141 away from the substrate 11. The distance between the surface of the partition structure 12 away from the substrate 11 and the substrate 11 can be understood as the thickness of the partition structure 12, and the distance between the surface of the first electrode 141 away from the substrate 11 and the substrate 11 can be understood as the thickness of the first electrode 141.
[0071] refer to Figure 8 In some embodiments of this application, along the thickness direction of the substrate 11, the ratio of the dimension L2 (i.e., the thickness of the partition structure 12) of the partition structure 12 to the dimension L1 (i.e., the thickness of the first electrode 141) of the first electrode 141 is not less than 1.5. This structure allows the first electrode layer 14 to be disconnected at the partition structure 12. Further, along the thickness direction of the substrate 11, the ratio of the dimension of the partition structure 12 to the dimension of the first electrode 141 is 1.5-2. Optionally, the ratio of the thickness of the partition structure 12 to the thickness of the first electrode 141 is 1.2, 1.3, 1.4, 1.5, 1.6, 1.8, 2.0, 2.2, 2.3, or 2.5.
[0072] A significant height difference between the partition structure 12 and the first electrode 141 facilitates the breaking of the first electrode layer 14. Conversely, a wider partition structure 12 also contributes to the breaking of the first electrode layer 14. Along the direction parallel to the substrate 11, the size of the partition structure 12 between two adjacent first electrodes 141 is 1-2 μm. That is, the larger the size of the partition structure 12 between two adjacent first electrodes 141, the more likely the first electrode layer is to be discontinuous. Optionally, along the direction parallel to the substrate 11, the size of the partition structure 12 between two adjacent first electrodes 141 is 1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, or 2 μm.
[0073] Multiple first electrodes are formed by a partition structure. Compared with the traditional etching process for forming first electrodes, the partition method is not limited by etching. The distance between two first electrodes formed by the partition can be smaller, which can achieve a high PPI, such as PPI of 1500 or more, thereby improving the display effect of the display panel.
[0074] refer to Figure 9 The display panel 10 also includes a pixel defining layer 17 located on the side of the partition structure 12 away from the substrate 11. The pixel defining layer 17 has a pixel opening 171, which corresponds to and communicates with the partition opening 121, exposing at least a portion of the first electrode 141. The orthographic projection of the partition structure 12 onto the substrate 11 lies within the orthographic projection of the pixel defining layer 17 onto the substrate 11. That is, the pixel defining layer 17 completely covers the partition structure 12.
[0075] In some embodiments of this application, the pixel defining layer 17 is located on the side of the partition structure 12 and the first electrode 141 away from the substrate 11. (See reference...) Figure 6 The first electrode layer 14 further includes a blocking portion 143 located on the side of the partition structure 12 away from the substrate 11, and the blocking portion 143 is located between the partition structure 12 and the pixel defining layer 17. The distance between the surface of the blocking portion 143 away from the substrate 11 and the substrate 11 is greater than the distance between the surface of the partition structure 12 away from the substrate 11 and the substrate 11. That is, with one surface of the substrate 11 as a reference, the height of the surface of the blocking portion 143 away from the substrate 11 is higher than the height of the surface of the partition structure 12 away from the substrate 11, and thus higher than the height of the surface of the first electrode 141 away from the substrate 11.
[0076] In one implementation, the blocking portion 143 completely covers the side of the partition structure 12 away from the substrate 11, that is, the orthographic projection of the blocking portion 143 on the substrate 11 completely overlaps with the orthographic projection of the partition structure 12 on the substrate 11. The pixel limiting layer 17 covers the ends of the blocking portion 143 and the first electrode 141.
[0077] refer to Figure 10In some embodiments of this application, the blocking portion 143 covers a portion of the partition structure 12. As one implementation, the orthographic projection of the blocking portion 143 onto the substrate 11 covers at least a portion of the edge of the orthographic projection of the partition structure 12 onto the substrate 11; that is, the blocking portion 143 is located on the side of the partition structure 12 near the partition opening 121, and does not completely cover the partition structure 12. The pixel defining layer 17 covers the ends of the partition structure 12, the blocking portion 143, and the first electrode 141. It is understood that the blocking portion 143 can be formed during the formation of the first electrode layer 14, where the first electrode layer 14 is discontinuous on the partition structure 12; alternatively, the blocking portion 143 can be formed by removing a portion of the first electrode layer 14 through etching or other processes after the first electrode layer 14 has been formed on the partition structure 12. As another implementation, the blocking portion 143 is located in the middle of the partition structure 12. The blocking portion 143 in this application can be arranged in a matrix or other patterns, and this application does not specifically limit its arrangement.
[0078] refer to Figure 11 Since the blocking portion 143 protrudes relative to the partition structure 12, the portion of the pixel limiting layer 17 corresponding to the blocking portion 143 has a protrusion 173, and the orthogonal projection of the protrusion 173 on the substrate 11 covers the orthogonal projection of the blocking portion 143 on the substrate 11.
[0079] refer to Figure 9 In some embodiments of this application, the pixel defining layer 17 covers the ends of the partition structure 12 and the first electrode 141. The side of the partition structure 12 away from the substrate 11 is in direct contact with the pixel defining layer 17, i.e., there is no obstruction portion 143 between the partition structure 12 and the pixel defining layer 17. When the partition structure 12 and the pixel defining layer 17 are made of the same type of material (such as inorganic materials), the direct contact between the partition structure 12 and the pixel defining layer 17 helps to improve their adhesion and helps to ensure the stability of the display panel 10 structure. The periphery of the orthographic projection of the pixel defining layer 17 on the substrate 11 overlaps with the periphery of the orthographic projection of the first electrode 141 on the substrate 11.
[0080] In some embodiments of this application, the pixel defining layer 17 only covers the partition structure 12 and does not cover the first electrode 141. The orthographic projection of the pixel defining layer 17 on the substrate 11 completely overlaps with the orthographic projection of the partition structure 12 on the substrate 11. The orthographic projection of the pixel defining layer 17 on the substrate 11 does not overlap with the orthographic projection of the first electrode 141 on the substrate 11.
[0081] refer to Figure 2The display panel 10 also includes a plurality of light-emitting devices 13, at least a portion of which is located within a pixel opening 171. Each light-emitting device 13 includes a first electrode 141, a light-emitting structure 132, and a second electrode 151 sequentially stacked along a direction away from the substrate 11. The light-emitting structure 132 is located within the pixel opening 171 and contacts the first electrode 141. The light-emitting structure 132 covers the first electrode 141 within the pixel opening 171, the sidewall of the pixel opening 171, and a portion of the pixel defining layer 17 facing away from the substrate 11. The orthographic projection of the light-emitting layer onto the substrate 11 partially overlaps with the orthographic projection of the pixel defining layer 17 onto the substrate 11.
[0082] The second electrode 151 covers the corresponding light-emitting structure 132. The orthographic projection of the light-emitting layer on the substrate 11 and the orthographic projection of the pixel-defining layer 17 on the substrate 11 are both located within the orthographic projection of the second electrode 151 on the substrate 11. In this application, the second electrode 151 of the display area is a continuous film layer. When the pixel-defining layer 17 has a protrusion 173, the second electrode 151 covers the protrusion 173 and needs to be continuous. In order to prevent the second electrode 151 from being interrupted, the thickness of the pixel-defining layer 17 is increased to make the protrusion 173 of the pixel-defining layer 17 more gradual, thereby not affecting the continuity of the second electrode 151.
[0083] The first electrode 141 can be an anode, and the second electrode 151 can be a cathode. The first electrode 141 of each light-emitting device 13 can be connected to the pixel circuit through a via, so that the pixel circuit drives the light-emitting device 13 to emit light.
[0084] The first electrode 141 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 151 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).
[0085] The light-emitting device 13 in this application includes a first light-emitting device 133, a second light-emitting device 134 and a third light-emitting device 135, which emit light of different colors, such as red light, green light and blue light respectively.
[0086] Figure 12This is a schematic diagram of a light-emitting structure 132 according to one embodiment of this application. The light-emitting structure 132 of the light-emitting device 13 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the substrate 11 (i.e., the Z direction). In some embodiments of this application, at least one of the hole injection layer HIL, hole transport layer HTL, electron blocking layer EBL, light-emitting material layer EML, hole blocking layer HBL, electron transport layer ETL, and electron injection layer EIL is a monolithic structure, that is, multiple light-emitting devices 13 share the above-mentioned film layer structure. The light-emitting structure 132 may include a single light-emitting material layer EML, or it may be a stacked light-emitting structure including multiple light-emitting material layers EML. The light-emitting material layer covers the first electrode 141 within the pixel opening 171 and extends to the sidewall of the pixel defining layer 17 and a portion of the surface (edge) of the pixel defining layer 17 away from the substrate 11. The hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer in the first light-emitting device 133, the second light-emitting device 134, and the third light-emitting device 135 are integral layer structures.
[0087] When the pixel defining layer 17 includes the protrusion 173, the side of the pixel defining layer 17 away from the substrate 11 is not flat. This increases the extension path of the hole injection layer HIL and the hole transport layer HTL on the surface of the pixel defining layer 17, which helps to increase the transport path of charge carriers between adjacent pixels. It may also be disconnected or discontinuous, blocking the transport of charge carriers between adjacent pixels, thereby reducing electrical crosstalk between adjacent pixels and improving the display effect.
[0088] In order for the light-emitting structure 132 to emit light, a pixel voltage is provided to the first electrode 141 and a common voltage is provided to the second electrode 151, forming a potential difference between the first electrode 141 and the second electrode 151, so that the light-emitting structure 132 disposed between the first electrode 141 and the second electrode 151 emits light. In one embodiment, if a potential difference is formed between the first electrode 141 and the second electrode 151 of the first light-emitting device 133a, the light-emitting material layer EML of the light-emitting structure 132 emits blue light; if a potential difference is formed between the first electrode 141 and the second electrode 151 of the second light-emitting device 134b, the light-emitting material layer EML of the light-emitting structure 132 emits green light; and if a potential difference is formed between the first electrode 141 and the second electrode 151 of the third light-emitting device 135c, the light-emitting material layer EML of the light-emitting structure 132 emits red light.
[0089] In this configuration, the pixel voltage of the first electrode 141 is provided by the pixel circuit 1, and the common voltage of the second electrode 151 is provided by the isolation structure 12. Specifically, the second electrode 151 is electrically connected to the isolation structure 12, and the common voltage is supplied to the second electrode 151 by providing the isolation structure 12. That is, the isolation structure 12 has the function of supplying a common voltage to the second electrode 151.
[0090] refer to Figure 9 The partition structure 12 in this application is used to partition the first electrode layer 14, and can also partition the hole injection layer HIL and the hole transport layer HTL, but the continuity of the second electrode 151 must be ensured. Therefore, the angle α between the sidewall of the partition structure 12 and the surface of the substrate 11 is greater than 60 degrees; further, the angle between the sidewall of the partition structure 12 and the surface of the substrate 11 is less than or equal to 90 degrees. This structure, combined with the size difference between the partition structure 12 and the first electrode 141, can partition the first electrode layer 14 while ensuring the continuity of the second electrode 151. Optionally, the angle between the sidewall of the partition structure 12 and the surface of the substrate 11 is 60 degrees, 65 degrees, 68 degrees, 70 degrees, 72 degrees, 75 degrees, 77 degrees, 78 degrees, 80 degrees, 82 degrees, 83 degrees, 85 degrees, 86 degrees, 88 degrees, or 90 degrees.
[0091] refer to Figure 13 The display panel 10 further includes a first encapsulation layer 161 covering the side of the light-emitting device 13 facing away from the substrate 11. The display panel 10 also includes a second encapsulation layer 162 and a third encapsulation layer 163, with the second encapsulation layer 162 covering the first encapsulation layer 161 and the third encapsulation layer 163 covering the second encapsulation layer 162. Both the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic materials, and the materials of the first encapsulation layer 161 and the third encapsulation layer 163 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 162 is an organic insulating material, such as epoxy resin, acrylic resin, or other resin materials. The first encapsulation layer 161, the second encapsulation layer 162, and the third encapsulation layer 163 are continuously disposed at least over the entire display area AA, with a portion also disposed in the bezel area NA.
[0092] The display panel 10 may also include at least one film layer such as a touch layer, a polarizer, a color filter substrate, and a protective cover. This film layer may also be bonded to the display panel 10 via an adhesive layer such as OCA (Optical Clear Adhesive).
[0093] The preparation method of the display panel 10 according to the embodiments of this application will be described below.
[0094] refer to Figure 14 The method for manufacturing the display panel 10 includes:
[0095] Step S10: Provide a substrate 11.
[0096] In step S20, a partition structure 12 is formed on one side of the substrate 11, and the partition structure 12 defines a plurality of partition openings 121.
[0097] In step S30, a first electrode layer 14 is prepared on the side of the partition structure 12 away from the substrate 11, with at least a portion of the first electrode layer 14 located within the partition opening 121, forming a plurality of spaced first electrodes 141.
[0098] In step S40, a pixel defining layer 17 is formed on the side of the first electrode layer 14 away from the substrate 11. The pixel defining layer 17 defines a plurality of pixel openings 171, and the pixel openings 171 expose at least a portion of the first electrode 141.
[0099] In some embodiments of this application, step S10: providing substrate 11;
[0100] Step S20: A barrier material layer is formed on one side of the substrate 11 (e.g., one side of the planarization layer 19), and the barrier material layer is etched to form a plurality of barrier openings 121. The plurality of barrier openings 121 include a plurality of first barrier openings 1211, a plurality of second barrier openings 1212, and a plurality of third barrier openings 1213. The first barrier openings 121 correspond to the first light-emitting device 133, the second barrier openings 121 correspond to the second light-emitting device 134, and the third barrier openings 121 correspond to the third light-emitting device 135.
[0101] Step S30: A first electrode material layer is prepared on the side of the partition structure 12 away from the substrate 11. The first electrode material layer is not etched, thus forming the first electrode layer 14. (Reference) Figure 6 The first electrode layer 14 includes a first electrode 141 located within the partition opening 121 and a blocking portion 143 located on the side of the partition structure 12 away from the substrate 11. The blocking portion 143 substantially covers the partition structure 12; optionally, the blocking portion 143 completely covers the partition structure 12. That is, the orthographic projection of the blocking portion 143 on the substrate 11 completely coincides with the orthographic projection of the partition structure 12 on the substrate 11. Optionally, the pixel defining layer 17 covers a portion of the first electrode 141, such as covering the edge of the first electrode 141.
[0102] Step S40: A pixel defining material layer is prepared on the side of the first electrode layer 14 away from the substrate 11. The pixel defining material layer is etched to form a plurality of pixel openings 171, which expose at least a portion of the first electrode 141. (Reference) Figure 9The pixel defining layer 17 covers the blocking portion 143. Optionally, the pixel defining layer 17 covers a portion of the first electrode 141, such as covering the edge of the first electrode 141. This structure helps protect the first electrode layer 14 and other film layers beneath it. Optionally, the pixel defining layer 17 covers the blocking portion 143 but does not cover the first electrode 141.
[0103] In some embodiments of this application, step S10: providing substrate 11;
[0104] Step S20: A barrier material layer is formed on one side of the substrate 11 (e.g., one side of the planarization layer 19), and the barrier material layer is etched to form a plurality of barrier openings 121. The plurality of barrier openings 121 include a plurality of first barrier openings 1211, a plurality of second barrier openings 1212, and a plurality of third barrier openings 1213. The first barrier openings 121 correspond to the first light-emitting device 133, the second barrier openings 1212 correspond to the second light-emitting device 134, and the third barrier openings 1213 correspond to the third light-emitting device 135.
[0105] Step S30: A first electrode material layer is prepared on the side of the partition structure 12 away from the substrate 11. The first electrode material layer is etched, that is, partially etched, to form a first electrode layer 14. The first electrode layer 14 includes a first electrode 141 located within the partition opening 121 and a blocking portion 143 located on the side of the partition structure 12 away from the substrate 11. In this structure, the blocking portion 143 is provided at a partial position on the partition structure 12, making the surface of the partition structure 12 away from the substrate 11 uneven, thereby affecting the flatness of the pixel limiting layer 17 and the carrier transport of the subsequent organic functional layer.
[0106] In some embodiments of this application, the first electrode material layer located in the middle portion of the partition structure 12 on the side facing away from the substrate 11 is removed, while the first electrode material layer located at the edge of the partition structure 12 on the side facing away from the substrate 11 is retained. Then, the orthogonal projection of the blocking portion 143 on the substrate 11 side of the partition structure 12 onto the substrate 11 covers at least a portion of the edge of the orthogonal projection of the partition structure 12 onto the substrate 11.
[0107] In some embodiments of this application, the first electrode material layer located at the edge of the partition structure 12 facing away from the substrate 11 is removed, while the first electrode material layer located in the middle portion of the partition structure 12 facing away from the substrate 11 is retained. This results in the blocking portion 143 being located in the middle position of the partition structure 12.
[0108] One implementation involves removing a portion of the blocking portion 143 using wet etching or a stripping process, while retaining a portion of the blocking portion 143, the partition structure 12, and the first electrode 141. Specifically, since the first electrode layer 14 is broken at the partition structure 12 to form the first electrode 141 and the blocking portion 143, the first electrode 141 and the blocking portion 143 are made of the same material. (See reference...) Figure 16 To avoid damaging the first electrode 141 while etching the blocking portion 143, a protective structure 145 is provided on the side of the first electrode 141 away from the substrate 11 before etching the blocking portion 143. This structure protects the first electrode 141 within the partition opening 121 with PR adhesive. Then, the blocking portion 143 on the partition structure 12 is etched to avoid etching damage or over-etching. Finally, the protective structure 145 on the first electrode 141 is removed.
[0109] Step S40: A pixel defining material layer is prepared on the side of the first electrode layer 14 away from the substrate 11. The pixel defining material layer is etched to form a plurality of pixel openings 171, which expose at least a portion of the first electrode 141. The pixel defining layer 17 covers the partition structure 12, the blocking portion 143, and the end of the first electrode 141. (Reference) Figure 10 A pixel-defining layer 17 is formed by a deposition process. The pixel-defining layer 17 has a protrusion 173 corresponding to the blocking portion 143. The extension path of the common layers in the light-emitting device 13, such as the hole injection layer HIL and the hole transport layer HTL, on the surface of the pixel-defining layer 17 is increased or interrupted, which helps to reduce the transmission of charge carriers between adjacent pixels, reduce electrical crosstalk between adjacent pixels, and improve the display effect.
[0110] In some embodiments of this application, step S10: providing substrate 11;
[0111] Step S20: A barrier material layer is formed on one side of the substrate 11 (e.g., one side of the planarization layer 19), and the barrier material layer is etched to form a plurality of barrier openings 121. The plurality of barrier openings 121 include a plurality of first barrier openings 1211, a plurality of second barrier openings 1212, and a plurality of third barrier openings 1213. The first barrier openings 121 correspond to the first light-emitting device 133, the second barrier openings 121 correspond to the second light-emitting device 134, and the third barrier openings 121 correspond to the third light-emitting device 135.
[0112] Step S30: A first electrode material layer is prepared on the side of the partition structure 12 away from the substrate 11. All blocking portions 143 on the side of the partition structure 12 away from the substrate 11 are removed to form a first electrode layer 14. The first electrode layer 14 includes a first electrode 141 located within the partition opening 121. (Reference) Figure 7The partition structure 12 and the first electrode 141 are retained, meaning that the side of the partition structure 12 away from the substrate 11 has no obstruction portion 143, and the pixel defining layer 17 is in direct contact with the partition structure 12. When the partition structure 12 and the pixel defining layer 17 are made of the same type of material (such as inorganic materials), the direct contact between the partition structure 12 and the pixel defining layer 17 helps to improve their adhesion and helps to ensure the stability of the display panel 10 structure. The periphery of the orthographic projection of the pixel defining layer 17 on the substrate 11 overlaps with the periphery of the orthographic projection of the first electrode 141 on the substrate 11.
[0113] In one implementation, the blocking portion 143 is removed by wet etching or a stripping process in this application. Specifically, since the first electrode layer 14 is broken at the partition structure 12 to form the first electrode 141 and the blocking portion 143, the first electrode 141 and the blocking portion 143 are made of the same material. To avoid damaging the first electrode 141 while etching the blocking portion 143, a protective structure 145 is provided on the side of the first electrode 141 away from the substrate 11 before etching the blocking portion 143, to protect the first electrode 141 within the partition opening 121 with (PR adhesive). Then, the blocking portion 143 on the partition structure 12 is etched to avoid etching damage or over-etching. Finally, the protective structure 145 on the first electrode 141 is removed.
[0114] Step S40: A pixel defining material layer is prepared on the side of the first electrode layer 14 away from the substrate 11. The pixel defining material layer is etched to form a plurality of pixel openings 171, which expose at least a portion of the first electrode 141. (Reference) Figure 17 The pixel limiting layer 17 covers the ends of the partition structure 12 and the first electrode 141.
[0115] In other embodiments of this application, step S31 is included after step S30: removing the partition structure 12 and retaining the first electrode 141. (See reference...) Figure 18 In this structure, a plurality of first electrodes 141 are disposed on the planarization layer 19, and a pixel defining layer 17 is formed on the first electrodes 141. The pixel defining layer 17 defines pixel openings 171 and exposes a portion of the first electrodes 141. This structure does not explicitly include the partition structure 12, but the plurality of first electrodes 141 formed by the partition structure 12 are not limited by etching compared to the formation of first electrodes 141 using conventional etching processes. The distance between two first electrodes 141 formed by the partition can be smaller, achieving a high PPI, which can reach over 1500, thereby improving the display effect of the display panel 10.
[0116] In this application, after step S40, step S50 is further included: fabricating a light-emitting device 13 on the pixel limiting layer 17 and the first electrode 141. Specifically, a light-emitting structure 132 and a second electrode 151 are sequentially fabricated along a direction away from the substrate 11. The light-emitting structure 132 in this application is fabricated using a vapor deposition process. The light-emitting structure 132 includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The light-emitting material layers in the first light-emitting device 133, the second light-emitting device 134, and the third light-emitting device 135 are fabricated separately. The light-emitting material layers cover the first electrode 141 within the pixel opening 171 and extend to the sidewall of the pixel limiting layer 17 and a portion of the surface (edge) of the pixel limiting layer 17 away from the substrate 11. The hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer in the first light-emitting device 133, the second light-emitting device 134, and the third light-emitting device 135 are fabricated simultaneously using the same process. That is, the above film structure is a monolithic structure.
[0117] A second electrode 151 is fabricated on the side of the light-emitting device 13 away from the substrate 11. The second electrode 151 is a monolayer structure.
[0118] Step S60: Prepare a first encapsulation layer 161, a second encapsulation layer 162 and a third encapsulation layer 163 on the side of the second electrode 151 away from the substrate 11.
[0119] The fabrication method employed in this application uses a partition structure 12 to separate the first electrode layer 14, forming multiple spaced first electrodes 141. Compared to traditional etching processes, the partitioning method is not limited by etching, and the distance between two first electrodes 141 formed by the partition can be smaller, achieving a high PPI and thus improving the display effect of the display panel 10. This process is simple and has a shorter cycle time compared to etching processes, helping to reduce the fabrication cycle and lower costs.
[0120] In some possible implementations, refer to Figure 19 This application also provides a display device 100, which includes the display panel 10 described in this application. The display device 100 may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because this display device includes the display panel described in this application, the reliability of this electronic device is higher.
[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0122] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A display panel, characterized in that, include substrate; A partition structure is located on one side of the substrate, and the partition structure defines a plurality of partition openings; The first electrode layer includes a plurality of first electrodes spaced apart, wherein the plurality of first electrodes are disposed corresponding to the plurality of partition openings and are located within the partition openings; A pixel defining layer is located on the side of the partition structure away from the substrate. The pixel defining layer defines a plurality of pixel openings, which are correspondingly disposed and connected to the partition openings. The pixel openings expose at least a portion of the first electrode.
2. The display panel according to claim 1, characterized in that, The first electrode layer further includes a blocking portion located on the side of the partition structure away from the substrate, the blocking portion being located between the partition structure and the pixel defining layer; Preferably, the distance between the surface of the partition structure away from the substrate and the substrate is greater than the distance between the surface of the first electrode away from the substrate and the substrate, and the distance between the surface of the blocking portion away from the substrate and the substrate is greater than the distance between the surface of the partition structure away from the substrate and the substrate; Preferably, the orthographic projection of the blocking portion on the substrate completely overlaps with the orthographic projection of the partition structure on the substrate; Preferably, the orthographic projection of the blocking portion on the substrate covers at least a portion of the edge of the orthographic projection of the partition structure on the substrate; Preferably, the pixel defining layer has a protrusion on the side away from the substrate, and the orthographic projection of the protrusion on the substrate covers the orthographic projection of the blocking portion on the substrate.
3. The display panel according to claim 1, characterized in that, The orthogonal projection of the partition structure on the substrate is located within the orthogonal projection of the pixel defining layer on the substrate; Preferably, the pixel defining layer covers a portion of the first electrode, and the orthographic projection of the pixel defining layer on the substrate overlaps with the periphery of the orthographic projection of the first electrode on the substrate; Preferably, the display panel further includes a light-emitting device, at least a portion of which is located within the pixel opening. The light-emitting device includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked along a direction away from the substrate. At least a portion of the light-emitting layer is located within the pixel opening, and the second electrode is located on the side of the light-emitting layer and the pixel defining layer away from the substrate. Preferably, the orthographic projection of the light-emitting layer on the substrate partially overlaps with the orthographic projection of the pixel-defining layer on the substrate, and both the orthographic projection of the light-emitting layer on the substrate and the orthographic projection of the pixel-defining layer on the substrate are located within the orthographic projection of the second electrode on the substrate.
4. The display panel according to claim 1, characterized in that, Along the thickness direction of the substrate, the ratio of the size of the partition structure to the size of the first electrode is not less than 1.5; Preferably, along the thickness direction of the substrate, the ratio of the size of the partition structure to the size of the first electrode is 1.5-2; Preferably, the size of the partition structure between two adjacent first electrodes is 1-2 μm along a direction parallel to the substrate.
5. The display panel according to claim 1 or 4, characterized in that, The angle between the sidewall of the partition structure and the surface of the substrate is greater than 60 degrees; Preferably, the angle between the sidewall of the partition structure and the surface of the substrate is less than or equal to 90 degrees.
6. A method for manufacturing a display panel, characterized in that, include A partition structure is fabricated on a substrate, the partition structure defining a plurality of partition openings; A first electrode layer is prepared on the side of the partition structure away from the substrate, and at least a portion of the first electrode layer is located within the partition opening, forming a plurality of spaced first electrodes; A pixel defining layer is formed on the side of the first electrode layer away from the substrate, the pixel defining layer defining a plurality of pixel openings, the pixel openings exposing at least a portion of the first electrode.
7. The method for manufacturing a display panel according to claim 6, characterized in that, After the first electrode layer is formed on the side of the partition structure away from the substrate, and before the pixel defining layer is formed on the side of the first electrode layer away from the substrate, the method further includes: removing at least a portion of the first electrode layer on the side of the partition structure away from the substrate. Preferably, the first electrode layer located in the middle portion of the side of the partition structure away from the substrate is removed to form a blocking portion; Preferably, before removing at least a portion of the first electrode layer on the side of the partition structure away from the substrate, the method further includes: providing a protective structure on the side of the first electrode within the partition opening away from the substrate.
8. The method for manufacturing a display panel according to claim 7, characterized in that, During the process of preparing the pixel defining layer on the side of the first electrode layer away from the substrate, the method further includes: forming the pixel defining layer on the side of the partition structure away from the substrate, wherein the orthographic projection of the partition structure on the substrate is located within the orthographic projection of the pixel defining layer on the substrate; Preferably, the blocking portion is provided on the edge of the partition structure away from the substrate. After the pixel defining layer is formed on the side of the partition structure away from the substrate, the pixel defining layer has a protrusion, and the orthogonal projection of the protrusion on the substrate covers the orthogonal projection of the blocking portion on the substrate.
9. The method for manufacturing a display panel according to claim 6, characterized in that, After the first electrode layer is formed on the side of the partition structure away from the substrate, and before the pixel defining layer is formed on the side of the first electrode layer away from the substrate, the method further includes: removing the partition structure and the first electrode layer located on the side of the partition structure away from the substrate.
10. A display device, characterized in that, It includes the display panel according to any one of claims 1-5, or the display panel prepared by the method of preparing the display panel according to claims 6-9.