Chip packaging structure, manufacturing method of chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging structure, a manufacturing method of the chip packaging structure and electronic equipment, the chip packaging structure comprises at least one sub-packaging structure, and the sub-packaging structure comprises at least one chip, a first interconnection layer, a first filling layer and a packaging layer; the packaging layer is provided with at least one groove, and each groove is used for accommodating at least one chip; the back surface of the chip is attached to the packaging layer through an adhesive layer; the side face of the chip is attached to the first surface of the first filling layer, the second surface of the first filling layer is attached to the packaging layer, and the first surface of the first filling layer is opposite to the second surface of the first filling layer; the front face of the chip is connected with the first interconnection layer and the first filling layer, and the front face of the chip is opposite to the back face of the chip. According to the invention, the problem that the chip is easy to warp or shift in the process of forming the packaging layer by plastic packaging can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, integrated circuit packaging has become particularly important for chips that are highly sensitive to reliability. The packaging layer in the packaging structure provides physical protection for the chip, preventing damage, contamination, or improper use; furthermore, it can resist environmental hazards such as chemicals, moisture, and gases, avoiding impact on chip performance. However, in current manufacturing processes, the packaging layer is generally formed only after the chip is connected to the interconnect layer. During the molding process to form the packaging layer, the chip is prone to warping or misalignment, affecting the chip's internal stress and even causing microcracks, thus impacting product quality. Summary of the Invention

[0003] In view of this, this application provides a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device to solve the problem that chips are prone to warping or shifting during the process of forming the packaging layer by plastic encapsulation in traditional solutions.

[0004] This application provides a chip packaging structure, comprising: at least one sub-package structure, the sub-package structure comprising: at least one chip, a first interconnect layer, a first fill layer, and a packaging layer; the packaging layer has at least one recess, each recess for accommodating at least one chip; the back side of the chip is bonded to the packaging layer by an adhesive layer; the side surface of the chip is bonded to a first surface of the first fill layer, the second surface of the first fill layer is bonded to the packaging layer, and the first surface of the first fill layer is opposite to the second surface of the first fill layer; the front side of the chip is connected to the first interconnect layer and the first fill layer, and the front side of the chip is opposite to the back side of the chip.

[0005] Optionally, the first interconnect layer includes: a first rewiring layer and a second fill layer, the first rewiring layer being electrically connected to the chip, the first rewiring layer being divided into a plurality of mutually insulated first rewiring sub-layers by the second fill layer, the first rewiring layer extending out of the second fill layer in a direction away from the chip and being connected to a first solder ball.

[0006] Optionally, the sub-package structure further includes: a second interconnect layer and conductive pillars, the conductive pillars being located within the package layer; the second interconnect layer including: a second rewiring layer, a third fill layer, and a fourth fill layer; the second rewiring layer being electrically connected to the first rewiring layer via the conductive pillars; the third fill layer being bonded to the upper surface of the package layer; the second rewiring layer being divided into multiple mutually insulated second rewiring sub-layers by the fourth fill layer; the second rewiring layer extending out of the third fill layer in a direction away from the chip and connecting to a second solder ball.

[0007] Optionally, the sub-package structure includes multiple chips, wherein adjacent chips are separated by the first filling layer.

[0008] Optionally, the first filler layer on the adjacent side of the chip is bonded to the encapsulation layer.

[0009] A second aspect of this application provides a method for manufacturing a chip package structure, comprising: forming a groove on the bottom surface of a package layer for accommodating a chip, each groove accommodating one chip; placing the chip in the groove and bonding the back side of the chip to the package layer with an adhesive layer; filling the gap between the chip and the groove with a first filler layer, and disposing the first filler layer on the front side of the chip, excluding the wiring area, with the front side of the chip facing the back side of the chip; and disposing an interconnect layer on the surface of the first filler layer away from the chip, and electrically connecting the interconnect layer to the chip.

[0010] Optionally, the process of creating a groove on the bottom surface of the encapsulation layer to accommodate the chip may further include: pressing the encapsulation layer with a mold to create the groove on the bottom surface of the encapsulation layer.

[0011] Optionally, the process of creating a groove on the bottom surface of the encapsulation layer to accommodate the chip may further include creating the groove on the bottom surface of the encapsulation layer by means of laser etching or plasma etching.

[0012] Optionally, the process of setting an interconnect layer on the surface of the first filling layer away from the chip and electrically connecting the interconnect layer to the chip may further include: setting a first redistribution layer on the surface of the first filling layer away from the chip and electrically connecting the first redistribution layer to the chip; etching the first redistribution layer and filling it with a second filling layer, such that the first redistribution layer is divided into a plurality of mutually insulated first redistribution sublayers by the second filling layer, and causing the first redistribution layer to extend out of the second filling layer in a direction away from the chip; implanting or electroplating the first solder ball on the end face of the first redistribution layer extending out of the second filling layer.

[0013] A third aspect of this application provides an electronic device, comprising: a chip packaging structure as described in any of the first aspects above.

[0014] The chip packaging structure provided in this application fixes the chip to the packaging layer by bonding the back of the chip to the packaging layer with an adhesive layer, thus preventing the chip from warping or shifting. A first filler layer fills the gap between the chip's sides and the packaging layer, further securing the chip. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0016] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application; Figure 2 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 3 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 4 This is a schematic diagram of a chip packaging structure according to another embodiment of this application; Figure 5 This is a flowchart of the steps of a method for manufacturing a chip packaging structure according to an embodiment of this application; Figures 5a-5d This is a schematic diagram of the structure obtained in each step of the manufacturing method of a chip packaging structure according to an embodiment of this application.

[0017] List of reference numerals in the attached diagram: Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0019] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0020] It should be understood that although this application may use the terms first, second, third, etc., to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0022] Figure 1 This is a schematic diagram of a chip packaging structure according to an embodiment of this application, as shown below. Figure 1 As shown, the chip packaging structure includes at least one sub-packaging structure 1, which includes at least one chip 11, a first interconnect layer 12, a first fill layer 13, and a packaging layer 14. The packaging layer 14 has at least one recess, each recess for accommodating at least one chip 11. The back side of the chip 11 is bonded to the packaging layer 14 via an adhesive layer 20. The side surface of the chip 11 is bonded to the first surface of the first fill layer 13, and the second surface of the first fill layer 13 is bonded to the packaging layer 14, with the first surface and second surface of the first fill layer 13 facing each other. The front side of the chip 11 is connected to the first interconnect layer 12 and the first fill layer 13, with the front side of the chip 11 facing the back side of the chip 11.

[0023] In the process of manufacturing the sub-package structure 1, the chip 11 is usually fixed onto the first interconnect layer 12 first, followed by corresponding processing steps, and finally the package layer 14 is formed. However, during the molding process of forming the package layer, the chip is prone to warping or misalignment, affecting the internal stress of the chip and even causing microcracks, thus affecting product quality. Therefore, the manufacturing steps of the sub-package structure 1 can be changed. First, the package layer 14 is formed, and then at least one groove is formed on the package layer 14, each groove being used to accommodate at least one chip 11. Then, an adhesive layer 20 is applied to the bottom surface of the groove to mount the chip 11 in the groove, thereby fixing the chip 11 to the package layer 14. To facilitate installation, the area of ​​the bottom surface of the groove is larger than the area of ​​the back surface of the chip 11. Therefore, after the chip 11 is mounted in the package layer 14, there is a gap between the side of the chip and the side of the package layer 14. Then, the gap between the side of the chip 11 and the encapsulation layer 14 is filled by the first filling layer 13, so that the side of the chip 11 is in contact with the first surface of the first filling layer 13, and the second surface of the first filling layer 13 is in contact with the encapsulation layer 14, with the first surface and the second surface of the first filling layer 13 facing each other. The first filling layer 13 can prevent the chip 11 from shifting in the groove, and plays a certain role in stabilizing the chip 11.

[0024] It should be noted that, in Figure 1 Two chips 11 are disposed in the groove shown, and the opposite sides of the two chips 11 are separated by a first filling layer 13. However, in other embodiments, such as Figure 2 As shown, the two first filling layers 13 adjacent to each other on the side of the chip 11 can also be bonded to the encapsulation layer 14 respectively. That is, the first filling layers 13 on the sides of the two chips 11 that are close to each other are separated by the encapsulation layer 14. With this arrangement, since the encapsulation layer 14 has higher strength, the stability between adjacent chips can be further improved.

[0025] also, Figure 1 The chip package structure shown includes multiple sub-package structures 1, but the chip package structure may include only one sub-package structure 1. Furthermore, in Figure 1 In the sub-package structure 1 shown, chip 11 is mounted in a flip chip (FC) manner, but sub-package structure 1 can also support wire bonding (WB) chip structure.

[0026] In this embodiment, the back of the chip 11 is bonded to the encapsulation layer 14 via an adhesive layer 20, which fixes the chip 11 to the encapsulation layer 14 and prevents the chip 11 from warping or shifting. The first filler layer 13 fills the gap between the side of the chip 11 and the encapsulation layer 14, further securing the chip 11.

[0027] Figure 3 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 3 As shown, the first interconnect layer 12 includes: a first rewiring layer 121 and a second fill layer 122. The first rewiring layer 121 is electrically connected to the chip 11. The first rewiring layer 121 is divided into a plurality of mutually insulated first rewiring sub-layers by the second fill layer 122. The first rewiring layer 121 extends out of the second fill layer 122 in a direction away from the chip 11 and is connected to the first solder ball 123.

[0028] The first interconnect layer 121 in the first interconnect layer 12 is used to realize communication between the chip 11 and the printed circuit board PCB. The first interconnect layer 121 is divided into multiple mutually insulated first interconnect sub-layers by the second fill layer 122. Each first interconnect sub-layer is electrically connected to the pin of the chip 11. The first interconnect layer 121 extends out of the second fill layer 122 in a direction away from the chip 11 and is connected to the first solder ball 123. The printed circuit board realizes electrical connection with the chip 11 by connecting with the first solder ball 123, thus forming a fan-out package.

[0029] In this embodiment, the first rewiring layer 121 is divided into multiple mutually insulated first rewiring sub-layers by the second filling layer 122, which enables the first solder ball 123 connected to the first rewiring layer 121 to communicate one-to-one with the output pin of the chip 11.

[0030] Figure 4 This is a schematic diagram of a chip packaging structure according to another embodiment of this application, as shown below. Figure 4 As shown, the sub-package structure 1 further includes a second interconnect layer 15 and conductive pillars 16. The conductive pillars 16 are located within the package layer 14. The second interconnect layer 15 includes a second redistribution layer 151, a third fill layer 152, and a fourth fill layer 153. The second redistribution layer 151 is electrically connected to the first redistribution layer 121 via the conductive pillars 16. The third fill layer 152 is attached to the upper surface of the package layer 14. The second redistribution layer 151 is divided into multiple mutually insulated second redistribution sub-layers by the fourth fill layer 153. The second redistribution layer 151 extends out of the third fill layer 152 in a direction away from the chip 11 and is connected to the second solder ball 154.

[0031] The second solder ball 154 can be connected to the first redistribution layer 121 of another sub-package structure 1 to form a 3D stacked package structure. At this time, the second solder ball 154 of the sub-package structure 1 is the first solder ball 123 of the other sub-package structure 1.

[0032] In this embodiment, the second interconnect layer 15 is electrically connected to the first interconnect layer 12 through the conductive pillar 16, thereby allowing other sub-package structures 1 to be stacked on the second interconnect layer 15, integrating more chips 11 into a package, reducing the number of chips mounted on the printed circuit board, wiring complexity and connector usage, and lowering the design and manufacturing costs of the printed circuit board.

[0033] Figure 5 This is a flowchart illustrating the steps of a method for manufacturing a chip packaging structure according to an embodiment of this application, as follows: Figure 5 As shown, the manufacturing method of the chip package structure includes the following steps: Step 101: Create a recess on the bottom surface of the encapsulation layer to accommodate the chip.

[0034] To manufacture the chip package structure, firstly, recesses are formed on the bottom surface of the package layer 14 to accommodate chips 11. Each recess is used to accommodate at least one chip 11. After this step is completed, the chip package structure can be manufactured as follows: Figure 5a As shown.

[0035] Step 102: Place the chip in the groove and attach the back of the chip to the encapsulation layer with adhesive.

[0036] The adhesive layer can be either DAA (Die Attach Adhesive) or DAF (Die Attach Film). After this step is completed, the chip package structure can be as follows: Figure 5b As shown.

[0037] Step 103: Fill the gap between the chip and the groove with a first filling layer, and set the first filling layer on the front side of the chip except for the wiring area, with the front side of the chip facing the back side of the chip.

[0038] After this step is completed, the chip packaging structure can be as follows: Figure 5c As shown.

[0039] Step 104: Deposit an interconnect layer on the surface of the first filling layer away from the chip, and electrically connect the interconnect layer to the chip.

[0040] After this step is completed, the chip packaging structure can be as follows: Figure 5d As shown.

[0041] In one possible implementation, the process of creating a recess on the bottom surface of the packaging layer to accommodate the chip may also include: The encapsulation layer is press-fitted using a mold to create grooves on its bottom surface. Alternatively, grooves can be created on the bottom surface of the encapsulation layer using laser etching or plasma etching.

[0042] The encapsulation layer 14 is press-fitted onto a mold by setting bumps on the mold. Using customized upper and lower molds with raised structures, the panel / wafer-grade EMC substrate is placed in the mold. High temperature and pressure cause plastic deformation of the EMC. The raised parts of the mold compress the EMC to form a groove matching the shape of the bump. After cooling, demolding completes the groove formation. This improves mass production efficiency, facilitates cost control, and ensures structural consistency. For example, a single pressing can simultaneously form all the required grooves on an entire panel (e.g., 600×600mm) or an entire wafer, eliminating the need for groove-by-groove processing and shortening the processing cycle (only requiring mold closing, pressurization, cooling, and demolding). Laser etching or plasma etching can be used to form the groove through laser / plasma bombardment. High-energy laser beams (e.g., ultraviolet lasers) or plasma (e.g., oxygen plasma) ablate / etch the EMC, removing a portion of the EMC material along a preset path to form the groove. Laser-based grooving relies on photothermal effects to melt / vaporize EMC, while plasma-based grooving removes EMC through the chemical etching of active particles. Both methods offer high customization capabilities and can support more precise structural fabrication. No dedicated molds are required; simply adjusting the laser / plasma scanning path and energy parameters via software allows for rapid switching of grooving dimensions (depth, width), shapes (square, circular, irregular), and spacing. Furthermore, grooves of different specifications can be fabricated on the same panel / wafer.

[0043] In one possible implementation, an interconnect layer is disposed on the surface of the first filling layer away from the chip, and the interconnect layer is electrically connected to the chip, including: A first redistribution layer 121 is formed on the surface of the first filling layer 13 away from the chip 11, and the first redistribution layer 121 is electrically connected to the chip 11. The first redistribution layer 121 is etched and filled with a second filling layer 122, so that the first redistribution layer 121 is divided into multiple mutually insulated first redistribution sublayers by the second filling layer 122, and the first redistribution layer 121 extends out of the second filling layer 122 in a direction away from the chip 11. A first solder ball 123 is implanted or electroplated on the end face of the first redistribution layer 121 that extends out of the second filling layer 122.

[0044] A chip package structure in which a first redistribution layer 121 is disposed on the surface of the first filling layer 13 away from the chip 11, and the first redistribution layer 121 is electrically connected to the chip 11, can be described as follows: Figure 5cAs shown. The first interconnect layer 121 in the first interconnect layer 12 is used to realize the communication between the chip 11 and the printed circuit board PCB. The first interconnect layer 121 is divided into multiple mutually insulated first interconnect sub-layers by the second fill layer 122. Each first interconnect sub-layer is electrically connected to the pin of the chip 11. The first interconnect layer 121 extends out of the second fill layer 122 in a direction away from the chip 11 and is connected to the first solder ball 123. The printed circuit board realizes the electrical connection with the chip 11 by connecting with the first solder ball 123, thus forming a fan-out package.

[0045] In this embodiment, the first rewiring layer 121 is divided into multiple mutually insulated first rewiring sub-layers by the second filling layer 122, which enables the first solder ball 123 connected to the first rewiring layer 121 to communicate one-to-one with the output pin of the chip 11.

[0046] This application provides an electronic device, which includes a chip packaging structure as described in any of the foregoing embodiments. The electronic device may include one chip packaging structure or multiple chip packaging structures.

[0047] It should be noted that the electronic devices in this application are specific applications of the chip packaging structures in the foregoing embodiments in various electronic products (such as smartphones and tablets). For specific chip packaging structures in electronic devices, please refer to the description in the foregoing chip packaging structure embodiments, which will not be repeated here.

[0048] In this embodiment, the electronic device includes a chip packaging structure. The back of the chip is bonded to the packaging layer via an adhesive layer, which secures the chip to the packaging layer and prevents warping or misalignment of the chip. A first filling layer further secures the chip by filling the gap between the chip's sides and the packaging layer.

[0049] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0050] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0052] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0053] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0054] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0055] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: At least one sub-package structure, the sub-package structure comprising: at least one chip, a first interconnect layer, a first fill layer, and a package layer; At least one groove is formed on the packaging layer, and each groove is used to accommodate at least one chip. The back of the chip is bonded to the encapsulation layer via an adhesive layer; The side of the chip is attached to the first surface of the first filling layer, the second surface of the first filling layer is attached to the encapsulation layer, and the first surface of the first filling layer and the second surface of the first filling layer are opposite to each other. The front side of the chip is connected to the first interconnect layer and the first fill layer, and the front side of the chip is opposite to the back side of the chip.

2. The chip packaging structure according to claim 1, characterized in that, The first interconnect layer includes: a first rewiring layer and a second fill layer. The first rewiring layer is electrically connected to the chip. The first rewiring layer is divided into a plurality of mutually insulated first rewiring sub-layers by the second fill layer. The first rewiring layer extends out of the second fill layer in a direction away from the chip and is connected to a first solder ball.

3. The chip packaging structure according to claim 2, characterized in that, The sub-package structure further includes: a second interconnect layer and conductive pillars, the conductive pillars being located within the package layer, and the second interconnect layer including: a second redistribution layer, a third fill layer, and a fourth fill layer; The second wiring layer is electrically connected to the first wiring layer through the conductive pillar; The third filler layer is attached to the upper surface of the encapsulation layer. The second redistribution layer is divided into multiple mutually insulated second redistribution sublayers by the fourth filler layer. The second redistribution layer extends out of the third filler layer in a direction away from the chip and is connected to the second solder ball.

4. The chip packaging structure according to claim 1, characterized in that, The sub-package structure includes multiple chips, and adjacent chips are separated by the first filling layer.

5. The chip packaging structure according to claim 4, characterized in that, The first filler layer on the adjacent side of the chip is bonded to the encapsulation layer.

6. A method for manufacturing a chip packaging structure, characterized in that, include: A recess is formed on the bottom surface of the encapsulation layer to accommodate a chip, and each recess is used to accommodate one chip; The chip is placed in the groove, and the back of the chip is bonded to the encapsulation layer with an adhesive layer; A first filling layer is filled into the gap between the chip and the groove, and the first filling layer is disposed on the front side of the chip except for the wiring area, with the front side of the chip facing the back side of the chip; An interconnect layer is disposed on the surface of the first filling layer away from the chip, and the interconnect layer is electrically connected to the chip.

7. The method according to claim 6, characterized in that, The method of creating a recess on the bottom surface of the encapsulation layer to accommodate the chip includes: The encapsulation layer is pressed into place using a mold to create the groove on the bottom surface of the encapsulation layer.

8. The method according to claim 6, characterized in that, The method of creating a recess on the bottom surface of the encapsulation layer to accommodate the chip includes: The groove is created on the bottom surface of the encapsulation layer by laser etching or plasma etching.

9. The method according to claim 6, characterized in that, The step of forming an interconnect layer on the surface of the first filling layer away from the chip and electrically connecting the interconnect layer to the chip includes: A first redistribution layer is disposed on the surface of the first filling layer away from the chip, and the first redistribution layer is electrically connected to the chip. The first super-wiring layer is etched and filled with a second fill layer, so that the first super-wiring layer is divided into multiple mutually insulated first super-wiring sub-layers by the second fill layer, and the first super-wiring layer extends out of the second fill layer in a direction away from the chip. The first solder ball is implanted or electroplated on the end face of the first wiring layer that extends through the second filler layer.

10. An electronic device, characterized in that, Includes the chip packaging structure as described in any one of claims 1-5.

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