Fiber integrated circuit device and preparation method and application thereof

Abstract

The invention provides a fiber integrated circuit device which is provided with an elastic matrix and a functional circuit layer wrapped in the elastic matrix, the fiber integrated circuit device is formed by winding a planar preform along an axis, and a multi-layer spiral laminated fiber body is formed; the planar prefabricated body comprises an elastic substrate, a functional circuit layer arranged on the elastic substrate, and an interlayer bonding layer covering the functional circuit layer; wherein the edge of one side, perpendicular to the winding direction, of the elastic substrate is provided with a local thickening structure, and the local thickening structure is located at the axis position of the fiber integrated circuit device after being wound to form a supporting core part; the interlayer bonding layers are continuously distributed in at least part of the circumferential range in the radial direction of the fiber integrated circuit device so that bonding between the adjacent spiral layers can be achieved. The invention also provides a preparation method and application of the fiber integrated circuit device.

Description

Technical Field

[0001] This invention belongs to the field of flexible electronics and wearable devices, specifically relating to a fiber integrated circuit device, its fabrication method, and its application. Background Technology

[0002] With the development of the Internet of Things and wearable technology, electronic textiles are gradually evolving from simple conductive connections to intelligent systems with sensing, display and energy storage functions.

[0003] However, while existing fiber optic devices have achieved single functions such as sensing, light emission, or energy harvesting, they still face significant challenges in constructing intelligent fiber optic systems capable of complex signal processing. Traditional fiber optic systems typically rely on external, rigid, and bulky silicon-based chips to process information, leading to complex interconnection problems, reduced wearing comfort, and the mismatch in mechanical properties between rigid chips and flexible fibers, which can easily cause interface failure. Although attempts have been made to fabricate circuits directly on fibers, the geometric shape of fiber bending and the limited surface area make it difficult to achieve high-density device integration. Furthermore, when fibers undergo severe deformations such as repeated bending, stretching, torsion, and even washing, the integrated circuit layer is highly susceptible to breakage or delamination, leading to functional failure.

[0004] For example, the existing technology CN113687734A provides an electronic fabric that uses different cell types corresponding to different weaving methods (such as yarn type, winding, density difference) to generate differentiated voltage signals when pressed to realize the recognition of touch position or feature information. The drawback of this technology is that the analog signals generated by the difference in physical structure are easily affected by the pressure and environmental interference, resulting in poor recognition accuracy. Moreover, the frequently changing weaving process makes it difficult to achieve high-density integration and standardized mass production.

[0005] Therefore, there is an urgent need for a fiber integrated circuit device that is as elastic and woven as ordinary fibers, and has high integration density, high processing precision, and excellent mechanical stability under complex deformation. Summary of the Invention

[0006] In view of the above-mentioned technical problems existing in the prior art, the present invention provides a fiber integrated circuit device having an elastic matrix and a functional circuit layer encapsulated in the elastic matrix. The fiber integrated circuit device is formed by winding a planar preform along an axis to form a multi-layered helical laminated fiber body. The planar preform includes an elastic substrate, a functional circuit layer disposed on the elastic substrate, and an interlayer adhesive layer covering the functional circuit layer. The elastic substrate has a locally thickened structure on one edge perpendicular to the winding direction. The locally thickened structure is located at the axial center of the fiber integrated circuit device after winding, forming a supporting core. The interlayer adhesive layer is continuously distributed along the radial direction of the fiber integrated circuit device in at least a partial circumferential range to achieve bonding between adjacent helical layers.

[0007] Preferably, the interlayer adhesive layer, the locally thickened structure, and the elastic substrate are made of the same or chemically compatible elastomer material. Using homogeneous or compatible materials (such as all being PDMS systems) can eliminate interfacial stress mismatch between materials, ensure coordinated deformation of each part of the device during thermal expansion and contraction or mechanical deformation, and prevent interfacial delamination.

[0008] Preferably, the interlayer adhesive layer can cover the entire elastic substrate.

[0009] Preferably, the elastomer material is selected from at least one of polydimethylsiloxane, polymethylvinylsiloxane, hydroxyl-terminated polydimethylsiloxane, vinyl-terminated polydimethylsiloxane, polyurethane, styrene-butadiene-styrene block copolymer, hydrogenated styrene-butadiene block copolymer, styrene-isoprene-styrene block copolymer, polyether-polyester block copolymer, polyether block amide, natural rubber, nitrile rubber, styrene-butadiene rubber, fluororubber, butyl rubber, chloroprene rubber, polyacrylamide, polyvinyl alcohol, alginate hydrogel, and poly(vinylidene fluoride-hexafluoropropylene) copolymer.

[0010] Preferably, a buffer layer is further provided between the elastic substrate and the functional circuit layer. The Young's modulus of the buffer layer is greater than that of the elastic substrate and less than that of the conductor material in the functional circuit layer. For example, according to ASTM D638, the Young's modulus of the elastic substrate is 0.5-3 MPa, the Young's modulus of the buffer layer is 2-6 GPa, and the Young's modulus of the conductor material in the functional circuit layer is 70-90 GPa.

[0011] A high-modulus buffer layer with a modulus between that of a soft elastic substrate and a rigid circuit material (such as metal / semiconductor) was introduced to construct a modulus heterostructure. According to finite element simulation and experimental verification, this buffer layer can effectively disperse the local strain applied to the functional circuit layer into the surrounding elastic matrix, significantly reducing the local stress concentration of the functional circuit layer under bending, tension or torsion, thereby preventing the fracture of brittle electrodes or semiconductor layers and greatly improving the mechanical ductility and durability of the device.

[0012] Preferably, in the planar preform, the thickness of the buffer layer is 50-800 nm.

[0013] Preferably, the buffer layer has a single-layer or multi-layer structure, and the material of the buffer layer is one or more of the following: parylene, polyimide, photoresist, epoxy resin, acrylic resin, polyurethane, polyvinyl alcohol, polyethylene terephthalate, or inorganic-organic composite film.

[0014] Preferably, the buffer layer is patterned into an island structure or a continuous thin film structure, and the buffer layer at least covers the functional circuit layer. In this invention, the buffer layer preferably covers only the functional circuit layer. In this invention, the excellent tensile properties of the fiber integrated circuit device are mainly provided by the elastomeric material constituting the elastic substrate and the interlayer bonding layer. Considering the differences between the buffer layer material and the elastomeric material in terms of Young's modulus and tensile properties, if the coverage area of ​​the buffer layer is too large, it will adversely affect the overall tensile properties of the device.

[0015] Preferably, the fiber optic integrated circuit device satisfies at least one of the following:

[0016] The diameter of the fibrous tissue is 50-1000 μm;

[0017] In the helical stack of the fibrous material, the equivalent thickness of each layer is 2-40 μm;

[0018] The width of the locally thickened structure is 2-20 μm, preferably 5-15 μm, and the thickness of the locally thickened structure is 1-30 μm, preferably 5-20 μm, compared to the unthickened area.

[0019] In planar preforms, the thickness of the elastic substrate is 1-30 μm, preferably 5-20 μm;

[0020] In planar preforms, the functional circuit layer covers 20-40% of the surface of the elastic substrate;

[0021] The functional circuit layer includes an active device region and an interconnection region, wherein the active device region includes at least one of organic electrochemical transistors, organic thin-film transistors, or metal oxide transistors.

[0022] The functional circuit layer includes device units and interconnect wires. The conductor material of the interconnect wires is selected from one or more of the following: gold, silver, copper, aluminum, platinum, titanium / gold composite layer, chromium / gold composite layer, conductive carbon material, conductive polymer, or transparent conductive material.

[0023] In this invention, the fiber diameter range of 50-1000 μm covers the diameters of common textile materials, from filaments to rovings. The fiber integrated circuit devices of this invention can be directly woven using industrial-standard air-jet looms, rapier looms, or knitting machines without requiring expensive modifications to the equipment.

[0024] In this invention, the width of the locally thickened structure is 2-20 μm, preferably 5-15 μm, which is 1-30 μm thicker than the unthickened area. During the initial winding stage of the transformation from a planar preform to a three-dimensional helical structure, the substrate is highly susceptible to micro-bending or wrinkling due to uneven stress or localized stress concentration. By setting the locally thickened structure within the aforementioned specific size range, the bending stiffness at the winding start point can be locally increased, resulting in a more uniform stress distribution. The 1-30 μm thickness increase is sufficient to provide the necessary mechanical support to suppress wrinkle nucleation and propagation, without causing significant protrusions or non-roundness in the fiber cross-section after winding due to excessive thickness. This ensures tight adhesion and flatness between functional layers, avoids electrode breakage or semiconductor layer delamination caused by wrinkles, and significantly improves the yield of fiber integrated circuit devices. For ease of operation, the local thickening structure is usually set to double the thickness of the original elastic substrate. For example, if the thickness of the elastic substrate is 15μm, the local thickening also increases the thickness of the original substrate by 15μm.

[0025] In the planar preform, the thickness of the elastic substrate is 1-30 μm. In the helical stack of the fiber body, the equivalent thickness of each layer (referring to the overall stack thickness of the planar preform constituting the fiber integrated circuit device before winding and assembly) is 2-40 μm. The thinner layer thickness significantly reduces the tensile / compressive strain experienced by the device when the fiber is bent or twisted, thereby endowing the fiber integrated circuit device with excellent mechanical stability and fatigue resistance under repeated bending, torsion and stretching operations, ensuring that the electrical performance does not degrade during long-term use.

[0026] Through a multi-layered helical structure design, the radial space within the fiber is fully utilized, achieving an extremely high volumetric integration density (above 30,000 transistors / cm fiber, reaching over 100,000 transistors / cm fiber), far exceeding traditional fiber devices that only utilize the surface. Simultaneously, the micron-level layer thickness and fiber diameter ensure that the device possesses flexibility and weavability similar to textile yarn.

[0027] Preferably, the fiber optic integrated circuit device satisfies one or more of the following characteristics:

[0028] The fibrous material is subjected to bending deformation with a bending radius of 1 mm, tensile deformation of 20% in the radial direction, and torsion angle of 180°·cm. -1After at least one of the mechanical deformations in the torsional deformation, the rate of change of the transistor on / off ratio and threshold voltage of the fiber integrated circuit device is less than 5%, and the fiber body does not delaminate.

[0029] After the fiber body is subjected to at least one of the following tests: at least 100,000 surface abrasion cycles, at least 10,000 bending cycles, and at least 10,000 tensile cycles, the change rate of the electrical performance of the fiber integrated circuit device is within 10%, and the fiber body does not delaminate.

[0030] The fiber body is held at 10% tensile strain for at least 10 days, or subjected to at least 1,000 thermal cycles at 40°C, and the resistance and output current change rate of the fiber integrated circuit device are within 6%, and the fiber body does not delaminate.

[0031] After the fiber body withstood an external crushing load of up to 15.6 tons, the device structure remained intact and the circuit function remained operational.

[0032] When the fiber is continuously operated at a working voltage of 10 V for 12 hours, its surface temperature is below 35°C.

[0033] The above performance indicators show that the device has excellent mechanical robustness and environmental stability, and can withstand extreme deformations (such as joint bending, fabric washing, accidental crushing) and thermal loads that may be encountered in actual wearable or implantable applications, solving the pain points of traditional rigid electronic devices being fragile and not resistant to deformation.

[0034] The present invention also provides a method for fabricating the above-mentioned fiber integrated circuit device, comprising the following steps:

[0035] S1: Prepare a planar elastic substrate on a sacrificial layer or carrier, and form a local thickening structure on one side edge of the elastic substrate by molding or coating process;

[0036] S2: Fabricate a buffer layer and / or a functional circuit layer on an elastic substrate;

[0037] S3: A semi-cured elastomer is coated on the surface of the functional circuit layer as an interlayer adhesive layer to form a planar preform;

[0038] S4: With the locally thickened structure as the axis, the planar prefabricated body is wound into a multi-layered spiral fiber body, with the elastic base on the outside of the fiber body;

[0039] S5: The wound fiber body is fully cured to crosslink and shape the interlayer adhesive layer, resulting in a fiber integrated circuit device. After curing, the interlayer adhesive layer and the elastic substrate form an integrated elastic matrix.

[0040] Preferably, step S1 further includes plasma treatment of the surface of the elastic substrate. Before plasma treatment, the root mean square roughness Rq of the surface of the elastic substrate is 5.0-10.0 nm and the average roughness Ra is 2.0-5.0 nm. After plasma treatment, the root mean square roughness Rq of the surface of the elastic substrate is 0.8-2.5 nm and the average roughness Ra is 0.5-1.5 nm.

[0041] The surface of raw elastic substrates (such as PDMS) is usually quite rough, which limits the precision of processes such as photolithography. Plasma treatment can significantly reduce surface roughness (achieving a smoothness Ra as low as 0.5 nanometers), making it possible to perform high-precision photolithographic patterning on elastic substrates, thereby achieving micrometer-level (e.g., 0.6-5 μm) linewidth resolution, which is a key prerequisite for achieving high-density integration.

[0042] Preferably, step S2 includes sequentially preparing a buffer layer and a functional circuit layer on an elastic substrate, wherein the buffer layer is formed by at least one of deposition, spin coating, spraying, thermal evaporation, and magnetron sputtering, and the root mean square roughness Rq of the surface of the buffer layer is 0.2-1.0 nm and the average roughness Ra is 0.1-0.8 nm.

[0043] Preferably, the plasma treatment is performed using a 50-200W plasma for 2-5 minutes; and / or the plasma is at least one selected from oxygen plasma, air plasma, argon plasma, nitrogen plasma, CF4 plasma, and SF6 plasma.

[0044] Preferably, the above preparation method satisfies at least one of the following:

[0045] The elastic substrate is formed by at least one of the following processes: spin coating, spray coating, and blade coating.

[0046] The functional circuit layer is formed by at least one of the following processes: photolithography-deposition-lift, etching, thin film printing, spin coating, evaporation, sputtering, electroplating, printing, spraying, and transfer. For example, photolithography-deposition-lift is suitable for metal electrodes, while evaporation is suitable for semiconductor layers. The appropriate fabrication process can be selected according to the required function.

[0047] Another aspect of the present invention provides an application of the aforementioned fiber integrated circuit device in smart electronic fabrics, smart wearable devices, biomedical implantable or interventional devices, human-computer interaction interfaces, soft robotic electronic skin, or Internet of Things edge computing nodes.

[0048] For example, the aforementioned fiber integrated circuit device is interwoven with ordinary textile yarn through weaving, knitting or embroidery processes to form a smart electronic fabric; the fiber integrated circuit device serves as a functional unit in the smart electronic fabric for data acquisition, processing, storage or transmission.

[0049] It can also be an intelligent wearable system that includes the aforementioned fiber integrated circuit devices; the intelligent wearable system is configured as intelligent clothing, intelligent gloves, intelligent wristbands, intelligent socks or skin-touch electronic patches for monitoring human physiological signals, recognizing motion postures, tactile sensing or human-computer interaction control.

[0050] It can also be a biomedical electronic device including the aforementioned fiber integrated circuit device; the biomedical electronic device is configured as an implantable probe, a minimally invasive surgical catheter, an in vivo neuromodulator or a biochemical sensor, utilizing the flexibility and biocompatibility of the fiber integrated circuit device to make conformal contact with biological tissue.

[0051] It can also be a distributed computing network node that includes the aforementioned fiber integrated circuit device, for example, in which the fiber integrated circuit device is configured as an edge computing node in the Internet of Things, performing signal amplification, analog-to-digital conversion or logic operations locally on the fiber to reduce the amount of data transmitted to the cloud.

[0052] The fiber integrated circuit device and its fabrication method provided by this invention have the following significant advantages:

[0053] 1. Through a unique planar prefabrication-spiral winding process, the bottleneck of limited traditional fiber surface area is broken, and the radial space of the fiber is fully developed by utilizing a multi-layer spiral structure. This allows tens of thousands of transistors to be integrated in a single fiber, achieving the density standard of very large-scale integrated circuits, thereby endowing the fiber with powerful signal processing, logic operation, and storage capabilities.

[0054] 2. The locally thickened structure introduced at the beginning of winding acts as the "fiber core" during the winding process, effectively increasing the local bending stiffness, suppressing random wrinkles caused by stress concentration in the early stage of winding, ensuring the uniformity and yield of the fiber structure, and making it possible to continuously manufacture long-distance (such as meter-level) fibers.

[0055] 3. The introduced semi-cured elastomer layer fully cures after winding, forming strong chemical bonds (such as cross-linked networks) between adjacent spiral layers, eliminating interlayer voids. This design greatly enhances interlayer peel strength (significantly improved compared to van der Waals forces), effectively preventing delamination failure of the device during repeated bending, stretching, or torsion, and ensuring the electrical continuity of the circuit.

[0056] 4. By introducing a high-modulus buffer layer (such as Parylene) between the soft elastic substrate and the rigid circuit layer, a heterogeneous structure with a modulus gradient was constructed. This buffer layer mechanically acts as a "strain dispersion," effectively dispersing the large local strain experienced by the circuit layer into the surrounding elastic matrix. This ensures that the functional circuit layer remains at a relatively low strain level (even when the fiber is stretched by 20% or subjected to severe bending), thereby preventing the generation and propagation of microcracks.

[0057] 5. The preparation method of this invention incorporates surface modification technology, making high-resolution photolithography on flexible elastomers a reality. This not only improves the performance consistency of the devices but also makes the technology compatible with existing microelectronic manufacturing processes, facilitating the transition from laboratory to large-scale production.

[0058] This invention, through structural design and optimized material selection, successfully fabricates fiber integrated circuit devices that combine high-performance computing capabilities, high flexibility, high durability, and biocompatibility, providing a solution for core information processing units in smart fabrics, wearable devices, and implantable medical electronics. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the fiber integrated circuit device in Embodiment 1 of the present invention;

[0060] Figure 2 A photograph of the fiber integrated circuit device in Embodiment 1 of the present invention;

[0061] Figure 3 This is a cross-sectional photograph of the fiber integrated circuit device in Embodiment 1 of the present invention;

[0062] Figure 4 This is a three-dimensional fluorescence micrograph of the fiber integrated circuit device in Embodiment 1 of the present invention;

[0063] Figure 5 The variation of strain applied to each layer of the fiber body in Embodiment 1 of the present invention under different bending radii;

[0064] Figure 6 The change in output current of the fiber integrated circuit device of Embodiments 1-2 of the present invention during 10,000 bending cycles;

[0065] Figure 7 This is an optical microscope photograph of the fiber integrated circuit device in Comparative Example 1 of the present invention;

[0066] Figure 8 This is an optical microscope image of the fiber integrated circuit device in Comparative Example 2 of the present invention;

[0067] Figure 9The results are the peel stress test results of the fibers in Example 1 and Comparative Example 2 of this invention. Detailed Implementation

[0068] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a deep understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0069] It should be noted that in this specification, similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0070] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of the invention is usually placed in during use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0071] In the description of this embodiment, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment based on the specific circumstances.

[0072] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0073] Example 1

[0074] 1) Preparation of elastic substrate and buffer layer

[0075] Spin-coating PDMS: Polydimethylsiloxane (PDMS-601, weight ratio 9:1, Wacker Chemie AG) was spin-coated onto polyethylene terephthalate (PET) sheets at a speed of 5,000 rpm for 120 seconds.

[0076] Curing: The PMDS substrate was cured under ultraviolet (UV) irradiation for 1 hour to achieve crosslinking. The thickness of the cured PMDS substrate was 10 μm. The root mean square roughness Rq of the cured PDMS surface was measured to be 5.13 nm, and the arithmetic mean roughness Ra was 3.81 nm, as measured by atomic force microscopy. Of course, in other embodiments of the present invention, different crosslinking curing conditions can be used for different elastomer materials.

[0077] Surface treatment: The cured PDMS surface was subjected to oxygen plasma treatment (75 W, 10 Pa) for 3 minutes using a reactive ion etching system (Trion T2) to improve surface uniformity and adhesion. After surface treatment, the Rq of the PDMS surface was measured to be 1.18 nm and Ra to be 0.95 nm using atomic force microscopy.

[0078] Deposited Buffer Layer: A high-modulus parylene buffer layer was deposited on plasma-treated PDMS using a parylene coater (PDS 2010, KISCO Co.) via chemical vapor deposition (CVD) to provide mechanical support for subsequent device layers. Atomic force microscopy revealed that the surface roughness (Rq) of the buffer layer was 0.64 nm, and the magnetic resonance (Ra) was 0.48 nm. The thickness of the buffer layer was 300 nm.

[0079] 2) Fabrication of the functional layer of the top-gate transistor

[0080] Source / drain (S / D) electrode patterning:

[0081] Gold (Au) with a thickness of 50 nm was thermally evaporated on the Parylene buffer layer at a rate of 0.5 Å / s.

[0082] Spin-coat S1813 photoresist (2,000 rpm, 20 seconds) and anneal at 60°C for 180 seconds to remove solvent.

[0083] Using a direct-write optical lithography system (MicroWriter ML3) at 135 mJ / cm 2 The dose was exposed and developed in the developer for 30 seconds, rinsed with deionized water, and dried with nitrogen.

[0084] The unprotected gold areas were etched for 10 seconds in an etching solution (a deionized aqueous solution of 15 wt% KI and 3 wt% I2), then cleaned and dried.

[0085] Soak in acetone for 20 seconds to remove any remaining photoresist.

[0086] Semiconductor layer deposition: A 20 nm thick pentacene layer was thermally evaporated at a controlled rate of 0.3 Å / s using an organic-metal vacuum thermal evaporation system (FS380-S8).

[0087] Dielectric layer deposition: Parylene dielectric layer was deposited by CVD using 0.75 g of parylene precursor.

[0088] Gate electrode patterning: Using the same photolithography etching process as the S / D electrode, a 50 nm thick gold gate electrode is patterned on the dielectric layer.

[0089] Overall patterning of device layers: Using a pre-fabricated gold electrode as a mask, the sample is subjected to oxygen plasma treatment (150W, 10 sccm oxygen flow) for a total of 10 minutes (using a cycle of 1 minute etching and 2 minutes rest to prevent overheating) to etch excess buffer layers, dielectric layers and semiconductor layers.

[0090] 3) Module interconnection

[0091] Parylene insulating layers are first deposited at the electrode gaps between different functional modules.

[0092] A 150 nm copper (Cu) sacrificial layer was thermally deposited and patterned using photolithography and FeCl3 etching.

[0093] The underlying gold junctions were exposed by 150 W O2 / N2 plasma etching for 360 seconds, followed by removal of the Cu sacrificial layer.

[0094] A 50 nm gold interconnect layer was thermally deposited, and the interconnect lines were defined using photolithography and etching processes.

[0095] Finally, excess Parylene is removed by plasma etching. The functional circuit layer covers 30% of the surface of the elastic substrate.

[0096] 4) Spiral winding assembly

[0097] Preparation of locally thickened regions: Before winding, a 10 μm wide (along the winding direction) and 10 μm thick (relative to the unthickened portion) PDMS thickening line is printed at the starting edge of the PDMS substrate. This structure is used to locally increase bending stiffness and suppress wrinkle formation during winding.

[0098] Interlayer bonding treatment: To prevent delamination during deformation, a semi-cured PDMS layer (PDMS-601, 9:1, pre-cured at 50°C for 1.5 minutes) is deposited on top of the film. Thickness: 5-10 μm.

[0099] Winding: Excess substrate is removed, and the sample is spirally wound into a fibrous shape at a speed of 0.2 cm / s using a custom-made winding machine.

[0100] Final curing: The wound fibers are fully cured at 50°C for 5 minutes to ensure reliable interlayer bonding. Thus, the fiber optic integrated circuit device has an elastic matrix and circuit layers and buffer layers encapsulated within the elastic matrix, wherein the elastic substrate and interlayer bonding layer form an integrated elastic matrix after curing.

[0101] The number of active devices such as transistors in the obtained fiber integrated circuit device is approximately 100,000 / cm. The device structure is complete and does not have layers, and there are no wrinkles inside the device.

[0102] In this invention, the functional circuit layer does not exhibit significant swelling, oxidation, or interface reaction during the curing of the elastomer material and long-term use.

[0103] Unless otherwise specified, all tests in this invention were conducted in a conventional laboratory environment with a temperature of 18-30°C and a relative humidity of 30-70%.

[0104] Figure 1 This is a schematic diagram of the fiber optic integrated circuit device in this embodiment. Optical images were captured using an Olympus EX51 optical microscope and a Sony A6000 digital camera. Figure 2 A photograph of the fiber integrated circuit device in this embodiment is shown, taken with the device placed on the index finger. The scale bar in the figure is 2mm. The fiber integrated circuit device is knotted, exhibiting good flexibility and structural integrity. Figure 3 This is a cross-sectional photograph of the fiber integrated circuit device in this embodiment. Under an optical microscope, there is no obvious gap between adjacent helical layers. The device core has a locally thickened structural region, which can locally improve bending stiffness and suppress wrinkle formation during winding. The scale bar in the figure is 40 μm.

[0105] Fluorescence images were taken using a Nuohai LS-18 light-sheet microscope to observe the internal structure. The microstructure and morphology of the fiber integrated circuit device were characterized using a cryogenic field emission scanning electron microscope (Zeiss FE-SEM Ultra 55, operating voltage 3 kV) equipped with an energy dispersive spectroscopy detector. Figure 4 This embodiment shows a three-dimensional fluorescence micrograph reconstructed from a fiber integrated circuit device, demonstrating the connectivity of the micro-devices, with the circuitry distributed within a 360° radius around the fiber circumference.

[0106] Figure 5This data is obtained by calculating the strain distribution of each layer (elastic matrix / buffer layer / circuit layer) in a fiber matrix under different bending radii using finite element simulation. In the model, PDMS and Parylene are represented by eight-node linear hexahedral elements (C3D8R), and Au is represented by four-node linear membrane elements (M3D4R). Material parameters are set as follows: Au density 1.932 × 10⁻⁶. -8 t / mm 3 Young's modulus 75,000 MPa; Parylene density 1.289 × 10⁻⁶ MPa. -9 t / mm 3 Young's modulus 2,900 MPa; PDMS density 9.65 × 10⁻⁶ -10 t / mm 3 The Young's modulus is 2 MPa. Colors indicate the magnitude and sign of the applied strain. A smaller radius indicates a greater overall curvature, resulting in higher and more concentrated tensile / compressive strain. Left image (R=100 mm): Strain is very small and uniformly distributed; the circuit layer is weakly affected. Middle image (R=10 mm): Strain increases but is still dispersed by the buffer layer. Right image (R=1 mm): The extremely small radius leads to high strain concentration on the outer side, but the buffer layer effectively protects the circuit layer by dispersing the strain into the elastic matrix.

[0107] In this embodiment, the fiber body of the fiber integrated circuit device is subjected to bending deformation with a bending radius of 1 mm, tensile deformation with a radial stretch of 20%, and torsion angle of 180°·cm. -1 After torsional deformation, the transistor on / off ratio and threshold voltage of the fiber integrated circuit device changed by less than 5% at a rate of change, and the fiber body did not delaminate. Bending performance was tested according to ASTM D522 standard, tensile performance according to ASTM D2256 standard, torsional deformation was tested using an Instron universal testing machine, and transistor on / off ratio and threshold voltage were tested using a Keysight 1500A semiconductor parameter analyzer.

[0108] In this embodiment, after the fiber integrated circuit device underwent 100,000 surface abrasion cycles, 10,000 bending cycles, and 10,000 tensile cycles, the change rate of the electrical properties of the fiber integrated circuit device was within 10%, and the fiber body did not delaminate. The surface abrasion cycles were performed as follows: the surface abrasion cycles were conducted using a Taber abrasion tester; the bending cycles were performed according to the ASTM D522 standard for reciprocating bending; and the tensile cycles were performed at 20% strain and a frequency of 1Hz for reciprocating tensile testing. The tested electrical properties were the on / off ratio, threshold voltage, and on-resistance, which were obtained using a Keysight 1500A parameter analyzer in conjunction with a Keithley 2612B source meter.

[0109] In this embodiment, the fiber body of the fiber integrated circuit device was held at a tensile strain of 10% for 10 days. The resistance and output current of the fiber integrated circuit device changed by less than 6%, and the fiber body did not delaminate. The tensile strain test was conducted by fixing the strain at 10% and keeping the device in a constant temperature and humidity environment (ambient temperature 40 ± 1°C, relative humidity 50 ± 5%) for 10 days. The resistance and output current were measured using a Keysight 1500A parameter analyzer in conjunction with a Keithley 2612B source meter.

[0110] In this embodiment, the fiber of the fiber integrated circuit device was subjected to 1,000 thermal cycles at 40°C. The resistance and output current of the fiber integrated circuit device changed by less than 6%, and the fiber did not delaminate. The thermal cycling test was conducted using a commercial high and low temperature alternating test chamber at 25°C to 40°C for 1,000 cycles. The resistance and output current were measured using a Keithley 2612B source meter.

[0111] After being subjected to an external crushing load of up to 15.6 tons, the fiber integrated circuit device remained structurally intact and its circuitry remained operational. The crushing load was achieved by crushing the fiber integrated circuit device of this embodiment with the left front wheel of a 15.6-ton truck (approximately 0.7 MPa of pressure). The operationality of the circuitry was evaluated based on the functional integrity observed by the external circuitry.

[0112] Thermal testing was conducted using a high-resolution infrared thermal imager. The fiber integrated circuit device (300 μm in diameter) of this embodiment was suspended in air (10 cm above a tabletop) and continuously operated for 12 hours at a typical operating voltage of 10 V under the control of a Keysight 1500A thermal imager (FOTRIC 226). Temperature distribution was monitored in real time. All tests were conducted under ambient conditions, with a consistent ambient temperature (28 ± 1°C) and relative humidity (50 ± 5%). The highest temperature after 12 hours of operation was below 34.5°C, indicating that the high specific surface area of ​​the fiber is beneficial for efficient heat dissipation. Of course, in other embodiments of the invention, a thin Cu thermally conductive layer can be deposited on the elastic substrate; under the same testing conditions, the highest temperature after 12 hours of operation is below 32°C, further improving the heat dissipation effect.

[0113] Example 2

[0114] It was manufactured in essentially the same manner as in Example 1, except that no buffer layer was deposited during the preparation of the elastic substrate and buffer layer in step 1). Figure 6The error bars represent the standard deviation of the output current of the fiber integrated circuit devices of Examples 1-2 during 10,000 bending cycles. In this example, the current of the fiber integrated circuit device rapidly decreases with increasing cycle number, dropping to around 30 μA after approximately 2,000 cycles and approaching 10 μA after 3,000 cycles, showing a clear failure trend and increased dispersion, indicating uneven crack / open circuit development among samples. In contrast, the output current of the fiber integrated circuit device of Example 1 remained relatively stable in the 100-110 μA range from 0 to 10,000 cycles, with a slight decrease (approximately 5-10%) and a small standard deviation, demonstrating high structural and performance stability and consistency.

[0115] Comparative Example 1

[0116] Manufactured in essentially the same manner as in Example 1, the only difference being that no locally thickened structure / region was prepared in step 4) of the spiral winding assembly. As a result, random wrinkles appeared in the fiber body during the initial assembly stage, leading to structural failure. Figure 7 As shown.

[0117] Comparative Example 2

[0118] Manufactured in essentially the same manner as in Example 1, the only difference being that interlayer bonding was not performed in step 4) of the spiral winding assembly, and a semi-cured elastomer layer was not prepared on the surface of the functional circuit layer. After cyclic bending, interlayer delamination occurred, leading to structural failure. Figure 8 As shown. Peel stress tests were conducted on the fibers of this comparative example and Example 1. The peel stress of this comparative example was close to zero, indicating almost no interfacial load-bearing capacity, and no effective bonding was established between the layers of the fiber. In contrast, after applying a semi-cured elastomer layer, the peel stress of the fiber in Example 1 increased with strain, demonstrating a higher and continuously increasing interfacial load-bearing capacity. Compared to this comparative example, the interlayer peel stress was significantly improved. Figure 9 As shown.

[0119] While the present invention has been illustrated and described with reference to certain preferred embodiments, those skilled in the art should understand that the above description is a further detailed explanation of the invention in conjunction with specific embodiments, and should not be construed as limiting the specific implementation of the invention to these descriptions. Various changes in form and detail can be made by those skilled in the art, including several simple deductions or substitutions, without departing from the spirit and scope of the invention.

Claims

1. A fiber optic integrated circuit device, characterized in that, The fiber integrated circuit device comprises an elastic matrix and a functional circuit layer encapsulated within the elastic matrix. It is formed by winding a planar preform along an axis to create a multi-layered helical fiber body. The planar preform includes an elastic substrate, a functional circuit layer disposed on the elastic substrate, and an interlayer adhesive layer covering the functional circuit layer. The elastic substrate has a locally thickened structure on one edge perpendicular to the winding direction. This locally thickened structure is located at the axial center of the fiber integrated circuit device after winding, forming a supporting core. The interlayer adhesive layer is continuously distributed radially along the fiber integrated circuit device within at least a portion of the circumferential range to achieve bonding between adjacent helical layers.

2. The fiber optic integrated circuit device as described in claim 1, characterized in that, The interlayer bonding layer, the local thickening structure, and the elastic substrate are prepared using the same or chemically compatible elastomer materials.

3. The fiber integrated circuit device as described in claim 2, characterized in that, The elastomer material is selected from at least one of polydimethylsiloxane, polymethylvinylsiloxane, hydroxyl-terminated polydimethylsiloxane, vinyl-terminated polydimethylsiloxane, polyurethane, styrene-butadiene-styrene block copolymer, hydrogenated styrene-butadiene block copolymer, styrene-isoprene-styrene block copolymer, polyether-polyester block copolymer, polyether block amide, natural rubber, nitrile rubber, styrene-butadiene rubber, fluororubber, butyl rubber, chloroprene rubber, polyacrylamide, polyvinyl alcohol, alginate hydrogel, and poly(vinylidene fluoride-hexafluoropropylene) copolymer.

4. The fiber optic integrated circuit device as described in claim 1, characterized in that, A buffer layer is further provided between the elastic substrate and the functional circuit layer. The Young's modulus of the buffer layer is greater than that of the elastic substrate and less than that of the conductor material in the functional circuit layer; and / or the thickness of the buffer layer is 50-800 nm in the planar preform.

5. The fiber integrated circuit device as described in claim 4, characterized in that, The buffer layer has a single-layer or multi-layer structure, and the material of the buffer layer is one or more of the following: parylene, polyimide, photoresist, epoxy resin, acrylic resin, polyurethane, polyvinyl alcohol, polyethylene terephthalate, or inorganic-organic composite film.

6. The fiber optic integrated circuit device as described in claim 4, characterized in that, The buffer layer is patterned into an island structure or a continuous thin film structure, and the buffer layer at least covers the functional circuit layer.

7. The fiber optic integrated circuit device according to any one of claims 1-6, characterized in that, The fiber optic integrated circuit device satisfies at least one of the following: The diameter of the fiber is 50-1000 μm; In the helical stack of the fiber body, the equivalent thickness of each layer is 2-40 μm; The width of the locally thickened structure is 2-20 μm, and the thickness of the locally thickened structure is 1-30 μm greater than that of the unthickened area. In the planar preform, the thickness of the elastic substrate is 1-30 μm; In the planar preform, the functional circuit layer covers 20-40% of the surface of the elastic substrate; The functional circuit layer includes an active device region and an interconnection region, wherein the active device region comprises at least one of an organic electrochemical transistor, an organic thin-film transistor, or a metal oxide transistor. The functional circuit layer includes device units and interconnecting wires, and the conductor material of the interconnecting wires is selected from one or more of gold, silver, copper, aluminum, platinum, titanium / gold composite layer, chromium / gold composite layer, conductive carbon material, conductive polymer or transparent conductive material.

8. The fiber optic integrated circuit device according to any one of claims 1-6, characterized in that, The fiber optic integrated circuit device satisfies one or more of the following characteristics: The fiber body is subjected to bending deformation with a bending radius of 1 mm, tensile deformation of 20% in the radial direction, and torsion angle of 180°·cm. -1 After at least one of the mechanical deformations in the torsional deformation, the rate of change of the transistor on / off ratio and threshold voltage of the fiber integrated circuit device is less than 5%, and the fiber body does not delaminate; After the fiber body undergoes at least one of the following tests: at least 100,000 surface abrasion cycles, at least 10,000 bending cycles, and at least 10,000 tensile cycles, the electrical performance of the fiber integrated circuit device changes by less than 10%, and the fiber body does not delaminate. The fiber body is held at 10% tensile strain for at least 10 days, or subjected to at least 1,000 thermal cycles at 40°C, and the resistance and output current change rate of the fiber integrated circuit device are within 6%, and the fiber body does not delaminate. The fiber body remained structurally intact and the circuit function was operational after withstanding an external crushing load of up to 15.6 tons. The fiber body operates continuously for 12 hours at a working voltage of 10 V, and its surface temperature is below 35°C.

9. A method for fabricating a fiber optic integrated circuit device, characterized in that, Includes the following steps: S1: Prepare a planar elastic substrate on a sacrificial layer or carrier, and form a locally thickened structure on one side edge of the elastic substrate by molding or coating process; S2: Prepare a buffer layer and / or a functional circuit layer on the elastic substrate; S3: A semi-cured elastomer is coated on the surface of the functional circuit layer as an interlayer adhesive layer to form a planar preform; S4: Using the locally thickened structure as the axis, the planar preform is wound into a multi-layered spiral laminated fiber body, with the elastic substrate on the outside of the fiber body; S5: The wound fiber body is completely cured to crosslink and shape the interlayer adhesive layer, thereby obtaining the fiber integrated circuit device.

10. The preparation method according to claim 9, characterized in that, Step S1 further includes plasma treatment of the surface of the elastic substrate. Before plasma treatment, the root mean square roughness Rq of the surface of the elastic substrate is 5.0-10.0 nm and the average roughness Ra is 2.0-5.0 nm. After plasma treatment, the root mean square roughness Rq of the surface of the elastic substrate is 0.8-2.5 nm and the average roughness Ra is 0.5-1.5 nm.

11. The preparation method according to claim 10, characterized in that, Step S2 includes sequentially preparing a buffer layer and a functional circuit layer on the elastic substrate, wherein the buffer layer is formed by at least one of deposition, spin coating, spraying, thermal evaporation, and magnetron sputtering, and the root mean square roughness Rq of the surface of the buffer layer is 0.2-1.0 nm and the average roughness Ra is 0.1-0.8 nm.

12. The preparation method according to claim 10, characterized in that, The plasma treatment is performed using a 50-200W plasma for 2-5 minutes; and / or the plasma is selected from at least one of oxygen plasma, air plasma, argon plasma, nitrogen plasma, CF4 plasma, and SF6 plasma.

13. The preparation method according to any one of claims 9-12, characterized in that, The preparation method satisfies at least one of the following: The elastic substrate is formed by at least one of spin coating, spray coating, and blade coating processes. The functional circuit layer is formed by at least one of the following processes: photolithography-deposition-stripping, etching, thin film printing, spin coating, evaporation, sputtering, electroplating, printing, spraying, and transfer.

14. The application of a fiber integrated circuit device as described in any one of claims 1-8 in smart electronic fabrics, smart wearable devices, biomedical implantable or interventional devices, human-computer interaction interfaces, soft robotic electronic skin, or Internet of Things edge computing nodes.

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