Narrow vector store instructions

Abstract

An apparatus comprises: an instruction decode circuit (10) for decoding an instruction; and issuing circuitry (12) for issuing at least one micro-operation to control the processing circuitry (16, 56) to perform the processing operation. In response to decoding of a narrowed vector store instruction specifying a plurality of vector source registers each for specifying a vector operand, the instruction decode circuit is configured to control the issue circuit to issue the at least one micro-operation to control the processing circuit: narrow data elements of the plurality of vector source registers from a second data element size to a first data element size, the first data element size being smaller than the second data element size; and store at least one vector of narrowed data elements including data elements narrowed to the first data element size of the plurality of vector source registers to a location in the memory system.

Description

[0001] This technology relates to the field of data processing.

[0002] The processing circuitry can support a vector processing architecture, where vector instructions can trigger vector operations to be performed on vector operands comprising multiple data elements. Compared to using separate scalar instructions to process each data element independently as a scalar implementation, using vector instructions to perform vector operations reduces the instruction fetching and decoding overhead for a given operation to be performed on each data element in a set of data elements.

[0003] At least some examples provide an apparatus comprising: an instruction decoding circuit for decoding an instruction; and a release circuit for releasing at least one micro-operation in response to the decoding of a given instruction by the instruction decoding circuit to control a processing circuit to perform a processing operation corresponding to the given instruction; wherein: in response to decoding a narrowing vector storage instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, the instruction decoding circuit is configured to control the release circuit to release at least one micro-operation to control the processing circuit to: narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size, the first data element size being smaller than the second data element size; and store at least one vector comprising the narrowed data elements of the plurality of vector source registers narrowed to the first data element size to a location in a memory system, the location in the memory system corresponding to a target memory address determined based on at least one address operand.

[0004] At least some examples provide computer-readable code for manufacturing an apparatus comprising: an instruction decoding circuit for decoding an instruction; and a issuing circuit for issuing at least one micro-operation in response to the decoding of a given instruction by the instruction decoding circuit to control a processing circuit to perform a processing operation corresponding to the given instruction; wherein: in response to decoding a narrowing vector storage instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, the instruction decoding circuit is configured to control the issuing circuit to issue at least one micro-operation to control the processing circuit to: narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size, the first data element size being smaller than the second data element size; and store at least one vector comprising the narrowed data elements of the plurality of vector source registers narrowed to the first data element size to a location in a memory system, the location in the memory system corresponding to a target memory address determined based on at least one address operand.

[0005] At least some examples provide a method comprising: decoding an instruction; and, in response to decoding a given instruction, issuing at least one micro-operation to control processing circuitry to perform a processing operation corresponding to the given instruction; wherein: in response to decoding a narrowing vector storage instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, the at least one micro-operation is issued to control the processing circuitry to: narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size, the first data element size being smaller than the second data element size; and store at least one vector comprising the narrowed data elements of the plurality of vector source registers narrowed to the first data element size to a location in a memory system, the location in the memory system corresponding to a target memory address determined based on at least one address operand.

[0006] At least some examples provide a computer program for controlling a host data processing device to provide an instruction execution environment for executing target program code. The computer program includes: instruction decoding program logic for decoding instructions of the target program code; and processing program logic for performing a processing operation corresponding to a given instruction decoded by the instruction decoding program logic; wherein: in response to decoding a narrowing vector storage instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, the instruction decoding program logic is configured to control a publishing program logic to publish at least one micro-operation to control the processing program logic to: narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size, the first data element size being smaller than the second data element size; and store at least one vector comprising the narrowed data elements of the plurality of vector source registers narrowed to the first data element size at a location in a simulated address space, the location in the simulated address space corresponding to a target memory address determined based on at least one address operand.

[0007] At least some examples provide a storage medium that stores the computer-readable code or computer program mentioned above. The storage medium can be a non-transitory storage medium.

[0008] Further aspects, features, and advantages of this technology will become apparent from the following description, taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 An example of a processing system for support vector processing is shown;

[0010] Figure 2An example of a vector register with a vector length indicated by a vector length parameter is shown;

[0011] Figure 3 A first example of an instruction decoding circuit and a issuing circuit is illustrated, in which the instruction decoding circuit and the issuing circuit are located within a processor such as a central processing unit (CPU);

[0012] Figure 4 An example is shown of using a coprocessor to handle an offloaded subset of operations from an operation flow to be executed by the main processor;

[0013] Figure 5 The functionality of both non-interleaved and interleaved variants of the narrowed vector storage instruction is illustrated;

[0014] Figure 6 The functionality of a non-interleaved variant of the narrowed vector storage instruction with assertions is illustrated;

[0015] Figure 7 The data processing methods are illustrated;

[0016] Figure 8 This illustrates a method for handling narrowed vector storage instructions;

[0017] Figure 9 An example is given of a method for handling interleaved variants of narrowed vector store instructions;

[0018] Figure 10 An example is given of a method for handling non-interleaved variants of narrowed vector store instructions;

[0019] Figure 11 A simulation example is shown.

[0020] An apparatus includes: an instruction decoding circuit for decoding instructions; and a issuing circuit for issuing at least one micro-operation in response to the decoding of a given instruction by the instruction decoding circuit to control processing circuitry to perform a processing operation corresponding to the given instruction. Designing an instruction set supported by the instruction decoding circuitry can be a relatively complex task because there may be a limited encoding space available compared to the theoretically wide range of operations that can be supported, and therefore a justification must be provided for supporting a particular instruction. Design choices and trade-offs made regarding which operations to support and how to encode those instructions can affect the performance and power consumption of the processing circuitry. Other factors to consider include the practicality of implementing the circuitry that executes the instructions and the flexibility offered by the architectural instructions to support different microarchitectural design choices for the specific implementation of the circuitry. Therefore, just because a given operation is theoretically possible does not automatically mean that its inclusion as a particular instruction will be desirable. Instruction set architects are generally extremely cautious about adding new instructions to the instruction set because once an instruction is included, it is extremely difficult to remove it, as continued support will be required to allow legacy software using the instruction to continue operating. If the introduction of instructions proves problematic in hardware implementation or results in insufficient coding space to represent a more preferable operation, the negative consequences of adding to the instruction set will be felt over time. Therefore, caution is advised when considering adding to the instruction set.

[0021] In the example below, the instruction decoding circuitry supports narrowed vector store instructions that specify at least one address operand and multiple vector source registers, each for specifying a vector operand with a given vector length. In response to decoding the narrowed vector store instruction, the instruction decoding circuitry controls the issuing circuitry to issue at least one micro-operation to control the processing circuitry: • Narrow the data elements of multiple vector source registers from the second data element size to the first data element size, where the first data element size is smaller than the second data element size; and • Store at least one vector of narrowed data elements, including multiple vector source registers and narrowed to the size of a first data element, at a location in a memory system corresponding to a target memory address determined based on at least one address operand.

[0022] Therefore, the narrow vector storage instruction enables both the narrowing of vector elements from multiple source registers and the storage of narrow vector elements from multiple source registers into memory in response to a single instruction.

[0023] This instruction can be helpful for workloads that process data elements stored in memory in a compressed data structure compared to the processing format of those data elements at the processing circuitry. For example, maintaining a vector in a vector register with a second data element size can be used to maintain high precision during intermediate steps of vector processing operations performed on those data elements, whereas storing a vector with elements narrowed to the first data element size can provide a denser storage format that sacrifices precision to reduce memory storage overhead for a given number of data elements. An example of a workload type where this is useful is image processing workloads, where it is very common for pixel data to be stored in memory with small data element sizes, but with wider data element sizes when loaded from memory to apply image processing kernels such as filtering, resizing, or rotation.

[0024] Vector processing architectures can be attractive for this type of workload because they can apply repetitive operations to multiple data elements in response to a single instruction. However, the inventors have recognized that existing vector instruction sets may be inefficient for handling this type of workload.

[0025] The narrowing vector store instructions described in this paper are more efficient than alternative instructions because, since both narrowing and store are in response to the execution of a single architecture instruction, there is no need to consume additional architecture registers (registers represented by one of a finite set of architecture register identifiers that can be encoded in the instruction code) to hold one or more temporary narrowing vectors between the narrowing operation and the store (in contrast, such architecture registers would be consumed if the narrowing and store instructions were executed as separate architecture instructions, where the narrowing instruction is a register-to-register instruction rather than a register-to-memory instruction). Therefore, narrowing vector store instructions can help reduce register pressure, which tends to improve performance because the code is less likely to run out of spare architecture registers, thus reducing the need to overflow register data into memory when register data might already be held in the register file corresponding to the architecture vector register.

[0026] Furthermore, providing instructions that store at least one vector of narrowed data elements from two or more source vector registers into memory can preserve the memory throughput (amount of data processed per store instruction) achieved against equivalent non-narrowed vector store instructions. In contrast, an alternative narrowing store instruction that stores narrowed data elements from a single vector source register into memory will have reduced memory throughput compared to the equivalent non-narrowed vector store instruction. This is because for narrowing store instructions, the data element size is reduced, so if the amount of data in the vector source registers includes a given number of elements with larger sizes, the amount of data stored into memory will be less than the amount of data in the vector source registers when the elements are narrowed to a smaller size and stored into memory. Therefore, a narrowing store instruction operating on a single vector source register will have reduced memory throughput compared to a non-narrowed vector store instruction. However, storing narrowed data elements from multiple vector source registers into memory means that the total amount of data stored per store operation is not reduced compared to a non-narrowed vector store instruction, because the data is stored from more than one vector source register, and thus memory throughput can be preserved. Executing a large number of store instructions for each volume of memory data processed incurs significant costs in terms of memory control bandwidth (e.g., increased number of memory translation lookups, consumed load / store slots, etc., which may limit the bandwidth available for other operations and thus limit performance). This cost can be reduced for a given amount of memory throughput by using the narrowed vector store instructions described above.

[0027] Therefore, narrow vector store instructions that store a vector of narrow data elements from multiple vector source registers into memory can provide several advantages for supporting workloads that require data elements to be processed in a larger size than their storage format in memory, and thus the additional coding space consumed by providing this type of instruction in the instruction set is justifiable.

[0028] Narrow vector storage instructions specify two or more vector source registers. In the encoding of narrow vector storage instructions, the vector source registers can be explicitly identified by two or more source register fields. Alternatively, the instruction can explicitly identify a first source register among the two or more source registers in the register field of the instruction encoding, and one or more other source registers among the two or more vector source registers can be implicitly identified as vector source registers whose schema register identifier is at a predetermined offset relative to the schema register identifier of the first source register. For example, the two or more vector source registers can be registers associated with a set of consecutive schema register identifiers starting from the schema register identifier of the first source register explicitly encoded in the instruction encoding. Using this method, software developers or compilers are constrained to select registers with consecutive schema register identifiers as sources for narrow vector storage instructions; however, this constraint has the advantage of reducing the amount of encoding space required to encode multiple source registers, which can be useful since instruction encoding space may be scarce.

[0029] Regardless of the specific method used to encode the vector source registers in the instruction, each vector source register, explicitly or implicitly identified by the instruction, is associated with a different schema register identifier and can therefore be individually designated as a source register or destination register by another instruction in the instruction set supported by the instruction decoding circuitry. That is, where a given vector instruction specifies a source / destination vector register field for identifying the corresponding vector register used as a source / destination operand, each vector source register of a narrow vector store instruction can have a different encoded schema register identifier associated with the source / destination register field of the given vector instruction. Therefore, each source register of a narrow vector store instruction can be independently designated as an operand for vector operations or a destination to be updated based on the result of the vector operations.

[0030] Narrowing vector store instructions can be mapped to one or more micro-operations by instruction decoding circuitry. In some examples, providing a single narrowing vector store instruction can result in a reduction in the number of micro-operations issued compared to examples using more than one instruction. For example, one method for storing narrowing vector data elements from multiple vector source registers into memory is to first narrow the data elements using a register-to-register zip instruction and combine the narrowing data elements from the multiple vector source registers and write the result to an architecture register, then use a store instruction to retrieve the narrowing data from the destination register of the zip instruction and store the data into memory. The store instruction itself can be mapped to two micro-operations: a micro-operation for retrieving data from the source registers, and a micro-operation for calculating the destination address and performing the store on the data retrieved from the registers in the first micro-operation. Therefore, the use of a zip instruction immediately following a store instruction can involve the use of at least three micro-operations. In contrast, the instruction decoder can map narrowing vector store instructions to fewer micro-operations, thereby reducing the number of micro-operations required to perform the operation and thus reducing the overhead associated with performing the operation.

[0031] Specifically, at least one micro-operation may include a first micro-operation and a second micro-operation, wherein the first micro-operation controls the processing circuitry to form at least one vector of narrowed data elements, and the second micro-operation controls the processing circuitry to consume at least one vector of narrowed data elements formed by the first micro-operation and store the consumed at least one vector of narrowed data elements in a location in the memory system. In some examples, the second micro-operation may also control the processing circuitry to determine the location in the memory system where at least one vector of narrowed data elements will be stored, based on at least one address operand. Because for narrowed vector store instructions, the intermediate step between narrowing and storing the narrowed data in memory is not stored in the architecture register, it is not necessary to provide a micro-operation for retrieving data from the architecture register, and instead, the micro-operation for storing the data in memory may consume data directly from the micro-operation for narrowing the data elements. Therefore, compared to examples that use more than one instruction to perform the operation, providing a single architecture instruction to store narrowed data elements from multiple vector source registers into memory can result in a reduction in the number of micro-operations issued, and thus an improvement in performance.

[0032] The amount of data stored in memory in response to a narrow vector store instruction is not particularly limited. However, in some examples, the narrow vector store instruction is encoded such that the size of at least one vector of the narrowed element stored in memory can be equal to the given vector length. Each instance of the narrow vector store instruction does not necessarily need to store an amount of data larger than or equal to the given vector length, because for some assertion cases, the assertion operand of the narrow vector store instruction may have already selected a valid portion of data smaller than the given vector length. However, the maximum amount of data that can be stored by the narrow vector store instruction can be greater than or equal to the given vector length. This is significantly different from a narrow vector store instruction that specifies a single vector source register, because in the case of a single vector register with a given vector length as a source, the data stored in memory when the data element of that single vector register is narrowed will be smaller than the given vector length. In contrast, because more than one vector source register is specified by this narrow vector store instruction, the total amount of data stored from multiple vector source registers can then be equal to or greater than the given vector length, even after the element has been narrowed. This helps to increase the number of narrow data elements stored in memory for a given open volume associated with executing a store instruction.

[0033] Some examples can support non-interleaved variants of narrow vector store instructions. In response to a non-interleaved variant of a narrow vector store instruction, the instruction decoding circuitry can control the issuing circuitry to issue at least one micro-operation to control the processing circuitry to store at least one vector of narrow data elements into memory at a location where the narrow data element corresponding to a given source vector register among a plurality of source vector registers is provided in a consecutive portion of at least one vector of the narrow data element, without interpolating narrow data elements corresponding to any other source vector register among the plurality of source vector registers. Therefore, the vector of the narrow data element can include multiple separate portions, each of the plurality of vector source registers corresponding to one portion, and each portion including the narrow data element of the corresponding vector source register. The non-interleaved variant can be used to support (compared to the interleaved variant discussed below) memory structures that do not interleave workloads across multiple channels.

[0034] Non-interleaved variants of narrowing vector store instructions can specify at least one assertion register, each specifying element assertion information indicating which data elements of a plurality of vector source registers are masked data elements, for which the corresponding portion of at least one vector of the narrowing data elements is used to specify a value unrelated to these masked data elements. For example, for a location in the memory system that would otherwise be written with a narrowing data element corresponding to a given masked data element without an assertion being applied, a value unrelated to the masked data element (e.g., zero) can be written instead. Alternatively, portions of the memory system corresponding to masked data elements of the vector source registers can be excluded from the store operation, and the store operation can omit any data from those portions of the memory system. Assertion information can be represented in different ways. Some examples may specify an assertion mask comprising multiple bit fields as at least one assertion value, each bit field indicating whether the corresponding set of one or more elements is masked or unmasked. Alternatively, an assertion counter can be used to indicate the total number of unmasked data elements (which can be implicitly considered to start from the first data element of the vector of narrowed data elements to be stored in the memory system). In other words, the assertion counter can indicate the boundary between the initial set of unmasked data elements and the subsequent set of masked data elements. Regardless of the specific way the assertion value represents the masked data elements, by supporting assertions, this enables software to prevent storage operations for narrowed vector storage instructions from overflowing into memory beyond the end of the data structure being processed, even if the data structure being processed has a total number of data elements that is not an exact multiple of the number of elements that can be processed using a single instance of narrowed vector storage instructions.

[0035] For non-interleaved variants of narrow vector store instructions, element assertion information can be specified by at least one assertion register at the granularity of the narrowed data elements to be stored in memory. Typically, the element assertion information for a store instruction can be sized to correspond to a given vector length, such that a single assertion register corresponds to a single vector source register. However, because elements are narrowed before being stored in response to a narrow vector store instruction, the amount of element assertion information provided for a given portion of memory with the narrowed data size can actually be applied to a larger amount of data in the source registers. This means that a given assertion register with a given granularity can correspond to more than one vector source register. Therefore, a given assertion register can specify element assertion information corresponding to two or more vector source registers among the multiple vector source registers of a narrow vector store instruction. This allows for a reduction in the number of assertion registers required for a given operation.

[0036] In some examples, in response to a narrow vector store instruction specifying N vector source registers, the instruction decoding circuit can control the issuing circuit to issue at least one micro-operation to control the processing circuit to narrow the data element to a size no greater than 1 / N times the size of the first data element, which is the size of the second data element. For example, if two source vector registers are specified, the narrowed data element can be no greater than half the size of the data element in the source vector registers. This ensures that the vector of the narrowed data element is no greater than the given vector length. This means that the amount of data stored in memory in response to a narrow vector store instruction does not exceed the amount of data stored in memory in response to a regular store operation on a source register with a given vector length. In this way, it is not necessary to extend the control information that would otherwise be used to control the size of the storage operation with the given vector length to accommodate the narrow vector store instruction. For example, assertions or other control values ​​may have a size corresponding to the given vector length, so by limiting the vector of the narrowed data element to the given vector length, it is not necessary to extend this control information and the narrow vector store instruction is not associated with additional overhead.

[0037] Some examples can support interleaved variants of narrow vector storage instructions. In response to an interleaved variant of the narrow vector storage instruction, the instruction decoding circuitry controls the issuing circuitry to issue at least one micro-operation to control the processing circuitry to store at least one interleaved vector of narrow data elements, comprising multiple interleaved channels, into the memory system, each interleaved channel corresponding to one of the source vector registers. The interleaved variant can be used to support workloads that operate on a storage structure comprising multiple interleaved channels of data elements, such as complex numbers represented as separate real and imaginary parts in two channels, or pixel data of an image represented in RGB (red, green, blue) or RGBA (red, green, blue, alpha) format, but requires the processing kernel to be applied to independent channels of data extracted from the stored multi-channel structure. Therefore, while data can be stored in vector registers in individual channels for processing, it may be desirable to store data back to memory in an interleaved mode, such that channels corresponding to specific groups of elements (e.g., specific pixels) are stored together in memory.

[0038] By combining interleaving operations with store operations, the number of micro-operations can be reduced (by removing the micro-operations used to retrieve interleaved elements from the architecture registers for subsequent store operations), and register pressure can be reduced because there is no need to temporarily assign interleaved elements to the architecture registers in the intermediate step between interleaving and store.

[0039] The interleaving pattern used to store a vector of narrowed data elements into a memory location can be implicitly defined by encoding an interleaved variant of the narrowed vector store instruction. Therefore, a deinterleaved variant of the narrowed vector store instruction is not required to specify an index operand that explicitly identifies the index value at each corresponding element location of the vector of narrowed data elements to be inserted into the location to be stored in memory. For example, an implicitly defined interleaving pattern could be a pattern that sequentially selects narrowed data elements from the corresponding vector source registers to provide the next element of the vector of narrowed data elements (e.g., if separate source registers exist for R, G, B, and A channels in an image processing example, elements could be sequentially selected from each register to provide an interleaved vector of narrowed data elements: RGBARGBARGBA…). Therefore, the interleaved variant of the narrowed vector store instruction can be architecturally constrained to control the processing circuitry to execute a specific implicitly defined interleaving pattern and cannot support any arbitrary general permutation where any single data element from the source vector can be arbitrarily permuted to any location within the vector of narrowed data elements. Using implicitly defined interleaving patterns can be advantageous because the index vectors used to control general permutations can make it difficult to write vector-length-agnostic software according to a scalable vector architecture (discussed further below). This is because the index values ​​used to index the vectors would need to be pre-computed in the software for a specific vector length, and the limited range of each index value available for the index vectors could constrain the maximum vector length that the general permutation operations controlled by the index vectors can support. These problems can be avoided by providing interleaved variants of narrow vector storage instructions that use implicitly defined interleaving patterns, and scalable vectorized software becomes available for handling workloads that operate on narrower data elements stored in memory as a packed interleaved data structure.

[0040] Interleaved variants of the narrowing vector storage instruction can also specify at least one assertion value that specifies element assertion information indicating which data elements in a plurality of vector source registers are masked data elements. For these masked data elements, the corresponding portion of at least one vector of the narrowing data elements is used to specify a value independent of these masked data elements. However, unlike the non-interleaved variant, for the interleaved variant, specifying element assertion information at the granularity of element groups, each element group comprising one data element from each of the plurality of interleaved channels, can be useful. For example, all elements within the same element group can have their assertions controlled by the same mask bit of the assertion mask, which is specified as at least one assertion value. Alternatively, in the case of an assertion counter, a monotonically increasing value of the assertion counter causes consecutive element groups to be selected as active (e.g., a count value of 3 causes another element group (comprising multiple data elements) to be selected as active, while a count value of 2 would mask the other element group). Therefore, for the interleaved variant, the encoding of the instructions constrains the assertions to either mask all data elements in the same element group or not mask any data elements in the same element group. Thus, it becomes impossible to partially mask some elements in an element group without masking other elements in the same element group. Applying assertions at the granularity of element groups can be particularly useful for the interleaved variant because, typically, if multiple channels of interleaved data need to be interleaved, each channel in a given element group will either need to be processed or not, and therefore the benefit of supporting partial assertions is minimal. Restricting assertions to the granularity of element groups also simplifies microarchitecture implementation because, when interleaving elements of a single element group, common assertion control can be applied to the corresponding element location in each vector source register.

[0041] The number of vector source registers specified by the narrow vector store instruction can vary. Some examples can support two-register variants of the narrow vector store instruction. For example, in an interleaved variant, this can be used to support interleaving of the real and imaginary parts of complex values. Other examples can support three-register and / or four-register versions of the instruction, or may support additional vector source registers. An interleaved variant with three vector source registers can be used to support operations on image data in RGB format. An interleaved variant with four vector source registers can be used to support operations on image data in RGBA format. On the other hand, regardless of whether the variant is interleaved or non-interleaved, supporting more than two vector source registers can help increase memory throughput, thereby allowing fewer vectorized loop iterations to be processed for a given amount of data. In cases where more than one variant of the instruction is supported corresponding to different numbers of vector source registers, the corresponding variant of the instruction can be distinguished by its instruction opcode or by another field in the instruction that identifies the number of vector source registers.

[0042] The processing circuitry is used to narrow the data elements of multiple vector source registers from a second data element size to a first data element size. There are no particular restrictions on how this is performed. For example, a rounding process can be performed when reducing the number of bits to the first data element size. In some examples, if the first number of bits is too small to represent the value of a data element, narrowing the data element can be done by taking a saturated value that is the maximum representable value among the data elements of the first size.

[0043] However, in workloads where data is stored in memory in a narrower size and manipulated in registers in a larger size, rounding may often not be necessary. In these workloads, it is expected that the value to be stored in memory will not be larger than that which can be represented using a first data element size, because the increase in data element size is for improving precision, not for representing values ​​larger than those that can be represented in a smaller data element size. For example, data may be stored in memory as an integer with a first data element size, loaded and expanded to a second data element size, converted to a more precise representation (e.g., from integer to floating-point), manipulated, converted back to a less precise representation (rounding may be performed at this stage), and then specified in a narrowing vector store instruction. Therefore, it is expected that the data to be narrowed and stored will not be significantly larger than the element initially loaded from memory with a first data element size. Thus, in some examples, the processing circuitry is configured to narrow a given data element by selecting a portion of the least significant bit of the given data element as the narrowing data element, which has a size equal to the first data element size. Narrowing the execution in this way through truncation is simple and avoids the overhead of unnecessary rounding when it is not expected to be necessary.

[0044] In some examples, narrowing vector storage instructions can allow at least one vector of the narrowed data elements to be stored to have a total size greater than or equal to twice the given vector length. For instance, this could be useful for a specific implementation that uses a 2x narrowing operation to store RGBA data from four vector source registers, resulting in the data values ​​of two vectors (i.e., data of twice the given vector length) being stored in memory. By enabling data of more than one vector length to be stored in a single instruction, memory throughput can be increased.

[0045] Some specific implementations may support a fixed definition of the size of the first data element and the size of the second data element (e.g., a fixed ratio between the size of the first data element and the size of the second data element, such as the second data element being two or four times the size of the first data element).

[0046] However, in some examples, at least one of the first and second data element sizes is variable, depending on at least one control parameter associated with the narrowing vector storage instruction. For example, this control parameter may include one or more of the following: the instruction's opcode, a field encoded by the instruction to specify element size information, and / or a parameter stored in a control register to specify element size information. For example, variations of the instruction corresponding to different settings of the control parameter can be provided to support two-fold and / or four-fold widening operations and to operate on elements of different sizes in memory. For example, variations can be provided for first and second data element sizes of 8 bits and 16 bits, 8 bits and 32 bits, and / or 16 bits and 32 bits, respectively.

[0047] In some implementations, the length of a given vector can be implicitly defined as a fixed value in the instruction set architecture. In other examples, the length of a given vector can be variable, depending on the parameters associated with the narrow vector storage instruction.

[0048] However, it can be useful for a device to include a vector length storage circuit to store a vector length parameter indicating a given vector length. This can help support vector length-agnostic software written according to a scalable vector instruction set architecture, where the given vector length used to execute narrowed vector stored instructions is unknown at compile time, allowing the same software to execute on different processing platforms (implementing vector lengths different from the given vector length), but instructions such as loop control instructions can be adapted to the implemented vector length based on the given vector length read from the vector length storage circuit.

[0049] In some examples, the apparatus including instruction decoding circuitry and issuing circuitry may also include processing circuitry controlled by the issuing circuitry to perform operations corresponding to narrowed vector storage instructions.

[0050] However, in other examples, for at least a subset of instruction types, the issuing circuitry can issue at least one micro-operation corresponding to a narrow vector memory instruction to off-chip processing circuitry on a separate integrated circuit. Therefore, the processing circuitry that performs the operation in response to the narrow vector memory instruction does not necessarily have to be part of the same apparatus as the instruction decoding circuitry and issuing circuitry that decodes the narrow vector memory instruction and issues one or more corresponding micro-operations. For example, the off-chip processing circuitry can include a coprocessor to which the main processor, including the instruction decoding circuitry and issuing circuitry, can offload the operation, wherein the coprocessor can be implemented on a chiplet separate from the instruction decoding / issuing circuitry logic of the main processor.

[0051] In some examples, the device may include a coprocessor configured to perform processing operations on a subset of instruction types offloaded from the main processor, and the coprocessor may include instruction decoding circuitry and dispatch circuitry for decoding instructions of said subset of instruction types. The coprocessor may reside on the same chip as the main processor or on a different chip. For each subset of instruction types offloaded to the coprocessor, the coprocessor may have its own internal instruction decoding and dispatch circuitry, and therefore the techniques discussed above can also be implemented within the coprocessor.

[0052] Therefore, there are various use cases where instruction decoding circuits and dispatch circuits that can support narrowed vector storage instructions exist.

[0053] The techniques discussed above can be implemented within a device with hardware circuitry provided for implementing instruction decoding circuitry, issuing circuitry (and, if provided in the same device, processing circuitry), as discussed above. However, the same techniques can also be implemented within a computer program that executes on a host data processing device to provide an instruction execution environment for executing object code. Such a computer program can control the host data processing device to simulate the architectural environment provided on the hardware device, which actually supports object code according to a given instruction set architecture, even if the host data processing device itself does not support that architecture.

[0054] A computer program may have instruction decoding logic and processing logic. The instruction decoding logic emulates the function of the instruction decoding circuitry discussed above, and the processing logic executes a processing operation corresponding to a given instruction decoded by the instruction decoding logic. For example, the instruction decoding logic may include if / if statements for controlling the selection of a corresponding code sequence (part of the processing logic) written in the native instruction set of the host data processing device in response to a given instruction in the target code, wherein execution of the code sequence will control the host data processing device to perform an operation corresponding to the decoded instruction. The instruction decoding logic and processing logic support narrowed vector memory instructions as discussed above, which cause the corresponding narrowed memory operations (with optional interleaving) to be executed by the processing logic. However, the register and memory address spaces that are expected to be provided in the instruction set architecture of the target program code may not actually be provided in the host device. Therefore, such register and memory address spaces can be simulated by mapping them to the host's memory device circuitry (e.g., the registers and memory of the host device). Therefore, in the simulation implementation, the storage target address of the narrowed vector storage instruction (calculated based on at least one address operand) represents an address in the simulated address space (which may differ from the address space of the host memory used to access the host data processing device), and the vector source register can be simulated using the corresponding region of the host memory device circuitry, rather than being mapped to any particular hardware register file.

[0055] For example, such computer simulation programs can be useful when executing legacy code written for one instruction set architecture on a host processor that supports different instruction set architectures. Additionally, simulation can allow software development for a newer version of the instruction set architecture to begin before the processing hardware supporting the new architecture is ready, because executing the software on a simulated execution environment allows software testing to be performed in parallel with ongoing development of the hardware device supporting the new architecture. The simulation program can be stored on a storage medium, which can be a non-transitory storage medium.

[0056] A specific example will now be described with reference to the accompanying drawings.

[0057] Figure 1An example of a data processing apparatus 2 is illustrated schematically. The data processing apparatus has a processing pipeline 4 comprising multiple pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 (an example of an instruction decoding circuit) for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; a release stage 12 (an example of a release circuit) for checking whether the operands required for the micro-operation are available in register 14, and for releasing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 (an example of a processing circuit) for performing a data processing operation corresponding to the micro-operation by processing the operands read from register 14 to generate a result value; and a write-back stage 18 for writing the result of the processing back to register 14. It will be understood that this is merely one example of a possible pipeline arrangement, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, a register renaming stage may be included to map the architecture registers specified by program instructions or micro-operations to physical register specifiers in the identifier register 14. In some examples, a one-to-one relationship may exist between program instructions decoded by the decoding stage 10 and corresponding micro-operations processed by the execution stage. It is also possible that a one-to-many or many-to-one relationship exists between program instructions and micro-operations, such that, for example, a single program instruction can be split into two or more micro-operations, or two or more program instructions can be merged to be processed as a single micro-operation.

[0058] Execution phase 16 includes multiple processing units for performing different types of processing operations. For example, the execution units may include a scalar processing unit 20 (e.g., a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations on scalar operands read from register 14); a vector processing unit 22 for performing vector operations on vectors comprising multiple vector elements; and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. Other examples of processing units that may be provided at the execution phase may include a floating-point unit for performing operations involving values ​​represented in floating-point format, or a branch unit for processing branch instructions.

[0059] Register 14 includes a scalar register 25 for storing scalar values, a vector register 26 for storing vector values, and an assertion register 27 for storing assertion values. Assertion value 27 can be used by vector processing unit 22 when processing vector instructions, wherein a given assertion value in the assertion register indicates which vector elements of the corresponding vector operand stored in vector register 26 are active (unmasked) vector elements or inactive (masked) vector elements (wherein the operation corresponding to inactive data elements can be suppressed or may not affect the resulting value generated by vector processing unit 22 in response to a vector instruction).

[0060] The Memory Management Unit (MMU) 36 controls the address translation between virtual addresses (specified by instruction fetching from fetch circuit 6 or load / store requests from load / store unit 28) and physical addresses identifying locations in the memory system, based on address mappings defined in a page table structure stored in the memory system. The page table structure can also define memory attributes that specify access permissions for corresponding pages in the address space, such as whether a region of the address space is read-only or read / write, which permission levels are allowed to access the region, and / or other properties that control how the corresponding region of the address space can be accessed. Entries from the page table structure can be cached in a Translation Lookahead (TLB) 38, a cache maintained by the MMU 36, to cache page table entries or other information to accelerate access to page table entries from the page table structure shown in the memory.

[0061] In this example, the memory system includes a tier-one data cache 30, a tier-one instruction cache 8, a shared tier-two cache 32, and main system memory 34. It will be understood that this is merely one example of a possible memory hierarchy, and other cache arrangements may be provided. The specific type of processing units 20 to 28 shown in execution phase 16 is only one example, and other specific implementations may have different sets of processing units or may include multiple instances of the same type of processing units, allowing multiple micro-operations of the same type to be processed in parallel. It will be understood that... Figure 1 This is merely a simplified representation of some components of a possible processor pipeline layout, and the processor may include many other elements not shown for the sake of simplicity.

[0062] Figure 2 An example is shown of the architecture register set that can be referenced by instructions encoded according to the instruction set architecture (ISA) supported by the processing system 2. Figure 2The physical register file provided in the hardware used to implement these architecture registers is not shown; only which registers are logically available for reference by instructions are shown. The specific mapping from the architecture registers logically referenced by instructions to the physical storage device within the physical register file 14 can be implemented in many different ways (e.g., using a one-to-one mapping between architecture registers and physical registers in an ordered processor or a variable mapping between architecture registers and physical registers controlled by register renaming in an out-of-order processor).

[0063] In this example, ISA supports: • General-purpose register group 25, which includes general-purpose scalar registers for specifying scalar operands for scalar processing operations; • Vector register group 26, which includes vector registers for specifying vector operands for vector processing operations, matrix operations, or other SIMD operations; • Assertion register group 27, which includes assertion registers for specifying assertion values ​​used for assertion vectors, matrices, or other SIMD operations; and • A set of control registers 40, which stores control values ​​for controlling the operation of the processing device 2. The information stored in the control registers can be automatically set in response to certain events, or can be programmable based on the execution of system register update instructions.

[0064] In this example, the ISA supported by processing device 2 is a scalable vector ISA (also known as a "vector length-agnostic" vector ISA) that supports operations on vectors of scalable vector lengths so that the same instruction sequence can be executed on devices with hardware that supports different maximum vector lengths. This allows different hardware designers implementing the processor to choose different maximum vector lengths based on their design priorities, such as high performance or reduced circuit area and power consumption, without requiring software developers to tailor their software to a specific hardware platform. Software written according to a scalable vector ISA can execute across any hardware platform that supports a scalable vector ISA, regardless of the specific maximum vector length supported by a particular hardware platform. Therefore, the vector length (and thus the assertion length of the corresponding assertion register 27) used for access by a specific vector instruction of the scalable vector ISA is unknown at compile time (neither defined as fixed in the ISA itself nor specified by parameters in the software itself). The operations performed in response to a given vector instruction of a scalable vector ISA can vary depending on the vector length chosen for a particular hardware implementation (e.g., hardware supporting a larger maximum vector length can process more vector elements for a given vector instruction compared to hardware supporting a smaller maximum vector length). Therefore, an implementation with a shorter vector length may require a larger number of loop iterations to implement a particular function compared to an implementation with a longer vector length.

[0065] The vector length agnostic property of scalable vector ISAs is useful because, within a fixed coding space of instructions available for encoding the ISA, it is impractical to create different instructions for every different vector length that processor designers might need, when considering a wide range of requirements scaling from relatively small, energy-efficient microcontrollers to servers and other high-performance computing systems. Since there is no known fixed vector length at compile time, the same ISA can be used to address multiple markets without the effort required by software developers to customize code for each performance / power / area point.

[0066] To achieve the scalable nature of a scalable vector ISA, the functionality of the vector instructions in the scalable vector ISA is referenced in the architecture to parameters indicating the vector length in use (when considering the maximum vector length supported in the hardware and any software-defined limitations using control register 40) (e.g., ...). Figure 2The VL 43 or SVL 42 shown below (described in more detail below) are used to define the vectors, where the parameter VL or SVL is unknown at compile time. Therefore, executing the same vector instruction on different systems can produce different results (typically varying depending on the number of vector elements generated; a subset of these vector elements may have the same result value on different platforms, but generally, platforms implementing larger vector lengths generate additional vector elements compared to platforms implementing smaller vector lengths). The assertion values ​​defined in assertion register 27 can be used to control which elements are generated in a given instance of an instruction and can be set based on the principle of unknown vector length, such as by automatically generating assertion values ​​for a specific loop iteration using comparison instructions or by applying a generally defined assertion pattern that can scale to different vector lengths. Some instructions can update loop control parameters (such as element count values) to track how many vector elements have been processed so far, such that implementations with wider and narrower vector lengths can ultimately achieve the same result but with different performance levels over all iterations of the loop as a whole, because implementations with wider vector lengths require fewer loop iterations than implementations with narrower vector lengths.

[0067] This particular example of the ISA also supports two different modes for performing vector operations: non-streaming operation mode and streaming operation mode. Mode indication status information 41, stored in control register 40, indicates whether the current mode is non-streaming or streaming, and can be set in response to the execution of a mode change instruction. Scalar operations using general-purpose register 25 can be processed in the same way regardless of whether the current mode is non-streaming or streaming, but operations using vector register 26 and assertion register 27 can be processed differently depending on whether the current mode is streaming or non-streaming.

[0068] In non-streaming mode, vector register 26 is architecturally specified to have a vector register length VL identified by the non-streaming vector length specification value 43 specified in control register 40, and assertion register 27 is architecturally specified to have a register length VL / X, where X is a constant corresponding to the minimum supported vector element size (e.g., for a specific implementation where the minimum vector element size is 8 bits, X may be equal to 8). In streaming mode, vector register 26 is architecturally specified to have a streaming mode vector length SVL identified by the streaming vector length specification value 42 specified in control register 40 (streaming vector length specification value 42 is separate from non-streaming vector length specification value 43), and assertion register 27 is architecturally specified to have a register length SVL / X. Therefore, when there is a mode change between streaming and non-streaming modes, both vector register 26 and assertion register 27 can be logically considered as changing their register lengths.

[0069] The non-streaming vector length specification 43 and the streaming mode vector length specification 42 can be implemented in different ways. In some examples, these vector length specifications 43, 42 may simply be fragments of hardwired state information that are not programmable by software, and may only indicate the maximum register length supported by the hardware for each mode. This can then be read by software to identify a specific vector length implemented on the hardware executing the program, allowing the same software to execute on different hardware with different vector lengths.

[0070] In other examples, the ISA may support higher-privileged software capable of limiting the maximum vector length that can be used by software executing in a lower-privileged state. For example, to save power, a given software segment may be limited so that it cannot utilize the full vector length supported in the hardware. Therefore, vector length specifications 43, 42 may include information that can be set by the software to specify the vector length to be used in each mode. However, even if the higher-privileged software imposes a limit on the vector length, the vector length used by the application software remains unknown at compile time because it will not be known whether the actual vector length implemented in a particular processor will be greater than or less than the limit defined in length specifications 43, 42. For a specific implementation with hardware that supports a maximum vector length smaller than the limit defined in length specifications 43, 42, a smaller vector length than indicated by the limit will actually be used. For example, the effective vector length seen by the software may correspond to the minimum of the maximum vector length supported in the hardware for the current mode and the vector length limit set by the software. The vector length specifications 43 and 42 can be grouped by exception level, allowing different limits to the maximum supported vector length to be specified for software executing at different exception levels (e.g., allowing software at one exception level to use a longer vector length than software at another exception level).

[0071] Therefore, the control status information stored in control register 40 can affect the vector length used for vector operations in various ways, but generally, some status information that enables the software to determine the effective vector length for each mode is available. Thus, a given vector length is defined for the vector associated with a given vector instruction to be executed.

[0072] Supporting both non-streaming and streaming modes can be useful because it provides hardware microarchitecture designers with greater flexibility to support, for example, Figure 3 and Figure 4 The different hardware implementations shown are illustrated. Figure 3 In the example, vector instructions are executed by the processing circuitry 16 of the main processor 2, without any operations being offloaded to the coprocessor. On the other hand, in Figure 4In the example, a coprocessor 50 is provided for performing a specific subset of vector operations using vector register 26 and assertion register 27. Coprocessor 50 may include coprocessor decoding circuitry 52 and coprocessor publishing circuitry 54. The coprocessor decoding circuitry decodes instructions published to coprocessor 50 by publishing circuitry 12 of main processor 2. The coprocessor publishing circuitry receives decoded micro-operations from coprocessor decoding circuitry 52 and determines when operands for those instructions will be available, and publishes the micro-operations to coprocessor processing circuitry 56 when operands are available. Coprocessor 50 may have its own register storage 58 separate from register storage 14 and main processor 2. Coprocessor 50 may have access to a shared memory system shared with main processor 2 and therefore may execute vector load / store instructions to load data from memory / store data to memory (e.g., coprocessor 50 may have access to one or more of the main processor's data caches 30, 32 and may also have access to main memory 34). The coprocessor processing circuit 56 refers to operands stored in the coprocessor register storage device 58 and data accessed from the memory system to perform load / store and computation operations represented by instructions unloaded from the main processor 2 to the coprocessor 50.

[0073] The architecturally defined streaming processing modes and the separate vector lengths for the corresponding mode indicator values ​​42, 43 simplify the hardware's determination of when instructions requiring vector registers should be offloaded to the coprocessor 50 or executed within the local execution unit 16 of the main processor 2. It also allows software to explicitly specify whether a particular workload is better suited to be executed on the general-purpose execution unit 16 of the processor 2 or on the more customized hardware of the coprocessor 50. This can be useful because for vector processing routines that require smaller vectors and / or workloads where vector operations are scattered with scalar operations, processing vector operations on the general-purpose execution unit 16 local to the processor 2 itself may be more appropriate, while the coprocessor 50 may be better suited to handle "streaming" workloads that require high throughput of vector operations on large datasets with relatively less need for intermediate scalar operations (e.g., workloads associated with machine learning applications such as neural network processing).

[0074] For such streaming workloads, longer vector lengths can be used to reduce the instruction fetch / decode overhead associated with processing a given number of vector elements. Therefore, although the ISA does not require it (the vector length for non-streaming mode can be chosen from a specific set of supported vector lengths, and the streaming mode vector length can be chosen from a second set of supported vector lengths, where there is no fixed relationship between the lengths chosen for non-streaming and streaming modes), in specific implementations of the coprocessor 50 chosen to support streaming vector modes, it is relatively likely that the streaming mode vector length can be greater than the non-streaming mode vector length, in some cases many times larger. As an example only (other lengths may also be used), an implementation may choose a maximum vector length of 128 bits in non-streaming mode and 512 bits in streaming mode, where the assertion register thus has an architectural vector length of 16 bits in non-streaming mode and 64 bits in streaming mode.

[0075] In use Figure 4 In the example of coprocessor 50 shown, coprocessor 50 may be on the same chip (integrated circuit) as main processor 2, or on a separate chip. For example, main processor 2 and coprocessor 50 may be implemented as separate chiplets on an interposer layer, each chiplet being manufactured as a separate component and then assembled on the interposer layer.

[0076] Therefore, when considering the instruction decoding circuit, the issuing circuit, and the processing circuit for implementing the narrowed vector storage instructions mentioned in this application, several different specific implementations are possible, including: • First example, in which the instruction decoding circuit 10, the issuing circuit 12, and the processing circuit 16 are all as follows: Figure 3 The setup shown is located within processor 2. • In the second example, the instruction decoding circuit 10 and the issuing circuit 12 are located in the main processor 2, but the processing circuitry executing the narrowed vector memory instructions is (at least in some operating modes such as the streaming mode described above) the coprocessor processing circuitry 56 in the coprocessor 50, which may be either on the same integrated circuit as the main processor 2 or an off-chip processing circuitry 56 on a separate integrated circuit from the main processor 2. In other operating modes (e.g., non-streaming modes), the processing circuitry executing the narrowed vector memory instructions may be the main processor 2 processing circuitry 16 as in the first example. •like Figure 4In the third example shown, the responsibility for decoding the narrowed vector storage instructions into one or more micro-operations rests with the coprocessor decoding circuit 52, and therefore the means for processing the narrowed vector storage instructions can be considered the coprocessor 50, which may or may not be on the same chip as the main processor 2. In this case, the instruction decoding circuit, the issuing circuit, and the processing circuit can be the coprocessor decoding circuit 52, the coprocessor issuing circuit 54, and the coprocessor processing circuit 56, respectively.

[0077] Since it is possible that the processing circuitry that actually performs the operations for narrow vector storage instructions can be on a different chip than the instruction decoding circuitry 10, 52 and the issuing circuitry 12, 54 that decode and issue narrow vector storage instructions, the processing circuitry 16, 56 itself does not need to be in the same device as the instruction decoding circuitry 10, 52 and the issuing circuitry 12, 54.

[0078] Although Figure 2 The examples discussed scalable vector ISAs, but the narrowing vector storage instructions described in this patent application can also be applied to non-scalable vector ISAs for which the vector length is known at compile time (either fixed in the architecture or variable based on software-specified parameters). Furthermore, while scalable vector ISAs supporting separate non-streaming and streaming modes have been described above, narrowing vector storage instructions can also be provided in scalable vector ISAs that do not support streaming modes, such that mode indicator 41 and streaming vector length parameter 42 are not provided, and the given vector length to be used for the vector instructions is defined by VL parameter 43.

[0079] Figure 5 Examples of both non-interleaved and interleaved variants of the narrow vector storage instruction are shown.

[0080] When handling certain workloads, such as image processing workloads, storing data elements in memory with small data element sizes may be relatively common. However, when the data is loaded from memory into registers, it may be relatively common to padded the data to process it as a wider data type library. For example, 8 bits of pixel data stored in memory can be widened to 16 bits per data element to allow for processing with higher precision. After processing, the data can then be stored back into memory in a narrower data type, and thus can be narrowed before being stored into memory. However, existing vector architectures can be inefficient when handling this type of operation.

[0081] One approach is to use a narrowing store instruction that specifies a single vector source operand. This instruction narrows the elements of the source registers and stores them in a contiguous region of memory. However, this method does not allow interleaving the elements of the source vector registers with elements of other source registers. Interleaving may be necessary in some workloads where narrowing store can be used, such as image processing, to store data from different channels (which can be loaded into different registers for individual processing) in interleaved channels of data elements located for each pixel (e.g., separate R, G, B, and A channels can be stored in memory as RGBARGBA…). Additionally, a narrowing store instruction that specifies a single vector source operand stores data values ​​smaller than the full vector length in memory. The single vector source operand will be up to the size of the vector length, so after narrowing, the amount stored in memory will be less than the vector length. A store operation may be able to handle data of at least the vector length, and therefore by storing data smaller than the vector length, the available capacity of the store operation may be unused (and the number of elements processed per store instruction may be reduced, thus requiring additional instances of store instructions to process a given number of elements, thereby increasing the load / store unit and memory translation overhead when processing that number of elements).

[0082] To allow interleaving and storing full-vector-length data in memory, an alternative approach could be to use a zip instruction, which fetches data from two or more source registers, narrows and combines the data elements from the two or more source registers, and stores the result in a schema destination register. This could be followed by a store instruction to fetch the narrowed and combined elements from the schema destination register and store the result in a memory location. However, the problem with this approach is that the schema register is assigned as the destination of the zip instruction, which increases register pressure because it means the software will run out of spare schema vector register identifiers available to identify new variables more quickly. This can degrade performance due to increased memory operations causing variables to overflow into memory that cannot fit within the schema register space. Another problem with this approach is that it can be broken down into a larger number of micro-operations than could be used in different approaches. Specifically, the store instruction could be broken down into two micro-operations, where the first micro-operation (“STDATA”) retrieves data from the schema source register (which is the destination register of the zip instruction) and the second micro-operation (“STADDRESS”) stores the retrieved data in memory. However, in the approach using narrowed vector storage instructions discussed below, the first micro-operation of these micro-operations can be avoided because the narrowed and combined data elements are not stored in the architecture register during the intermediate stage of the operation.

[0083] These problems can be addressed by providing a narrow vector store instruction as a supported instruction in the instruction set architecture. This narrow vector store instruction specifies at least one address operand for defining the target memory address of the store operation and specifies multiple vector source registers 26. The instruction can also specify assertion information, for example, using an assertion register 27. The function of this instruction is to cause the processing circuits 16, 56 to narrow the data elements of the multiple specified vector source registers from a second data element size to a first data element size, and to store a vector of narrowed data elements of the first data element size from the multiple vector source registers into memory at the location corresponding to the target memory address.

[0084] Therefore, in Figure 5 In the example, the instruction specifies two vector source registers Z1 and Z2, and is used to store a vector with narrowed data elements of a first data element size (e.g., 8 bits) from the elements of the two source registers Z1 and Z2, which have a second data element size (e.g., 16 bits), into memory. Each source register has a given vector length VL, SVL currently used for the vector processing operation.

[0085] For example, narrow vector storage instructions can specify various operands, such as:

[0086] ST1B { <z1> .H, <z2> .H}, <p0>[X17, X16]

[0087] Of course, the instruction encoding seen by the instruction decoding circuits 10 and 52 will include binary values ​​encoded to represent the corresponding information. Here, ST1B indicates the type of instruction and may correspond to an opcode encoded in binary. Register identifiers Z1 and Z2 identify two vector source registers. In some examples, these may all be explicitly identified in the instruction encoding, or alternatively, the instruction may be constrained to select a set of vector registers with adjacent register identifiers as source registers, and only one of these register identifiers may be explicitly encoded in the instruction encoding, while the other register identifiers are implicitly located at some offset relative to the encoded register identifier. The symbol .H indicates that the second data element size to be used for the unnarrowed data element is a "half-word" size (16 bits) (opposite to byte size .B (8 bits) or full word size .W (32 bits)). In this example, implicitly, the first data element size of the narrowed data element to be stored in memory is 8 bits, but other examples may include operands used to identify the size of the first data element. The assertion register identifier P0 identifies the assertion register that provides the assertion value. Register identifiers X17 and X16 represent address operands used to identify the target memory address (e.g., X17 could identify the base register and X16 could identify the register used to specify the offset to be added to the value stored in the base register to generate the target address). It will be understood that this is only one example of addressing modes and any other addressing mode can be used (e.g., other examples could use an immediate value, a program counter value, and / or a stack pointer value as one of the address operands).

[0088] Therefore, when an instruction is decoded by instruction decoding circuits 10 and 52, the instruction decoding circuits 10 and 52 generate at least one micro-operation. This micro-operation, when issued by issuing circuits 12 and 54, causes processing circuits 16 and 56 to narrow the data elements of multiple vector source registers from a second size to a first size, and stores the vector of the narrowed data elements at a location in memory. Narrowing can be performed by taking a portion of the least significant bit of each data element, which has a size equal to the size of the narrowed data element. For example, as... Figure 5 As illustrated, element A1 can be narrowed down to element A1', which includes the lowest order bit of A1 (e.g., it is expected that the higher order bits of A1 are zero).

[0089] Both interleaved and non-interleaved variants are possible. With the interleaved variant, the vector of narrowed data elements stored in memory can include interleaved elements taken sequentially from each vector source register, e.g., A1B1A2B2… This can be particularly useful in examples involving processing data in channels. For example, in image processing data, individual pixels can be represented together by R, G, and B values ​​stored in memory as RGBRGB, etc. Individual channels can be deinterleaved at load time so they can be processed as separate channels, but can then be interleaved again at store time. Therefore, variants of narrowed vector store instructions that interleave elements from multiple vector source registers can be particularly useful. In the non-interleaved variant, the vector of narrowed data elements stored in memory can include consecutive portions from each vector source register without interpolating elements from another vector source register, e.g., A1A2A3A4B1B2B3B4. This variant can be useful in workloads where the contents of each vector source register are processed separately, both in memory and in the register.

[0090] Although Figure 5 An example of a dual-source register instruction is shown, but it will be understood that other variants can store data from a different number of vector source registers (e.g., a three-register variant could be provided for handling RGB interleaved data, or a four-register variant could be provided for handling RGBA data).

[0091] Additionally, variants can be provided to support different element sizes for the first and second data element sizes, possibly with different ratios between the second and first data element sizes (e.g., 4x narrowing instead of 2x narrowing). 16-bit to 8-bit narrowing is just one example, and other examples can vary the data element size based on programmable parameters referenced by the instruction (either in the instruction code itself, in the control register, or a combination of both). Using specific combinations of vector source register numbers and narrowing, operations can store data values ​​of more than one vector length into memory. Therefore, a narrowed vector store instruction can generate more than one vector of narrowed data elements. For example, narrowing 4 vector source registers by 2x would mean storing two vectors of narrowed data elements into memory.

[0092] Using this type of instruction offers several advantages. It can mean that fewer micro-operations can be issued to the processing circuitry. Specifically, because no schema register is used as the destination for the narrowing operation, the micro-operation for storing the narrowed element into memory can directly consume the result of the narrowing operation, and no micro-operation for retrieving data from a register is required (e.g., the "STDATA" micro-operation is unnecessary). Furthermore, no schema register needs to be specified to store the result of the narrowing operation. Additionally, memory throughput can be increased by storing data of the full vector length into memory compared to examples that store data smaller than the full vector length.

[0093] Figure 6 A non-interleaved variant of the narrowed memory instruction with assertions applied is shown. Two assertion values ​​Pg are illustrated, which can be provided in the register specified by the narrowed vector memory instruction (or, at least in the case of a counter, specified in the encoding of the narrowed vector memory instruction). The assertion values ​​control the assertion at the granularity of the narrowed data element in memory. Figure 6 As shown, if the elements of a vector of narrowed data elements to be stored in memory are indicated as masked by an assertion (e.g., if the corresponding element of the assertion is in...), Figure 6 If the element has a value of "0" or is located at an element with an index higher than the assertion counter value, then the storage operation may prevent that element from being stored in memory. For example, in Figure 6 In the vector of narrowed data elements, elements 0-8 are not masked and elements 9-15 are masked, so only the values ​​of elements 0-8 are stored in memory.

[0094] What we will see is that assertions operate at the granularity of data elements in memory. For example, an assertion mask could have elements provided in a one-to-one relationship with the elements in a vector of narrowed data elements, or each increment of an assertion counter could correspond to a narrowed data element and the assertion counter could have a maximum value corresponding to the number of narrowed data elements. If the store instruction is non-narrowing such that the source vector register has the same number of elements as the vector stored in memory, this would mean that the assertion register could only be used for assertions of one source vector register. However, because the narrowing vector store instruction reduces the size of the elements in the vector source registers, meaning that there are fewer data elements in each source vector register compared to the vector of narrowed data elements, then the assertion value could then be used for assertions of two or more vector source registers. Figure 6 Specifically, it shows how the assertion mask Pg can be used for assertions from elements of both vector source registers Z1 and Z2.

[0095] although Figure 6 An example of an assertion for a non-interleaved variant is illustrated, but it will be understood that assertions can also be applied to interleaved variants of narrowed vector store instructions. However, in the interleaved variant, assertion values ​​can be controlled at the granularity of groups of elements rather than the granularity of narrowed data elements. Each group of elements comprises a contiguous block of narrowed data elements in a memory-based structure, and each group of elements comprises a single data element from each channel in the channel. If a given group of elements is indicated to be masked by an assertion, the narrowed data element corresponding to that group is not stored in memory as part of the store operation. For example, in Figure 5 In the array, the element group may include elements A1'B1', and a single bit of the assertion mask can be controlled in response to a narrow vector storage instruction to control whether both elements are stored in memory or no elements are stored in memory.

[0096] Figure 7 A method for performing data processing is illustrated. At step 100, instruction decoding circuits 10 and 52 decode instructions encoded according to a given instruction set architecture. At step 102, in response to the decoding of the instructions by instruction decoding circuits 10 and 52, issuing circuits 12 and 54 issue at least one micro-operation corresponding to the instruction. At step 104, processing circuits 16 and 56 perform a corresponding processing operation in response to at least one micro-operation.

[0097] Figure 8 An example is illustrated of the steps performed at step 104 when the instruction decoded at step 100 is a narrowed vector store instruction. At step 110, processing circuits 16 and 56 narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size. At step 112, processing circuits 16 and 56 store a vector containing the narrowed data elements narrowed at step 110 into memory at a location corresponding to the target memory address calculated based on at least one address operand of the narrowed vector store instruction.

[0098] Figure 9 The steps performed at step 104 are illustrated for the processing operation executed when the instruction decoded at step 100 is an interleaved variant of a narrowed vector store instruction. At step 120, processing circuits 16 and 56 narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size. At step 122, processing circuits 16 and 56 interleave the narrowed data elements from the plurality of vector source registers in a vector of narrowed data elements. The vector of narrowed data elements thus includes multiple interleaving channels, each corresponding to one of the vector source registers. At step 124, the processing circuits store the interleaved vector of narrowed data elements in memory at a location corresponding to the target memory address calculated based on at least one address operand of the narrowed vector store instruction. An assertion can be applied at step 124 such that a subset of the elements of the vector of narrowed data elements is not stored in memory. The assertion value applied at step 124 can be applied at the granularity of a group of elements, which includes elements at the same location in each of the multiple vector source registers, provided in a continuous portion of the vector of narrowed data elements.

[0099] Figure 10 The steps performed at step 104 are illustrated for the processing operation executed when the instruction decoded at step 100 is a non-interleaved variant of a narrowed vector store instruction. At step 130, processing circuits 16, 56 narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size. At step 132, processing circuits 16, 56 provide at least one vector of narrowed data elements, wherein the narrowed data element corresponding to a given source vector register in the source vector registers is provided in a continuous portion of the vector of narrowed data elements without interpolating narrowed data elements corresponding to any other source vector register in the plurality of source vector registers. Thus, each element can be taken from the first vector source register, then each element from the second vector source register, and so on. At step 134, the processing circuits store the vector of narrowed data elements in memory at a location corresponding to the target memory address calculated based on at least one address operand of the narrowed vector store instruction. An assertion can be applied at step 134 such that a subset of the elements of the vector of narrowed data elements is not stored in memory. The assertion value used for the control assertion at step 134 can correspond to more than one of the multiple vector source registers.

[0100] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0101] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0102] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0103] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0104] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transient computer-readable medium such as semiconductors, disks, or optical discs. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0105] Figure 11 Examples of emulator implementations that can be used are illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as emulators, in part because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the emulator implementation can run on a host processor 330 having host storage circuitry 332 (e.g., registers and / or memory), optionally running a host operating system 320, thereby supporting the emulator program 310. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide emulator implementations that executed at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation can provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with different hardware architectures. An overview of simulation is given in the following literature: "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0106] With respect to embodiments previously described with reference to specific hardware constructions or features, equivalent functionality may be provided in simulated embodiments by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware (such as registers or caches) may be implemented as software data structures stored in host storage devices (e.g., memory or registers) of host processor 330 in simulated embodiments. Where one or more of the hardware elements referenced in the previously described embodiments are present in the arrangement on the host hardware (e.g., host processor 330), some simulated embodiments may utilize the host hardware where appropriate.

[0107] The simulator program 310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 300 (which may include an application program, an operating system, and a management program), the same as the interface of the hardware architecture modeled by the simulator program 310. Therefore, the simulator program 310 can be used to execute the program instructions of the target code 300 from within the instruction execution environment, enabling a host computer 330, which does not actually possess the hardware features of the device 2 discussed above (e.g., the instruction decoder 10 and processing circuitry 16 supporting narrowed vector storage instructions as discussed above), to emulate these features.

[0108] Therefore, the simulator program 310 may have instruction decoding program logic 312 for decoding the instructions of the target code 300 and mapping them to corresponding instruction sets in the native instruction set of the host device 330, which are provided as part of the simulator program's processing program logic 313. The instruction decoding program logic 312 includes decoding program logic 313 for decoding narrowed vector memory instructions as described above. Register emulation program logic 314 maps register accesses requested by the instructions of the target code to accesses to corresponding data structures maintained in the host memory circuitry 332 of the host device 330, such as by accessing data in the registers or memory of the host device 330. Memory management program logic 316 implements address translation, page table traversal, and access permission checks in a manner corresponding to the MMU 36 described in the hardware implementation above, to simulate accesses to the simulated address space by the target code 300. Memory address space emulation program logic 318 is provided to map simulated physical addresses, obtained by memory management program logic 316 based on address translation using page table information maintained by the software of target program code 300, to host virtual addresses for accessing host memory of host processor 330. These host virtual addresses themselves can be translated into host physical addresses using standard address translation mechanisms supported by the host (the translation from host virtual address to host physical address is outside the scope controlled by emulator program 310).

[0109] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" refers to the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0110] In this application, a list of features beginning with the phrase "at least one of" means that any one or more of those features may be provided independently or in combination. For example, "at least one of [A], [B], and [C]" covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0111] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims. < / z2> < / z1>

Claims

1. An apparatus, the apparatus comprising: An instruction decoding circuit, wherein the instruction decoding circuit is used to decode instructions; and A publishing circuit, configured to, in response to the decoding of a given instruction by the instruction decoding circuit, publish at least one micro-operation to control the processing circuit to perform a processing operation corresponding to the given instruction; wherein: In response to the decoding of a narrowed vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand with a given vector length, the instruction decoding circuit is configured to control the issuing circuit to issue at least one micro-operation to control the processing circuit: The data elements of the plurality of vector source registers are narrowed from the second data element size to the first data element size, where the first data element size is smaller than the second data element size; and At least one vector, comprising a narrowed data element narrowed to the size of the first data element and including the plurality of vector source registers, is stored in a location in the memory system corresponding to a target memory address determined based on the at least one address operand.

2. The apparatus according to claim 1, wherein the at least one micro-operation includes a first micro-operation and a second micro-operation; The first micro-operation is used to control the processing circuit to form at least one vector of narrowed data elements, and the second micro-operation is used to control the processing circuit to consume at least one vector of narrowed data elements formed by the first micro-operation and store at least one vector of consumed narrowed data elements in the location of the memory system.

3. The apparatus of claim 2, wherein the second micro-operation is used to control the processing circuitry to determine the location in the memory system based on the at least one address operand.

4. The apparatus according to any of the preceding claims, wherein the encoding of the narrowing vector storage instruction allows the size of the at least one vector of the narrowing element to be equal to the given vector length.

5. The apparatus according to any preceding claim, wherein, in response to a non-interleaved variant of the narrowed vector storage instruction, the instruction decoding circuit is configured to control the publishing circuit to publish the at least one micro-operation to control the processing circuit to store the at least one vector of the narrowed data element into the location in the memory, wherein the narrowed data element corresponding to a given source vector register among the plurality of source vector registers is provided in a consecutive portion of the at least one vector of the narrowed data element, without interpolating narrowed data elements corresponding to any other source vector register among the plurality of source vector registers.

6. The apparatus of claim 5, wherein the non-interleaved variant of the narrowed vector storage instruction specifies at least one assertion register, each assertion register specifying element assertion information, the element assertion information indicating which data elements of the plurality of vector source registers are masked data elements, and the corresponding portion of the at least one vector of the narrowed data element for the masked data elements is used to specify a value independent of the masked data element. The given assertion register specifies element assertion information corresponding to two or more of the plurality of vector source registers.

7. The apparatus according to any of the preceding claims, wherein in response to the narrowing vector storage instruction specifying N vector source registers, the instruction decoding circuit is configured to control the publishing circuit to publish the at least one micro-operation to control the processing circuit to narrow the data element to a size no greater than 1 / N times the size of the second data element of the first data element.

8. The apparatus according to any of the preceding claims, wherein, In response to an interleaved variant of the narrowed vector storage instruction, the instruction decoding circuit is configured to control the publishing circuit to publish the at least one micro-operation to control the processing circuit to store at least one interleaved vector of narrowed data elements comprising multiple interleaved channels of narrowed data elements into the memory system, each interleaved channel corresponding to one of the source vector registers.

9. The apparatus of claim 8, wherein the interleaving pattern for interleaving the data elements of the plurality of source vector registers in the at least one vector of narrowed data elements is implicitly defined by encoding the interleaving variant of the narrowed storage instruction.

10. The apparatus according to any one of claims 8 and 9, wherein the plurality of vector source registers comprises at least three vector source registers.

11. The apparatus according to any preceding claim, wherein the processing circuitry is configured to narrow the given data element by selecting a portion of the lowest order bit of the given data element as the narrowed data element, the portion having a size equal to the size of the first data element.

12. The apparatus according to any of the preceding claims, wherein the first data element size and the second data element size are variable depending on control parameters associated with the narrowed vector storage instruction.

13. The apparatus according to any of the preceding claims, wherein the first size is not greater than half the second size.

14. The apparatus according to any of the preceding claims, the apparatus comprising a vector length storage device circuit for storing a vector length parameter indicating the given vector length.

15. The apparatus according to any of the preceding claims, wherein the apparatus includes the processing circuit.

16. The apparatus according to any of the preceding claims, wherein, For at least a subset of instruction types, the publishing circuit is configured to publish the at least one micro-operation to off-chip processing circuitry on an integrated circuit separate from the publishing circuit.

17. The apparatus according to any one of claims 1 to 15, the apparatus comprising a coprocessor configured to perform processing operations on a subset of instruction types unloaded by a main processor, the coprocessor including the instruction decoding circuitry for decoding instructions of the subset of instruction types and the dispatch circuitry.

18. A computer-readable code for manufacturing an apparatus, the apparatus comprising: An instruction decoding circuit, wherein the instruction decoding circuit is used to decode instructions; and A publishing circuit, configured to, in response to the decoding of a given instruction by the instruction decoding circuit, publish at least one micro-operation to control the processing circuit to perform a processing operation corresponding to the given instruction; wherein: In response to the decoding of a narrowed vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand with a given vector length, the instruction decoding circuit is configured to control the issuing circuit to issue at least one micro-operation to control the processing circuit: The data elements of the plurality of vector source registers are narrowed from the second data element size to the first data element size, where the first data element size is smaller than the second data element size; and At least one vector, comprising a narrowed data element narrowed to the size of the first data element and including the plurality of vector source registers, is stored in a location in the memory system corresponding to a target memory address determined based on the at least one address operand.

19. A method comprising: Decode the instructions; as well as In response to the decoding of a given instruction, at least one micro-operation is issued to control the processing circuitry to perform a processing operation corresponding to the given instruction; wherein: In response to the decoding of a narrow vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand with a given vector length, at least one micro-operation is issued to control the processing circuitry: Narrowing the data elements of the plurality of vector source registers from a second data element size to a first data element size, wherein the first data element size is smaller than the second data element size; and At least one vector, comprising a narrowed data element narrowed to the size of the first data element and including the plurality of vector source registers, is stored in a location in the memory system corresponding to a target memory address determined based on the at least one address operand.

20. A computer program for controlling a host data processing device to provide an instruction execution environment for executing target program code, the computer program comprising: Instruction decoding program logic, which is used to decode the instructions of the target program code; and Processing logic, the processing logic being used to perform processing operations corresponding to a given instruction decoded by the instruction decoding logic; wherein: In response to the decoding of a narrowed vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand with a given vector length, the instruction decoding program logic is configured to control the release program logic to release at least one micro-operation to control the processing program logic: The data elements of the plurality of vector source registers are narrowed from the second data element size to the first data element size, where the first data element size is smaller than the second data element size; and At least one vector, including the plurality of vector source registers, narrowed to the size of the first data element, is stored at a location in a simulated address space, the location in the simulated address space corresponding to a target memory address determined based on the at least one address operand.

21. A storage medium storing computer-readable code as claimed in claim 18 or a computer program as claimed in claim 20.

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