Pixel circuit, pixel driving method and display device

Abstract

The invention discloses a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a driving circuit (10), a first storage circuit (11), a second storage circuit (12) and an initialization circuit (20), the first end of the first storage circuit (11) is electrically connected with the first node (N1), and the second end of the first storage circuit (11) is electrically connected with the first voltage end (VZ); the first end of the second storage circuit (12) is electrically connected with the first node (N1), and the second end of the second storage circuit (12) is electrically connected with the writing node (A); under the control of a first scanning signal and a second scanning signal, the initialization circuit (20) simultaneously starts resetting the potential of a first node (N1) and the potential of a write node (A) through a first reset voltage and simultaneously stops resetting the potential of the first node (N1) and the potential of the write node (A). And the influence of reset voltage jump on a driving transistor (DT) in the driving circuit (10) is avoided.

Description

Pixel circuits, pixel driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] When the relevant pixel circuit is working, there will be a reset voltage jump, which in turn affects the driving transistor in the driving circuit through the storage capacitor.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a first storage circuit, a second storage circuit, and an initialization circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0006] The first end of the first storage circuit is electrically connected to the first node, and the second end of the first storage circuit is electrically connected to the first voltage terminal.

[0007] The first end of the second storage circuit is electrically connected to the first node, and the second end of the second storage circuit is electrically connected to the write node;

[0008] The initialization circuit is electrically connected to the first scan terminal, the second scan terminal, the first reset voltage terminal, the first node, and the write node, respectively. Under the control of the first scan signal provided by the first scan terminal and the second scan signal provided by the second scan terminal, it simultaneously begins to reset the potentials of the first node and the write node using the first reset voltage provided by the first reset voltage terminal, and simultaneously stops resetting the potentials of the first node and the write node. Optionally, the initialization circuit includes a first reset circuit and an on / off control circuit.

[0009] The first reset circuit is electrically connected to the first scan terminal, the first reset voltage terminal and the first node respectively, and is used to write the first reset voltage into the first node during the initialization phase under the control of the first scan signal.

[0010] The on / off control circuit is electrically connected to the second scanning end, the writing node, and the first node, respectively, and is used to control the connection between the writing node and the first node during the initialization phase and the light emission phase under the control of the second scanning signal, and to control the disconnection between the writing node and the first node during the data writing phase and the compensation phase.

[0011] Optionally, the first storage circuit includes a first capacitor, and the second storage circuit includes a second capacitor;

[0012] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.

[0013] The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the write node;

[0014] The capacitance value of the first capacitor is greater than or equal to the capacitance value of the second capacitor.

[0015] Optionally, the ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is greater than or equal to 1.5.

[0016] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a compensation control circuit;

[0017] The compensation control circuit is electrically connected to the third scanning end, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node during the compensation stage under the control of the third scanning signal provided by the third scanning end.

[0018] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element and a first light-emitting control circuit;

[0019] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first pole of the light-emitting element, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the third node and the first pole of the light-emitting element during the light-emitting stage, and controls the disconnection between the third node and the first pole of the light-emitting element during the initialization stage, the compensation stage, and the data writing stage.

[0020] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0021] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit;

[0022] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the third node and the first electrode of the light-emitting element during the compensation and light-emitting phases, and controls the disconnection between the third node and the first electrode of the light-emitting element during the initialization and data writing phases. The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0023] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the power supply voltage terminal and the second node during the compensation phase and the light-emitting phase, and controls the disconnection between the power supply voltage terminal and the second node during the initialization phase and the data writing phase.

[0024] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element and a second light-emitting control circuit;

[0025] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the power supply voltage terminal and the second node during the compensation phase and the light-emitting phase, and controls the disconnection between the power supply voltage terminal and the second node during the initialization phase and the data writing phase.

[0026] The third node is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0027] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit and a second reset circuit;

[0028] The data writing circuit is electrically connected to the fourth scanning end, the data line and the writing node respectively, and is used to write the data voltage provided by the data line to the writing node during the data writing stage under the control of the fourth scanning signal provided by the fourth scanning end.

[0029] The second reset circuit is electrically connected to the fifth scanning terminal, the second reset voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second reset voltage provided by the second reset voltage terminal into the first electrode of the light-emitting element during the initialization phase under the control of the fifth scanning signal provided by the fifth scanning terminal.

[0030] Optionally, the driving circuit includes a driving transistor, the first reset circuit includes a first transistor, and the on / off control circuit includes a second transistor;

[0031] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0032] The gate of the first transistor is electrically connected to the first scan terminal, the first terminal of the first transistor is electrically connected to the first reset voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0033] The on / off control circuit includes a second transistor;

[0034] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the write node.

[0035] Optionally, the compensation control circuit includes a third transistor;

[0036] The gate of the third transistor is electrically connected to the third scanning terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node.

[0037] Optionally, the first light-emitting control circuit includes a fifth transistor;

[0038] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0039] Optionally, the first light-emitting control circuit includes a fifth transistor; the second light-emitting control circuit includes a sixth transistor.

[0040] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0041] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second node.

[0042] Optionally, the second light-emitting control circuit includes a sixth transistor;

[0043] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0044] Optionally, the data writing circuit includes a fourth transistor; the second reset circuit includes a seventh transistor;

[0045] The gate of the fourth transistor is electrically connected to the fourth scan terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the write node.

[0046] The gate of the seventh transistor is electrically connected to the fifth scanning terminal, the first terminal of the seventh transistor is electrically connected to the second reset voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element. In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0047] The driving circuit generates a driving current under the control of the potential of the first node;

[0048] The initialization circuit simultaneously begins resetting the potentials of the first node and the write node using the first reset voltage provided by the first reset voltage terminal, and simultaneously stops resetting the potentials of the first node and the write node. Optionally, the initialization circuit includes a first reset circuit and an on / off control circuit; the display cycle of the pixel circuit includes a sequentially set initialization phase, compensation phase, data writing phase, and light emission phase; the pixel driving method includes:

[0049] During the initialization phase, the first reset circuit, under the control of the first scan signal, writes the first reset voltage into the first node;

[0050] During the compensation phase, the data writing phase, and the light emission phase, the first reset circuit, under the control of the first scan signal, controls the first reset voltage terminal to disconnect from the first node.

[0051] During the initialization phase and the light emission phase, the on / off control circuit controls the connection between the writing node and the first node;

[0052] During the compensation phase and the data writing phase, the on / off control circuit controls the writing node to disconnect from the first node.

[0053] Optionally, the pixel circuit further includes a compensation control circuit;

[0054] The pixel driving method further includes:

[0055] During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the third scanning signal;

[0056] At the start of the compensation phase, the drive circuit, under the control of the potential of the first node, controls the connection between the second and third nodes, and the power supply voltage signal charges the first storage circuit until the drive circuit is turned off.

[0057] Optionally, the pixel circuit further includes a second light-emitting control circuit; the pixel driving method further includes:

[0058] During the compensation phase, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node.

[0059] Optionally, the pixel circuit further includes a data writing circuit; the pixel driving method includes:

[0060] During the data writing phase, the data writing circuit writes the data voltage to the writing node under the control of the fourth scan signal.

[0061] Optionally, the pixel driving method described in at least one embodiment of this disclosure further includes:

[0062] Before the data writing phase begins, the data line provides a data voltage.

[0063] Optionally, the pixel circuit further includes a second reset circuit; the pixel driving method further includes:

[0064] During the initialization phase, the second reset circuit, under the control of the fifth scan signal, writes the second reset voltage into the first electrode of the light-emitting element.

[0065] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0066] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] Figure 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] Figure 11A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 10 of this disclosure;

[0077] Figure 11B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 10 of this disclosure;

[0078] Figure 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] Figure 13A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of this disclosure;

[0080] Figure 13B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of this disclosure;

[0081] Figure 14 is a simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of this disclosure;

[0082] Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] Figure 16A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 15 of this disclosure;

[0084] Figure 16B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 15 of this disclosure. Detailed Implementation

[0085] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0086] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0087] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0088] As shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure includes a driving circuit 10, a first storage circuit 11, a second storage circuit 12, and an initialization circuit 20.

[0089] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1.

[0090] The first terminal of the first storage circuit 11 is electrically connected to the first node N1, and the second terminal of the first storage circuit 11 is electrically connected to the first voltage terminal V1.

[0091] The first end of the second storage circuit 12 is electrically connected to the first node N1, and the second end of the second storage circuit 12 is electrically connected to the write node A;

[0092] The initialization circuit 20 is electrically connected to the first scan terminal S1, the second scan terminal S2, the first reset voltage terminal REST, the first node N1, and the write node A, respectively. Under the control of the first scan signal provided by the first scan terminal S1 and the second scan signal provided by the second scan terminal S2, it simultaneously starts to reset the potential of the first node N1 and the potential of the write node A through the first reset voltage Vrest provided by the first reset voltage terminal REST, and simultaneously stops resetting the potential of the first node N1 and the potential of the write node A.

[0093] In at least one embodiment of the pixel circuit shown in Figure 1 of this disclosure, during the initialization phase, the initialization circuit 20 starts to reset the potential of the first node N1 and the potential of the write node A through the first reset voltage Vrest provided by the first reset voltage terminal REST, and simultaneously stops resetting the potential of the first node N1 and the potential of the write node A to avoid the impact of the reset voltage jump on the drive transistor in the drive circuit 10.

[0094] When the pixel circuit described in at least one embodiment of this disclosure is in operation, by setting the ratio of the capacitance value of the first capacitor included in the first storage circuit 11 to the capacitance value of the second capacitor included in the second storage circuit 12, the adjustable range of the data voltage can be magnified by a factor of two, making Gamma adjustment easy and grayscale transitions delicate.

[0095] In the pixel circuit described in at least one embodiment of this disclosure, the second storage circuit is electrically connected to the first node N1 and the write node A respectively. When the potential of the write node A changes, the potential of the first node N1 changes by a volt, and the potential information after the change is stored at the first terminal of the first storage circuit 11.

[0096] In at least one embodiment of this disclosure, the capacitance value of the first capacitor included in the first storage circuit is set to be greater than or equal to the capacitance value of the second capacitor included in the second storage circuit. This allows the second storage circuit to quickly complete the voltage level transition and the first storage circuit to stably maintain a frame of light emission, thus avoiding pixel dark spots caused by leakage of the second capacitor.

[0097] Optionally, the first voltage terminal can be a reference voltage terminal.

[0098] Optionally, the driving circuit includes a driving transistor, the first storage circuit includes a first capacitor, the second storage circuit includes a second capacitor, and the data writing circuit includes a first transistor.

[0099] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0100] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.

[0101] The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the write node;

[0102] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the write node.

[0103] In at least one embodiment of this disclosure, the capacitance value of the first capacitor is greater than or equal to the capacitance value of the second capacitor.

[0104] In at least one embodiment of this disclosure, the ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor may be greater than or equal to 1.5; for example, the ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor may be equal to 2.

[0105] In at least one embodiment of this disclosure, the initialization circuit includes a first reset circuit and an on / off control circuit;

[0106] The first reset circuit is electrically connected to the first scan terminal, the first reset voltage terminal and the first node respectively, and is used to write the first reset voltage into the first node during the initialization phase under the control of the first scan signal.

[0107] The on / off control circuit is electrically connected to the second scanning end, the writing node, and the first node, respectively, and is used to control the connection between the writing node and the first node during the initialization phase and the light emission phase under the control of the second scanning signal, and to control the disconnection between the writing node and the first node during the data writing phase and the compensation phase.

[0108] In a specific implementation, the initialization circuit may include an on / off control circuit. During the light-emitting stage, the on / off control circuit, under the control of the second scan signal, controls the connection between the first node and the writing node to completely eliminate source-direction (the source direction can be the direction extending along the data line) voltage crosstalk.

[0109] The source-to-voltage crosstalk can refer to: a voltage jump in the second storage circuit caused by a data voltage jump on the data line.

[0110] In related technologies, there is a problem of source-to-voltage crosstalk caused by incomplete turn-off of transistors in the data writing circuit. That is, the brightness of a display area is affected by the display brightness of the display area above it and the display brightness of the display area below it. Moreover, compared with large-size OLEDs, silicon-based OLEDs have a faster response speed, so the problem of source-to-voltage crosstalk caused by incomplete turn-off of transistors in the data writing circuit is particularly serious.

[0111] In at least one embodiment of this disclosure, the initialization circuit may include a first reset circuit and an on / off control circuit, and the display cycle may include an initial stage, a compensation stage, a data writing stage and a light-emitting stage set sequentially.

[0112] During the initialization phase, the first reset circuit writes the first reset voltage to the first node, and the on / off control circuit controls the connection between the writing node and the first node so that the first reset circuit is simultaneously written to the first node and the writing node.

[0113] After the initialization phase ends, during the compensation phase, data writing phase, and light emission phase, the first reset circuit controls the first reset voltage terminal to disconnect from the first node, stopping the supply of the first reset voltage to the first node and the writing node.

[0114] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the initialization circuit includes an on / off control circuit 21 and a first reset circuit 22.

[0115] The on / off control circuit 21 is electrically connected to the second scanning terminal S2, the first node N1 and the writing node A respectively, and is used to control the writing node A and the first node N1 to be connected during the initialization stage and the light emission stage under the control of the second scanning signal, and to control the writing node A and the first node N1 to be disconnected during the data writing stage and the compensation stage.

[0116] The first reset circuit 22 is electrically connected to the first scan terminal S1, the first reset voltage terminal REST, and the first node N1, respectively. Under the control of the first scan signal, it writes the first reset voltage to the first node N1 during the initialization phase, and controls the first node N1 to disconnect from the first reset voltage terminal REST during the compensation phase, the data writing phase, and the light emission phase.

[0117] In at least one embodiment of the pixel circuit shown in Figure 2 of this disclosure, during the compensation phase, the on / off control circuit controls the first node N1 to disconnect from the write node A in order to facilitate threshold voltage compensation.

[0118] The pixel circuit described in at least one embodiment of this disclosure further includes a compensation control circuit;

[0119] The compensation control circuit is electrically connected to the third scanning end, the first node, and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the third scanning signal provided by the third scanning end.

[0120] In a specific implementation, the pixel circuit may further include a compensation control circuit. During the compensation phase, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node to perform threshold voltage compensation.

[0121] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a compensation control circuit 23;

[0122] The compensation control circuit 23 is electrically connected to the third scanning terminal S3, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N2 under the control of the third scanning signal provided by the third scanning terminal S3.

[0123] In at least one embodiment of this disclosure, the pixel circuit further includes a light-emitting element and a first light-emitting control circuit;

[0124] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first pole of the light-emitting element, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the third node and the first pole of the light-emitting element during the light-emitting stage, and controls the disconnection between the third node and the first pole of the light-emitting element during the initialization stage, the compensation stage, and the data writing stage.

[0125] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0126] In a specific implementation, the pixel circuit may further include a light-emitting element and a first light-emitting control circuit. Under the control of the light-emitting control signal, the first light-emitting control circuit controls the connection or disconnection between the third node and the first pole of the light-emitting element to perform light-emitting control.

[0127] Optionally, the second voltage terminal can be a low voltage terminal.

[0128] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure may further include a light-emitting element E1 and a first light-emitting control circuit 51.

[0129] The first light-emitting control circuit 51 is electrically connected to the light-emitting control terminal EM, the third node N3 and the first pole of the light-emitting element E1 respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0130] The second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2. In at least one embodiment of this disclosure, the pixel circuit further includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit;

[0131] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the third node and the first electrode of the light-emitting element during the compensation and light-emitting phases, and controls the disconnection between the third node and the first electrode of the light-emitting element during the initialization and data writing phases. The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0132] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively. Under the control of the light-emitting control signal provided by the light-emitting control terminal, it controls the connection between the power supply voltage terminal and the second node during the compensation phase and the light-emitting phase, and controls the disconnection between the power supply voltage terminal and the second node during the initialization phase and the data writing phase.

[0133] In specific implementation, the pixel circuit described in at least one embodiment of this disclosure may further include a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; the first light-emitting control circuit controls the connection or disconnection between the third node and the first pole of the light-emitting element under the control of the light-emitting control signal, and the second light-emitting control circuit controls the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal, so as to perform light-emitting control.

[0134] In at least one embodiment of the pixel circuit described in this disclosure, during the light-emitting stage, a first light-emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element, and a second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node to perform light-emitting control.

[0135] During the compensation phase, the second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node so as to charge the first storage circuit through the power supply voltage signal provided by the power supply voltage terminal.

[0136] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1, a first light-emitting control circuit 51, and a second light-emitting control circuit 52.

[0137] The first light-emitting control circuit 51 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0138] The second light-emitting control circuit 52 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0139] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element and a second light-emitting control circuit;

[0140] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0141] The third node is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0142] In a specific implementation, the pixel circuit may further include a light-emitting element and a second light-emitting control circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection or disconnection between the power supply voltage terminal and the second node to perform light-emitting control.

[0143] In at least one embodiment of the pixel circuit described in this disclosure, during the light-emitting stage, a second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node to perform light-emitting control.

[0144] During the compensation phase, the second light-emitting control circuit controls the connection between the power supply voltage terminal and the second node, so as to charge the first storage circuit through the power supply voltage signal provided by the power supply voltage terminal. As shown in FIG6, based on at least one embodiment of the pixel circuit shown in FIG3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1 and a second light-emitting control circuit 52;

[0145] The second light-emitting control circuit 52 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0146] The third node N3 is electrically connected to the first electrode of the light-emitting element E1, and the second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0147] The pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit and a second reset circuit;

[0148] The data writing circuit is electrically connected to the fourth scanning end, the data line and the writing node respectively, and is used to write the data voltage provided by the data line to the writing node during the data writing stage under the control of the fourth scanning signal provided by the fourth scanning end.

[0149] The second reset circuit is electrically connected to the fifth scanning terminal, the second reset voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second reset voltage provided by the second reset voltage terminal into the first electrode of the light-emitting element during the initialization phase under the control of the fifth scanning signal provided by the fifth scanning terminal.

[0150] In a specific implementation, the pixel circuit may further include a data writing circuit and a second reset circuit.

[0151] During the data writing phase, the data writing circuit, under the control of the fourth scan signal, writes the data voltage provided by the data line into the writing node;

[0152] During the initialization phase, under the control of the fifth scan signal, the second reset circuit writes the second reset voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element and prevent residual brightness.

[0153] Optionally, the first reset voltage terminal and the second reset voltage terminal can be the same reset voltage terminal, and the fourth scan terminal and the fifth scan terminal can be the same scan terminal, so as to reduce the number of signal terminals used.

[0154] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit of at least one embodiment of this disclosure further includes a second reset circuit 80 and a data writing circuit 81.

[0155] The data writing circuit 81 is electrically connected to the fourth scanning terminal S4, the data line DL and the writing node A, respectively, and is used to write the data voltage provided by the data line DL into the writing node A during the data writing stage under the control of the fourth scanning signal provided by the fourth scanning terminal S4.

[0156] The second reset circuit 80 is electrically connected to the fifth scanning terminal S5, the second reset voltage terminal VR, and the first electrode of the light-emitting element E1, respectively, and is used to write the second reset voltage provided by the second reset voltage terminal VR into the first electrode of the light-emitting element E1 under the control of the fifth scanning signal provided by the fifth scanning terminal S5.

[0157] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit of at least one embodiment of this disclosure further includes a second reset circuit 80 and a data writing circuit 81.

[0158] The data writing circuit 81 is electrically connected to the fourth scanning terminal S4, the data line DL and the writing node A, respectively, and is used to write the data voltage provided by the data line DL into the writing node A during the data writing stage under the control of the fourth scanning signal provided by the fourth scanning terminal S4.

[0159] The second reset circuit 80 is electrically connected to the fifth scanning terminal S5, the second reset voltage terminal VR, and the first electrode of the light-emitting element E1, respectively, and is used to write the second reset voltage provided by the second reset voltage terminal VR into the first electrode of the light-emitting element E1 under the control of the fifth scanning signal provided by the fifth scanning terminal S5.

[0160] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 6, the pixel circuit of at least one embodiment of this disclosure further includes a second reset circuit 80 and a data writing circuit 81.

[0161] The data writing circuit 81 is electrically connected to the fourth scanning terminal S4, the data line DL and the writing node A, respectively, and is used to write the data voltage provided by the data line DL into the writing node A during the data writing stage under the control of the fourth scanning signal provided by the fourth scanning terminal S4.

[0162] The second reset circuit 80 is electrically connected to the fifth scanning terminal S5, the second reset voltage terminal VR, and the first electrode of the light-emitting element E1, respectively, and is used to write the second reset voltage provided by the second reset voltage terminal VR into the first electrode of the light-emitting element E1 under the control of the fifth scanning signal provided by the fifth scanning terminal S5.

[0163] Optionally, the first reset circuit includes a first transistor, and the on / off control circuit includes a second transistor;

[0164] The gate of the first transistor is electrically connected to the first scan terminal, the first terminal of the first transistor is electrically connected to the first reset voltage terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0165] The gate of the second transistor is electrically connected to the second scan terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the write node.

[0166] Optionally, the compensation control circuit includes a third transistor;

[0167] The gate of the third transistor is electrically connected to the third scanning terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node.

[0168] Optionally, the first light-emitting control circuit includes a fifth transistor;

[0169] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0170] Optionally, the first light-emitting control circuit includes a fifth transistor; the second light-emitting control circuit includes a sixth transistor.

[0171] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0172] The gate of the sixth transistor is electrically connected to the light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0173] Optionally, the data writing circuit includes a fourth transistor; the second reset circuit includes a seventh transistor;

[0174] The gate of the fourth transistor is electrically connected to the fourth scan terminal, the first terminal of the fourth transistor is electrically connected to the data line, and the second terminal of the fourth transistor is electrically connected to the write node.

[0175] The gate of the seventh transistor is electrically connected to the fifth scanning terminal, the first terminal of the seventh transistor is electrically connected to the second reset voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0176] Optionally, the light-emitting element can be an OLED (organic light-emitting diode), for example, the light-emitting element can be a Micro OLED.

[0177] In related technologies, Micro OLEDs have a higher PPI (pixel density), resulting in more pronounced uneven grayscale transitions.

[0178] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 7, the driving circuit includes a driving transistor DT, the first storage circuit includes a first capacitor C1, the second storage circuit includes a second capacitor C2, the data writing circuit includes a fourth transistor T4, and the light-emitting element is an organic light-emitting diode O1.

[0179] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the power supply voltage terminal VDD, and the drain of the driving transistor DT is electrically connected to the third node N3.

[0180] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the reference voltage terminal REF; the reference voltage terminal is used to provide a reference voltage Vref.

[0181] The first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the write node A.

[0182] The gate of the fourth transistor T4 is electrically connected to the fourth scan terminal S4, the source of the fourth transistor T4 is electrically connected to the data line DL, and the drain of the fourth transistor T4 is electrically connected to the write node A.

[0183] The on / off control circuit includes a second transistor T2;

[0184] The gate of the second transistor T2 is electrically connected to the second scan terminal S2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the write node A.

[0185] The compensation control circuit includes a third transistor T3;

[0186] The gate of the third transistor T3 is electrically connected to the third scanning terminal S3, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0187] The first reset circuit includes a first transistor T1;

[0188] The gate of the first transistor T1 is electrically connected to the first scan terminal S1, the source of the first transistor T1 is electrically connected to the first reset voltage terminal REST, and the drain of the first transistor T1 is electrically connected to the first node N1; the first reset voltage terminal REST is used to provide the first reset voltage Vrest.

[0189] The first light-emitting control circuit includes a fifth transistor T5;

[0190] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the third node N3, and the drain of the fifth transistor T5 is electrically connected to the anode of O1.

[0191] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0192] The second reset circuit includes a seventh transistor T7;

[0193] The gate of the seventh transistor T7 is electrically connected to the fourth scan terminal S4, the source of the seventh transistor T7 is electrically connected to the first reset voltage terminal REST, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0194] In at least one embodiment of the pixel circuit shown in Figure 10, all transistors are PMOS (p-type metal-oxide-semiconductor) transistors, but this is not a limitation. In specific implementations, the transistors in the pixel circuit may also be replaced with n-type transistors.

[0195] Optionally, the voltage value of Vrest can be 0V, but it is not limited to this.

[0196] In at least one embodiment of the pixel circuit shown in Figure 10, C1z / C2z equals 2, C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0197] In at least one embodiment of the pixel circuit shown in Figure 10, in order to reduce the number of transistors used and improve PPI, the emission duration control within a frame can be achieved by T5 alone.

[0198] At least one embodiment of the pixel circuit shown in FIG10 of this disclosure, during operation, TM1, T1 and T2 are turned on during the initialization phase, and the potentials of A and N1 are reset simultaneously, and the reset of the potentials of A and N1 is stopped simultaneously.

[0199] As shown in FIG11A, at least one embodiment of the pixel circuit shown in FIG10 of this disclosure, when in operation, displays a cycle including an initialization phase TM1, a compensation phase TM2, a data writing phase TM3, and a light emission phase TM4 set sequentially.

[0200] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0201] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure.

[0202] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0203] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, and S4 provides a low voltage signal. T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable range of the voltage of the writing node A is K+1 times that of the adjustable range of the voltage of the first node N1, where K is equal to C1z / C2z. This makes Gamma adjustment easier and the grayscale transition more delicate.

[0204] During the light-emitting phase, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T5 is turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0205] To address three issues in silicon-based OLED (organic light-emitting diode) pixel circuits: incomplete threshold voltage compensation of the driving transistor causing uneven pixel brightness; incomplete turn-off of the first transistor used for writing data voltage causing source-to-voltage crosstalk; and a narrow adjustable range of data voltage leading to difficult gamma tuning and coarse grayscale transitions, at least one embodiment of this disclosure stores the threshold voltage of the driving transistor in a first storage circuit and combines it with the voltage-level jump effect of a second storage circuit to completely compensate for the threshold voltage of the driving transistor; completely eliminates source-to-voltage crosstalk by means of an on / off control circuit; and by setting the ratio of the capacitance value of the first capacitor included in the first storage circuit to the capacitance value of the second capacitor included in the second storage circuit, the adjustable range of the data voltage can be multiplied, making gamma tuning easier and grayscale transitions smoother.

[0206] Compared with related technologies, at least one embodiment of this disclosure significantly improves the brightness uniformity of the light-emitting element, eliminates source-to-voltage crosstalk, makes Gamma adjustment easier and grayscale transitions smoother, and does not increase cost or process difficulty (no increase in the number of masks).

[0207] As shown in Figure 11B, at least one embodiment of the pixel circuit shown in Figure 10 of this disclosure operates as follows:

[0208] The display cycle includes the initialization phase TM1, compensation phase TM2, data writing phase TM3, and light emission phase TM4, which are set sequentially.

[0209] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0210] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure.

[0211] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0212] Before the data writing phase TM3, DL begins to provide data voltage Vdata to write node A, which enables faster data writing and reduces the impact of data line loading.

[0213] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, and S4 provides a low voltage signal. T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable range of the voltage of the writing node A is K+1 times that of the adjustable range of the voltage of the first node N1, where K is equal to C1z / C2z. This makes Gamma adjustment easier and the grayscale transition more delicate.

[0214] During the light-emitting phase, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T5 is turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0215] As shown in Figure 12, based on at least one embodiment of the pixel circuit shown in Figure 9, the driving circuit includes a driving transistor DT, the first storage circuit includes a first capacitor C1, the second storage circuit includes a second capacitor C2, the data writing circuit includes a fourth transistor T4, and the light-emitting element is an organic light-emitting diode O1.

[0216] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the second node N2, the drain of the driving transistor DT is electrically connected to the third node N3, and the third node N3 is electrically connected to the anode of O1.

[0217] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the reference voltage terminal REF; the reference voltage terminal is used to provide a reference voltage Vref.

[0218] The first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the write node A.

[0219] The gate of the fourth transistor T4 is electrically connected to the fourth scan terminal S4, the source of the fourth transistor T4 is electrically connected to the data line DL, and the drain of the fourth transistor T4 is electrically connected to the write node A.

[0220] The on / off control circuit includes a second transistor T2;

[0221] The gate of the second transistor T2 is electrically connected to the second scan terminal S2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the write node A.

[0222] The compensation control circuit includes a third transistor T3;

[0223] The gate of the third transistor T3 is electrically connected to the third scanning terminal S3, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0224] The first reset circuit includes a first transistor T1;

[0225] The gate of the first transistor T1 is electrically connected to the first scan terminal S1, the source of the first transistor T1 is electrically connected to the first reset voltage terminal REST, and the drain of the first transistor T1 is electrically connected to the first node N1; the first reset voltage terminal REST is used to provide the first reset voltage Vrest.

[0226] The second light-emitting control circuit includes a sixth transistor T6;

[0227] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2.

[0228] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0229] The second reset circuit includes a seventh transistor T7;

[0230] The gate of the seventh transistor T7 is electrically connected to the fourth scan terminal S4, the source of the seventh transistor T7 is electrically connected to the first reset voltage terminal REST, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0231] In at least one embodiment of the pixel circuit shown in Figure 12, all transistors are PMOS (p-type metal-oxide-semiconductor) transistors, but this is not a limitation. In specific implementations, the transistors in the pixel circuit may also be replaced with n-type transistors.

[0232] Optionally, the voltage value of Vrest can be 0V, but it is not limited to this.

[0233] In at least one embodiment of the pixel circuit shown in Figure 12, C1z / C2z equals 2, C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0234] In at least one embodiment of the pixel circuit shown in Figure 12, in order to reduce the number of transistors used and improve PPI, the emission duration control within a frame can be achieved by T6 alone; and, in order to avoid the source of DT being electrically connected to VDD for a long time, T6 can be set between VDD and DT.

[0235] At least one embodiment of the pixel circuit shown in FIG12 of this disclosure, during operation, TM1, T1 and T2 are turned on during the initialization phase, and the potentials of A and N1 are reset simultaneously, and the reset of the potentials of A and N1 is stopped simultaneously.

[0236] As shown in FIG13A, at least one embodiment of the pixel circuit shown in FIG12 of this disclosure, when in operation, displays a cycle including an initialization phase TM1, a compensation phase TM2, a data writing phase TM3, and a light emission phase TM4, which are set sequentially.

[0237] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0238] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure; EM provides a low voltage signal, and T6 is turned on.

[0239] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0240] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, S1 provides a low voltage signal, T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable voltage range of the writing node A is K+1 times the adjustable voltage range of the first node N1, where K is equal to C1z / C2z, thus making Gamma adjustment easier and grayscale transitions smoother.

[0241] During the light-emitting stage, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T6 is turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0242] As shown in FIG13B, at least one embodiment of the pixel circuit shown in FIG12 of this disclosure, when in operation, displays a cycle including an initialization phase TM1, a compensation phase TM2, a data writing phase TM3, and a light emission phase TM4, which are set sequentially.

[0243] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0244] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure; EM provides a low voltage signal, and T6 is turned on.

[0245] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0246] Before the data writing phase TM3, DL begins to provide data voltage Vdata to write node A, which enables faster data writing and reduces the impact of data line loading.

[0247] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, S1 provides a low voltage signal, T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable voltage range of the writing node A is K+1 times the adjustable voltage range of the first node N1, where K is equal to C1z / C2z, thus making Gamma adjustment easier and grayscale transitions smoother.

[0248] During the light-emitting stage, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T6 is turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0249] Figure 14 is a simulation timing diagram of at least one embodiment of the pixel circuit shown in Figure 12 of this disclosure.

[0250] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 8, the driving circuit includes a driving transistor DT, the first storage circuit includes a first capacitor C1, the second storage circuit includes a second capacitor C2, the data writing circuit includes a fourth transistor T4, and the light-emitting element is an organic light-emitting diode O1.

[0251] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3.

[0252] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the reference voltage terminal REF; the reference voltage terminal is used to provide a reference voltage Vref.

[0253] The first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the write node A.

[0254] The gate of the fourth transistor T4 is electrically connected to the fourth scan terminal S4, the source of the fourth transistor T4 is electrically connected to the data line DL, and the drain of the fourth transistor T4 is electrically connected to the write node A.

[0255] The on / off control circuit includes a second transistor T2;

[0256] The gate of the second transistor T2 is electrically connected to the second scan terminal S2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the write node A.

[0257] The compensation control circuit includes a third transistor T3;

[0258] The gate of the third transistor T3 is electrically connected to the third scanning terminal S3, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0259] The first reset circuit includes a first transistor T1;

[0260] The gate of the first transistor T1 is electrically connected to the first scan terminal S1, the source of the first transistor T1 is electrically connected to the first reset voltage terminal REST, and the drain of the first transistor T1 is electrically connected to the first node N1; the first reset voltage terminal REST is used to provide the first reset voltage Vrest.

[0261] The first light-emitting control circuit includes a fifth transistor T5;

[0262] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the third node N3, and the drain of the fifth transistor T5 is electrically connected to the anode of O1.

[0263] The second light-emitting control circuit includes a sixth transistor T6;

[0264] The gate of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2.

[0265] The cathode of O1 is electrically connected to the low-voltage terminal VSS;

[0266] The second reset circuit includes a seventh transistor T7;

[0267] The gate of the seventh transistor T7 is electrically connected to the fourth scan terminal S4, the source of the seventh transistor T7 is electrically connected to the first reset voltage terminal REST, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0268] In at least one embodiment of the pixel circuit shown in Figure 15, all transistors are PMOS (p-type metal-oxide-semiconductor) transistors, but this is not a limitation. In practice, the transistors in the pixel circuit may also be replaced with n-type transistors.

[0269] Optionally, the voltage value of Vrest can be 0V, but it is not limited to this.

[0270] In at least one embodiment of the pixel circuit shown in Figure 15, C1z / C2z equals 2, C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0271] In at least one embodiment of the pixel circuit shown in Figure 15, in order to avoid the source of DT being electrically connected to VDD for a long time and to completely shut off the leakage current flowing through O1 during the non-light-emitting stage, T5 can be set between the third node N3 and the anode of O1, and T6 can be set between VDD and the source of DT.

[0272] At least one embodiment of the pixel circuit shown in FIG15 of this disclosure, during operation, TM1, T1 and T2 are turned on during the initialization phase, and the potentials of A and N1 are reset simultaneously, and the reset of the potentials of A and N1 is stopped simultaneously.

[0273] As shown in Figure 16A, at least one embodiment of the pixel circuit shown in Figure 15 of this disclosure, when in operation, displays a cycle including an initialization phase TM1, a compensation phase TM2, a data writing phase TM3, and a light emission phase TM4, which are set sequentially.

[0274] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0275] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure; EM provides a low voltage signal, and T6 is turned on.

[0276] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0277] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, and S4 provides a low voltage signal. T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable range of the voltage of the writing node A is K+1 times that of the adjustable range of the voltage of the first node N1, where K is equal to C1z / C2z. This makes Gamma adjustment easier and the grayscale transition more delicate.

[0278] During the light-emitting phase, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T5 and T6 are turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0279] As shown in FIG16B, at least one embodiment of the pixel circuit shown in FIG15 of this disclosure, when in operation, displays a cycle including an initialization phase TM1, a compensation phase TM2, a data writing phase TM3, and a light emission phase TM4, which are set sequentially.

[0280] During the initialization phase TM1, S1 provides a low voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, S4 provides a high voltage signal, EM provides a high voltage signal, T7 is turned on, and REST provides Vrest to the anode of O1 to clear the residual charge on the anode of O1; T1 is turned on, and REST provides Vrest to N1 so that DT can be turned on at the start of the compensation phase TM2; T2 is turned on, and N1 is connected to A to write Vrest to A; the potential of the first node N1 and the potential of the writing node A are 0V;

[0281] During the compensation phase TM2, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a low voltage signal, S4 provides a high voltage signal, T3 is turned on, N1 and N3 are connected, and DT forms a diode structure; EM provides a low voltage signal, and T6 is turned on.

[0282] At the start of the compensation phase TM2, DT is turned on, and the power supply voltage signal provided by VDD charges the capacitor, changing the potential of N1 until DT is turned off. The potential of N1 then becomes Vdd + Vth, where Vdd is the voltage value of the power supply voltage signal provided by VDD, and Vth is the threshold voltage of DT.

[0283] Before the data writing phase TM3, DL begins to provide data voltage Vdata to write node A, which enables faster data writing and reduces the impact of data line loading.

[0284] During the data writing phase TM3, S1 provides a high voltage signal, S2 provides a high voltage signal, S3 provides a high voltage signal, and S4 provides a low voltage signal. T4 is turned on, and DL provides the data voltage Vdata to the writing node A. The potential of the writing node A jumps from 0V to Vdata. Affected by the voltage step change effect of C2, the potential of the first node N1 changes from Vdd+Vth to Vdd+Vth+Vdata×C2z / (C1z+C2z), where C1z is the capacitance value of C1 and C2z is the capacitance value of C2. During this process, the adjustable range of the voltage of the writing node A is K+1 times that of the adjustable range of the voltage of the first node N1, where K is equal to C1z / C2z. This makes Gamma adjustment easier and the grayscale transition more delicate.

[0285] During the light-emitting phase, TM4, S1, S3, and S4 all provide high-voltage signals, S2 provides a low-voltage signal, T2 is turned on, A and N1 are connected, EM provides a low-voltage signal, T5 and T6 are turned on, and DT drives O1 to emit light; Id equals Kd × (Vdata × C2z / (C1z + C2z)). 2 Where Kd is the current coefficient of DT, and Id is the driving current generated by DT, that is, the current flowing through O1; Id is not affected by the threshold voltage of DT, thus completely realizing threshold voltage compensation and greatly improving the brightness uniformity of O1.

[0286] The pixel driving method described in this disclosure is applied to the pixel circuit described above, and the pixel driving method includes:

[0287] The driving circuit generates a driving current under the control of the potential of the first node;

[0288] The initialization circuit simultaneously begins to reset the potential of the first node and the potential of the write node using the first reset voltage provided by the first reset voltage terminal, and simultaneously stops resetting the potential of the first node and the potential of the write node.

[0289] In the pixel driving method described in this embodiment, during the initialization phase, the initialization circuit starts by resetting the potential of the first node and the potential of the write node using the first reset voltage, and simultaneously stops resetting the potential of the first node and the potential of the write node to avoid the impact of the reset voltage jump on the driving transistor in the driving circuit.

[0290] In at least one embodiment of this disclosure, the second storage circuit is electrically connected to the first node and the write node respectively. During the data writing stage, the data writing circuit provides the data voltage to the write node under the control of the first scan signal. When the potential of the write node changes, the potential of the first node changes by a voltage step, and the potential information after the change is stored at the first terminal of the first storage circuit. By setting the first storage circuit and the second storage circuit, the second storage circuit can quickly complete the voltage step change, and the first storage circuit can stably maintain one frame of light emission, avoiding pixel dark spots caused by leakage of the second capacitor. It can also multiply the adjustable range of the data voltage, making Gamma adjustment easier and grayscale transitions more delicate.

[0291] In at least one embodiment of this disclosure, the initialization circuit includes a first reset circuit and an on / off control circuit; the display cycle of the pixel circuit includes an initialization phase, a compensation phase, a writing phase, and a light-emitting phase, which are set sequentially; the pixel driving method includes:

[0292] During the initialization phase, the first reset circuit, under the control of the first scan signal, writes the first reset voltage into the first node;

[0293] During the compensation phase, the writing phase, and the light emission phase, the first reset circuit, under the control of the first scan signal, controls the first reset voltage terminal to disconnect from the first node.

[0294] During the initialization phase and the light emission phase, the on / off control circuit controls the connection between the writing node and the first node;

[0295] During the compensation phase and the writing phase, the on / off control circuit controls the writing node to disconnect from the first node.

[0296] In a specific implementation, the initialization circuit may include an on / off control circuit. During the light-emitting stage, the on / off control circuit, under the control of the second scan signal, controls the connection between the first node and the writing node to completely eliminate voltage crosstalk in the source direction (the source direction can be the direction extending along the data line).

[0297] In at least one embodiment of this disclosure, the pixel circuit further includes a compensation control circuit;

[0298] The pixel driving method further includes:

[0299] During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the third scanning signal;

[0300] At the start of the compensation phase, the driving circuit, under the control of the potential of the first node, controls the connection between the second and third nodes, and the power supply voltage signal charges the first storage circuit until the driving circuit is turned off to perform threshold voltage compensation.

[0301] In at least one embodiment of this disclosure, the pixel circuit further includes a second light-emitting control circuit; the pixel driving method further includes:

[0302] During the compensation phase, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node.

[0303] In a specific implementation, when the pixel circuit further includes a second light-emitting control circuit, during the compensation stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node, so as to charge the first storage circuit through the power supply voltage signal provided by the power supply voltage terminal.

[0304] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the pixel driving method includes:

[0305] During the data writing phase, the data writing circuit writes the data voltage to the writing node under the control of the fourth scan signal.

[0306] The pixel driving method described in at least one embodiment of this disclosure further includes:

[0307] Before the data writing phase begins, the data line provides a data voltage, which enables faster data writing and reduces the impact of data line loading.

[0308] Optionally, the pixel circuit further includes a second reset circuit; the pixel driving method further includes:

[0309] During the initialization phase, under the control of the fifth scan signal, the second reset circuit writes the second reset voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0310] The display device described in this disclosure includes the pixel circuit described above.

[0311] In at least one embodiment of this disclosure, the organic light-emitting diode can be a silicon-based OLED, and the pixel circuit can be fabricated on a silicon substrate. The optimization cycle and cost of silicon-based OLEDs are far greater than those of large-size OLEDs.

[0312] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit comprising a driving circuit, a first storage circuit, a second storage circuit and an initialization circuit; a control end of the driving circuit is electrically connected with a first node, a first end of the driving circuit is electrically connected with a second node, a second end of the driving circuit is electrically connected with a third node, and the driving circuit is configured to generate a driving current under the control of a potential of the first node; a first end of the first storage circuit is electrically connected with the first node, and a second end of the first storage circuit is electrically connected with a first voltage end; a first end of the second storage circuit is electrically connected with the first node, and a second end of the second storage circuit is electrically connected with a write node; the initialization circuit is electrically connected with a first scan end, a second scan end, a first reset voltage end, the first node and the write node respectively, and is configured to, under the control of a first scan signal provided by the first scan end and a second scan signal provided by the second scan end, simultaneously start to reset a potential of the first node and a potential of the write node by a first reset voltage provided by the first reset voltage end, and simultaneously stop to reset the potential of the first node and the potential of the write node.

2. The pixel circuit of claim 1, wherein, the initialization circuit comprises a first reset circuit and a pass-through control circuit; the first reset circuit is electrically connected with the first scan end, the first reset voltage end and the first node respectively, and is configured to, under the control of the first scan signal, write the first reset voltage into the first node in an initialization stage; the pass-through control circuit is electrically connected with the second scan end, the write node and the first node respectively, and is configured to, under the control of the second scan signal, control the write node to be in communication with the first node in the initialization stage and a light-emitting stage, and control the write node to be disconnected from the first node in a data writing stage and a compensation stage.

3. The pixel circuit of claim 1, wherein, the first storage circuit comprises a first capacitor, and the second storage circuit comprises a second capacitor; a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the first voltage end; a first end of the second capacitor is electrically connected with the first node, and a second end of the second capacitor is electrically connected with the write node; a capacitance value of the first capacitor is greater than or equal to a capacitance value of the second capacitor.

4. The pixel circuit of claim 3, wherein, a ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is greater than or equal to 1.

5.

5. The pixel circuit of claim 1, wherein, the pixel circuit further comprises a compensation control circuit; the compensation control circuit is electrically connected with a third scan end, the first node and the third node respectively, and is configured to, under the control of a third scan signal provided by the third scan end, control the first node to be in communication or disconnected from the third node in a compensation stage. the pixel circuit further comprises a light-emitting element and a first light-emitting control circuit; 6. The pixel circuit of any one of claims 1 to 5, wherein, ​ The first light emitting control circuit is electrically connected with the light emitting control end, the third node and the first electrode of the light emitting element respectively, and is configured to, under the control of a light emitting control signal provided by the light emitting control end, control the third node to be in communication with the first electrode of the light emitting element in a light emitting stage, and control the third node to be disconnected from the first electrode of the light emitting element in an initialization stage, a compensation stage and a data writing stage. The second electrode of the light emitting element is electrically connected with the second voltage end.

7. The pixel circuit of any one of claims 1 to 5, wherein, The display panel further comprises a light emitting element, a first light emitting control circuit and a second light emitting control circuit. The first light emitting control circuit is electrically connected with the light emitting control end, the third node and the first electrode of the light emitting element respectively, and is configured to, under the control of a light emitting control signal provided by the light emitting control end, control the third node to be in communication with the first electrode of the light emitting element in a compensation stage and a light emitting stage, and control the third node to be disconnected from the first electrode of the light emitting element in an initialization stage and a data writing stage. The second light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the second node respectively, and is configured to, under the control of a light emitting control signal provided by the light emitting control end, control the power voltage end to be in communication with the second node in a compensation stage and a light emitting stage, and control the power voltage end to be disconnected from the second node in an initialization stage and a data writing stage.

8. The pixel circuit of any one of claims 1 to 5, wherein, The display panel further comprises a light emitting element and a second light emitting control circuit. The second light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the second node respectively, and is configured to, under the control of a light emitting control signal provided by the light emitting control end, control the power voltage end to be in communication with the second node in a compensation stage and a light emitting stage, and control the power voltage end to be disconnected from the second node in an initialization stage and a data writing stage. The third node is electrically connected with the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected with the second voltage end.

9. The pixel circuit of any one of claims 1 to 5, wherein, The display panel further comprises a data writing circuit and a second reset circuit. The data writing circuit is electrically connected with the fourth scanning end, the data line and the writing node respectively, and is configured to, under the control of a fourth scanning signal provided by the fourth scanning end, write a data voltage provided by the data line to the writing node in a data writing stage. The second reset circuit is electrically connected with the fifth scanning end, the second reset voltage end and the first electrode of the light emitting element respectively, and is configured to, under the control of a fifth scanning signal provided by the fifth scanning end, write a second reset voltage provided by the second reset voltage end to the first electrode of the light emitting element in an initialization stage.

10. The pixel circuit of claim 2, wherein, The driving circuit comprises a driving transistor, the first reset circuit comprises a first transistor, and the on-off control circuit comprises a second transistor. The gate electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node. A gate of the first transistor is electrically connected with the first scan end, a first electrode of the first transistor is electrically connected with the first reset voltage end, and a second electrode of the first transistor is electrically connected with the first node; The on-off control circuit comprises a second transistor; A gate of the second transistor is electrically connected with the second scan end, a first electrode of the second transistor is electrically connected with the first node, and a second electrode of the second transistor is electrically connected with the write node.

11. The pixel circuit of claim 5, wherein, The compensation control circuit comprises a third transistor; A gate of the third transistor is electrically connected with the third scan end, a first electrode of the third transistor is electrically connected with the first node, and a second electrode of the third transistor is electrically connected with the third node.

12. The pixel circuit of claim 6, wherein, The first light-emitting control circuit comprises a fifth transistor; A gate of the fifth transistor is electrically connected with the light-emitting control end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with a first electrode of the light-emitting element.

13. The pixel circuit of claim 7, wherein, The first light-emitting control circuit comprises a fifth transistor, and the second light-emitting control circuit comprises a sixth transistor; A gate of the fifth transistor is electrically connected with the light-emitting control end, a first electrode of the fifth transistor is electrically connected with the third node, and a second electrode of the fifth transistor is electrically connected with a first electrode of the light-emitting element; A gate of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the power voltage end, and a second electrode of the sixth transistor is electrically connected with the second node.

14. The pixel circuit of claim 8, wherein, The second light-emitting control circuit comprises a sixth transistor; A gate of the sixth transistor is electrically connected with the light-emitting control end, a first electrode of the sixth transistor is electrically connected with the power voltage end, and a second electrode of the sixth transistor is electrically connected with the second node.

15. The pixel circuit of claim 9, wherein, The data write circuit comprises a fourth transistor, and the second reset circuit comprises a seventh transistor; A gate of the fourth transistor is electrically connected with the fourth scan end, a first electrode of the fourth transistor is electrically connected with the data line, and a second electrode of the fourth transistor is electrically connected with the write node; A gate of the seventh transistor is electrically connected with the fifth scan end, a first electrode of the seventh transistor is electrically connected with the second reset voltage end, and a second electrode of the seventh transistor is electrically connected with a first electrode of the light-emitting element.

16. A pixel driving method applied to the pixel circuit in any one of claims 1 to 15, the pixel driving method comprising: The driving circuit generates a driving current under the control of the potential of the first node; The initialization circuit simultaneously starts to reset the potential of the first node and the potential of the write node by the first reset voltage provided by the first reset voltage end, and simultaneously stops to reset the potential of the first node and the potential of the write node.

17. The pixel driving method of claim 16, wherein, The initialization circuit comprises a first reset circuit and an on-off control circuit; the display period of the pixel circuit comprises an initialization stage, a compensation stage, a data write stage and a light-emitting stage arranged in sequence; and the pixel driving method comprises: In the initialization stage, the first reset circuit writes the first reset voltage into the first node under the control of the first scan signal; In the compensation stage, the data writing stage and the light emitting stage, the first reset circuit controls the disconnection between the first reset voltage terminal and the first node under the control of the first scan signal; In the initialization stage and the light emitting stage, the on-off control circuit controls the connection between the writing node and the first node; In the compensation stage and the data writing stage, the on-off control circuit controls the disconnection between the writing node and the first node.

18. The pixel driving method of claim 17, wherein, The pixel circuit further comprises a compensation control circuit; The pixel driving method further comprises: In the compensation stage, the compensation control circuit controls the connection between the first node and the third node under the control of the third scan signal; At the beginning of the compensation stage, the driving circuit controls the connection between the second node and the third node under the control of the potential of the first node, and charges the first storage circuit with the power voltage signal until the driving circuit is turned off.

19. The pixel driving method of claim 18, wherein, The pixel circuit further comprises a second light emitting control circuit; The pixel driving method further comprises: In the compensation stage, the second light emitting control circuit controls the connection between the power voltage terminal and the second node under the control of the light emitting control signal.

20. The pixel driving method of claim 17, wherein, The pixel circuit further comprises a data writing circuit; the pixel driving method comprises: In the data writing stage, the data writing circuit writes the data voltage into the writing node under the control of the fourth scan signal respectively.

21. The pixel driving method of claim 20, wherein, Further comprising: Before the beginning of the data writing stage, the data line provides the data voltage.

22. The pixel driving method of claim 17, wherein, The pixel circuit further comprises a second reset circuit; the pixel driving method further comprises: In the initialization stage, the second reset circuit writes the second reset voltage into the first electrode of the light emitting element under the control of the fifth scan signal.

23. A display device comprising the pixel circuit according to any one of claims 1 to 15.

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