Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises: a substrate; the shading layer is located on the substrate; the second signal line layer is located on the side, away from the substrate, of the shading layer. The light shielding layer comprises a plurality of first light shielding lines and a plurality of second light shielding lines which are connected together. Each first shading line extends along a first direction. Each of the second shading lines extends along a second direction. The second signal line layer comprises a plurality of fourth reset signal lines. Each of the fourth reset signals in the plurality of fourth reset signal lines extends in the second direction. The orthographic projection of each fourth reset signal line on the substrate basically covers the orthographic projection of the corresponding second shading line on the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently one of the hottest research areas in flat panel displays. OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate, comprising: a substrate; a light-shielding layer located on the substrate; and a second signal line layer located on the side of the light-shielding layer away from the substrate; wherein the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines interconnected; each of the plurality of first light-shielding lines extends along a first direction; each of the plurality of second light-shielding lines extends along a second direction; the second signal line layer includes a plurality of fourth reset signal lines; each of the plurality of fourth reset signal lines extends along the second direction; and the orthographic projection of each fourth reset signal line on the substrate substantially covers the orthographic projection of the corresponding second light-shielding line on the substrate.

[0004] Optionally, each of the first light-shielding light sources includes a plurality of light-shielding blocks connected by a plurality of bridges; and the orthographic projection of each of the plurality of light-shielding blocks on the substrate substantially covers the orthographic projection of the active layer of the driving transistor on the substrate.

[0005] Optionally, the ratio of the number of columns of the pixel driving circuit to the number of the plurality of second light shields is in the range of 1.8:1 to 2.2:1; and the ratio of the number of columns of the pixel driving circuit to the number of the plurality of fourth reset signal lines is in the range of 1.8:1 to 2.2:1.

[0006] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of first power lines, a plurality of second power lines, and a power connection pad; each of the plurality of first power lines extends along a first direction; each of the plurality of second power lines extends along a second direction; each second power line includes a plurality of segments spaced apart from each other; two adjacent segments of the plurality of segments of each second power line are connected to the power connection pad; the plurality of first power lines are located on a first signal line layer; the plurality of second power lines are located on a second signal line layer; and the power connection pad is located on the first signal line layer.

[0007] Optionally, the array substrate further includes a power network; wherein the power network includes a plurality of second power lines; the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); the plurality of second power lines exist between the (4k)th column and the (4k-1)th column, and between the (4k-2)th column and the (4k-3)th column; and the plurality of second power lines do not exist between the (4k-1)th column and the (4k-2)th column.

[0008] Optionally, the array substrate further includes: a plurality of first reset signal lines located in a third gate metal layer; and a power network including a plurality of first power lines located in a first signal line layer, the first signal line layer being located on the side of the third gate metal layer away from the substrate; wherein the orthographic projection of each of the plurality of first reset signal lines on the substrate substantially covers the orthographic projection of the corresponding first power line among the plurality of first power lines on the substrate.

[0009] Optionally, the array substrate further includes a plurality of fourth reset signal lines located in the second signal line layer; wherein, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); the plurality of fourth reset signal lines exist between the (4k-1)th column and the (4k-2)th column; and the plurality of fourth reset signal lines do not exist between the (4k)th column and the (4k-1)th column, nor between the (4k-2)th column and the (4k-3)th column.

[0010] Optionally, the plurality of fourth reset signal lines includes one or more fifth reset signal lines; wherein, the array substrate includes a second reset signal network; the second reset signal network includes a plurality of second reset signal lines and the one or more fifth reset signal lines interconnected with each other; each of the one or more fifth reset signal lines is connected to at least one of the plurality of second reset signal lines; each of the plurality of second reset signal lines is connected to at least one of the one or more fifth reset signal lines; the plurality of second reset signal lines are located in a second gate metal layer; and the one or more fifth reset signal lines are located in a second signal line layer, the second signal line layer being located on the side of the second gate metal layer away from the substrate.

[0011] Optionally, the plurality of fourth reset signal lines includes one or more sixth reset signal lines; wherein the array substrate includes a first reset signal network; wherein the first reset signal network includes a plurality of first reset signal lines and the one or more sixth reset signal lines interconnected with each other; each of the one or more sixth reset signal lines is connected to at least one of the plurality of first reset signal lines; each of the plurality of first reset signal lines is connected to at least one of the one or more sixth reset signal lines; the plurality of first reset signal lines are located in a third gate metal layer; and the one or more sixth reset signal lines are located in a second signal line layer, the second signal line layer being located on the side of the third gate metal layer away from the substrate.

[0012] Optionally, the array substrate further includes a plurality of second reset control signal lines located on a first gate metal layer, the first gate metal layer being located on the side of the third gate metal layer closer to the substrate; wherein the orthographic projection of each of the first reset signal lines on the substrate substantially covers the orthographic projection of the corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

[0013] Optionally, the plurality of fourth reset signal lines includes one or more seventh reset signal lines; wherein, the array substrate includes a third reset signal network; wherein, the third reset signal network includes a plurality of third reset signal lines and the one or more seventh reset signal lines interconnected together; each of the one or more seventh reset signal lines is connected to at least one of the plurality of third reset signal lines; each of the plurality of third reset signal lines is connected to at least one of the one or more seventh reset signal lines; the plurality of third reset signal lines are located in a third gate metal layer; and the one or more seventh reset signal lines are located in a second signal line layer, the second signal line layer being located on the side of the third gate metal layer away from the substrate.

[0014] Optionally, the array substrate further includes a plurality of first reset control signal lines located on a first gate metal layer, the first gate metal layer being located on the side of the third gate metal layer closer to the substrate; wherein the orthographic projection of each of the third reset signal lines on the substrate substantially covers the orthographic projection of the corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate.

[0015] Optionally, the plurality of fourth reset signal lines include one or more fifth reset signal lines, one or more sixth reset signal lines, and one or more seventh reset signal lines; wherein, the array substrate includes a plurality of pixel driving circuits arranged in M ​​columns, where M is a positive integer; the M columns include the (12m-11)th column, the (12m-10)th column, the (12m-9)th column, the (12m-8)th column, the (12m-7)th column, the (12m-6)th column, the (12m-5)th column, and the M columns... The (12m-4)th column, the (12m-3)th column, the (12m-2)th column, the (12m-1)th column, and the 12mth column of the M columns, where m is a positive integer and 1 ≤ m ≤ M / 12; the one or more fifth reset signal lines exist between the (12m-9)th and (12m-10)th columns; the one or more sixth reset signal lines exist between the (12m-5)th and (12m-6)th columns; and the one or more seventh reset signal lines exist between the (12m-1)th and (12m-2)th columns.

[0016] Optionally, the array substrate further includes a plurality of reference signal lines and a plurality of voltage supply lines; wherein each of the plurality of reference signal lines is connected to a second capacitor electrode of a storage capacitor in a pixel driving circuit; and each of the plurality of voltage supply lines is connected to a first electrode of a third transistor in the pixel driving circuit.

[0017] Optionally, the array substrate further includes a reference signal network; wherein the reference signal network includes a plurality of reference signal lines and a plurality of second reference signal lines interconnected with each other; each reference signal line extends along the second direction; each of the plurality of second reference signal lines extends along the first direction; each second reference signal line includes a plurality of second capacitor electrodes from a plurality of storage capacitors in a plurality of pixel driving circuits in the same row; each reference signal line is connected to at least one of the plurality of second reference signal lines; and each second reference signal line is connected to at least one of the plurality of reference signal lines.

[0018] Optionally, the array substrate further includes reference signal connection pads located in the first signal line layer; wherein each reference signal line is connected to the reference signal connection pad through a via; the reference signal connection pad is connected to a corresponding second reference signal line through a via; and the plurality of second reference signal lines are located in a second gate metal layer, the second gate metal layer being located on the side of the first signal line layer closer to the substrate.

[0019] Optionally, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); the plurality of reference signal lines exist between the (4k)th column and the (4k-1)th column, and between the (4k-2)th column and the (4k-3)th column; and the plurality of reference signal lines do not exist between the (4k-1)th column and the (4k-2)th column.

[0020] Optionally, the array substrate further includes a voltage supply network; wherein the voltage supply network includes a plurality of voltage supply lines and a plurality of second voltage supply lines interconnected with each other; each voltage supply line extends along the second direction; each of the plurality of second voltage supply lines extends along the first direction; each voltage supply line is connected to at least one of the plurality of second voltage supply lines; each second voltage supply line is connected to at least one of the plurality of voltage supply lines; and the plurality of second voltage supply lines are located in a first signal line layer, the first signal line layer being located on the side of the second signal line layer closer to the substrate.

[0021] Optionally, the array substrate further includes a first anode, a voltage connection pad, and a third connection line; wherein the first anode includes a first corner portion, a second corner portion, a third corner portion, a fourth corner portion, and a center portion; the voltage connection pad includes a connector portion, a first branch portion connected to the connector portion, a second branch portion connected to the connector portion, and a third branch portion connected to the connector portion; the third connection line includes a connection portion, a first side portion connected to the connection portion, a second side portion connected to the connection portion, and an extension portion connected to the connection portion; the orthographic projection of the first corner portion on the substrate at least partially overlaps with the orthographic projection of the connection portion of the third connection line on the substrate, and at least partially overlaps with the orthographic projection of the extension portion of the third connection line on the substrate; the orthographic projection of the second corner portion on the substrate at least partially overlaps with the orthographic projection of the first branch portion of the voltage connection pad on the substrate; and the orthographic projection of the center portion on the substrate at least partially overlaps with the orthographic projection of the first branch portion of the voltage connection pad on the substrate.

[0022] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2BThis is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in a portion of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A The diagram depicts the arrangement of pixel driving circuits in an array substrate.

[0029] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in the array substrate is depicted.

[0030] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted.

[0031] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0032] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0033] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted.

[0034] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0035] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure.

[0036] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0037] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0038] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0039] Figure 4 It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0040] Figure 5 This is a schematic diagram illustrating a power network according to some embodiments of the present disclosure.

[0041] Figure 6 This is a schematic diagram illustrating a corresponding first power supply line and a corresponding first reset signal line in some embodiments according to the present disclosure.

[0042] Figure 7 This is a schematic diagram illustrating a second reset signal network according to some embodiments of the present disclosure.

[0043] Figure 8 This is a schematic diagram illustrating a first reset signal network according to some embodiments of the present disclosure.

[0044] Figure 9 This is a schematic diagram showing the corresponding second reset control signal line and the corresponding first reset signal line according to some embodiments of the present disclosure.

[0045] Figure 10 This is a schematic diagram illustrating a third reset signal network according to some embodiments of the present disclosure.

[0046] Figure 11 This is a schematic diagram showing a corresponding first reset control signal line and a corresponding third reset signal line according to some embodiments of the present disclosure.

[0047] Figure 12 It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0048] Figure 13 This is a schematic diagram illustrating the structure of a reset signal network according to some embodiments of the present disclosure.

[0049] Figure 14 This is a schematic diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 15 This is a schematic diagram showing a fourth reset signal line and a light-shielding layer according to some embodiments of the present disclosure.

[0051] Figure 16 This is a schematic diagram illustrating the structure of the first signal line layer and the anode layer in an array substrate according to some embodiments of the present disclosure.

[0052] Figure 17 This is a schematic diagram illustrating the structure of the first anode in an array substrate according to some embodiments of the present disclosure.

[0053] Figure 18 This is a schematic diagram illustrating the structure of voltage connection pads in an array substrate according to some embodiments of the present disclosure.

[0054] Figure 19 This is a schematic diagram illustrating the structure of a third connection line in an array substrate according to some embodiments of the present disclosure.

[0055] Figure 20 This is a schematic diagram illustrating the structure of a second anode in an array substrate according to some embodiments of the present disclosure.

[0056] Figure 21A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0057] Figure 21B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0058] Figure 22A This is a schematic diagram illustrating the structure of a pixel driving circuit in a portion of an array substrate according to some embodiments of the present disclosure.

[0059] Figure 22B It is shown Figure 22A The diagram depicts the arrangement of pixel driving circuits in an array substrate.

[0060] Figure 22C It is shown Figure 22A A schematic diagram of the structure of the light-shielding layer in the array substrate is depicted.

[0061] Figure 22D It is shown Figure 22A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted.

[0062] Figure 22E It is shown Figure 22A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0063] Figure 22F It is shown Figure 22A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0064] Figure 22G It is shown Figure 22A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted.

[0065] Figure 22H It is shown Figure 22A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0066] Figure 22I It is shown Figure 22A A schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure.

[0067] Figure 22J It is shown Figure 22A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0068] Figure 22K It is shown Figure 22A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0069] Figure 22L It is shown Figure 22A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0070] Figure 23 It is along Figure 22A A cross-sectional view of line B-B' in the diagram.

[0071] Figure 24 This is a schematic diagram illustrating a reference signal network according to some embodiments of the present disclosure.

[0072] Figure 25 This is a schematic diagram illustrating a voltage supply network according to some embodiments of the present disclosure. Detailed Implementation

[0073] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0074] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes: a substrate; a light-shielding layer located on the substrate; and a second signal line layer located on the side of the light-shielding layer away from the substrate. Optionally, the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines interconnected. Optionally, each of the plurality of first light-shielding lines extends along a first direction. Optionally, each of the plurality of second light-shielding lines extends along a second direction. Optionally, the second signal line layer includes a plurality of fourth reset signal lines. Optionally, each of the plurality of fourth reset signal lines extends along a second direction. Optionally, the orthographic projection of each fourth reset signal line on the substrate substantially overlaps the orthographic projection of the corresponding second light-shielding line on the substrate.

[0075] Various suitable pixel driving circuits can be used in the array substrate of this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate of this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0076] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (e.g., each first gate line GL1), a plurality of second gate lines (e.g., each second gate line GL2), a plurality of data lines (e.g., each data line DL), a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd), and a plurality of first power lines (e.g., each first power line Vss1). Each sub-pixel Sp is driven to emit light by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each of the plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0077] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line G among a plurality of second gate lines. The transistor T2 has a gate, a first electrode connected to the storage capacitor Cst's first capacitor electrode Ce1 and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding first voltage supply line Vdd among a plurality of first voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0078] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0079] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0080] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0081] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of the form S1-S2-S3, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 form is a C1-C2-C3 form, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 form is an RGB form, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0082] In another example, the array of multiple sub-pixels includes a repeating array of the form S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 form is C1-C2-C3-C4, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In yet another example, the S1-S2-S3-S4 form is C1-C2-C3-C2', where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C2' represents each fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' form is RGBG, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0083] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0084] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0085] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2AThe second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0086] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light-emitting sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to turn off. In the initial sub-stage t0, a cutoff signal is provided to the corresponding first gate line GL1, therefore the first transistor T1 is turned off.

[0087] In reset phase t1, the turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, turning on the first reset transistor Tr1; this causes the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and then to node N4. The anode of the light-emitting element LE is initialized. The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1, turning on the third reset transistor Tr3; this causes the initialization voltage signal from the corresponding third reset signal line Vint3 to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding first voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During reset phase t1, a cutoff signal is provided to the corresponding first gate line GL1, thus turning off the first transistor T1. A high voltage signal is provided to the corresponding light-emitting control signal line em, causing the third transistor T3 and the fourth transistor T4 to turn off.

[0088] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2, turning on the second reset transistor Tr2. This causes the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to its second electrode, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is then initialized.

[0089] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to be turned off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level at node N1 gradually rises to (Vdata + Vth) during the data write sub-stage t2, where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0090] In the light-emitting phase t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is also provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing both the first and third reset transistors Tr1 and Tr3 to turn off. Cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning off the first transistor T1 and the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em, turning on the third transistor T3 and the fourth transistor T4. The voltage level at node N1 is maintained at (Vdata + Vth) in the light-emitting phase t3, and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0091] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in a portion of an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A The diagram depicts the arrangement of pixel driving circuits in an array substrate. Figure 3A and Figure 3B A portion of an array substrate with four adjacent pixel driving circuits (including PDC1, PDC2, PDC3 and PDC4) is depicted.

[0092] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in the array substrate is depicted. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 3I It is shown Figure 3AA schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 4 It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0093] Reference Figures 3A to 3L as well as Figure 4 In some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; and a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate insulating layer. One side of the metal layer Gate2; the second interlayer dielectric layer ILD2, located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second planarization layer SD2, located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; and the second planarization layer PLN2, located on the side of the second signal line layer SD2 away from the first planarization layer PLN1.

[0094] Reference Figure 2A , Figure 3A , Figure 3C ,and Figure 5 In some embodiments, the light-shielding layer LSL includes a light-shielding element LS. In some embodiments, the light-shielding element LS is an integral structure extending across a plurality of sub-pixels.

[0095] Reference Figure 2A , Figure 3A , Figure 3D ,and Figure 5 In some embodiments, the first semiconductor material layer SML1 includes at least an active layer of a plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode for a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0096] exist Figure 3D In the middle, the corresponding numbers are marked. Figure 3B The pixel driving circuit of PDC2 is labeled with reference numerals to each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0097] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACTr3 and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3 and Sd), and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0098] In some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of an integral structure. Optionally, the portion of the second reset transistor Tr2 located in the first semiconductor material layer (ACTr2, Sr2, Dr2) is spaced apart from the integral structure (T1, T3, T4, Tr1, and Td) in the same pixel driving circuit. Figure 3D As shown, in some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of a plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in two adjacent pixel driving circuits, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure.

[0099] Reference Figure 2A , Figure 3A , Figure 3E and Figure 5 In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of light emission control signal lines (e.g., each light emission control signal line em), and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0100] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of light emission control signal lines (e.g., each light emission control signal line em), and the first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0101] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines and first capacitor electrodes Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple first gate lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines and the steps of forming first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0102] Reference Figure 2A , Figure 3A , Figure 3F and Figure 5In some embodiments, the second gate metal layer Gate2 includes at least portions of a plurality of second gate lines (e.g., first branches GL2-1 of each second gate line), a plurality of second reset signal lines (e.g., each second reset signal line Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least portions of the plurality of second gate lines (e.g., first branches GL2-1 of each second gate line), the plurality of second reset signal lines (e.g., each second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0103] Reference Figure 2A , Figure 3A , Figure 3G and Figure 5 In some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2 of the second transistor T2, the first electrode S2, and the second electrode D2. In the array substrate of this disclosure, the at least active layer ACT2 of the second transistor T2 is located in a layer different from the at least active layers of other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.

[0104] exist Figure 3G In the middle, the corresponding numbers are marked. Figure 3B The pixel driving circuit of PDC2 is indicated by the label, which indicates the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are located on the same layer.

[0105] Reference Figure 2A , Figure 3A , Figure 3H and Figure 5 In some embodiments, the third gate metal layer Gate3 includes at least portions of a plurality of second gate lines (e.g., second branches GL2-2 of each second gate line), a plurality of first reset signal lines (e.g., each first reset signal line Vint1), and a plurality of third reset signal lines (e.g., each third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third gate metal layer Gate3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0106] Figure 3I It shows the extension through Figure 3A The vias in the passivation layer of the array substrate are depicted.

[0107] Reference Figure 2A , Figure 3A , Figure 3J and Figure 5 In some embodiments, the first signal line layer SD1 includes: a plurality of first power lines (e.g., each first power line Vss1); a voltage connection pad VCP; a data connection pad DCP; a power connection pad SCP; a first node connection line Cln1; a second node connection line Cln2; a third node connection line Cln3; a relay electrode RE; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3.

[0108] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple first power lines (e.g., individual first power lines Vss1), voltage connection pads VCP, data connection pads DCP, power connection pads SCP, first node connection lines Cln1, second node connection lines Cln2, third node connection lines Cln3, relay electrodes RE, first reset signal connection lines Cli1, second reset signal connection lines Cli2, and third reset signal connection lines Cli3 are located in the same layer.

[0109] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (Refer to...) Figure 4 The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the first electrode S2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 is depicted in the diagram.

[0110] Reference Figure 2A , Figure 3A , Figure 3E , Figure 3F and Figure 5 In some embodiments, a portion of the second capacitor electrode Ce2 is absent from the via region H. Optionally, except for the via region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the via region H, and the insulating layer IN.

[0111] In some embodiments, the first node connection line Cln1 intersects with a corresponding second gate line among a plurality of second gate lines. For example... Figure 3A and Figure 5As shown, the first node connection line Cln1 intersects with the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0112] In some embodiments, the second node connection line Cln2 connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode Dr3 of the third reset transistor Tr3, the second electrode D3 of the third transistor T3, and the first electrode Sd of the driving transistor Td.

[0113] In some embodiments, the third node connection line Cln3 is connected to the second electrode Dd of the driving transistor Td, to the second electrode Dr2 of the second reset transistor Tr2, and to the first electrode S4 of the fourth transistor T4.

[0114] In some embodiments, a first reset signal connection line Cli1 connects a corresponding first reset signal line Vint1 among a plurality of first reset signal lines to a first electrode Sr1 of a first reset transistor Tr1. The first reset signal connection line Cli1 is configured to transmit a reset signal from the corresponding first reset signal line Vint1 to the first electrode Sr1 of the first reset transistor Tr1.

[0115] In some embodiments, the second reset signal connection line Cli2 connects a corresponding second reset signal line Vint2 among a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Cli2 is configured to transmit a reset signal from the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2.

[0116] In some embodiments, the third reset signal connection line Cli3 connects a corresponding third reset signal line Vint3 among a plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor Tr3. The third reset signal connection line Cli3 is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In one example, the third reset signal connection line Cli3 is connected to the first electrode of the third reset transistor of two adjacent pixel driving circuits in the same row, and is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode of the third reset transistor of the two adjacent pixel driving circuits in the same row.

[0117] Figure 3K It shows the extension through Figure 3A The vias in the first planarization layer of the array substrate are depicted in the figure.

[0118] Reference Figure 2A , Figure 3A , Figure 3B , Figure 3L and Figure 5 In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., individual first voltage supply lines Vdd), a plurality of second low voltage supply lines (e.g., individual second low voltage supply lines Vss2), an anode contact pad ACP, a plurality of data lines (e.g., individual data lines DL), and a plurality of fourth reset signal lines (e.g., individual fourth reset signal lines Vint4). Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple first voltage supply lines (e.g., each first voltage supply line Vdd), multiple second low voltage supply lines (e.g., each second low voltage supply line Vss2), anode contact pad ACP, multiple data lines (e.g., each data line DL), and multiple fourth reset signal lines (e.g., each fourth reset signal line Vint4) are located on the same layer.

[0119] In some embodiments, refer to Figures 3A to 3L and Figure 4 The relay electrode RE is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) and to the anode contact pad ACP. In one example, the anode contact pad ACP is located on the second signal line layer SD2, and the relay electrode RE is located on the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the relay electrode RE via a via extending through the first planarization layer PLN1, and the relay electrode RE2 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0120] In some embodiments, the data connection pad DCP is connected to the first electrode S1 of the first transistor T1 and to a corresponding data line DL among a plurality of data lines. In one example, the data connection pad DCP is located on the first signal line layer SD1, and the corresponding data line DL is located on the second signal line layer SD2. In another example, the corresponding data line DL is connected to the data connection pad DCP via a via extending through the first planarization layer PLN1, and the data connection pad DCP is connected to the first electrode S1 of the first transistor T1 via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0121] In some embodiments, each of the plurality of first voltage supply lines, Vdd, is connected to a voltage connection pad, VCP, which is connected to a first electrode of a third transistor T3, thereby providing a voltage supply signal to the first electrode of the third transistor T3. In some embodiments, the voltage connection pad VCP is also connected to a second capacitor electrode Ce2 of a storage capacitor Cst, thereby providing a voltage supply signal to the second capacitor electrode Ce2 of the storage capacitor Cst.

[0122] In some embodiments, the voltage connection pad VCP is connected to the first electrode of a third transistor in two adjacent pixel drive circuits in the same row.

[0123] In some embodiments, refer to Figures 3A to 3L The first pixel driving circuits that are directly adjacent to each other and in the current level (e.g., in the same row) Figure 3C The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 3C The corresponding layer of PDC2 in the array has, for example, a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines and has substantially mirror symmetry with respect to each other (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or perfectly symmetrical).

[0124] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a first signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third gate metal layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second gate metal layer.

[0125] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and at least one conductive layer of the second pixel driving circuit. In one specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first semiconductor material layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first gate metal layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a second semiconductor material layer.

[0126] Figure 5 This is a schematic diagram illustrating a power network according to some embodiments of the present disclosure. (Refer to...) Figure 5 In some embodiments, the power network includes a plurality of first power lines and a plurality of second power lines. Optionally, each of the plurality of first power lines, Vss1, extends along a first direction DR1. Optionally, each of the plurality of second power lines, Vss2, extends along a second direction DR2.

[0127] In some embodiments, each of the plurality of second power lines Vss2 comprises a plurality of segments spaced apart from each other. In some embodiments, two adjacent segments of the plurality of segments of each second power line Vss2 are connected to the power connection pad SCP.

[0128] In some embodiments, a plurality of first power lines are located on a first signal line layer, a plurality of second power lines are located on a second signal line layer, and a power connection pad SCP is located on the first signal line layer.

[0129] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0130] As used herein, the terms "column (4k-3)," "column (4k-2)," "column (4k-1)," and "column (4k)" are used in the context of K columns. The array substrate may or may not include additional columns preceding the first column of the K columns and / or additional columns following the last column of the K columns. In the context of the array substrate, the terms "column (4k-3)" or "column (4k-1)" do not necessarily indicate an odd-numbered column, and the terms "column (4k-2)" or "column (4k)" do not necessarily indicate an even-numbered column. In one example, column (4k-3) is an odd-numbered column in the context of K columns, but may be an even-numbered column in the context of the array substrate. In another example, column (4k-3) is an odd-numbered column in the context of K columns and also an odd-numbered column in the context of the array substrate. In one example, column (4k-2) is an even-numbered column in the context of K columns, but may be an odd-numbered column in the context of the array substrate. In another example, column (4k-2) is an even column against the background of the K columns, and also an even column against the background of the array substrate. In one example, column (4k-1) is an odd column against the background of the K columns, but can be an even column against the background of the array substrate. In another example, column (4k-1) is an odd column against the background of the K columns, and also an odd column against the background of the array substrate. In one example, column (4k) is an even column against the background of the K columns, but can be an odd column against the background of the array substrate. In another example, column (4k) is an even column against the background of the K columns, and also an even column against the background of the array substrate.

[0131] In some embodiments, a plurality of second power lines exist between column (4k) C(4k) and column (4k-1) C(4k-1), and between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, the plurality of second power lines do not exist between column (4k-1) C(4k-1) and column (4k-2) C(4k-2).

[0132] Figure 6This is a schematic diagram illustrating corresponding first power supply lines and corresponding first reset signal lines according to some embodiments of the present disclosure. (Refer to...) Figure 6 In some embodiments, the orthographic projection of each first power line Vss1 on the substrate at least partially overlaps with the orthographic projection of the corresponding first reset signal line Vint1 on the substrate. In some embodiments, the orthographic projection of each first reset signal line Vint1 on the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the corresponding first power line Vss1 on the substrate. The inventors of this disclosure have found that by providing such a structure, interference to components in the second semiconductor material layer, the second gate metal layer, and the first gate metal layer caused by the corresponding first power line Vss1 can be reduced or prevented.

[0133] In some embodiments, each first power line Vss1 is located on a first signal line layer, and each first reset signal line Vint1 is located on a third gate metal layer.

[0134] Figure 7 This is a schematic diagram illustrating a second reset signal network according to some embodiments of the present disclosure. (Refer to...) Figure 3L and Figure 7 In some embodiments, the plurality of fourth reset signal lines includes one or more fifth reset signal lines. In some embodiments, the second reset signal network includes a plurality of second reset signal lines and one or more fifth reset signal lines interconnected together. Each fifth reset signal line Vint5 is connected to at least one of the plurality of second reset signal lines. Each second reset signal line Vint2 is connected to at least one of the one or more fifth reset signal lines.

[0135] In some embodiments, a plurality of second reset signal lines are located in a second gate metal layer, and one or more fifth reset signal lines are located in a second signal line layer. Each fifth reset signal line Vint5 is connected to at least one of the plurality of second reset signal lines via a via extending through a first planarization layer, a passivation layer, a second interlayer dielectric layer, and a first interlayer dielectric layer.

[0136] Figure 8 This is a schematic diagram illustrating a first reset signal network according to some embodiments of the present disclosure. (Refer to...) Figure 3L and Figure 8In some embodiments, the plurality of fourth reset signal lines includes one or more sixth reset signal lines. In some embodiments, the first reset signal network includes a plurality of first reset signal lines and one or more sixth reset signal lines interconnected with each other. Each sixth reset signal line Vint6 is connected to at least one of the plurality of first reset signal lines. Each first reset signal line Vint1 is connected to at least one of the one or more sixth reset signal lines.

[0137] In some embodiments, a plurality of first reset signal lines are located on a third gate metal layer, and one or more sixth reset signal lines are located on a second signal line layer. Each sixth reset signal line Vint6 is connected to at least one of the plurality of first reset signal lines via vias extending through a first planarization layer and a passivation layer.

[0138] Figure 9 This is a schematic diagram illustrating corresponding second reset control signal lines and corresponding first reset signal lines according to some embodiments of the present disclosure. (Refer to...) Figure 9 In some embodiments, the orthographic projections of each first reset signal line Vint1 onto the substrate at least partially overlap with the orthographic projections of the corresponding second reset control signal line rst2 onto the substrate. In some embodiments, the orthographic projections of each first reset signal line Vint1 onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) cover the orthographic projection of the corresponding second reset control signal line rst2 onto the substrate. The inventors of this disclosure have found that by providing such a structure, interference to components in other layers caused by the corresponding second reset control signal line rst2 can be reduced or prevented.

[0139] In some embodiments, each of the second reset control signal lines rst2 is located in the first gate metal layer, and the corresponding first reset signal line Vint1 is located in the third gate metal layer.

[0140] Figure 10 This is a schematic diagram illustrating a third reset signal network according to some embodiments of the present disclosure. (Refer to...) Figure 3L and Figure 10 In some embodiments, the plurality of fourth reset signal lines includes one or more seventh reset signal lines. In some embodiments, the third reset signal network includes a plurality of third reset signal lines and one or more seventh reset signal lines interconnected together. Each seventh reset signal line Vint7 is connected to at least one of the plurality of third reset signal lines. Each third reset signal line Vint3 is connected to at least one of the one or more seventh reset signal lines.

[0141] In some embodiments, a plurality of third reset signal lines are located on a third gate metal layer, and one or more seventh reset signal lines are located on a second signal line layer. Each seventh reset signal line Vint7 is connected to at least one of the plurality of third reset signal lines via vias extending through a first planarization layer and a passivation layer.

[0142] Figure 11 This is a schematic diagram illustrating corresponding first reset control signal lines and corresponding third reset signal lines according to some embodiments of the present disclosure. (Refer to...) Figure 11 In some embodiments, the orthographic projection of each third reset signal line Vint3 on the substrate at least partially overlaps with the orthographic projection of the corresponding first reset control signal line rst1 on the substrate. In some embodiments, the orthographic projection of each third reset signal line Vint3 on the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the corresponding first reset control signal line rst1 on the substrate. The inventors of this disclosure have found that by providing such a structure, interference to components in other layers caused by the corresponding first reset control signal line rst1 can be reduced or prevented.

[0143] In some embodiments, each of the first reset control signal lines rst1 is located in the first gate metal layer, and each of the third reset signal lines Vint3 is located in the third gate metal layer.

[0144] Figure 12 It is shown Figure 3A The diagram depicts a schematic of the structure of the second signal line layer in the array substrate. In some embodiments, a plurality of fourth reset signal lines exist between column (4k-1) C(4k-1) and column (4k-2) C(4k-2). Optionally, the plurality of fourth reset signal lines do not exist between column (4k) C(4k) and column (4k-1) C(4k-1), nor between column (4k-2) C(4k-2) and column (4k-3) C(4k-3).

[0145] In some embodiments, the plurality of fourth reset signal lines include one or more fifth reset signal lines, one or more sixth reset signal lines, and one or more seventh reset signal lines arranged alternately.

[0146] Figure 13 This is a schematic diagram illustrating the structure of a reset signal network according to some embodiments of the present disclosure. (Refer to...) Figure 13In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in M ​​columns, where M is a positive integer; the M columns include the (12m-11)th column, the (12m-10)th column, the (12m-9)th column, the (12m-8)th column, the (12m-7)th column, the (12m-6)th column, the (12m-5)th column, the (12m-4)th column, the (12m-3)th column, the (12m-2)th column, the (12m-1)th column, and the 12mth column, where m is a positive integer, and 1≤m≤M / 12.

[0147] As used herein, the terms "column (12m-11)," "column (12m-10)," "column (12m-9)," "column (12m-8)," "column (12m-7)," "column (12m-6)," "column (12m-5)," "column (12m-4)," "column (12m-3)," "column (12m-2)," "column (12m-1)," and "column 12m" are used in the context of M columns. The array substrate may or may not include additional columns preceding the first column of the M columns and / or additional columns following the last column of the M columns. Against the backdrop of an array substrate, the terms "column (12m-11)," "column (12m-9)," "column (12m-7)," "column (12m-5)," "column (12m-3)," or "column (12m-1)" do not necessarily represent an odd-numbered column, and the terms "column (12m-10)," "column (12m-6)," "column (12m-4)," "column (12m-2)," or "column (12m)" do not necessarily represent an even-numbered column. In one example, column (12m-11) is an odd-numbered column against the backdrop of M columns, but can be an even-numbered column against the backdrop of an array substrate. In another example, column (12m-11) is an odd-numbered column against the backdrop of M columns, and is also an odd-numbered column against the backdrop of an array substrate. In one example, column (12m-10) is an even-numbered column against the backdrop of M columns, but can be an odd-numbered column against the backdrop of an array substrate. In another example, column (12m-10) is an even column against the background of M columns, and also an even column against the background of the array substrate. In one example, column (12m-9) is an odd column against the background of M columns, but can be an even column against the background of the array substrate. In another example, column (12m-9) is an odd column against the background of M columns, and also an odd column against the background of the array substrate. In one example, column (12m-8) is an even column against the background of M columns, but can be an odd column against the background of the array substrate. In another example, column (12m-8) is an even column against the background of M columns, and also an even column against the background of the array substrate. In one example, column (12m-7) is an odd column against the background of M columns, but can be an even column against the background of the array substrate. In another example, column (12m-7) is an odd column against the background of M columns, and also an odd column against the background of the array substrate. In one example, column (12m-6) is an even column against the background of M columns, but can be an odd column against the background of the array substrate. In another example, column (12m-6) is an even column against the background of M columns, and is also an even column against the background of the array substrate. In one example, column (12m-5) is an odd column against the background of M columns, but can be an even column against the background of the array substrate.In another example, column (12m-5) is an odd column against the background of M columns, and also an odd column against the background of the array substrate. In one example, column (12m-4) is an even column against the background of M columns, but can be an odd column against the background of the array substrate. In another example, column (12m-4) is an even column against the background of M columns, and also an even column against the background of the array substrate. In one example, column (12m-3) is an odd column against the background of M columns, but can be an even column against the background of the array substrate. In another example, column (12m-3) is an odd column against the background of M columns, and also an odd column against the background of the array substrate. In one example, column (12m-2) is an even column against the background of M columns, but can be an odd column against the background of the array substrate. In another example, column (12m-2) is an even column against the background of M columns, and also an even column against the background of the array substrate. In one example, column (12m-1) is an odd column against the background of M columns, but can be an even column against the background of the array substrate. In another example, column (12m-1) is an odd column against the background of M columns, and is also an odd column against the background of the array substrate. In one example, column (12m) is an even column against the background of M columns, but can be an odd column against the background of the array substrate. In another example, column (12m) is an even column against the background of M columns, and is also an even column against the background of the array substrate.

[0148] In some embodiments, one or more fifth reset signal lines exist between column (12m-9) C(12m-9) and column (12m-10) C(12m-10). Optionally, one or more fifth reset signal lines do not exist between column (12m) C(12m) and column (12m-1) C(12m-1), between column (12m-1) C(12m-1) and column (12m-2) C(12m-2), between column (12m-2) C(12m-2) and column (12m-3) C(12m-3), between column (12m-3) C(12m-3) and column (12m-4) C(12m-4), or between column (12m-4) C(12m-4) and column (12m-5) C(12m-10). Between -5), between column (12m-5) C(12m-5) and column (12m-6) C(12m-6), between column (12m-6) C(12m-6) and column (12m) C(12m-7), between column (12m-7) C(12m-7) and column (12m-8) C(12m-8), between column (12m-8) C(12m-8) and column (12m-9) C(12m-9), and between column (12m-10) C(12m-10) and column (12m-11) C(12m-11).

[0149] In some embodiments, one or more sixth reset signal lines exist between column (12m-5) C(12m-5) and column (12m-6) C(12m-6). Optionally, one or more sixth reset signal lines do not exist between column (12m) C(12m) and column (12m-1) C(12m-1), between column (12m-1) C(12m-1) and column (12m-2) C(12m-2), between column (12m-2) C(12m-2) and column (12m-3) C(12m-3), between column (12m-3) C(12m-3) and column (12m-4) C(12m-4), and between column (12m-4) C(12m-4) and column (12m-5) C(12m-5). Between (12m-6) and (12m-7) C(12m-7), between (12m-7) and (12m-8) C(12m-8), between (12m-8) and (12m-9) C(12m-9), between (12m-9) and (12m-10) C(12m-10), and between (12m-10) and (12m-11) C(12m-11).

[0150] In some embodiments, one or more seventh reset signal lines exist between column (12m-1) C(12m-1) and column (12m-2) C(12m-2). Optionally, one or more seventh reset signal lines do not exist between column (12m) C(12m) and column (12m-1) C(12m-1), between column (12m-2) C(12m-2) and column (12m-3) C(12m-3), between column (12m-3) C(12m-3) and column (12m-4) C(12m-4), between column (12m-4) C(12m-4) and column (12m-5) C(12m-5), or between column (12m-5) C(12m-5) and column (12m-6) C(12m-5). Between -6), between column (12m-6) C(12m-6) and column (12m-7) C(12m-7), between column (12m-7) C(12m-7) and column (12m) C(8m), between column (12m-8) C(12m-8) and column (12m-9) C(12m-9), between column (12m-9) C(12m-9) and column (12m-10) C(12m-10), and between column (12m-10) C(12m-10) and column (12m-11) C(12m-11).

[0151] In an alternative embodiment, a plurality of fourth reset signal lines (including one or more fifth reset signal lines, one or more sixth reset signal lines, and one or more seventh reset signal lines) are located on the first signal line layer. In an alternative embodiment, a plurality of fourth reset signal lines (including one or more fifth reset signal lines, one or more sixth reset signal lines, and one or more seventh reset signal lines) are alternately located on the first signal line layer and the second signal line layer.

[0152] Figure 14 This is a schematic diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 14 In some embodiments, the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines interconnected. Each of the plurality of first light-shielding lines LSL1 extends along a first direction DR1. Each of the plurality of second light-shielding lines LSL2 extends along a second direction DR2.

[0153] In some embodiments, each first light-shielding light LSL1 includes a plurality of light-shielding blocks connected by a plurality of bridges Br. In some embodiments, refer to Figures 3A to 3L The orthographic projection of each of the multiple light-shielding blocks LSBs on the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the active layer ACTd of the driving transistor Td on the substrate.

[0154] Figure 15 This is a schematic diagram illustrating a fourth reset signal line and a light-shielding layer according to some embodiments of the present disclosure. (Refer to...) Figure 3A , Figure 3C , Figure 3L , Figure 14 and Figure 15 In some embodiments, the orthographic projection of each of the plurality of fourth reset signal lines Vint4 onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the corresponding second shielding light LSL2 onto the substrate. The inventors of this disclosure have found that by providing this structure, the transmittance of the array substrate can be significantly improved compared to the associated array substrate.

[0155] In some embodiments, the ratio of the number of columns of the pixel driving circuit to the number of the plurality of second light-shielding rays is in the range of 1.8:1 to 2.2:1, for example, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, or 2.1:1 to 2.2:1. In one example, the ratio of the number of columns of the pixel driving circuit to the number of the plurality of second light-shielding rays is 2:1.

[0156] In some embodiments, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is in the range of 1.8:1 to 2.2:1, for example, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, or 2.1:1 to 2.2:1. In one example, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is 2:1.

[0157] In alternative embodiments, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of second light-shielding rays is in the range of 3.6:1 to 4.4:1, for example, 3.6:1 to 3.8:1, 3.8:1 to 4.0:1, 4.0:1 to 4.2:1, or 4.2:1 to 4.4:1. In one example, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of second light-shielding rays is 4:1.

[0158] In alternative embodiments, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is in the range of 3.6:1 to 4.4:1, for example, 3.6:1 to 3.8:1, 3.8:1 to 4.0:1, 4.0:1 to 4.2:1, or 4.2:1 to 4.4:1. In one example, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is 4:1.

[0159] In alternative embodiments, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of second light-shielding rays is in the range of 5.4:1 to 6.6:1, for example, 5.4:1 to 5.6:1, 5.6:1 to 5.8:1, 5.8:1 to 6.0:1, 6.0:1 to 6.2:1, 6.2:1 to 6.4:1, or 6.4:1 to 6.6:1. In one example, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of second light-shielding rays is 6:1.

[0160] In alternative embodiments, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is in the range of 5.4:1 to 6.6:1, for example, 5.4:1 to 5.6:1, 5.6:1 to 5.8:1, 5.8:1 to 6.0:1, 6.0:1 to 6.2:1, 6.2:1 to 6.4:1, or 6.4:1 to 6.6:1. In one example, the ratio of the number of columns of the pixel driving circuitry to the number of the plurality of fourth reset signal lines is 6:1.

[0161] The inventors of this disclosure have also discovered that the non-uniformity of the anode in an array substrate or display panel can adversely affect image display. For example, color shift may be caused by anode tilt. This disclosure finds that the signal lines beneath the anode can significantly affect the degree of anode tilt. In one example, a signal line is positioned on one side below the anode, while no signal line is present on the other side. This results in an uneven surface of the planarization layer above the signal lines. The uneven surface of the planarization layer, in turn, causes the anode above the planarization layer to tilt. The tilted anode reflects more light towards one side of the array substrate or display panel. In the array substrate or display panel, the tilted anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in sub-pixels of different colors is reflected at different angles to different colors of light. The cumulative effect of this problem leads to color shift at wide viewing angles.

[0162] Therefore, the array substrate of this disclosure employs a fine anode and signal line structure to achieve a flat surface of the planarization layer beneath the anode. This mitigates color shift issues. Figure 16 This is a schematic diagram illustrating the structure of the first signal line layer and the anode layer in an array substrate according to some embodiments of the present disclosure. Figure 17 This is a schematic diagram illustrating the structure of the first anode in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, the first anode AD1 includes four corner portions. In some embodiments, the first anode AD1 includes a first corner portion CR1, a second corner portion CR2, a third corner portion CR3, and a fourth corner portion CR4. The first corner portion CR1 is located on the side opposite to the second corner portion CR2, and the third corner portion CR3 is located on the side opposite to the fourth corner portion CR4. In some embodiments, the first anode AD1 also includes a central portion CP surrounded by the first corner portion CR1, the second corner portion CR2, the third corner portion CR3, and the fourth corner portion CR4.

[0163] In some embodiments, the first corner portion CR1 and the second corner portion CR2 are arranged in a direction substantially parallel to the second direction DR2. In some embodiments, the third corner portion CR3 and the fourth corner portion CR4 are arranged in a direction substantially parallel to the first direction DR1. As used herein, the term "substantially parallel" means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0164] Figure 18 This is a schematic diagram illustrating the structure of voltage connection pads in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 18In some embodiments, the voltage connection pad VCP includes a connector portion JP, a first branch portion BH1 connected to the connector portion JP, a second branch portion BH2 connected to the connector portion JP, and a third branch portion BH3 connected to the connector portion JP. Optionally, the connector portion JP is the portion of the voltage connection pad VCP that is connected to the second capacitor electrode Ce2 through a via. Optionally, the first branch portion BH1 is the portion of the voltage connection pad VCP that is connected to the first electrodes of two adjacent third transistors in the same row and two adjacent columns of pixel driving circuits. Optionally, the second branch portion BH2 and the third branch portion BH3 are portions of the voltage connection pad VCP that are respectively connected to two adjacent voltage supply lines among a plurality of voltage supply lines.

[0165] In some embodiments, the first branch portion BH1 extends in a direction substantially parallel to the second direction DR2. Optionally, at least a portion of the second branch portion BH2 extends in a direction substantially parallel to the first direction DR1. Optionally, at least a portion of the third branch portion BH3 extends in a direction substantially parallel to the first direction DR1.

[0166] Figure 19 This is a schematic diagram illustrating the structure of a third interconnect line in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 19 In some embodiments, the third connection line Cli3 includes a connection portion CTP, a first side portion SP1 connected to the connection portion CTP, a second side portion SP2 connected to the connection portion CTP, and an extension portion EP connected to the connection portion CTP. Optionally, the connection portion CTP is the portion of the third connection line Cli3 connected to a corresponding third reset signal line among a plurality of third reset signal lines. Optionally, the first side portion SP1 and the second side portion SP2 are the portions of the third connection line Cli3 connected to the first electrodes of two adjacent third reset transistors in the same row and two adjacent columns of pixel driving circuits.

[0167] In some embodiments, the connecting portion CTP and the extension portion EP are arranged in a direction substantially parallel to the second direction DR2. In some embodiments, the first side portion SP1, the connecting portion CTP, and the second side portion SP2 are arranged in a direction substantially parallel to the first direction DR1.

[0168] In some embodiments, refer to Figures 16 to 19 The orthographic projection of the first corner portion CR1 on the substrate at least partially overlaps with the orthographic projection of the third connecting line Cli3 on the substrate; the orthographic projection of the second corner portion CR2 on the substrate at least partially overlaps with the orthographic projection of the voltage connection pad VCP on the substrate; and the orthographic projection of the central portion CP on the substrate at least partially overlaps with the orthographic projection of the voltage connection pad VCP on the substrate.

[0169] In some embodiments, the orthographic projection of the first corner portion CR1 on the substrate at least partially overlaps with the orthographic projection of the connection portion CTP of the third connection line Cli3 on the substrate, and at least partially overlaps with the orthographic projection of the extension portion EP of the third connection line Cli3 on the substrate; the orthographic projection of the second corner portion CR2 on the substrate at least partially overlaps with the orthographic projection of the first branch portion BH1 of the voltage connection pad VCP on the substrate; and the orthographic projection of the center portion CP on the substrate at least partially overlaps with the orthographic projection of the first branch portion BH1 of the voltage connection pad VCP on the substrate.

[0170] In some embodiments, the orthographic projection of the third corner portion CR3 on the substrate at least partially overlaps with the orthographic projection of the second node connection line Cln2 in the pixel driving circuit of the first adjacent column pixel driving circuit on the substrate, and the orthographic projection of the fourth corner portion CR4 on the substrate at least partially overlaps with the orthographic projection of the second node connection line Cln2 in the pixel driving circuit of the second adjacent column pixel driving circuit on the substrate, wherein the first adjacent column pixel driving circuit and the second adjacent column pixel driving circuit are adjacent to each other.

[0171] Figure 20 This is a schematic diagram illustrating the structure of a second anode in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 20 In some embodiments, the second anode AD2 includes four corner portions. In some embodiments, the second anode AD2 includes a fifth corner portion CR5, a sixth corner portion CR6, a seventh corner portion CR7, and an eighth corner portion CR8. The fifth corner portion CR5 is located on the side opposite to the sixth corner portion CR6, and the seventh corner portion CR7 is located on the side opposite to the eighth corner portion CR8.

[0172] In some embodiments, the fifth corner portion CR5 and the sixth corner portion CR6 are arranged in a direction substantially parallel to the second direction DR2. In some embodiments, the seventh corner portion CR7 and the eighth corner portion CR8 are arranged in a direction substantially parallel to the first direction DR1.

[0173] In some embodiments, refer to Figure 16 , Figure 18 and Figure 20 The orthographic projection of the fifth corner portion CR5 on the substrate at least partially overlaps with the orthographic projection of the power connection pad SCP in the next row of the same column pixel driving circuit on the substrate; the orthographic projection of the sixth corner portion CR6 on the substrate at least partially overlaps with the orthographic projection of the connector portion JP of the voltage connection pad VCP on the substrate.

[0174] In some embodiments, the orthographic projection of the seventh corner portion CR7 on the substrate at least partially overlaps with the orthographic projection of the relay electrode RE in the pixel driving circuit of the third adjacent column pixel driving circuit on the substrate; the orthographic projection of the eighth corner portion CR8 on the substrate at least partially overlaps with the orthographic projection of the relay electrode RE in the pixel driving circuit of the fourth adjacent column pixel driving circuit on the substrate, wherein the third adjacent column pixel driving circuit and the fourth adjacent column pixel driving circuit are adjacent to each other.

[0175] In some embodiments, the orthographic projection of the second anode AD2 onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the second node connection line in two adjacent column pixel driving circuits onto the substrate.

[0176] In some embodiments, the orthographic projection of the second anode AD2 onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthographic projection of the first branch portion BH1 of the voltage connection pad VCP onto the substrate.

[0177] In some embodiments, the orthogonal projection of the second anode AD2 onto the substrate substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers the orthogonal projection of the third connection line Cli3 onto the substrate.

[0178] Figure 21A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 21AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line G among a plurality of second gate lines. The transistor T2 has a gate, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding first voltage supply line Vdd among a plurality of first voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 has a gate connected to each light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to a corresponding reference signal line Vref among a plurality of reference signal lines.

[0179] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0180] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0181] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of the form S1-S2-S3, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 form is a C1-C2-C3 form, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 form is an RGB form, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0182] In another example, the array of multiple sub-pixels includes a repeating array of the form S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 form is C1-C2-C3-C4, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In yet another example, the S1-S2-S3-S4 form is C1-C2-C3-C2', where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C2' represents each fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2' form is RGBG, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0183] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0184] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0185] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 21AThe second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0186] Figure 21B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 21A and Figure 21B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light-emitting sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to turn off. In the initial sub-stage t0, a cutoff signal is provided to the first gate line GL1, therefore the first transistor T1 is turned off.

[0187] In reset phase t1, the turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, turning on the first reset transistor Tr1; this causes the initialization voltage signal from the corresponding first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and then to node N4. The anode of the light-emitting element LE is initialized. The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1, turning on the third reset transistor Tr3; this causes the initialization voltage signal from the corresponding third reset signal line Vint3 to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding reference signal line Vref. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During reset phase t1, a cutoff signal is provided to the corresponding first gate line GL1, thus turning off the first transistor T1. A high voltage signal is provided to the corresponding light-emitting control signal line em, causing the third transistor T3 and the fourth transistor T4 to turn off.

[0188] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2, turning on the second reset transistor Tr2. This causes the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to its second electrode, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is then initialized.

[0189] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing the first reset transistor Tr1 and the third reset transistor Tr3 to be turned off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level of node N1 gradually rises to (Vdata + Vth) during the data write sub-stage t2, where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0190] In the light-emitting phase t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, causing the second reset transistor Tr2 to turn off. A cutoff reset control signal is also provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, causing both the first and third reset transistors Tr1 and Tr3 to turn off. Cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, respectively, turning off the first transistor T1 and the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em, turning on the third transistor T3 and the fourth transistor T4. The voltage level of node N1 is maintained at (Vdata + Vth) in the light-emitting phase t3, and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0191] Figure 22A This is a schematic diagram illustrating the structure of a pixel driving circuit in a portion of an array substrate according to some embodiments of the present disclosure. Figure 22B It is shown Figure 22A The diagram depicts the arrangement of pixel driving circuits in an array substrate. Figure 22A and Figure 22B A portion of an array substrate with four adjacent pixel driving circuits (including PDC1, PDC2, PDC3 and PDC4) is depicted.

[0192] Figure 22C It is shown Figure 22A A schematic diagram of the structure of the light-shielding layer in the array substrate is depicted. Figure 22D It is shown Figure 22A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted. Figure 22E It is shown Figure 22A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted. Figure 22F It is shown Figure 22A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 22G It is shown Figure 22A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted. Figure 22H It is shown Figure 22A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 22I It is shown Figure 22AA schematic diagram of the structure of the passivation layer in the array substrate is shown in the figure. Figure 22J It is shown Figure 22A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 22K It is shown Figure 22A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted. Figure 22L It is shown Figure 22A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 23 It is along Figure 22A A cross-sectional view of line B-B' in the diagram.

[0193] Reference Figures 22A to 22L and Figure 23 In some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; and a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate insulating layer. One side of the metal layer Gate2; the second interlayer dielectric layer ILD2, located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second planarization layer SD2, located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; and the second planarization layer PLN2, located on the side of the second signal line layer SD2 away from the first planarization layer PLN1.

[0194] Reference Figure 2A , Figure 22A , Figure 22C and Figure 23 In some embodiments, the light-shielding layer LSL includes a light-shielding element LS. In some embodiments, the light-shielding element LS is an integral structure extending across a plurality of sub-pixels.

[0195] Reference Figure 2A , Figure 22A , Figure 22D and Figure 23 In some embodiments, the first semiconductor material layer SML1 includes at least an active layer of a plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td). Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode for a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0196] exist Figure 22D In the middle, the corresponding numbers are marked. Figure 22B The pixel driving circuit of PDC2 is labeled with reference numerals to indicate components of each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0197] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACTr3 and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3 and Sd) and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0198] In some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure. Optionally, the portion of the second reset transistor Tr2 located in the first semiconductor material layer (ACTr2, Sr2, Dr2) is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td) in the same pixel driving circuit. Figure 22D As shown, in some embodiments, at least a portion of the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of a plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in two adjacent pixel driving circuits, at least a portion of the first electrode (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrode (D1, D3, D4, Dr1, Dr3, and Dd) are part of the overall structure.

[0199] Reference Figure 2A , Figure 22A , Figure 22E and Figure 23 In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of light emission control signal lines (e.g., each light emission control signal line em), and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0200] Reference Figure 2A , Figure 22A , Figure 22F and Figure 23In some embodiments, the second gate metal layer Gate2 includes at least a portion of a plurality of second gate lines (e.g., first branches GL2-1 of each second gate line), a plurality of second reset signal lines (e.g., each second reset signal line Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit.

[0201] Reference Figure 2A , Figure 22A , Figure 22G and Figure 23 In some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2 of the second transistor T2, the first electrode S2, and the second electrode D2. In the array substrate of this disclosure, the at least active layer ACT2 of the second transistor T2 is located in a layer different from the at least active layers of other transistors in the pixel driving circuit.

[0202] exist Figure 22G In the middle, the corresponding numbers are marked. Figure 22B The pixel driving circuit of PDC2 is indicated by the label, which indicates the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are located on the same layer.

[0203] Reference Figure 2A , Figure 22A , Figure 22H and Figure 23 In some embodiments, the third gate metal layer Gate3 includes at least a portion of a plurality of second gate lines (e.g., second branches GL2-2 of each second gate line), a plurality of first reset signal lines (e.g., each first reset signal line Vint1), and a plurality of third reset signal lines (e.g., each third reset signal line Vint3).

[0204] Figure 22I It shows the extension through Figure 22A The vias in the passivation layer of the array substrate are depicted.

[0205] Reference Figure 2A , Figure 22A , Figure 22J and Figure 23In some embodiments, the first signal line layer SD1 includes: a plurality of first power lines (e.g., each first power line Vss1); a voltage connection pad VCP; a data connection pad DCP; a reference signal connection pad RCP; a first node connection line Cln1; a second node connection line Cln2; a third node connection line Cln3; a relay electrode RE; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3.

[0206] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (Refer to...) Figure 23 The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the first electrode S2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 is depicted in the diagram.

[0207] Reference Figure 2A , Figure 22A , Figure 22E , Figure 22F and Figure 23 In some embodiments, a portion of the second capacitor electrode Ce2 is absent from the via region H. Optionally, except for the via region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the via region H, and the insulating layer IN.

[0208] In some embodiments, the first node connection line Cln1 intersects with a corresponding second gate line among a plurality of second gate lines. For example... Figure 22A and Figure 23 As shown, the first node connection line Cln1 intersects with the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0209] In some embodiments, the second node connection line Cln2 connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode Dr3 of the third reset transistor Tr3, the second electrode D3 of the third transistor T3, and the first electrode Sd of the driving transistor Td.

[0210] In some embodiments, the third node connection line Cln3 is connected to the second electrode Dd of the driving transistor Td, to the second electrode Dr2 of the second reset transistor Tr2, and to the first electrode S4 of the fourth transistor T4.

[0211] In some embodiments, a first reset signal connection line Cli1 connects a corresponding first reset signal line Vint1 among a plurality of first reset signal lines to a first electrode Sr1 of a first reset transistor Tr1. The first reset signal connection line Cli1 is configured to transmit a reset signal from the corresponding first reset signal line Vint1 to the first electrode Sr1 of the first reset transistor Tr1.

[0212] In some embodiments, the second reset signal connection line Cli2 connects a corresponding second reset signal line Vint2 among a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Cli2 is configured to transmit a reset signal from the corresponding second reset signal line Vint2 to the first electrode Sr2 of the second reset transistor Tr2.

[0213] In some embodiments, the third reset signal connection line Cli3 connects a corresponding third reset signal line Vint3 among a plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor Tr3. The third reset signal connection line Cli3 is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In one example, the third reset signal connection line Cli3 is connected to the first electrode of the third reset transistor of two adjacent pixel driving circuits in the same row, and is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode of the third reset transistor of the two adjacent pixel driving circuits in the same row.

[0214] Figure 22K It shows the extension through Figure 22A The vias in the first planarization layer of the array substrate are depicted in the figure.

[0215] Reference Figure 2A , Figure 22A , Figure 22B , Figure 22L and Figure 23 In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., each first voltage supply line Vdd), a plurality of reference signal lines (e.g., each reference signal line Vref), an anode contact pad ACP, a plurality of data lines (e.g., each data line DL), and a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vint4).

[0216] In some embodiments, refer to Figures 22A to 22L and Figure 23 The relay electrode RE is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) and to the anode contact pad ACP. In one example, the anode contact pad ACP is located on the second signal line layer SD2, and the relay electrode RE is located on the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the relay electrode RE via a via extending through the first planarization layer PLN1, and the relay electrode RE2 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0217] In some embodiments, the data connection pad DCP is connected to the first electrode S1 of the first transistor T1 and to a corresponding data line DL among a plurality of data lines. In one example, the data connection pad DCP is located on the first signal line layer SD1, and the corresponding data line DL is located on the second signal line layer SD2. In another example, the corresponding data line DL is connected to the data connection pad DCP via a via extending through the first planarization layer PLN1, and the data connection pad DCP is connected to the first electrode S1 of the first transistor T1 via a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0218] In some embodiments, each of the plurality of first voltage supply lines Vdd is connected to a voltage connection pad VCP, which is connected to a first electrode of a third transistor T3, thereby providing a voltage supply signal to the first electrode of the third transistor T3.

[0219] In some embodiments, the voltage connection pad VCP is connected to the first electrode of a third transistor in two adjacent pixel drive circuits in the same row.

[0220] In some embodiments, refer to Figures 22A to 22L The first pixel driving circuits that are directly adjacent to each other and in the current level (e.g., in the same row) Figure 22C The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 22C The corresponding layer of PDC2 in the array has, for example, a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines and has substantially mirror symmetry with respect to each other (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or perfectly symmetrical).

[0221] Figure 24 This is a schematic diagram illustrating a reference signal network according to some embodiments of the present disclosure. (Refer to...) Figure 24 In some embodiments, the reference signal network includes a plurality of reference signal lines and a plurality of second reference signal lines. Optionally, each of the plurality of reference signal lines, Vref, extends along a second direction DR2. Optionally, each of the plurality of second reference signal lines, Vref2, extends along a first direction DR1. Optionally, each second reference signal line Vref2 includes a plurality of second capacitor electrodes from a plurality of storage capacitors in a plurality of pixel driving circuits in the same row.

[0222] In some embodiments, each reference signal line Vref is connected to at least one of a plurality of second reference signal lines; each second reference signal line Vref2 is connected to at least one of a plurality of reference signal lines.

[0223] In some embodiments, the reference signal network further includes a reference signal connection pad (RCP). Each reference signal line (Vref) is connected to the reference signal connection pad (RCP) via a via, and the reference signal connection pad (RCP) is connected to the corresponding second reference signal line (Vref2) via a via.

[0224] In some embodiments, a plurality of reference signal lines are located on a second signal line layer, a plurality of second reference signal lines are located on a second gate metal layer, and a reference signal connection pad (RCP) is located on a first signal line layer.

[0225] In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4).

[0226] In some embodiments, multiple reference signal lines exist between column (4k) C(4k) and column (4k-1) C(4k-1), and between column (4k-2) C(4k-2) and column (4k-3) C(4k-3). Optionally, multiple reference signal lines do not exist between column (4k-1) C(4k-1) and column (4k-2) C(4k-2).

[0227] In some embodiments, the ratio of the number of columns of the pixel driving circuit to the number of the plurality of reference signal lines is in the range of 1.8:1 to 2.2:1, for example, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, or 2.1:1 to 2.2:1. In one example, the ratio of the number of columns of the pixel driving circuit to the number of the plurality of reference signal lines is 2:1.

[0228] Figure 25 This is a schematic diagram illustrating a voltage supply network according to some embodiments of the present disclosure. (Refer to...) Figure 25 In some embodiments, the voltage supply network includes a plurality of interconnected voltage supply lines and a plurality of second voltage supply lines. Each of the plurality of voltage supply lines, Vdd, extends along a second direction DR2. Each of the plurality of second voltage supply lines, Vdd2, extends along a first direction DR1. Each voltage supply line Vdd is connected to at least one of the plurality of second voltage supply lines. Each second voltage supply line Vdd2 is connected to at least one of the plurality of voltage supply lines.

[0229] In some embodiments, a plurality of voltage supply lines are located on a second signal line layer, and a plurality of second voltage supply lines are located on a first signal line layer.

[0230] In addition to multiple voltage supply lines, multiple reference signal lines are also provided to electrically isolate the first electrode of the third transistor from the second capacitor electrode of the storage capacitor. The use of multiple reference signal lines stabilizes the voltage at the second capacitor electrode of the storage capacitor, thereby minimizing the impact on the voltage drop across the array substrate.

[0231] Multiple voltage supply lines have a significant impact on the voltage drop of the array substrate. The inventors of this disclosure have discovered that by incorporating multiple second voltage supply lines in a first signal line layer made of a metal with relatively high conductivity, the load on the voltage supply network can be reduced. The multiple voltage supply signal lines in the second signal line layer have relatively large linewidths, resulting in a smaller load.

[0232] In an alternative embodiment, the first electrode of the third transistor in the pixel driving circuit, which is configured to drive light-emitting elements of different colors, is connected to voltage supply lines that are electrically isolated from each other.

[0233] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0234] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a light-shielding layer on a substrate; and forming a second signal line layer on a side of the light-shielding layer away from the substrate. Optionally, forming the light-shielding layer includes: forming a plurality of first light-shielding lines and a plurality of second light-shielding lines interconnected with each other. Optionally, each of the plurality of first light-shielding lines extends along a first direction. Optionally, each of the plurality of second light-shielding lines extends along a second direction. Optionally, forming the second signal line layer includes: forming a plurality of fourth reset signal lines. Optionally, each of the plurality of fourth reset signal lines extends along a second direction. Optionally, the orthographic projection of each fourth reset signal line on the substrate substantially covers the orthographic projection of the corresponding second light-shielding line on the substrate.

[0235] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: Substrate; A light-shielding layer is located on the substrate. as well as The second signal line layer is located on the side of the light-shielding layer away from the substrate. The light-shielding layer includes a plurality of first light-shielding rays and a plurality of second light-shielding rays that are connected together. Each of the plurality of first shielding rays extends along a first direction; Each of the plurality of second shielding rays extends along a second direction; The second signal line layer includes multiple fourth reset signal lines; Each of the plurality of fourth reset signal lines extends along the second direction; and The orthogonal projection of each of the fourth reset signal lines on the substrate substantially covers the orthogonal projection of the corresponding second shielding light on the substrate.

2. The array substrate according to claim 1, wherein, Each of the first light-shielding lines includes multiple light-shielding blocks connected by multiple bridges; and The orthographic projection of each of the plurality of light-shielding blocks on the substrate substantially covers the orthographic projection of the active layer of the driving transistor on the substrate.

3. The array substrate according to claim 1, wherein, The ratio of the number of columns of the pixel driving circuit to the number of the plurality of second light-blocking rays is in the range of 1.8:1 to 2.2:1; as well as The ratio of the number of columns of the pixel driving circuit to the number of the plurality of fourth reset signal lines is in the range of 1.8:1 to 2.2:

1.

4. The array substrate according to any one of claims 1 to 3, further comprising a power supply network; in, The power network includes a plurality of first power lines, a plurality of second power lines, and power connection pads; Each of the plurality of first power lines extends along the first direction; Each of the plurality of second power lines extends along the second direction; Each of the second power lines comprises multiple segments spaced apart from each other; Two adjacent segments of the plurality of segments of each second power line are connected to the power connection pad; The plurality of first power lines are located in the first signal line layer; The plurality of second power lines are located in the second signal line layer; and The power connection pad is located on the first signal line layer.

5. The array substrate according to any one of claims 1 to 3, further comprising a power supply network; in, The power network includes multiple second power lines; The array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); The plurality of second power lines exist between the (4k)th column and the (4k-1)th column, and between the (4k-2)th column and the (4k-3)th column; and The plurality of second power lines are not present between the (4k-1)th column and the (4k-2)th column.

6. The array substrate according to any one of claims 1 to 3, further comprising: Multiple first reset signal lines located in the third gate metal layer; as well as A power network comprising a plurality of first power lines located on a first signal line layer, the first signal line layer being located on the side of the third gate metal layer away from the substrate. Wherein, the orthographic projection of each of the plurality of first reset signal lines on the substrate substantially covers the orthographic projection of the corresponding first power line among the plurality of first power lines on the substrate.

7. The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth reset signal lines located in the second signal line layer; in, The array substrate includes a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); The plurality of fourth reset signal lines exist between the (4k-1)th column and the (4k-2)th column; and The plurality of fourth reset signal lines are not present between the (4k)th column and the (4k-1)th column, nor between the (4k-2)th column and the (4k-3)th column.

8. The array substrate according to claim 7, wherein, The plurality of fourth reset signal lines includes one or more fifth reset signal lines; The array substrate includes a second reset signal network; The second reset signal network includes a plurality of second reset signal lines interconnected with each other and the one or more fifth reset signal lines; Each of the one or more fifth reset signal lines is connected to at least one of the plurality of second reset signal lines; Each of the plurality of second reset signal lines is connected to at least one of the one or more fifth reset signal lines; The plurality of second reset signal lines are located in the second gate metal layer; and The one or more fifth reset signal lines are located in the second signal line layer, which is located on the side of the second gate metal layer away from the substrate.

9. The array substrate according to claim 7, wherein, The plurality of fourth reset signal lines includes one or more sixth reset signal lines; The array substrate includes a first reset signal network; The first reset signal network includes a plurality of first reset signal lines and one or more sixth reset signal lines that are interconnected. Each of the one or more sixth reset signal lines is connected to at least one of the plurality of first reset signal lines; Each of the plurality of first reset signal lines is connected to at least one of the one or more sixth reset signal lines; The plurality of first reset signal lines are located in the third gate metal layer; and The one or more sixth reset signal lines are located in the second signal line layer, which is located on the side of the third gate metal layer away from the substrate.

10. The array substrate according to claim 9, further comprising a plurality of second reset control signal lines located in a first gate metal layer, wherein the first gate metal layer is located on the side of the third gate metal layer closer to the substrate; in, The orthographic projection of each of the first reset signal lines on the substrate substantially covers the orthographic projection of the corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

11. The array substrate according to claim 7, wherein, The plurality of fourth reset signal lines includes one or more seventh reset signal lines; The array substrate includes a third reset signal network; The third reset signal network includes a plurality of third reset signal lines and one or more seventh reset signal lines that are interconnected. Each of the one or more seventh reset signal lines is connected to at least one of the plurality of third reset signal lines; Each of the plurality of third reset signal lines is connected to at least one of the one or more seventh reset signal lines; The plurality of third reset signal lines are located in the third gate metal layer; and The one or more seventh reset signal lines are located in the second signal line layer, which is located on the side of the third gate metal layer away from the substrate.

12. The array substrate according to claim 11, further comprising a plurality of first reset control signal lines located in a first gate metal layer, wherein the first gate metal layer is located on the side of the third gate metal layer closer to the substrate. in, The orthographic projection of each of the third reset signal lines on the substrate substantially covers the orthographic projection of the corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate.

13. The array substrate according to claim 7, wherein, The plurality of fourth reset signal lines include one or more fifth reset signal lines, one or more sixth reset signal lines, and one or more seventh reset signal lines; The array substrate includes multiple pixel driving circuits arranged in M ​​columns, where M is a positive integer; the M columns include the (12m-11)th column, the (12m-10)th column, the (12m-9)th column, the (12m-8)th column, the (12m-7)th column, the (12m-6)th column, the (12m-5)th column, the (12m-4)th column, the (12m-3)th column, the (12m-2)th column, the (12m-1)th column, and the 12mth column, where m is a positive integer, and 1 ≤ m ≤ M / 12; The one or more fifth reset signal lines are located between the (12m-9)th column and the (12m-10)th column; The one or more sixth reset signal lines are located between the (12m-5)th column and the (12m-6)th column; and The one or more seventh reset signal lines are located between the (12m-1)th column and the (12m-2)th column.

14. The array substrate according to any one of claims 1 to 3, further comprising a plurality of reference signal lines and a plurality of voltage supply lines; in, Each of the plurality of reference signal lines is connected to the second capacitor electrode of the storage capacitor in the pixel driving circuit. as well as Each of the plurality of voltage supply lines is connected to the first electrode of the third transistor in the pixel driving circuit.

15. The array substrate according to claim 14, further comprising a reference signal network; in, The reference signal network includes a plurality of reference signal lines and a plurality of second reference signal lines that are interconnected. Each of the reference signal lines extends along the second direction; Each of the plurality of second reference signal lines extends along the first direction; Each of the second reference signal lines includes multiple second capacitor electrodes from multiple storage capacitors in multiple pixel driving circuits in the same row; Each reference signal line is connected to at least one of the plurality of second reference signal lines; as well as Each of the second reference signal lines is connected to at least one of the plurality of reference signal lines.

16. The array substrate according to claim 15, further comprising a reference signal connection pad located on the first signal line layer; in, Each reference signal line is connected to the reference signal connection pad via a via; The reference signal connection pad is connected to the corresponding second reference signal line via a via; and The plurality of second reference signal lines are located in a second gate metal layer, which is located on the side of the first signal line layer closer to the substrate.

17. The array substrate according to claim 14, comprising a plurality of pixel driving circuits arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); The plurality of reference signal lines exist between the (4k)th column and the (4k-1)th column, and between the (4k-2)th column and the (4k-3)th column; and The plurality of reference signal lines do not exist between the (4k-1)th column and the (4k-2)th column.

18. The array substrate according to claim 14, further comprising a voltage supply network; in, The voltage supply network includes a plurality of voltage supply lines and a plurality of second voltage supply lines that are interconnected. Each voltage supply line extends along the second direction; Each of the plurality of second voltage supply lines extends along the first direction. Each voltage supply line is connected to at least one of the plurality of second voltage supply lines; Each of the second voltage supply lines is connected to at least one of the plurality of voltage supply lines; as well as The plurality of second voltage supply lines are located in the first signal line layer, which is located on the side of the second signal line layer closer to the substrate.

19. The array substrate according to any one of claims 1 to 18, further comprising a first anode, a voltage connection pad, and a third connection line; in, The first anode includes a first corner portion, a second corner portion, a third corner portion, a fourth corner portion, and a central portion; The voltage connection pad includes a connector portion, a first branch portion connected to the connector portion, a second branch portion connected to the connector portion, and a third branch portion connected to the connector portion; The third connecting line includes a connecting portion, a first side portion connected to the connecting portion, a second side portion connected to the connecting portion, and an extension portion connected to the connecting portion; The orthographic projection of the first corner portion on the substrate at least partially overlaps with the orthographic projection of the connecting portion of the third connecting line on the substrate, and at least partially overlaps with the orthographic projection of the extended portion of the third connecting line on the substrate; The orthographic projection of the second corner portion on the substrate at least partially overlaps with the orthographic projection of the first branch portion of the voltage connection pad on the substrate; as well as The orthographic projection of the central portion onto the substrate at least partially overlaps with the orthographic projection of the first branch portion of the voltage connection pad onto the substrate.

20. A display device comprising an array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

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