Display panel and display device

Abstract

According to the display panel and the display device, a display area of the display panel comprises a first display area and a second display area, the second display area is located on one side of the first display area in the row direction, and the display panel comprises a substrate, a plurality of pixel driving circuits, a data line and an electrode layer. The plurality of pixel driving circuits are located in a display area of the display panel, and orthographic projections of the plurality of pixel driving circuits on the substrate are distributed in an array mode in the row-column direction; orthographic projections of the data lines on the substrate extend in the column direction, and the data lines are used for providing data signals for the pixel driving circuits located in the same column; the electrode layer comprises a plurality of electrode parts, and at least partial structures of the electrode parts are used for forming first electrodes of the light-emitting units; wherein the pixel driving circuits located in the first display area are correspondingly provided with one electrode part, at least part of the pixel driving circuits located in the second display area are correspondingly provided with a plurality of electrode parts, and the pixel driving circuits are used for providing driving currents for the corresponding electrode parts.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. BACKGROUND

[0002] In the related art, in some special light emitting unit distribution modes, the number of light emitting units in the regions on the left and right sides of the display panel is greater than the number of pixel driving circuits, so that some light emitting units cannot be normally driven.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] According to an aspect of the present disclosure, a display panel is provided, wherein a display area of the display panel includes a first display area and a second display area located on one side of the first display area in a row direction, and the display panel includes:

[0006] a substrate substrate;

[0007] a plurality of pixel driving circuits located in the display area of the display panel, and the orthogonal projection of the plurality of pixel driving circuits on the substrate substrate is arrayed in a row-column direction;

[0008] a data line, the orthogonal projection of which on the substrate substrate extends in a column direction, and the data line is configured to provide a data signal to a plurality of pixel driving circuits located in the same column;

[0009] an electrode layer including a plurality of electrode portions, at least part of the structure of the electrode portions being configured to form a first electrode of a light emitting unit;

[0010] wherein one electrode portion is provided for a pixel driving circuit located in the first display area, and a plurality of electrode portions are provided for at least part of the pixel driving circuits located in the second display area, and the pixel driving circuit is configured to provide a driving current to the electrode portion corresponding thereto.

[0011] In an exemplary embodiment of the present disclosure, the plurality of electrode portions include a first electrode portion and a second electrode portion, and the first electrode portion and the second electrode portion are respectively configured to form a first electrode of a light emitting unit of different colors;

[0012] the plurality of first electrode portions and the plurality of second electrode portions form a plurality of columns of multi-color electrode portions, and the plurality of columns of multi-color electrode portions include first electrode portions and second electrode portions distributed in a column direction;

[0013] In at least two columns of the plurality of multi-color electrode part columns, the first electrode part in different multi-color electrode part columns is connected to the same column of pixel driving circuit, and the second electrode part in different multi-color electrode part columns is connected to another column of pixel driving circuit.

[0014] In an example embodiment of the present disclosure, the plurality of multi-color electrode part columns includes a first multi-color electrode part column, and the first multi-color electrode part column is located at the outermost side of the plurality of electrode parts in the row direction.

[0015] The first electrode part in the first multi-color electrode part column is connected to the first electrode part in other multi-color electrode part columns, and the second display area includes the area where the pixel driving circuit connected to the first electrode part in the first multi-color electrode part column is located.

[0016] Alternatively, the second electrode part in the first multi-color electrode part column is connected to the second electrode part in other multi-color electrode part columns, and the second display area includes the area where the pixel driving circuit connected to the second electrode part in the first multi-color electrode part column is located.

[0017] In an example embodiment of the present disclosure, the plurality of multi-color electrode part columns includes two first multi-color electrode part columns, and the two first multi-color electrode part columns form a first sub multi-color electrode part column and a second sub multi-color electrode part column, respectively.

[0018] The first sub multi-color electrode part column and the second sub multi-color electrode part column are respectively located at the outermost side of the plurality of electrode parts in the row direction.

[0019] The first electrode part in the first sub multi-color electrode part column is connected to the first electrode part outside the first sub multi-color electrode part column.

[0020] The second electrode part in the second sub multi-color electrode part column is connected to the second electrode part outside the second sub multi-color electrode part column.

[0021] The second display area includes a first sub display area and a second sub display area, and the first sub display area and the second sub display area are respectively located on both sides of the first display area in the row direction. The first sub display area is located in the area where the pixel driving circuit connected to the first electrode part in the first sub multi-color electrode part column is located, and the second sub display area is located in the area where the pixel driving circuit connected to the second electrode part in the second sub multi-color electrode part column is located.

[0022] In an example embodiment of the present disclosure, the first electrode part and the second electrode part are arrayed in the row and column direction in the orthographic projection on the substrate, and the plurality of first electrode parts and the plurality of second electrode parts in the same row form a multi-color electrode part row, and the plurality of first electrode parts and the plurality of second electrode parts in the same column form the multi-color electrode part column.

[0023] The first electrode portion and the second electrode portion in the same multi-color electrode portion row are alternately arranged along the row direction in the orthographic projection on the substrate.

[0024] The first electrode portion and the second electrode portion in the same multi-color electrode portion column are alternately arranged along the column direction in the orthographic projection on the substrate.

[0025] The first electrode portion in the first multi-color electrode portion column and the first electrode portion connected thereto are respectively located in adjacent multi-color electrode portion rows and are respectively located in two multi-color electrode portion columns which are separated by one multi-color electrode portion column.

[0026] The second electrode portion in the first multi-color electrode portion column and the second electrode portion connected thereto are respectively located in adjacent multi-color electrode portion rows and are respectively located in two multi-color electrode portion columns which are separated by one multi-color electrode portion column.

[0027] In an example embodiment of the present disclosure, the first electrode portions and the second electrode portions are arrayed along the row and column directions in the orthographic projection on the substrate, the first electrode portions in the same row form a multi-color electrode portion row, and the second electrode portions in the same row form a multi-color electrode portion row.

[0028] The first electrode portion and the second electrode portion in the same multi-color electrode portion row are alternately arranged along the row direction in the orthographic projection on the substrate.

[0029] The first electrode portion and the second electrode portion in the same multi-color electrode portion column are alternately arranged along the column direction in the orthographic projection on the substrate.

[0030] The first electrode portion in the first multi-color electrode portion column and the first electrode portion connected thereto are respectively located in the same multi-color electrode portion row and are respectively located in two multi-color electrode portion columns which are separated by one multi-color electrode portion column.

[0031] The second electrode portion in the first multi-color electrode portion column and the second electrode portion connected thereto are respectively located in the same multi-color electrode portion row and are respectively located in two multi-color electrode portion columns which are separated by one multi-color electrode portion column.

[0032] In an example embodiment of the present disclosure, the first electrode portion in the first multi-color electrode portion column and the first electrode portion in other multi-color electrode portion columns are connected in the same layer.

[0033] The second electrode portion in the first multi-color electrode portion column and the second electrode portion in other multi-color electrode portion columns are connected in the same layer.

[0034] In an example embodiment of the present disclosure, the display panel further comprises:

[0035] A pixel defining layer is located on a side of the electrode layer away from the substrate, and a plurality of pixel openings are formed on the pixel defining layer;

[0036] The electrode portion includes a body portion, the pixel opening and the body portion are correspondingly arranged, and a projection of the body portion on the substrate and a projection of the corresponding pixel opening on the substrate coincide;

[0037] In the first electrode portion in the first multi-color electrode portion column and the first electrode portion connected thereto, the area of the projection of the body portion on the substrate in the two first electrode portions is different;

[0038] In the second electrode portion in the first multi-color electrode portion column and the second electrode portion connected thereto, the area of the projection of the body portion on the substrate in the two second electrode portions is different.

[0039] In an example embodiment of the present disclosure, the electrode layer further includes a connecting portion, the connecting portion is connected between the electrode portion and the pixel driving circuit;

[0040] Among them, the connecting portion corresponding to the same color light emitting unit has the same or approximately the same extension length on the substrate.

[0041] In an example embodiment of the present disclosure, the plurality of electrode portions include a first electrode portion and a second electrode portion, the first electrode portion and the second electrode portion are respectively used to form a first electrode of a light emitting unit of different colors;

[0042] The plurality of first electrode portions and the plurality of second electrode portions form a plurality of multi-color electrode portion rows, the multi-color electrode portion rows include the first electrode portions and the second electrode portions distributed along a row direction;

[0043] The electrode layer further includes a connecting portion, the connecting portion is connected between the electrode portion and the pixel driving circuit;

[0044] In the two adjacent multi-color electrode portion rows, the connecting portion connected by the first electrode portion or the second electrode portion in one multi-color electrode portion row forms a first connecting portion, and the connecting portion connected by the first electrode portion or the second electrode portion in the other multi-color electrode portion row forms a second connecting portion;

[0045] The first connecting portion includes a first extension segment and a second extension segment, and the projection of the first extension segment and the second extension segment on the substrate has an included angle greater than or equal to 95° and less than or equal to 180°;

[0046] The second connecting portion includes a third extending segment and a fourth extending segment, and an included angle of the third extending segment and the fourth extending segment in the orthographic projection on the substrate is less than or equal to 90°.

[0047] In an example embodiment of the present disclosure, the plurality of electrode portions include a first electrode portion and a second electrode portion, and the first electrode portion and the second electrode portion are respectively used to form a first electrode of a light-emitting unit of different colors.

[0048] The plurality of first electrode portions and the plurality of second electrode portions form a plurality of rows of multi-color electrode portions, and the rows of multi-color electrode portions include the first electrode portions and the second electrode portions distributed along a row direction.

[0049] The electrode layer further includes a connecting portion connected between the electrode portion and the pixel driving circuit.

[0050] In the same row of multi-color electrode portions, the orthographic projection of the first electrode portion and the second electrode portion on the substrate is located on the same side of the orthographic projection of the connecting portion connected thereto on the substrate.

[0051] In an example embodiment of the present disclosure, the connecting portion and the electrode portion are connected in the same layer.

[0052] In an example embodiment of the present disclosure, the plurality of electrode portions further include a third electrode portion, and the first electrode portion, the second electrode portion, and the third electrode portion are respectively used to form a first electrode of a light-emitting unit of different colors.

[0053] The orthographic projection of the plurality of third electrode portions on the substrate is arrayed along a row-column direction, and a plurality of third electrode portions in the same row form a row of single-color electrode portions, and a plurality of third electrode portions in the same column form a column of single-color electrode portions.

[0054] The orthographic projection of the plurality of first electrode portions and the plurality of second electrode portions on the substrate is arrayed along a row-column direction, a plurality of first electrode portions and a plurality of second electrode portions in the same row form a row of multi-color electrode portions, and a plurality of first electrode portions and a plurality of second electrode portions in the same column form a column of multi-color electrode portions.

[0055] In the same row of multi-color electrode portions, the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second electrode portion on the substrate are sequentially and alternately distributed along the row direction.

[0056] In the same column of multi-color electrode portions, the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second electrode portion on the substrate are sequentially and alternately distributed along the column direction.

[0057] The orthogonal projection of the single-color electrode part column on the substrate substrate is at least partially located between the orthogonal projection of two adjacent multi-color electrode part columns on the substrate substrate, and the orthogonal projection of the single-color electrode part row on the substrate substrate is at least partially located between the orthogonal projection of two adjacent multi-color electrode part rows on the substrate substrate.

[0058] In the plurality of electrode parts connected to the same row of pixel driving circuits, the first electrode part, the third electrode part, the second electrode part, and the third electrode part are alternately arranged in the row direction.

[0059] In an example embodiment of the present disclosure, the four pixel driving circuits located in the same row and adjacent to each other are connected in the row direction in the order of the first electrode part, the third electrode part, the second electrode part, and the third electrode part.

[0060] Or, the four pixel driving circuits located in the same row and adjacent to each other are connected in the row direction in the order of the first electrode part, the second electrode part, the third electrode part, and the third electrode part.

[0061] Or, the four pixel driving circuits located in the same row and adjacent to each other are connected in the row direction in the order of the first electrode part, the third electrode part, the third electrode part, and the second electrode part.

[0062] In an example embodiment of the present disclosure, the total number of the multi-color electrode part columns and the single-color electrode part columns is greater than the number of columns of pixel driving circuits.

[0063] In an example embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, and a ninth transistor.

[0064] The first electrode of the ninth transistor is connected to the gate electrode of the driving transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the second electrode of the ninth transistor, the first electrode of the second transistor is connected to the second electrode of the ninth transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor.

[0065] The display panel further includes:

[0066] A first gate layer is located between the substrate substrate and the electrode layer, and includes a first reset signal line and a first gate line. The orthogonal projection of the first reset signal line and the first gate line on the substrate substrate extends in the row direction. Part of the structure of the first reset signal line is used to form the gate electrode of the first transistor, and part of the structure of the first gate line is used to form the gate line of the second transistor.

[0067] a third gate layer located between the first gate layer and the electrode layer, the third gate layer comprising a second gate line, a projection of the second gate line on the substrate substrate extending along a row direction, and a partial structure of the second gate line being configured to form a top gate of the ninth transistor;

[0068] wherein, in the same pixel driving circuit, a projection of the second gate line on the substrate substrate is located between a projection of the first gate line on the substrate substrate and a projection of the first reset signal line on the substrate substrate.

[0069] In an example embodiment of the present disclosure, the pixel driving circuit comprises a driving transistor, a second transistor, a first electrode of the second transistor being connected to a gate electrode of the driving transistor, and a second electrode of the second transistor being connected to a second electrode of the driving transistor.

[0070] The display panel further comprises:

[0071] a first active layer located between the substrate substrate and the electrode layer, the first active layer comprising a second active part and a third active part, the second active part being configured to form a channel region of the second transistor, and the third active part being configured to form a channel region of the driving transistor.

[0072] a shielding layer located between the substrate substrate and the first active layer, the shielding layer comprising a first shielding part and a second shielding part, a projection of the first shielding part on the substrate substrate at least partially overlapping a projection of the third active part on the substrate substrate, and a projection of the second shielding part on the substrate substrate at least partially overlapping a projection of the second active part on the substrate substrate.

[0073] In an example embodiment of the present disclosure, the pixel driving circuit comprises a driving transistor, a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor.

[0074] a first electrode of the first transistor being connected to a first initial signal line, and a second electrode of the first transistor being connected to a gate electrode of the driving transistor.

[0075] a first electrode of the fifth transistor being connected to a power supply line, and a second electrode of the fifth transistor being connected to a first electrode of the driving transistor.

[0076] a first electrode of the seventh transistor being connected to a second initial signal line, and a second electrode of the seventh transistor being connected to a first electrode of the light emitting unit.

[0077] a first electrode of the eighth transistor being connected to a third initial signal line, and a second electrode of the eighth transistor being connected to a first electrode of the driving transistor.

[0078] The display panel further comprises:

[0079] a first gate layer between the substrate and the electrode layer, the first gate layer comprising an enable signal line, a second reset signal line, a projection of the enable signal line and the second reset signal line on the substrate extends along a row direction, a part of the enable signal line is configured to form a gate of the fifth transistor, a part of the second reset signal line is configured to form a gate of the eighth transistor;

[0080] a third gate layer between the substrate and the electrode layer, the third gate layer comprising the first initial signal line, a third initial signal line, a projection of the first initial signal line and the third initial signal line on the substrate extends along a row direction;

[0081] wherein a projection of the third initial signal line in the current row of pixel driving circuits on the substrate and a projection of the second reset signal line in the current row of pixel driving circuits on the substrate at least partially overlap, a projection of the first initial signal line in the current row of pixel driving circuits on the substrate and a projection of the enable signal line in the adjacent previous row of pixel driving circuits on the substrate at least partially overlap.

[0082] In an example embodiment of the present disclosure, the pixel driving circuit comprises a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a capacitor.

[0083] a first electrode of the ninth transistor is connected to a gate of the driving transistor;

[0084] a first electrode of the first transistor is connected to the first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the ninth transistor;

[0085] a first electrode of the second transistor is connected to the second electrode of the ninth transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0086] a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor;

[0087] a first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;

[0088] a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of a light emitting unit;

[0089] a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit;

[0090] The first electrode of the eighth transistor is connected to a third initial signal line, and the second electrode is connected to the first electrode of the driving transistor.

[0091] The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power supply line.

[0092] According to one aspect of the present disclosure, there is provided a display device, wherein the display device comprises the display panel described above.

[0093] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0094] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0095] FIG. 1 is a structural schematic diagram of an exemplary embodiment of a display panel of the present disclosure;

[0096] FIG. 2 is a partial structural schematic diagram of an exemplary embodiment of a display panel of the present disclosure;

[0097] FIG. 3 is a partial structural schematic diagram of an exemplary embodiment of a display panel of the present disclosure;

[0098] FIG. 4 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0099] FIG. 5 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0100] FIG. 6 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0101] FIG. 7 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0102] FIG. 8 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0103] FIG. 9 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0104] FIG. 10 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0105] FIG. 11 is a partial structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0106] FIG. 12 is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure;

[0107] FIG. 13 is a structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0108] FIG. 14 is a structural layout of the shielding layer in the display panel shown in FIG. 13;

[0109] FIG. 15 is a structural layout of the first active layer in the display panel shown in FIG. 13;

[0110] FIG. 16 is a structural layout of the first gate layer in the display panel shown in FIG. 13;

[0111] FIG. 17 is a structural layout of the second gate layer in the display panel shown in FIG. 13;

[0112] FIG. 18 is a structural layout of the second active layer in the display panel shown in FIG. 13;

[0113] FIG. 19 is a structural layout of the third gate layer in the display panel shown in FIG. 13;

[0114] FIG. 20 is a structural layout of the first source-drain layer in the display panel shown in FIG. 13;

[0115] FIG. 21 is a structural layout of the second source-drain layer in the display panel shown in FIG. 13;

[0116] FIG. 22 is a structural layout of the electrode layer in the display panel shown in FIG. 13;

[0117] FIG. 23 is a structural layout of the shielding layer, the first active layer in the display panel shown in FIG. 13;

[0118] FIG. 24 is a structural layout of the shielding layer, the first active layer, the first gate layer in the display panel shown in FIG. 13;

[0119] FIG. 25 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer in the display panel shown in FIG. 13;

[0120] FIG. 26 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer in the display panel shown in FIG. 13;

[0121] FIG. 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer in the display panel shown in FIG. 13;

[0122] FIG. 28 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer in the display panel shown in FIG. 13;

[0123] FIG. 29 is a structure layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in the display panel shown in FIG. 13;

[0124] FIG. 30 is a partial cross-sectional view of the display panel shown in FIG. 13 taken along the dotted line CC. DETAILED DESCRIPTION

[0125] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views of the drawings, and description of the same will be omitted.

[0126] The use of the terms "one" and "the" and "said" are used as synonymous for the indefinite article "a" or "an", as appropriate, so that "an" should be understood to mean one or more, unless expressly stated otherwise. The use of the term "including" as well as "comprising" as used herein, is meant to be synonymous and be open-ended, and specifically intended to mean that zero, one, or more items can be present.

[0127] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "first", "second", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance. The term "multiple" means two or more. The term "and / or" includes any combination of one or more associated listed items and all combinations thereof. In particular, reference to "the" or "one" object is equally intended to mean one of a possible plurality of such objects.

[0128] Unless otherwise specified or explained, the terms "connection", "fixation", and the like should be interpreted broadly, for example, "connection" can be fixed connection, or detachable connection, or integral connection, or electrical connection, or signal connection; "connection" can be direct connection, or indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0129] Further, in the description of the present disclosure, it needs to be understood that the orientation words such as "upper", "lower", "inner", "outer" and the like described in the example embodiments of the present disclosure are described in the angle shown in the drawings, and should not be understood as the limitation of the example embodiments of the present disclosure. It also needs to be understood that in the context, when referring to one element or feature connected to another element or one or more "upper", "lower", or "inner", "outer", it can not only be directly connected to another element or one or more "upper", "lower", or "inner", "outer", but also indirectly connected to another element or one or more "upper", "lower", or "inner", "outer" through intermediate elements.

[0130] The present example embodiment first provides a display panel. As shown in FIG. 1, it is a structural schematic diagram of an example embodiment of the display panel of the present disclosure. The display area AA of the display panel includes a first display area AA1 and a second display area AA2. The second display area AA2 is located on one side of the first display area AA1 in the row direction X. The display panel includes: a substrate, a plurality of pixel driving circuits Pix, a data line Da, and an electrode layer (not shown). The plurality of pixel driving circuits Pix are located in the display area AA of the display panel. The orthogonal projection of the plurality of pixel driving circuits Pix on the substrate is arrayed along the row and column directions. The orthogonal projection of the data line Da on the substrate extends along the column direction Y. The data line Da is used to provide a data signal to the plurality of pixel driving circuits Pix located in the same column. The electrode layer includes a plurality of electrode parts. At least part of the structure of the electrode part is used to form a first electrode of a light emitting unit. Among them, the pixel driving circuit Pix located in the first display area AA1 corresponds to one electrode part. At least part of the pixel driving circuit Pix located in the second display area AA2 corresponds to a plurality of electrode parts. The pixel driving circuit Pix is used to provide a driving current to the electrode part corresponding thereto.

[0131] In the present example embodiment, the plurality of electrode parts are driven by at least part of the pixel driving circuits in the second display area AA2, so that the sub-pixels on the left and right sides of the display panel can be normally driven.

[0132] As shown in FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram of a partial structure of an example embodiment of the display panel of the present disclosure, and FIG. 3 is a schematic diagram of a partial structure of an example embodiment of the display panel of the present disclosure. FIG. 2 shows a schematic diagram of a partial structure on the left side of the display panel, and FIG. 3 shows a schematic diagram of a partial structure on the right side of the display panel. The plurality of electrode portions include a first electrode portion R and a second electrode portion B, and the first electrode portion R and the second electrode portion B are respectively used to form a first electrode of a light-emitting unit of a different color. For example, the first electrode portion R can be used to form a first electrode of a red light-emitting unit, and the second electrode portion B can be used to form a first electrode of a blue light-emitting unit. The plurality of first electrode portions R and the plurality of second electrode portions B form a plurality of columns of multi-color electrode portion columns Dv, and the multi-color electrode portion columns Dv include the first electrode portions R and the second electrode portions B distributed along a column direction Y; wherein, in at least two columns of multi-color electrode portion columns Dv, the first electrode portions R located in different multi-color electrode portion columns Dv are connected to a same column of pixel driving circuits, and the second electrode portions B located in different multi-color electrode portion columns Dv are connected to another column of pixel driving circuits. For example, as shown in FIG. 2, from left to right, the first electrode portions R in the first column of multi-color electrode portion columns Dv and the first electrode portions R in the second column of multi-color electrode portion columns Dv are connected to the first column of pixel driving circuits, and the second electrode portions B in the second column of multi-color electrode portion columns Dv and the second electrode portions B in the third column of multi-color electrode portion columns Dv are connected to the third column of pixel driving circuits.

[0133] In the example embodiment, the same type of electrode portions (first electrodes of light-emitting units of the same color) located in different multi-color electrode portion columns Dv are connected to the same column of pixel driving circuits, and the data lines can provide data signals to the light-emitting units of the same color, so that the data lines only need to jump within the gamma voltages corresponding to the light-emitting units of one color, which can reduce the power consumption of the display panel.

[0134] As shown in FIG. 2 and FIG. 3, the same type of electrode portions in two adjacent columns of multi-color electrode portion columns Dv are connected to the same column of pixel driving circuits. It should be understood that, in other example embodiments, the same type of electrode portions in other number of columns of multi-color electrode portion columns Dv can also be connected to the same column of pixel driving circuits, and the same type of electrode portions connected to the same column of pixel driving circuits can also be located in non-adjacent multi-color electrode portion columns.

[0135] As shown in FIG. 2 and FIG. 3, in the same multi-color electrode portion column Dv, the orthographic projections of the first electrode portions R and the second electrode portions B on the substrate substrate are alternately distributed along the column direction Y. It should be understood that, in other example embodiments, the first electrode portions R and the second electrode portions B in the same multi-color electrode portion column Dv can also be distributed in other arbitrary manners, as long as the multi-color electrode portion column Dv includes the first electrode portions and the second electrode portions, and the example embodiments can reduce the power consumption of the display panel through the above-mentioned manners.

[0136] In the example embodiment, the plurality of multi-color electrode part columns Dv includes a first multi-color electrode part column Dv1, which is located at the outermost side of the plurality of electrode parts in the row direction X. The second electrode parts B in the first multi-color electrode part column Dv1 are connected to the second electrode parts B in the other multi-color electrode part columns, or the first electrode parts R in the first multi-color electrode part column Dv1 are connected to the first electrode parts R in the other multi-color electrode part columns.

[0137] For example, as shown in FIGS. 1-3, the second display area AA2 includes a first sub-display area AA21 and a second sub-display area AA22, which are located at the two sides of the first display area AA1 in the row direction X, respectively. The plurality of multi-color electrode part columns includes two first multi-color electrode part columns Dv1, which form a first sub-multi-color electrode part column Dv11 and a second sub-multi-color electrode part column Dv12, respectively. The first sub-multi-color electrode part column Dv11 and the second sub-multi-color electrode part column Dv12 are located at the outermost sides of the plurality of electrode parts in the row direction, for example, the first sub-multi-color electrode part column Dv11 is located at the rightmost side of the plurality of electrode parts, and the second sub-multi-color electrode part column Dv12 is located at the leftmost side of the plurality of electrode parts.

[0138] As shown in FIGS. 1-3, the first electrode parts R in the first sub-multi-color electrode part column Dv11 are connected to the first electrode parts R outside the first sub-multi-color electrode part column Dv11, and the second electrode parts B in the second sub-multi-color electrode part column Dv12 are connected to the second electrode parts B outside the second sub-multi-color electrode part column Dv12. Accordingly, the first sub-display area AA21 is located in the area where the pixel driving circuit connected to the first electrode parts R in the first sub-multi-color electrode part column Dv11 is located, and the second sub-display area AA22 is located in the area where the pixel driving circuit connected to the second electrode parts B in the second sub-multi-color electrode part column Dv22 is located.

[0139] In the example embodiment, as shown in FIG. 2, on the left side of the display panel, the second electrode part B in the first multi-color electrode part column Dv1 is connected with the second electrode part B in other multi-color electrode part columns; as shown in FIG. 3, on the right side of the display panel, the first electrode part R in the first multi-color electrode part column Dv1 is connected with the first electrode part R in other multi-color electrode part columns. It should be understood that in other example embodiments, the second electrode part B in the first sub multi-color electrode part column Dv11 on the right side can be connected with the second electrode part B in other multi-color electrode part columns, and the first electrode part R in the first sub multi-color electrode part column Dv11 on the right side is independently arranged; the first electrode part R in the second sub multi-color electrode part column Dv12 on the left side can be connected with the first electrode part R in other multi-color electrode part columns, and the second electrode part B in the second sub multi-color electrode part column Dv12 on the left side is independently arranged. In addition, the display panel can also only include one first multi-color electrode part column Dv1, which can be located at the leftmost or rightmost side of the display panel. That is, the display panel only has the structure of the same electrode part being connected on one side of the left side or the right side.

[0140] In the example embodiment, as shown in FIGS. 2 and 3, the orthographic projection of the plurality of first electrode parts R and the plurality of second electrode parts B on the substrate is arrayed along the row and column directions, the plurality of first electrode parts R and the plurality of second electrode parts B in the same row form a multi-color electrode part row Dh, and the plurality of first electrode parts R and the plurality of second electrode parts B in the same column form a multi-color electrode part column Dv; in the same multi-color electrode part row Dh, the orthographic projection of the first electrode part R and the second electrode part B on the substrate is alternately arranged along the row direction X; in the same multi-color electrode part column Dv, the orthographic projection of the first electrode part R and the second electrode part B on the substrate is alternately arranged along the column direction Y.

[0141] In the example embodiment, as shown in FIG. 3, on the right side of the display panel, the first electrode part R in the first multi-color electrode part column Dv1 and the first electrode part R connected therewith are respectively located in adjacent multi-color electrode part rows and are respectively located in adjacent multi-color electrode part columns; as shown in FIG. 2, on the left side of the display panel, the second electrode part B in the first multi-color electrode part column Dv1 and the second electrode part B connected therewith are respectively located in adjacent multi-color electrode part rows and are respectively located in adjacent multi-color electrode part columns.

[0142] It should be understood that in other example embodiments, the first electrode part R or the second electrode part B in the first multi-color electrode part column Dv1 can also be connected with the same electrode part at other positions. For example, as shown in FIGS. 4 and 5, FIG. 4 is a schematic diagram of part of the structure in another example embodiment of the display panel of the present disclosure, and FIG. 5 is a schematic diagram of part of the structure in another example embodiment of the display panel of the present disclosure. Among them, FIG. 4 shows a schematic diagram of part of the structure on the left side of the display panel, and FIG. 5 shows a schematic diagram of part of the structure on the right side of the display panel.

[0143] As shown in FIG. 5, on the right side of the display panel, the first electrode part R in the first multi-color electrode part column Dv1 and the first electrode part R connected thereto are respectively located in the same multi-color electrode part row and in two multi-color electrode part columns which are separated by one multi-color electrode part column; as shown in FIG. 4, on the left side of the display panel, the second electrode part B in the first multi-color electrode part column Dv1 and the second electrode part B connected thereto are respectively located in the same multi-color electrode part row and in two multi-color electrode part columns which are separated by one multi-color electrode part column.

[0144] In the present exemplary embodiment, as shown in FIGS. 2-5, the plurality of electrode parts can further include third electrode parts G, the first electrode part R, the second electrode part B and the third electrode part G are respectively used for forming the first electrode of the light-emitting unit of different colors; the orthographic projection of the plurality of third electrode parts G on the substrate substrate is arrayed along the row and column direction, the plurality of third electrode parts G located in the same row form a single-color electrode part row Ch, and the plurality of third electrode parts G located in the same column form a single-color electrode part column Cv; wherein the orthographic projection of the single-color electrode part column Cv on the substrate substrate is at least partially located between the orthographic projection of the adjacent two multi-color electrode part columns Dv on the substrate substrate, and the orthographic projection of the single-color electrode part row Ch on the substrate substrate is at least partially located between the orthographic projection of the adjacent two multi-color electrode part rows Dh on the substrate substrate; and in the plurality of electrode parts connected to the same row of pixel driving circuit, the first electrode part R, the third electrode part G, the second electrode part B and the third electrode part G are alternately distributed in the row direction.

[0145] In the present exemplary embodiment, as shown in FIGS. 2-5, the four pixel driving circuits located in the same row and adjacent to each other are sequentially connected with the first electrode part R, the third electrode part G, the second electrode part B and the third electrode part G in the row direction.

[0146] It should be understood that in other exemplary embodiments, the pixel driving circuit and the electrode portion can also have other connection manners. For example, as shown in FIGS. 6 and 7, FIG. 6 is a schematic diagram of a partial structure in another exemplary embodiment of the display panel of the present disclosure, and FIG. 7 is a schematic diagram of a partial structure in another exemplary embodiment of the display panel of the present disclosure. FIG. 6 shows a schematic diagram of a partial structure on the left side of the display panel, and FIG. 7 shows a schematic diagram of a partial structure on the right side of the display panel. In the present exemplary embodiment, four pixel driving circuits located in the same row and adjacent to each other are sequentially connected with the first electrode portion R, the second electrode portion B, the third electrode portion G, and the third electrode portion G in the row direction. For another example, as shown in FIGS. 8 and 9, FIG. 8 is a schematic diagram of a partial structure in another exemplary embodiment of the display panel of the present disclosure, and FIG. 9 is a schematic diagram of a partial structure in another exemplary embodiment of the display panel of the present disclosure. FIG. 8 shows a schematic diagram of a partial structure on the left side of the display panel, and FIG. 9 shows a schematic diagram of a partial structure on the right side of the display panel. In the present exemplary embodiment, four pixel driving circuits located in the same row and adjacent to each other are sequentially connected with the first electrode portion R, the third electrode portion G, the third electrode portion G, and the second electrode portion B in the row direction.

[0147] As shown in FIGS. 2-11, the electrode layer further includes a connection portion QL connected between the electrode portion and the pixel driving circuit Pix. The embodiments shown in FIGS. 6-9 can reduce the extension length of the orthographic projection of the connection portion QL on the substrate, thereby improving the transmittance of the display panel and reducing the brightness difference of the odd and even rows of light emitting units.

[0148] In the present exemplary embodiment, as shown in FIGS. 2-9, the total column number of the multi-color electrode portion columns Dv and the single-color electrode portion column Cv is greater than the column number of the pixel driving circuits.

[0149] In the present exemplary embodiment, as shown in FIGS. 2-9, the first electrode portion R in the first multi-color electrode portion column Dv1 and the first electrode portion R in the other multi-color electrode portion columns can be connected in the same layer; the second electrode portion B in the first multi-color electrode portion column and the second electrode portion B in the other multi-color electrode portion columns can be connected in the same layer. It should be understood that in other exemplary embodiments, the first electrode portion R in the first multi-color electrode portion column Dv1 and the first electrode portion R in the other multi-color electrode portion columns can also be bridged by other conductive layers, and the second electrode portion B in the first multi-color electrode portion column and the second electrode portion B in the other multi-color electrode portion columns can also be bridged by other conductive layers.

[0150] In the present exemplary embodiment, as shown in FIGS. 2-9, the display panel further includes a pixel defining layer located on the side of the electrode layer away from the substrate, and a plurality of pixel openings are formed on the pixel defining layer; the electrode portion includes a body portion X1, the pixel opening and the body portion are correspondingly arranged, and the orthographic projection of the body portion X1 on the substrate and the orthographic projection of the pixel opening corresponding thereto on the substrate coincide.

[0151] As shown in FIGS. 2-9, in the first electrode portion R in the first multi-color electrode portion column Dv1 and the first electrode portion R connected thereto, the area of the orthographic projection of the body portion on the substrate can be the same in the two first electrode portions R; in the second electrode portion B in the first multi-color electrode portion column Dv1 and the second electrode portion B connected thereto, the area of the orthographic projection of the body portion on the substrate can be the same in the two second electrode portions B.

[0152] It should be understood that in other exemplary embodiments, in the first electrode portion R in the first multi-color electrode portion column and the first electrode portion R connected thereto, the area of the orthographic projection of the body portion K1 on the substrate can be different in the two first electrode portions R, wherein the area of the orthographic projection of the body portion on the substrate in the first electrode portion R in the first multi-color electrode portion column can be greater than or less than the area of the orthographic projection of the body portion on the substrate in the first electrode portion connected thereto. In the second electrode portion B in the first multi-color electrode portion column and the second electrode portion B connected thereto, the area of the orthographic projection of the body portion on the substrate can be different in the two second electrode portions B, wherein the area of the orthographic projection of the body portion on the substrate in the second electrode portion B in the first multi-color electrode portion column can be greater than or less than the area of the orthographic projection of the body portion on the substrate in the second electrode portion B connected thereto. This arrangement can adjust the luminance of the light emitting unit by adjusting the area of the body portion in the two connected electrode portions, thereby improving the color deviation problem of the display panel.

[0153] For example, as shown in FIGS. 10, 11, FIG. 10 is a schematic diagram of part of the structure in another exemplary embodiment of the display panel of the present disclosure, and FIG. 11 is a schematic diagram of part of the structure in another exemplary embodiment of the display panel of the present disclosure. Among them, FIG. 10 shows a schematic diagram of part of the structure on the left side of the display panel, and FIG. 11 shows a schematic diagram of part of the structure on the right side of the display panel. Based on FIG. 2, the display panel shown in FIG. 10 reduces the area of the body portion of the second electrode portion B in the first multi-color electrode portion column; based on FIG. 3, the display panel shown in FIG. 11 reduces the area of the body portion of the first electrode portion R in the first multi-color electrode portion column. It should be understood that in the display panel shown in FIGS. 4-9, the area of the body portion in the first electrode portion in the first multi-color electrode portion column and the first electrode portion connected thereto can be differentially arranged, and similarly, the area of the body portion in the second electrode portion in the first multi-color electrode portion column and the second electrode portion connected thereto can also be differentially arranged.

[0154] As shown in FIG. 2, the extension length of the normal projection of the connecting portion QL corresponding to the light emitting unit of the same color on the substrate is the same or substantially the same. This arrangement can make the parasitic capacitance of the equipotential portion of the first electrode portion in the light emitting unit of the same color the same or substantially the same, thereby avoiding the display panel from having horizontal lines and other defects. The extension length of the normal projection of the connecting portion QL corresponding to the light emitting unit of the same color on the substrate is substantially the same, which can be understood as the ratio of the maximum difference of the extension length of the normal projection of the connecting portion QL corresponding to the light emitting unit of the same color on the substrate to the extension length of the normal projection of the connecting portion QL corresponding to the light emitting unit of the same color on the substrate being less than or equal to 5%.

[0155] As shown in FIG. 2, in the two adjacent rows of multi-color electrode portion rows Dh, the connecting portion connected by the first electrode portion R or the second electrode portion B in one row of multi-color electrode portion rows Dh forms a first connecting portion QL1, and the connecting portion connected by the first electrode portion R or the second electrode portion B in the other row of multi-color electrode portion rows Dh forms a second connecting portion QL2; the first connecting portion QL1 includes a first extension segment QL11 and a second extension segment QL12, and the included angle of the normal projection of the first extension segment QL11 and the second extension segment QL12 on the substrate is greater than or equal to 95° and less than or equal to 180°; the second connecting portion QL2 includes a third extension segment QL23 and a fourth extension segment QL24, and the included angle of the normal projection of the third extension segment QL23 and the fourth extension segment QL24 on the substrate is less than or equal to 90°. That is, the second connecting portion QL2 can be wound in a way such that the extension length of the second connecting portion QL2 and the first connecting portion QL1 corresponding to the light emitting unit of the same color is the same or substantially the same.

[0156] As shown in FIG. 3-11, the display panel can also make the extension length of the normal projection of the connecting portion QL corresponding to the light emitting unit of the same color on the substrate the same or substantially the same by winding the second connecting portion.

[0157] In the present exemplary embodiment, as shown in FIG. 2-11, in the same row of multi-color electrode portion rows Dh, the normal projection of the first electrode portion R and the second electrode portion B on the substrate is on the same side of the normal projection of the connecting portion QL connected thereto. For example, as shown in FIG. 2, in the first row of multi-color electrode portion rows Dh from top to bottom, the first electrode portion R and the second electrode portion B are both on the left side of the connecting portion connected thereto, and in the second row of multi-color electrode portion rows Dh from top to bottom, the first electrode portion R and the second electrode portion B are both on the right side of the connecting portion connected thereto. This arrangement can avoid the intersection of the connecting portion and too many signal lines.

[0158] In the present exemplary embodiment, as shown in FIG. 2-11, the connecting portion QL and the electrode portion can be connected in the same layer.

[0159] As shown in FIG. 12, a structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure is shown. The pixel driving circuit can include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor, and a capacitor C. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to a first gate driving signal terminal G1. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to an enable signal terminal EM. The gate electrode of the driving transistor T3 is connected to a first node N1. The first electrode of the second transistor T2 is connected to a second node N2, the second electrode is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to the first gate driving signal terminal G1. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate electrode is connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and the gate electrode is connected to a second reset signal terminal Re2. The second electrode of the first transistor T1 is connected to the second node N2, the first electrode is connected to a first initial signal terminal Vinit1, and the gate electrode is connected to a first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to a third initial signal terminal Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate electrode is connected to the second reset signal terminal Re2. The first electrode of the ninth transistor T9 is connected to the first node N1, the second electrode is connected to the second node N2, and the gate electrode is connected to a second gate driving signal terminal G2. The first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit L, and the pixel driving circuit is used to drive the light emitting unit L to emit light. The light emitting unit L can be connected between the second electrode of the sixth transistor T6 and a second power supply terminal VSS. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, and the ninth transistor T9 can be an N-type transistor.

[0160] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light emitting stage. In the reset stage, the first reset signal end Re1 outputs a low-level signal, the second reset signal end Re2 outputs a low-level signal, the second gate driving signal end G2 outputs a high-level signal, the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, the first initial signal end Vinit1 inputs a first initial signal to the first node N1, the second initial signal end Vinit2 inputs a second initial signal to the first electrode of the light emitting unit, and the third initial signal end Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal end G1 outputs a low-level signal, the second gate driving signal end G2 outputs a high-level signal, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are turned on, and the data signal end Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the light emitting stage, the enable signal end EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current. Wherein I is the output current of the driving transistor; μ is the carrier mobility; Cox is the unit area gate capacitance, W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0161] In the example embodiment, the display panel can include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, a second source-drain layer, and an electrode layer which are sequentially stacked. An insulating layer can be disposed between adjacent layers. As shown in FIGS. 13-29, FIG. 13 is a structural layout of a display panel according to an example embodiment of the present disclosure, FIG. 14 is a structural layout of the shielding layer in the display panel of FIG. 13, FIG. 15 is a structural layout of the first active layer in the display panel of FIG. 13, FIG. 16 is a structural layout of the first gate layer in the display panel of FIG. 13, FIG. 17 is a structural layout of the second gate layer in the display panel of FIG. 13, FIG. 18 is a structural layout of the second active layer in the display panel of FIG. 13, FIG. 19 is a structural layout of the third gate layer in the display panel of FIG. 13, FIG. 20 is a structural layout of the first source-drain layer in the display panel of FIG. 13, FIG. 21 is a structural layout of the second source-drain layer in the display panel of FIG. 13, FIG. 22 is a structural layout of the electrode layer in the display panel of FIG. 13, FIG. 23 is a structural layout of the shielding layer and the first active layer in the display panel of FIG. 13, FIG. 24 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel of FIG. 13, FIG. 25 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel of FIG. 13, FIG. 26 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel of FIG. 13, FIG. 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel of FIG. 13, FIG. 28 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in the display panel of FIG. 13, and FIG. 29 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in the display panel of FIG. 13. The display panel can include a plurality of pixel driving circuits as shown in FIG. 1.

[0162] As shown in FIG. 29, the display panel can include a plurality of repeating units distributed in the row direction X and the column direction Y, each of the repeating units including two pixel driving circuits adjacent in the row direction: a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2, and the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 are at least partially mirror-symmetrically arranged along the symmetry axis BB in the orthogonal projection on the substrate. For example, the channel regions of the same type of transistors in the two pixel driving circuits which are at least partially mirror-symmetrically arranged are mirror-symmetrically arranged in the orthogonal projection on the substrate. For example, the channel region of the first transistor in the first pixel driving circuit Pix1 and the channel region of the first transistor in the second pixel driving circuit Pix2 are mirror-symmetrically arranged along the symmetry axis BB in the orthogonal projection on the substrate.

[0163] As shown in FIGS. 13, 14, 23, the shielding layer includes a plurality of first shielding portions 81 and second shielding portions 82 arranged in the row direction X and the column direction Y, the first shielding portions 81 are connected to each other, and the second shielding portions 82 are connected to the first shielding portions 81.

[0164] As shown in FIGS. 13, 15, 23, 24, the first active layer can include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and an eighteenth active portion 718. The first active portion 71 is used to form a channel region of the first transistor T1; the second active portion 72 is used to form a channel region of the second transistor T2; the third active portion 73 can be used to form a channel region of the driving transistor T3; the fourth active portion 74 can be used to form a channel region of the fourth transistor T4; the fifth active portion 75 can be used to form a channel region of the fifth transistor T5; the sixth active portion 76 can be used to form a channel region of the sixth transistor T6; the seventh active portion 77 can be used to form a channel region of the seventh transistor T7; the eighth active portion 78 can be used to form a channel region of the eighth transistor T8; the tenth active portion 710 is connected between the first active portion 71 and the second active portion 72; the eleventh active portion 711 is connected to an end of the first active portion 71 away from the second active portion 72; the twelfth active portion 712 is connected to an end of the fourth active portion 74 away from the third active portion 73; the thirteenth active portion 713 is connected between the third active portion 73 and the fifth active portion 75; the fourteenth active portion 714 is connected to an end of the fifth active portion 75 away from the third active portion 73; the fifteenth active portion 715 and the sixteenth active portion 716 are connected to two ends of the eighth active portion 78; the seventeenth active portion 717 is connected to an end of the seventh active portion 77 away from the sixth active portion 76; and the eighteenth active portion 718 is connected between the seventh active portion 77 and the sixth active portion 76.

[0165] In the present exemplary embodiment, the active layer can be formed of a polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0166] As shown in FIGS. 13, 15, 23, 24, in the same repeating unit, the two seventh active portions 77 are connected through the seventeenth active portion 717, and in the two repeating units adjacent in the row direction X, the two fifth active portions 75 in the adjacent pixel driving circuits are connected through the fourteenth active portion 714.

[0167] As shown in FIG. 13, 15, 23, the first shielding portion 81 can at least partially overlap the third active portion 73 in the orthographic projection on the substrate, and the first shielding portion 81 can shield the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The second shielding portion 82 can at least partially overlap the second active portion 72 in the orthographic projection on the substrate, and the second shielding portion 82 can shield the second active portion 72 to improve the stability of the output characteristics of the second transistor. The shielding layer can be a conductive structure, the shielding layer can be connected to a stable voltage source, the shielding layer can shield the signal of the pixel driving circuit, and the shielding layer can be connected to the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power terminal, the second power terminal, and other stable voltage sources in FIG. 12.

[0168] As shown in FIG. 13, 16, 24, the first gate layer can include: the first conductive part 11, the first gate line G1, the enable signal line EM, the first reset signal line Re1, the second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal end in FIG. 12; the enable signal line EM can be used to provide the enable signal end in FIG. 12; the first reset signal line Re1 can be used to provide the first reset signal end in FIG. 12; the second reset signal line Re2 can be used to provide the second reset signal end in FIG. 12. The orthographic projection of the first gate line G1, the enable signal line EM, the first reset signal line Re1, the second reset signal line Re2 on the substrate substrate can extend along the row direction X. The orthographic projection of the first gate line G1 on the substrate substrate covers the orthographic projection of the fourth active part 74 on the substrate substrate, the orthographic projection of the second active part 72 on the substrate substrate, and part of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and part of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM on the substrate substrate covers the orthographic projection of the fifth active part 75 on the substrate substrate, the orthographic projection of the sixth active part 76 on the substrate substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate substrate can cover the orthographic projection of the first active part 71 on the substrate substrate, and part of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate substrate can cover the orthographic projection of the seventh active part 77 on the substrate substrate, the orthographic projection of the eighth active part 78 on the substrate substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive part 11 on the substrate substrate covers the orthographic projection of the third active part 73 on the substrate substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.

[0169] As shown in FIG. 13, 16, 24, the first reset signal line Re1 in the current row of pixel driving circuit can be multiplexed as the second reset signal line in the previous row of pixel driving circuit. In addition, the display panel can use the first gate layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first gate layer can form the channel region of the transistor, and the region of the first active layer not covered by the first gate layer forms a conductor structure.

[0170] As shown in FIGS. 13, 17, and 25, the second gate layer can include a second conductive portion 22, a second initial signal line Vinit2, and a third gate line 2G2. The orthogonal projection of the second conductive portion 22 on the substrate substrate can at least partially overlap the orthogonal projection of the first conductive portion 11 on the substrate substrate, and the second conductive portion 22 is configured to form a second electrode of a capacitor C. The orthogonal projection of the second initial signal line Vinit2 on the substrate substrate extends along the row direction X, and the second initial signal line Vinit2 can be configured to provide a second initial signal terminal in FIG. 12. The orthogonal projection of the third gate line 2G2 on the substrate substrate extends along the row direction X, and the third gate line 2G2 is configured to provide a second gate drive signal terminal in FIG. 12.

[0171] As shown in FIGS. 13, 18, and 26, the second active layer can include a ninth active portion 99, a nineteenth active portion 919, and a twentieth active portion 920, the ninth active portion 99 is configured to form a channel region of a ninth transistor T9, and the nineteenth active portion 919 and the twentieth active portion 920 are connected to both ends of the ninth active portion 99. The second active layer can be formed of indium gallium zinc oxide, and accordingly, the ninth transistor T9 can be an N-type metal oxide thin film transistor. The orthogonal projection of the third gate line 2G2 on the substrate substrate can cover the orthogonal projection of the ninth active portion 99 on the substrate substrate, and part of the structure of the third gate line 2G2 can be configured to form a bottom gate of the ninth transistor T9.

[0172] As shown in FIGS. 13, 19, and 27, the third gate layer can include a second gate line 3G2, a first initial signal line Vinit1, and a third initial signal line Vinit3. The orthogonal projection of the second gate line 3G2, the first initial signal line Vinit1, and the third initial signal line Vinit3 on the substrate substrate can all extend along the row direction X. The second gate line 3G2 can be configured to provide a second gate drive signal terminal in FIG. 12, the orthogonal projection of the second gate line 3G2 on the substrate substrate can cover the orthogonal projection of the ninth active portion 99 on the substrate substrate, and part of the structure of the second gate line 3G2 can be configured to form a top gate of the ninth transistor T9, and at the same time, the second gate line 3G2 can be connected to the third gate line 2G2 through a via located in the frame area of the display panel. The first initial signal line Vinit1 can be configured to provide a first initial signal terminal in FIG. 12, and the third initial signal line Vinit3 can be configured to provide a third initial signal terminal in FIG. 12. In addition, the display panel can perform a conductorization process on the second active layer using the third gate layer as a mask, that is, the region of the second active layer covered by the third gate layer can form a channel region of a transistor, and the region of the second active layer not covered by the third gate layer forms a conductor structure.

[0173] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers, for example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the first active layer, the second gate layer, the third gate layer, the first source-drain layer, etc.

[0174] In the same pixel driving circuit in the present exemplary embodiment, the orthogonal projection of the second gate line 3G2 on the substrate substrate is located between the orthogonal projection of the first gate line G1 on the substrate substrate and the orthogonal projection of the first reset signal line Re1 on the substrate substrate.

[0175] The orthogonal projection of the third initial signal line Vinit3 in the present row of pixel driving circuits on the substrate substrate at least partially overlaps with the orthogonal projection of the second reset signal line Re2 in the present row of pixel driving circuits on the substrate substrate, and the orthogonal projection of the first initial signal line Vinit1 in the present row of pixel driving circuits on the substrate substrate at least partially overlaps with the orthogonal projection of the enable signal line EM in the adjacent previous row of pixel driving circuits on the substrate substrate. This arrangement can improve the light transmittance of the display panel.

[0176] As shown in FIGS. 13, 20, and 28, the first source-drain layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a tenth bridge portion 410, and a first fan-out line FIPH.

[0177] As shown in FIGS. 13, 20 and 28, the first bridge portion 41 can be connected to the eleventh active portion 711 and the first initial signal line Vinit1 by vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The second bridge portion 42 can be connected to the nineteenth active portion 919 and the tenth active portion 710 by vias, respectively, to connect the second electrode of the ninth transistor T9 and the second electrode of the first transistor T1, the first electrode of the second transistor. The third bridge portion 43 can be connected to the twelfth active portion 712 by a via to connect the first electrode of the fourth transistor T4. The fourth bridge portion 44 can be connected to the twentieth active portion 920 and the first conductive portion 11 by vias, respectively, to connect the first electrode of the ninth transistor T9 and the gate electrode of the driving transistor T3, wherein the second conductive portion 22 has an opening 221 formed therein, and the via connected between the fourth bridge portion 44 and the first conductive portion 11 is disposed through the opening 221. The fifth bridge portion 45 can be connected to the fourteenth active portion 714 and the second conductive portion 22 by vias, respectively, to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The sixth bridge portion 46 can be connected to the thirteenth active portion 713 and the sixteenth active portion 716 by vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 can be connected to the eighteenth active portion 718 by a via to connect the second electrode of the sixth transistor. The eighth bridge portion 48 can be connected to the fifteenth active portion 715 and the third initial signal line Vinit3 by vias to connect the first electrode of the eighth transistor T8 and the third initial signal line Vinit3. The ninth bridge portion 49 can be connected to the seventeenth active portion 717 and the second initial signal line Vinit2 by vias to connect the first electrode of the seventh transistor T7 and the second initial signal terminal. The first fan-out line FIPH can extend in the row direction X in the orthographic projection of the first fan-out line FIPH on the substrate, and the first fan-out line FIPH can be a row-direction fan-out line for connecting data lines in a FIP (Fanout In Pixel).

[0178] As shown in FIGS. 13, 21, 29, the second source-drain layer can include a data line Da, a power supply line VDD, a second fan-out line FIPV, an initial connection line Vinitx, and an eleventh bridge portion 511. The data line Da, the power supply line VDD, the second fan-out line FIPV, and the initial connection line Vinitx each have a projection on the substrate that extends in the column direction Y. The data line Da can be used to provide the data signal terminal in FIG. 12, and the data line Da can be connected to the third bridge portion 43 through a via to connect the data signal terminal and the first electrode of the fourth transistor T4. The power supply line VDD can be used to provide the first power supply terminal in FIG. 12, and the power supply line VDD can be connected to the fifth bridge portion 45 through a via to connect the first power supply terminal and the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The initial connection line Vinitx can be any one of a first initial connection line, a second initial connection line, and a third initial connection line. The first initial connection line can be connected to the first initial signal line through a via, the second initial connection line can be connected to the second initial signal line through a via, and the third initial connection line can be connected to the third initial signal line through a via. Each two columns of pixel driving circuits can correspond to one initial connection line Vinitx, and the display panel can include a plurality of initial connection lines Vinitx. Some of the initial connection lines Vinitx can form the first initial connection line, some of the initial connection lines Vinitx can form the second initial connection line, and some of the initial connection lines Vinitx can form the first power supply connection line. For example, the first initial connection line, the second initial connection line, and the first power supply connection line can be arranged alternately in the row direction on the substrate. The second fan-out line FIPV can be a column-direction fan-out line for connecting the data lines in the FIP (Fanout In Pixel), and the second fan-out line FIPV can include a plurality of fan-out line segments arranged at intervals in the column direction, and adjacent fan-out line segments can be connected by the tenth bridge portion 410. The eleventh bridge portion 511 can be connected to the seventh bridge portion 47 through a via.

[0179] As shown in FIGS. 13, 22, the electrode layer can include a plurality of electrode portions, including a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each of the electrode portions can be connected to the eleventh bridge portion 511 through a via to connect the second electrode of the sixth transistor.

[0180] As shown in FIG. 30, it is a partial cross-sectional view of the display panel shown in FIG. 13 along the dotted line CC. The display panel can also include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planar layer 108, and a second planar layer 109. Among them, the substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planar layer 108, the second source-drain layer, the second planar layer 109, the electrode layer, and the pixel defining layer 110 are sequentially stacked. The pixel defining layer 110 is formed with a pixel opening H, and a light emitting unit can be formed in the pixel opening H. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; and the materials of the first planar layer 108 and the second planar layer 109 can be organic materials such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), and the like. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy thereof, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer and the second source-drain layer can include a metal material, for example, one of molybdenum, aluminum, copper, titanium, and niobium or an alloy thereof, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer. The sheet resistance of any one of the first source-drain layer and the second source-drain layer can be less than the sheet resistance of any one of the first gate layer, the second gate layer, and the third gate layer.

[0181] It should be noted that, as shown in FIGS. 2-30, the black squares drawn on the side of the first source-drain layer away from the substrate represent vias of the first source-drain layer connecting other levels facing the substrate side; the black squares drawn on the side of the second source-drain layer away from the substrate represent vias of the second source-drain layer connecting other levels facing the substrate side; and the black squares drawn on the side of the electrode layer away from the substrate represent vias of the electrode layer connecting other levels facing the substrate side. The vias at different positions can penetrate different insulating layers.

[0182] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto, for example: the width-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the number shown in the figure, and the drawings described in the present disclosure are only schematic diagrams. In addition, the adjectives first, second, etc. are only used to define different structure names, and do not have the meaning of a specific order, and the same structure layer can be formed by the same patterning process. In the present exemplary embodiment, the orthographic projection of a certain structure on the substrate substrate extends along a certain direction, which can be understood as that the orthographic projection of the structure on the substrate substrate extends linearly or bends along the direction.

[0183] The present exemplary embodiment also provides a display device, comprising the display panel described above. The display device can be a mobile phone, a tablet computer, a television, etc.

[0184] Other embodiments of the present disclosure will be apparent to those skilled in the art with the consideration of the specification and practice of the disclosure disclosed herein. The present application is intended to cover any variations, uses, or adaptive changes of the present disclosure that follow the general principles of the present disclosure and include common knowledge or conventional techniques in the art that are not disclosed by the present disclosure. The specification and examples are only considered as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0185] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A display panel, wherein, The display area of the display panel includes a first display area and a second display area located on one side of the first display area in a row direction, and the display panel includes: a substrate substrate; a plurality of pixel driving circuits located in the display area of the display panel, and the orthogonal projection of the plurality of pixel driving circuits on the substrate substrate is arrayed in a row-column direction; a data line, the orthogonal projection of which on the substrate substrate extends in a column direction, and the data line is used to provide a data signal to a plurality of pixel driving circuits in the same column; an electrode layer including a plurality of electrode parts, at least part of the structure of the electrode part being used to form a first electrode of a light-emitting unit; wherein the pixel driving circuit located in the first display area is correspondingly provided with one electrode part, and at least part of the pixel driving circuit located in the second display area is correspondingly provided with a plurality of electrode parts, and the pixel driving circuit is used to provide a driving current to the electrode part corresponding thereto.

2. The display panel of claim 1, wherein, The plurality of electrode parts includes a first electrode part and a second electrode part, and the first electrode part and the second electrode part are respectively used to form a first electrode of a light-emitting unit of different colors; a plurality of the first electrode parts and a plurality of the second electrode parts form a plurality of columns of multi-color electrode parts, and the multi-color electrode part column includes a first electrode part and a second electrode part distributed in a column direction; wherein, in at least two columns of multi-color electrode part columns, the first electrode part located in different multi-color electrode part columns is connected to the same column of pixel driving circuits, and the second electrode part located in different multi-color electrode part columns is connected to another column of pixel driving circuits.

3. The display panel of claim 2, wherein, The plurality of multi-color electrode part columns includes a first multi-color electrode part column, and the first multi-color electrode part column is located at the outermost side of the plurality of electrode parts in the row direction; the first electrode part in the first multi-color electrode part column is connected to the first electrode part in the other multi-color electrode part column, and the second display area includes the area where the pixel driving circuit connected to the first electrode part in the first multi-color electrode part column is located; or, the second electrode part in the first multi-color electrode part column is connected to the second electrode part in the other multi-color electrode part column, and the second display area includes the area where the pixel driving circuit connected to the second electrode part in the first multi-color electrode part column is located. The plurality of multi-color electrode part columns includes two first multi-color electrode part columns, and the two first multi-color electrode part columns form a first sub multi-color electrode part column and a second sub multi-color electrode part column, respectively; 4. The display panel of claim 3, wherein, the first sub multi-color electrode part column and the second sub multi-color electrode part column are respectively located at the outermost side of the plurality of electrode parts in the row direction; the first electrode part in the first sub multi-color electrode part column is connected to the first electrode part outside the first sub multi-color electrode part column; the second electrode part in the second sub multi-color electrode part column is connected to the second electrode part outside the second sub multi-color electrode part column; ​ The second display area includes a first sub-display area and a second sub-display area, the first sub-display area and the second sub-display area are respectively located on both sides of the first display area in the row direction, the first sub-display area is located in the region where the pixel driving circuit connected with the first electrode part in the first sub-multicolor electrode part column, and the second sub-display area is located in the region where the pixel driving circuit connected with the second electrode part in the second sub-multicolor electrode part column.

5. The display panel of claim 3 or 4, wherein, The first electrode part and the second electrode part are arrayed in the row and column directions on the substrate substrate, and the first electrode part and the second electrode part in the same row form a multicolor electrode part row, and the first electrode part and the second electrode part in the same column form the multicolor electrode part column. In the same multicolor electrode part row, the first electrode part and the second electrode part are alternately distributed in the row direction on the substrate substrate. In the same multicolor electrode part column, the first electrode part and the second electrode part are alternately distributed in the column direction on the substrate substrate. The first electrode part in the first multicolor electrode part column and the first electrode part connected therewith are respectively located in adjacent multicolor electrode part rows and are respectively located in adjacent multicolor electrode part columns. And / or, the second electrode part in the first multicolor electrode part column and the second electrode part connected therewith are respectively located in adjacent multicolor electrode part rows and are respectively located in adjacent multicolor electrode part columns.

6. The display panel of claim 3 or 4, wherein, The first electrode part and the second electrode part are arrayed in the row and column directions on the substrate substrate, and the first electrode part and the second electrode part in the same row form a multicolor electrode part row, and the first electrode part and the second electrode part in the same column form the multicolor electrode part column. In the same multicolor electrode part row, the first electrode part and the second electrode part are alternately distributed in the row direction on the substrate substrate. In the same multicolor electrode part column, the first electrode part and the second electrode part are alternately distributed in the column direction on the substrate substrate. The first electrode part in the first multicolor electrode part column and the first electrode part connected therewith are respectively located in the same multicolor electrode part row and are respectively located in two multicolor electrode part columns separated by one multicolor electrode part column. And / or, the second electrode part in the first multicolor electrode part column and the second electrode part connected therewith are respectively located in the same multicolor electrode part row and are respectively located in two multicolor electrode part columns separated by one multicolor electrode part column.

7. The display panel according to any one of claims 3-6, wherein, The first electrode part in the first multicolor electrode part column and the first electrode part in other multicolor electrode part columns are connected in the same layer. And / or, the second electrode part in the first multicolor electrode part column and the second electrode part in other multicolor electrode part columns are connected in the same layer.

8. The display panel of claim 3 or 4, wherein, The display panel further comprises: A pixel definition layer is located on the side of the electrode layer away from the substrate substrate, and a plurality of pixel openings are formed on the pixel definition layer; The electrode part includes a body part, the pixel opening and the body part are correspondingly arranged, and the projection of the body part on the substrate substrate and the projection of the pixel opening corresponding thereto on the substrate substrate coincide. The area of the orthographic projection of the body part of the two first electrode parts on the substrate is different; The area of the orthographic projection of the body part of the two second electrode parts on the substrate is different.

9. The display panel according to any one of claims 1-8, wherein, The electrode layer further comprises a connecting part connected between the electrode part and the pixel driving circuit; The orthographic projection of the connecting part corresponding to the same color light emitting unit on the substrate has the same or approximately the same extension length.

10. The display panel according to any one of claims 1-9, wherein, The plurality of electrode parts comprises a first electrode part and a second electrode part, and the first electrode part and the second electrode part are respectively used to form a first electrode of a light emitting unit of different colors; The plurality of first electrode parts and the plurality of second electrode parts form a plurality of rows of multi-color electrode parts, and the rows of multi-color electrode parts comprise the first electrode parts and the second electrode parts distributed along the row direction; The electrode layer further comprises a connecting part connected between the electrode part and the pixel driving circuit; In the two adjacent rows of multi-color electrode parts, the connecting part connected by the first electrode part or the second electrode part in one row of multi-color electrode parts forms a first connecting part, and the connecting part connected by the first electrode part or the second electrode part in the other row of multi-color electrode parts forms a second connecting part; The first connecting part comprises a first extension segment and a second extension segment, and the included angle of the orthographic projection of the first extension segment and the second extension segment on the substrate is greater than or equal to 95° and less than or equal to 180°; The second connecting part comprises a third extension segment and a fourth extension segment, and the included angle of the orthographic projection of the third extension segment and the fourth extension segment on the substrate is less than or equal to 90°.

11. The display panel according to any one of claims 1-10, wherein, The plurality of electrode parts comprises a first electrode part and a second electrode part, and the first electrode part and the second electrode part are respectively used to form a first electrode of a light emitting unit of different colors; The plurality of first electrode parts and the plurality of second electrode parts form a plurality of rows of multi-color electrode parts, and the rows of multi-color electrode parts comprise the first electrode parts and the second electrode parts distributed along the row direction; The electrode layer further comprises a connecting part connected between the electrode part and the pixel driving circuit; In the same row of multi-color electrode parts, the orthographic projection of the first electrode part and the second electrode part on the substrate is located on the same side of the orthographic projection of the connecting part connected thereto on the substrate.

12. The display panel of claim 11, wherein, The connecting part and the electrode part are connected in the same layer.

13. The display panel of claim 2, wherein, The plurality of electrode parts further comprises a third electrode part, and the first electrode part, the second electrode part, and the third electrode part are respectively used to form a first electrode of a light emitting unit of different colors; The orthographic projection of the plurality of third electrode parts on the substrate is arrayed along the row and column direction, and the plurality of third electrode parts located in the same row form a row of single-color electrode parts, and the plurality of third electrode parts located in the same column form a column of single-color electrode parts; The orthogonal projection of the first electrode part and the second electrode part on the substrate substrate is arrayed along the row and column direction, the first electrode part and the second electrode part in the same row form a multi-color electrode part row, and the first electrode part and the second electrode part in the same column form a multi-color electrode part column. In the same multi-color electrode part row, the orthogonal projection of the first electrode part on the substrate substrate and the orthogonal projection of the second electrode part on the substrate substrate are alternately arranged along the row direction. In the same multi-color electrode part column, the orthogonal projection of the first electrode part and the orthogonal projection of the second electrode part on the substrate substrate are alternately arranged along the column direction. The orthogonal projection of the single-color electrode part column on the substrate substrate is at least partially located between the orthogonal projection of the adjacent two multi-color electrode part columns on the substrate substrate, and the orthogonal projection of the single-color electrode part row on the substrate substrate is at least partially located between the orthogonal projection of the adjacent two multi-color electrode part rows on the substrate substrate. In the plurality of electrode parts connected to the same row pixel driving circuit, the first electrode part, the third electrode part, the second electrode part, and the third electrode part are alternately arranged along the row direction.

14. The display panel of claim 13, wherein, The four pixel driving circuits located in the same row and adjacent to each other are sequentially connected to the first electrode part, the third electrode part, the second electrode part, and the third electrode part along the row direction. Or, the four pixel driving circuits located in the same row and adjacent to each other are sequentially connected to the first electrode part, the second electrode part, the third electrode part, and the third electrode part along the row direction. Or, the four pixel driving circuits located in the same row and adjacent to each other are sequentially connected to the first electrode part, the third electrode part, the third electrode part, and the second electrode part along the row direction.

15. The display panel of claim 13, wherein, The total column number of the multi-color electrode part column and the single-color electrode part column is greater than the column number of the pixel driving circuit.

16. The display panel of any of claims 1-15, wherein, The pixel driving circuit comprises a driving transistor, a first transistor, a second transistor, and a ninth transistor. The first electrode of the ninth transistor is connected to the gate electrode of the driving transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the second electrode of the ninth transistor, the first electrode of the second transistor is connected to the second electrode of the ninth transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor. The display panel further comprises: A first gate layer is located between the substrate substrate and the electrode layer, and the first gate layer comprises a first reset signal line and a first gate line. The orthogonal projection of the first reset signal line and the first gate line on the substrate substrate extends along the row direction. Part of the structure of the first reset signal line is used to form the gate electrode of the first transistor, and part of the structure of the first gate line is used to form the gate line of the second transistor. A third gate layer is located between the first gate layer and the electrode layer, and the third gate layer comprises a second gate line. The orthogonal projection of the second gate line on the substrate substrate extends along the row direction. Part of the structure of the second gate line is used to form the top gate of the ninth transistor. The second gate line is located between the first gate line and the first reset signal line on the substrate.

17. The display panel of any of claims 1-15, wherein, The pixel driving circuit comprises a driving transistor, a second transistor, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor. The display panel further comprises: A first active layer is located between the substrate and the electrode layer, and the first active layer comprises a second active part and a third active part, the second active part is used to form a channel region of the second transistor, and the third active part is used to form a channel region of the driving transistor. A shielding layer is located between the substrate and the first active layer, and the shielding layer comprises a first shielding part and a second shielding part, a projection of the first shielding part on the substrate and a projection of the third active part on the substrate at least partially overlap, and a projection of the second shielding part on the substrate and a projection of the second active part on the substrate at least partially overlap.

18. The display panel of any of claims 1-15, wherein, The pixel driving circuit comprises a driving transistor, a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor. A first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate electrode of the driving transistor. A first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor. A first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light-emitting unit. A first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode of the eighth transistor is connected to a first electrode of the driving transistor. The display panel further comprises: A first gate layer is located between the substrate and the electrode layer, and the first gate layer comprises an enable signal line and a second reset signal line, a projection of the enable signal line and a projection of the second reset signal line on the substrate extend along a row direction, and part of a structure of the enable signal line is used to form a gate electrode of the fifth transistor, and part of a structure of the second reset signal line is used to form a gate electrode of the eighth transistor. A third gate layer is located between the substrate and the electrode layer, and the third gate layer comprises the first initial signal line and the third initial signal line, and a projection of the first initial signal line and a projection of the third initial signal line on the substrate extend along the row direction. A projection of the third initial signal line on the substrate in the pixel driving circuit in the current row and a projection of the second reset signal line on the substrate in the pixel driving circuit in the current row at least partially overlap, and a projection of the first initial signal line on the substrate in the pixel driving circuit in the current row and a projection of the enable signal line on the substrate in the pixel driving circuit in the adjacent previous row at least partially overlap.

19. The display panel of any of claims 1-15, wherein, The pixel driving circuit comprises a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a capacitor. A first electrode of the ninth transistor is connected to a gate electrode of a driving transistor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode thereof is connected to a second electrode of the ninth transistor; A second electrode of the ninth transistor is connected to a second electrode of the first transistor; A first electrode of the second transistor is connected to the second electrode of the ninth transistor, and a second electrode thereof is connected to a second electrode of the driving transistor; A first electrode of the fourth transistor is connected to a data line, and a second electrode thereof is connected to a first electrode of the driving transistor; A first electrode of the fifth transistor is connected to a power supply line, and a second electrode thereof is connected to a first electrode of the driving transistor; A first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode thereof is connected to a first electrode of a light emitting unit; A first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode thereof is connected to the first electrode of the light emitting unit; A first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode thereof is connected to a first electrode of the driving transistor; A first electrode of the capacitor is connected to a gate electrode of the driving transistor, and a second electrode thereof is connected to the power supply line.

20. A display device comprising: The display device includes the display panel of any one of claims 1 to 19.

Images