Display substrate and display device

Abstract

The invention provides a display substrate which comprises a light-transmitting area, a lead area and a display area. The n data lines are located on the substrate and comprise i first data lines and i second data lines, the first data lines continuously extend to the other side of the display area from one side of the display area in the second direction, and the second data lines comprise first data segments and second data segments; the b grid signal lines respectively comprise two grid signal sections located on the two sides of the light-transmitting area in the first direction, the a grid signal lines further comprise c winding wires, the winding wires are located in the lead area, and the grid signal sections are electrically connected through the winding wires; at least part of the second data lines further comprise bridging wires, one ends of the bridging wires are electrically connected with the first data segments, the other ends of the bridging wires are electrically connected with the second data segments, and the bridging wires are located in the display area; the display substrate further comprises a plurality of conducting layers located on the substrate, and the c winding wires are located in at least two conducting layers.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] At present, full screen has become a development trend, and consumers' demand for narrow frame, ultra-narrow frame, and even frameless display products is becoming more and more intense. In order to further improve the screen ratio, many display products use AA Hole design, that is, an opening design is arranged in an active area (AA area), so that an optical sensor such as a camera can be placed at the opening (Hole) in the AA area, so as to reduce the frame of the screen and improve the screen ratio. The black edge specification of the Hole is also getting smaller and smaller. At present, how to reduce the frame width of the Hole is one of the issues that the researchers of display products are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute the prior art.

[0004] SUMMARY

[0005] In one aspect, a display substrate is provided, the display substrate includes a light-transmitting region, a lead region surrounding a periphery of the light-transmitting region, a display region surrounding a periphery of the lead region, and a peripheral region located at a periphery of the display region, the display substrate includes:

[0006] a substrate substrate;

[0007] n data lines located on the substrate substrate, including i first data lines and i second data lines, the i first data lines and the i second data lines are arranged along a first direction and extend along a second direction, the first direction intersects the second direction, the first data lines continuously extend along the second direction from one side of the display region to the other side of the display region, the second data lines include first data segments and second data segments, the first data segments and the second data segments are respectively located on both sides of the lead region along the second direction, n, i, and j are positive integers, and the sum of i and j is less than or equal to n; and

[0008] a gate signal lines located on the substrate substrate, the gate signal lines extend along the first direction, b of the gate signal lines respectively include two gate signal segments located on both sides of the light-transmitting region along the first direction, the a gate signal lines further include c windings, the windings are located in the lead region, the two gate signal segments in at least part of the gate signal lines are electrically connected through the windings, 2≤c≤b 2

[0009] wherein at least part of the second data lines further comprises a bridge wire, one end of the bridge wire is electrically connected with the first data segment and the other end of the bridge wire is electrically connected with the second data segment, and the bridge wire is located in the display area; and

[0010] The display substrate further comprises a plurality of conductive layers on the substrate, and the c conductive lines are located in at least two of the conductive layers.

[0011] According to some exemplary embodiments, the bridge wire comprises at least two first bridge segments and at least one second bridge segment, the first bridge segments extend along the first direction, and the second bridge segment extends along the second direction; and

[0012] One end of one of the first bridge segments is electrically connected with one end of the first data segment close to the light-transmitting area, and the other end of the first bridge segment is electrically connected with a first end of the second bridge segment, and one end of another first bridge segment is electrically connected with one end of the second data segment close to the light-transmitting area, and the other end of the first bridge segment is electrically connected with a second end of the second bridge segment.

[0013] According to some exemplary embodiments, the display substrate comprises a first conductive layer on the substrate, a second conductive layer on a side of the first conductive layer close to the substrate, the first data segment, the second data segment and the second bridge segment are located in the first conductive layer, and the second bridge segment is located in the second conductive layer.

[0014] According to some exemplary embodiments, the first conductive layer further comprises a plurality of first signal lines, the first signal lines are arranged along the first direction and extend along the second direction, the first signal lines are used for transmitting a first signal, and part of the first signal lines respectively form a plurality of first wire groups with a plurality of the second bridge segments; and

[0015] One of the first wire groups comprises one of the second bridge segments and one of the first signal lines, the first signal line comprises two first signal segments extending along the second direction and spaced apart from each other, the second bridge segment is located between the two first signal segments, and the second bridge segment is spaced apart from the two first signal segments.

[0016] According to some exemplary embodiments, the second conductive layer further comprises a plurality of second signal lines, the second signal lines are arranged along the second direction and extend along the first direction, the second signal lines are used for transmitting the first signal, at least part of the second signal lines are electrically connected with at least part of the first signal lines, and part of the second signal lines respectively form a plurality of second wire groups with a plurality of the first bridge segments; and

[0017] One of the second wiring groups comprises the second signal line and the first bridge segment, and the second signal line and the first bridge segment are arranged at intervals.

[0018] According to some exemplary embodiments, the a number of gate signal lines comprises a number of first gate signal lines, the first gate signal lines are used for transmitting gate signals of threshold compensation transistors; the wirings comprise first wirings; the display substrate further comprises a gate drive circuit on the substrate, the gate drive circuit comprises a number of first gate signal output terminals, and at least two of the first gate signal lines are electrically connected to one of the first gate signal output terminals respectively; and

[0019] The at least one first gate signal line comprises at least two first gate signal segments respectively located on two sides of the lead region along the first direction, and the at least two first gate signal segments are electrically connected by the first wirings.

[0020] According to some exemplary embodiments, the a number of gate signal lines further comprises a number of second gate signal lines, a number of third gate signal lines and a number of fourth gate signal lines, and a number of the wirings further comprises a number of second wirings, a number of third wirings and a number of fourth wirings.

[0021] Each of the second gate signal lines is arranged along the second direction, at least one of the second gate signal lines comprises at least two second gate signal segments respectively located on two sides of the lead region along the first direction, and the at least two second gate signal segments are electrically connected by the second wirings.

[0022] Each of the third gate signal lines is arranged along the second direction, at least one of the third gate signal lines comprises at least two third gate signal segments respectively located on two sides of the lead region along the first direction, and the at least two third gate signal segments are electrically connected by the third wirings.

[0023] Each of the fourth gate signal lines is arranged along the second direction, at least one of the third gate signal lines comprises at least two fourth gate signal segments respectively located on two sides of the lead region along the first direction, and the at least two fourth gate signal segments are electrically connected by the fourth wirings.

[0024] The first wirings, the second wirings, the third wirings and the fourth wirings are located in at least two of the conductive layers.

[0025] According to some exemplary embodiments, the a number of gate signal lines further comprises a number of fifth gate signal lines, each of the fifth gate signal lines is arranged along the second direction, and the fifth gate signal lines are used for transmitting gate signals of data write transistors.

[0026] The peripheral region includes a first peripheral region and a second peripheral region located on both sides of the display region along the first direction, and the gate drive circuit includes a plurality of fifth gate signal output ends located in the first peripheral region and a plurality of fifth gate signal output ends located in the second peripheral region.

[0027] Among them, one end of the two adjacent fifth gate signal lines close to the first peripheral region is respectively electrically connected with the two fifth gate signal output ends located in the first peripheral region, and one end of the two adjacent fifth gate signal lines close to the second peripheral region is respectively electrically connected with the two fifth gate signal output ends located in the second peripheral region.

[0028] According to some exemplary embodiments, the display region has a first edge and a second edge on both sides along the first direction, the center of the light-transmitting region is closer to the first edge than to the second edge, at least one of the fifth gate signal lines includes at least two fifth gate signal segments respectively located on both sides of the lead region along the first direction, and the wire winding includes a fifth wire winding, and the at least two fifth gate signal segments are electrically connected through the fifth wire winding.

[0029] According to some exemplary embodiments, the first gate signal segment and the first wire winding are located in the same conductive layer, the second gate signal segment and the second wire winding are located in the same conductive layer, the third gate signal segment and the third wire winding are located in different conductive layers, the fourth gate signal segment and the fourth wire winding are located in different conductive layers, and the fifth gate signal segment and the fifth wire winding are located in different conductive layers.

[0030] According to some exemplary embodiments, the first wire winding, the second wire winding, the third wire winding, the fourth wire winding and the fifth wire winding are located in four conductive layers.

[0031] According to some exemplary embodiments, the plurality of conductive layers include a third conductive layer located on the side of the second conductive layer close to the substrate substrate, a fourth conductive layer located on the side of the third conductive layer close to the substrate substrate, a fifth conductive layer located on the side of the fourth conductive layer close to the substrate substrate, and a sixth conductive layer located on the side of the fifth conductive layer close to the substrate substrate.

[0032] Among them, the third wire winding and the fourth wire winding are located in the third conductive layer, the first wire winding is located in the fourth conductive layer, the fifth wire winding is located in the fifth conductive layer, and the second wire winding is located in the sixth conductive layer.

[0033] According to some exemplary embodiments, the gate driving circuit comprises a plurality of second gate signal output terminals, two adjacent second gate signal lines are respectively electrically connected to one of the second gate signal output terminals, and a second gate signal line segment in the two adjacent second gate signal lines is electrically connected by two second windings;

[0034] The gate driving circuit comprises a plurality of third gate signal output terminals, two adjacent third gate signal lines are respectively electrically connected to one of the third gate signal output terminals, and a third gate signal line segment in the two adjacent third gate signal lines is electrically connected by one third winding.

[0035] The gate driving circuit comprises a plurality of fourth gate signal output terminals, two adjacent fourth gate signal lines are respectively electrically connected to one of the fourth gate signal output terminals, and a fourth gate signal line segment in the two adjacent fourth gate signal lines is electrically connected by one fourth winding.

[0036] According to some exemplary embodiments, a projection of the second winding on the substrate substrate is spaced apart from a projection of the fifth winding on the substrate substrate.

[0037] A projection of the first winding on the substrate substrate partially overlaps a projection of the second winding on the substrate substrate, and a projection of the first winding on the substrate substrate partially overlaps a projection of the fifth winding on the substrate substrate; and

[0038] A projection of the third winding and the fourth winding on the substrate substrate is spaced apart from a projection of the first winding on the substrate substrate, a projection of the third winding and the fourth winding on the substrate substrate partially overlaps a projection of the second winding on the substrate substrate, and a projection of the third winding and the fourth winding on the substrate substrate partially overlaps a projection of the fifth winding on the substrate substrate.

[0039] According to some exemplary embodiments, a distance between a projection of the second winding on the substrate substrate and a projection of the fifth winding on the substrate substrate is greater than or equal to 0.5 μm.

[0040] According to some exemplary embodiments, the c second data lines further comprise c sixth windings located in the lead line region, two second data segments in one second data line are electrically connected by one sixth winding, d sixth windings are located in the first conductive layer, (c-d) sixth windings are located in the second conductive layer, 2≤c

[0041] According to some exemplary embodiments, a sixth wire loop located at the first conductive layer is spaced apart from a sixth wire loop located at the second conductive layer on the substrate;

[0042] A sixth wire loop located at the first conductive layer at least partially overlaps a third wire loop and a fourth wire loop on the substrate;

[0043] A sixth wire loop located at the second conductive layer at least partially overlaps a first wire loop on the substrate.

[0044] According to some exemplary embodiments, a sixth wire loop located at the first conductive layer is spaced apart from a sixth wire loop located at the second conductive layer on the substrate;

[0045] A sixth wire loop located at the first conductive layer at least partially overlaps a fifth wire loop on the substrate; and

[0046] A sixth wire loop located at the second conductive layer at least partially overlaps a second wire loop on the substrate.

[0047] According to some exemplary embodiments, a second wire loop on the substrate is spaced apart from a fifth wire loop on the substrate;

[0048] A first wire loop on the substrate is spaced apart from a fifth wire loop on the substrate and a first wire loop on the substrate at least partially overlaps a second wire loop on the substrate; and

[0049] A third wire loop and a fourth wire loop on the substrate are spaced apart from a first wire loop on the substrate and a third wire loop and a fourth wire loop on the substrate at least partially overlap a fifth wire loop on the substrate.

[0050] According to some exemplary embodiments, at least two second data lines further comprise a sixth wire loop located at the lead region, two second data segments in one of the second data lines are electrically connected by the sixth wire loop, part of the sixth wire loop is located at the first conductive layer, and the remaining part of the sixth wire loop is located at the second conductive layer;

[0051] A projection, onto the substrate, of the sixth wire wound on the first conductive layer is spaced apart from a projection, onto the substrate, of the sixth wire wound on the second conductive layer;

[0052] A projection, onto the substrate, of the sixth wire wound on the first conductive layer at least partially overlaps a projection, onto the substrate, of the fifth wire.

[0053] A projection, onto the substrate, of the sixth wire wound on the second conductive layer at least partially overlaps a projection, onto the substrate, of the second wire.

[0054] According to some exemplary embodiments, the display region has a first edge and a second edge on two sides along a first direction, a center of the light-transmissive region is equidistant from the first edge and the second edge, and at least one of the fifth gate signal lines includes two fifth gate signal segments respectively located on two sides of the lead wire region along the first direction, and an end of the fifth gate signal segment close to the light-transmissive region is cut off outside the lead wire region.

[0055] According to some exemplary embodiments, each of the second data lines includes the bridge trace.

[0056] According to some exemplary embodiments, the plurality of conductive layers include a third conductive layer located on a side of the second conductive layer close to the substrate, a fourth conductive layer located on a side of the third conductive layer close to the substrate, a fifth conductive layer located on a side of the fourth conductive layer close to the substrate, and a sixth conductive layer located on a side of the fifth conductive layer close to the substrate.

[0057] The second wire is located on the sixth conductive layer, the first wire is located on the fifth conductive layer, the third wire is located on one of the third conductive layer and the second conductive layer, the fourth wire is located on one of the second conductive layer and the first conductive layer, and the third wire and the fourth wire are not located on the second conductive layer at the same time.

[0058] In another aspect, a display device is provided, and the display device includes the display substrate described above. BRIEF DESCRIPTION OF DRAWINGS

[0059] Other objects and advantages of the present disclosure will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0060] FIG. 1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0061] Figure 2A schematically shows a structure diagram of the data lines and the first signal lines in the region F1 in Figure 1.

[0062] Figure 2B schematically shows an enlarged view of the region B1 in Figure 2A.

[0063] Figure 2C schematically shows another structure diagram of the data lines and the first signal lines in the region F1 in Figure 1.

[0064] Figure 3A schematically shows a structure diagram of the first gate signal lines in the region F2 in Figure 1.

[0065] Figure 3B schematically shows an enlarged view of the region B2 in Figure 3A.

[0066] Figure 4 schematically shows a structure diagram taken along E1-E2 in Figure 1.

[0067] Figure 5 schematically shows a structure diagram of the second signal lines and the bridge traces in the region F1 in Figure 1.

[0068] Figure 6 shows a comparison diagram of the brightness test of the display substrate 1 and the display substrate 2.

[0069] Figure 7 schematically shows a structure diagram of the second gate signal lines in the region F2 in Figure 1.

[0070] Figure 8 schematically shows a structure diagram of the second gate signal lines in the region F2 in Figure 1.

[0071] Figure 9 schematically shows a structure diagram of the second gate signal lines in the region F2 in Figure 1.

[0072] Figure 10 schematically shows another structure diagram taken along E1-E2 in Figure 1.

[0073] Figure 11 schematically shows a structure diagram of the fifth gate signal lines in the region F3 in Figure 1.

[0074] Figure 12 schematically shows a circuit structure diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0075] Figure 13 schematically shows another structure diagram taken along E1-E2 in Figure 1.

[0076] Figure 14 schematically shows yet another structure diagram taken along E1-E2 in Figure 1.

[0077] Figure 15 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0078] Figure 16 schematically shows a structure diagram of the fifth gate signal lines in the region F3 in Figure 15.

[0079] FIG. 17 schematically illustrates yet another structural schematic view taken along E1-E2 in FIG. 1.

[0080] It is to be noted that, for the sake of clarity, the size of layers, structures or regions can be exaggerated or minimized in the drawings used to describe the embodiments of the present disclosure, i.e., the drawings are not drawn to scale. DETAILED DESCRIPTION

[0081] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments. It is apparent, however, that various exemplary embodiments can be practiced without

[0082] In the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. As such, the dimensions and relative sizes of various elements in the drawings can not be to scale. When exemplary embodiments can be carried out in different ways, specific procedural sequences can be performed in a different order than described. For example, two consecutively described processes can be performed at substantially the same time or in reverse order. Additionally, the same reference numerals can be used to designate the same elements throughout the specification and the drawings.

[0083] When an element is referred to as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of relationship between elements are to be interpreted in a like fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" can refer to physical or electrical connection, communication connection, and / or fluid connection. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean any one of X, Y, Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0084] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments.

[0085] FIG. 1 schematically illustrates a plan view of a display substrate according to some embodiments of the present disclosure. FIG. 2A schematically illustrates a structure of data lines and first signal lines in region F1 in FIG. 1. FIG. 3A schematically illustrates a structure of first gate signal lines in region F2 in FIG. 1. FIG. 4 schematically illustrates a structure taken along E1-E2 in FIG. 1.

[0086] Embodiments of the present disclosure provide a display substrate, referring to FIG. 1, the display substrate includes a light-transmitting region HA, a lead region HB surrounding an outer periphery of the light-transmitting region HA, a display region AA surrounding an outer periphery of the lead region HB, and a peripheral region NA located at a periphery of the display region AA. The peripheral region NA includes a first peripheral region NA1 and a second peripheral region NA2 located at both sides of the display region AA along a first direction X, and a third peripheral region NA3 and a fourth peripheral region NA4 located at both sides of the display region AA along a second direction Y. The display region AA has a first edge AA1 and a second edge AA2 located at both sides of the display region AA along the first direction X.

[0087] Referring to FIG. 2A and FIG. 3A, the display substrate includes a substrate 100 and n data lines D and a gate signal lines G on the substrate 100, any two of the n data lines D and the a gate signal lines G are insulated from each other.

[0088] The substrate 100 has a hollow hole in the light-transmitting region HA for placing an optical sensing element such as a camera, and the substrate 100 can be a rigid substrate or a flexible substrate.

[0089] The n data lines D are arranged along a first direction X and extend along a second direction Y. Since the display substrate has a light-transmitting region HA, a part of the data lines D will be interrupted by the light-transmitting region HA. The data lines D that are not interrupted by the light-transmitting region HA are defined as first data lines D1, and the data lines interrupted by the light-transmitting region HA are defined as second data lines D2. That is, the n data lines include i first data lines D1 and j second data lines D2, n, i and j are positive integers, and the sum of i and j is less than or equal to n. For example, in the n data lines arranged along the first direction X, the first data line to the z-th data line are first data lines D1, the z+1-th data line to the z+j-th data line are second data lines D2, and the z+j+1-th data line to the n-th data line are first data lines D1, 1 < z < i, and z is an integer.

[0090] Referring to FIG. 1 and FIG. 2A, the first data lines D1 continuously extend along the second direction Y from the third peripheral region NA3 to the fourth peripheral region NA4. The second data lines D2 include a first data segment D21 and a second data segment D22, and the first data segment D21 and the second data segment D22 are respectively located on both sides of the lead region HB along the second direction Y. That is, the first data segment D21 continuously extends along the second direction Y from the third peripheral region NA3 to the display region AA outside the lead region HB, and the second data segment D22 continuously extends along the second direction Y from the fourth peripheral region NA4 to the display region AA outside the lead region HB.

[0091] Continuing to refer to FIG. 2A, at least part of the second data lines D2 further include a bridge trace D23, one end of the bridge trace D23 is electrically connected to the first data segment D21 and the other end is electrically connected to the second data segment D22, and the bridge trace D23 is located in the display region AA. In the display substrate, part or all of the second data lines D2 are arranged to realize the electrical connection between the first data segment D21 and the second data segment D22 through the bridge trace D23 located in the display region AA. The bridge trace D23 replaces or partially replaces the winding structure in the related art located in the lead region HB, which is beneficial to reduce the width of the lead region HB.

[0092] Referring to FIG. 3A, a-gate signal lines G extend along the first direction X, and due to the display substrate having the light-transmissive region HA, a portion of the gate signal lines G is interrupted in the light-transmissive region HA. Specifically, b-gate signal lines G of the a-gate signal lines G each include two gate signal segments Gx located on two sides of the light-transmissive region HA along the first direction, and the gate signal segments Gx of the b-gate signal lines G are electrically connected by c-wire loops R. The wire loops R are located in the lead region HB, and the wire loops R extend along edges of the light-transmissive region HA. At least two gate signal segments Gx of the gate signal lines G are electrically connected by the wire loops R, 2≤c≤b<a, and a, b, and c are integers. The remaining (a-b) gate signal lines G extend continuously from the first peripheral region NA1 to the second peripheral region NA2 along the first direction X.

[0093] Referring to FIG. 4, the display substrate further includes a plurality of conductive layers M located on the substrate 100, and the c-wire loops are located in at least two conductive layers M. That is, the c-wire loops R are distributed in as many conductive layers M as possible, so that the arrangement area of the c-wire loops in the lead region HB can be compressed, thereby facilitating further reduction of the width of the lead region HB.

[0094] For example, the display substrate includes a plurality of sub-pixels arranged in an array, and the plurality of sub-pixels can be divided into n columns of sub-pixel columns arranged along the second direction Y, or the plurality of sub-pixels can be divided into m rows of sub-pixel rows arranged along the first direction X. The number of data lines is the same as the number of sub-pixel columns, and each data line is electrically connected to each sub-pixel in a column of sub-pixel columns, and is used to provide a data voltage signal to each sub-pixel.

[0095] According to some example embodiments, referring to FIG. 2A, the bridge wire D23 includes at least two first bridge segments D231 and at least one second bridge segment D232, the first bridge segments D231 extend along the first direction X, and the second bridge segment D232 extends along the second direction Y. Referring to FIG. 1, the second bridge segment D232 has a first end close to the third peripheral region NA3 and a second end close to the fourth peripheral region NA4. One end of one of the first bridge segments D231 is electrically connected to one end of the first data segment D21 close to the light-transmissive region HA, and the other end is electrically connected to the first end of the second bridge segment D232. One end of the other of the first bridge segments D231 is electrically connected to one end of the second data segment D22 close to the light-transmissive region HA, and the other end is electrically connected to the second end of the second bridge segment D232.

[0096] According to some example embodiments, referring to FIG. 4, the display substrate includes a first conductive layer M1 located on the substrate 100, a second conductive layer M2 located on a side of the first conductive layer M1 close to the substrate 100, the first data segment D21, the second data segment D22, and the second bridge segment D232 are located in the first conductive layer M1, and the first bridge segment D231 is located in the second conductive layer M2.

[0097] According to some exemplary embodiments, referring back to FIG. 2A, the first conductive layer M1 further comprises a plurality of first signal lines L1 arranged along the first direction X and extending along the second direction Y, the first signal lines L1 being configured to transmit a first signal.

[0098] It is to be noted that the first signal can be a direct current signal used for driving display. For example, the display substrate further comprises a light emitting device layer located on a side of the first signal lines L1 away from the substrate 100, the light emitting device layer comprising a cathode layer, the first signal can be a second power signal connected to the cathode layer, and the first signal lines L1 are electrically connected to the cathode layer to transmit the second power signal to the cathode layer. For example, the light emitting device layer comprises an anode layer, and the first signal can be a first power signal connected to the anode layer. For another example, the first signal can also be an initialization signal. For example, the first signal can be a first initialization signal connected to a first electrode of a first transistor as mentioned in the following description, or the first signal can be a second initialization signal connected to a first electrode of a seventh transistor, or the first signal can be a third initialization signal connected to a first electrode of an eighth transistor. Part of the first signal lines L1 are respectively connected to a plurality of second bridge segments D232 to form a plurality of first routing groups L1a, one first routing group L1a comprising one second bridge segment D232 and one first signal line L1, the first signal line L1 comprising two first signal segments L11 extending along the second direction Y and spaced apart, the two first signal segments L11 having a spacing distance, and the spacing distance being greater than a length of the second bridge segment D232 along the second direction Y, and further, the second bridge segment D232 is arranged between the two first signal segments L11 while being spaced apart from the two first signal segments L11, i.e., the second bridge segment D232 is insulated from the two first signal segments L11. That is, part of the first signal lines L1 conventionally arranged is omitted, and the second bridge segment D232 is arranged in the region where the first signal line L1 is omitted, i.e., the second bridge segment D232 does not need to occupy additional arrangement space.

[0099] FIG. 5 schematically shows a structure of the second signal lines and the bridge routing in the region F1 in FIG. 1.

[0100] According to some exemplary embodiments, referring to FIG. 5, the second conductive layer M2 further comprises a plurality of second signal lines L2 arranged along the second direction Y and extending along the first direction X, the second signal lines L2 being configured to transmit the first signal, and at least part of the second signal lines L2 are electrically connected to at least part of the first signal lines L1, i.e., the plurality of first signal lines L1 and the plurality of second signal lines L2 form a grid-shaped routing for transmitting the first signal.

[0101] The plurality of first bridge sections D231 and the partial second signal lines L2 form a plurality of second wiring groups L2a, respectively. Some of the second wiring groups L2a are separated by the light-transmitting region HA, and some of the second wiring groups L2a are not separated by the light-transmitting region HA. The wiring structures of the two are different, as described below.

[0102] Referring to FIG. 5, in the second wiring group L2a that is not separated by the light-transmitting region HA, one second wiring group L2a includes one second signal line L2 and two first bridge sections D231. The second signal line L2 includes a first second signal section L21, a second second signal section L21, and a third second signal section L21, which are arranged at intervals along the first direction X.

[0103] The first second signal section L21 and the second second signal section L21 have a certain interval distance, which is greater than the length of the first bridge section D231 along the first direction X. The first bridge section D231 is thus arranged between the first second signal section L21 and the second second signal section L21, and is spaced apart from the first second signal section L21 and the second second signal section L21, i.e., insulated from the first second signal section L21 and the second second signal section L21.

[0104] The second second signal section L21 and the third second signal section L21 have a certain interval distance, which is greater than the length of the other first bridge section D231 along the first direction X. The other first bridge section D231 is thus arranged between the second second signal section L21 and the third second signal section L21, and is spaced apart from the second second signal section L21 and the third second signal section L21, i.e., insulated from the second second signal section L21 and the third second signal section L21.

[0105] Continuing to refer to FIG. 5, in the second wiring group L2a that is separated by the light-transmitting region HA, one second wiring group L2a includes one second signal line L2 and two first bridge sections D231. The second signal line L2 includes two second signal sections L21 arranged at intervals along the first direction X.

[0106] Referring to FIG. 1, one first bridge segment D231 is spaced apart from one second signal segment L21 along the first direction X and located at one side of the lead region HB along the first direction X, specifically, one first bridge segment D231 is located at one side of the lead region HB close to the first peripheral region NA1, the second signal segment L21 extends from the first peripheral region NA1 toward the second peripheral region NA2, one end of the first bridge segment D231 close to the first peripheral region NA1 is spaced apart from one end of the second signal segment L21 away from the first peripheral region NA1, and one end of the first bridge segment D231 close to the second peripheral region NA2 is located outside the display region AA of the lead region HB.

[0107] Referring to FIG. 1, another first bridge segment D231 is spaced apart from another second signal segment L21 along the first direction X and located at another side of the lead region HB along the first direction X, specifically, another first bridge segment D231 is located at one side of the lead region HB close to the second peripheral region NA2, the second signal segment L21 extends from the second peripheral region NA2 toward the first peripheral region NA1, one end of the first bridge segment D231 close to the second peripheral region NA2 is spaced apart from one end of the second signal segment L21 away from the second peripheral region NA2, and one end of the first bridge segment D231 close to the first peripheral region NA1 is located outside the display region AA of the lead region HB.

[0108] That is, part of the second signal line L2 arranged in the conventional manner is omitted, and the first bridge segment D231 is arranged in the region where the second signal line L2 is omitted, that is, the first bridge segment D231 does not need to occupy additional arrangement space. At the same time, since the plurality of first signal lines L1 and the plurality of second signal lines L2 form a grid-shaped trace, even if part of the first signal line L1 and the second signal line L2 is omitted, the transmission of the first signal will hardly be affected.

[0109] FIG. 2B schematically shows an enlarged view of the region B1 in FIG. 2A.

[0110] Referring to FIGS. 2A, 2B and 5, the first signal line L1, the data line D and the first power line VDD are located in the first conductive layer, and the second signal line L2 is located in the second conductive layer. The first signal line L1 can be a straight line type trace extending along the second direction Y, the data line D and the first power line VDD can be a broken line type trace extending along the second direction, and the second signal line L2 can be a straight line type trace extending along the first direction X.

[0111] The second data line D2 extends along the second direction Y until the light-transmitting region periphery is disconnected, and a normal projection of the second data segment D22 in the second data line D2 on the substrate substrate overlaps with a normal projection of the first bridge segment D231 on the substrate substrate (as shown by the dashed box marked as a in FIG. 2B), and in the overlapping area, the second data segment D22 and the first bridge segment D231 are electrically connected by a via. The normal projection of the first bridge segment D231 on the substrate substrate overlaps with the normal projection of the second bridge segment D232 on the substrate substrate (as shown by the dashed box marked as b in FIG. 2B), and in the overlapping area, the first bridge segment D231 and the second bridge segment D232 are electrically connected by a via. It should be understood that the connection mode of the first data segment of the second data line D2 located on the other side of the light-transmitting region and the other first bridge segment is similar, and will not be described here.

[0112] It should be noted that the connection via of the second data segment D22 and the first bridge segment D231 can also be located at the dashed box marked as c in FIG. 2B, and when the connection via is located here, a connection part located at the dashed box marked as c and connected with the first bridge segment D231 can be added. The connection via of the first bridge segment D231 and the second bridge segment D232 can also be located at the dashed box marked as d in FIG. 2B, and when the connection via is located here, a connection part located at the dashed box marked as d and connected with the first bridge segment D231 can be added.

[0113] According to some exemplary embodiments, the first bridge segment D231 has a break K1 with the adjacent second signal segment L21, and a normal projection of the break K1 on the substrate substrate is located within a normal projection of the first power line VDD on the substrate substrate. The first power line VDD can shield the break K1, thereby avoiding the problem of display difference between the area provided with the break K1 and the area not provided with the break K1.

[0114] According to some exemplary embodiments, the second bridge segment D232 is located between two adjacent first power lines VDD, and the first power line VDD can act as a shielding structure of the second bridge segment D232, effectively avoiding the data signal transmitted in the second bridge segment D232 from being interfered by other signals.

[0115] According to some exemplary embodiments, referring to FIGS. 2A and 2B, the second data segment D22 includes a first portion D221 located on a side of the first bridge segment D231 away from the winding region HB and a second portion D222 located on a side of the first bridge segment D231 away from the winding region HB, the first portion D221 is used for transmitting data signals, and the second portion D222 is disconnected after extending to the edge of the winding region HB to ensure the wiring uniformity of the display region as much as possible. It should be understood that the first data segment D21 located on the other side of the winding region HB has a similar structure design, which will not be described here.

[0116] According to some exemplary embodiments, referring back to FIG. 3A, the a number of gate signal lines include a number of first gate signal lines G1, each first gate signal line G1 is arranged along the second direction Y, and the first gate signal line G1 is used for transmitting a gate signal of a threshold compensation transistor. For example, the a number of gate signal lines include m first gate signal lines G1, the number of the first gate signal lines G1 is the same as the number of the sub-pixel rows, one first gate signal line G1 is electrically connected to each sub-pixel in one row of sub-pixel rows, and is used for providing a first gate signal to each sub-pixel. Part of the m first gate signal lines G1 is interrupted by the light-transmissive region HA, and the remaining part of the first gate signal lines G1 is continuously arranged along the first direction X. The first gate signal line G1 interrupted by the light-transmissive region HA includes two first gate signal segments G11 located on both sides of the lead region HB along the first direction X, a number of windings R include a number of first windings R1, and the two first gate signal segments G11 in one first gate signal line G1 are electrically connected by the first winding R1.

[0117] The display substrate further includes a gate drive circuit GOA located on the substrate 100 and located in the peripheral region NA, the gate drive circuit GOA includes a plurality of first gate signal output terminals GOA1, and the plurality of first gate signal output terminals GOA1 are located in the first peripheral region NA or the second peripheral region NA. The plurality of first gate signal lines G1 are divided into a plurality of first gate signal groups G1a, one first gate signal group G1a includes two adjacent first gate signal lines G1, and the two first gate signal lines G1 are respectively electrically connected to one first gate signal output terminal GOA1.

[0118] In some first gate signal groups G1a, the two first gate signal lines G1 each include two first gate signal segments G11 located on both sides of the lead region HB along the first direction X, the two first gate signal segments G11 in one first gate signal line G1 are electrically connected by one first winding R1, and the two first gate signal segments G11 in the other first gate signal line G1 are electrically connected by the other first winding R1.

[0119] It is to be further explained that, in one or two first gate signal groups G1a, only one of the two first gate signal lines G1 can include two first gate signal segments G11 respectively located at two sides of the lead region HB along the first direction X, and the two first gate signal segments G11 are also electrically connected by one first wire R1, and the other first gate signal line extends continuously along the first direction X.

[0120] In the related art, the two first gate signal lines in one first gate signal group are electrically connected to the same first gate signal output terminal, and thus when the two first gate signal lines in the first gate signal group are both interrupted by the light-transmissive region, they usually share one wire to be electrically connected. However, the inventors have found that this is the key reason for the display unevenness of the display area AA around the light-transmissive region HA, which has a larger difference in display brightness compared to other display areas AA. When the two interrupted first gate signal lines G1 in the first gate signal group G1a are respectively electrically connected by two first wires R1, the display unevenness can be effectively improved.

[0121] To this end, comparative verification is performed, and two display substrates, i.e., a display substrate 1 and a display substrate 2, are provided. The display substrate 1 and the display substrate 2 have basically the same structure, and the only difference is that in the display substrate 1, the two first gate signal lines in the first gate signal group interrupted by the light-transmissive region are commonly electrically connected by one first wire, and in the display substrate 2, the two first gate signal lines in the first gate signal group interrupted by the light-transmissive region are respectively electrically connected by two first wires. The display substrate 1 and the display substrate 2 are subjected to brightness testing, and FIG. 6 shows a comparison chart of the brightness testing of the display substrate 1 and the display substrate 2. Referring to FIG. 6, the abscissa represents the column number of the green sub-pixel column, and the ordinate represents the relative brightness, i.e., the percentage of the test brightness compared to the standard brightness. The light-transmissive region in the display substrate 1 and the display substrate 2 is approximately located around the 720th row. It can be clearly seen that in the display substrate 1, the brightness of the pixel column corresponding to the light-transmissive region is obviously reduced, and in the display substrate 2, the brightness reduction of the pixel column corresponding to the light-transmissive region is effectively improved. Specifically, the difference between the maximum brightness and the minimum brightness in each pixel column in the display substrate 1 is 3.2%, and the difference between the maximum brightness and the minimum brightness in each pixel column in the display substrate 2 is reduced to 0.6%.

[0122] FIG. 7 schematically shows a structure diagram of the second gate signal line in the region F2 in FIG. 1. FIG. 8 schematically shows a structure diagram of the second gate signal line in the region F2 in FIG. 1. FIG. 9 schematically shows a structure diagram of the second gate signal line in the region F2 in FIG. 1.

[0123] According to some exemplary embodiments, referring to FIGS. 7-9, the a number of gate signal lines further include a number of second gate signal lines G2, a number of third gate signal lines G3, and a number of fourth gate signal lines G4. For example, the second gate signal lines G2 are used to transmit gate signals of the first reset transistors, the third gate signal lines G3 are used to transmit gate signals of the light emitting control transistors, and the fourth gate signal lines G4 are used to transmit gate signals of the second reset transistors. The number of windings R further include a number of second windings R2, a number of third windings R3, and a number of fourth windings R4.

[0124] Referring to FIG. 7, the second gate signal lines G2 are arranged along the second direction Y, and at least one second gate signal line G2 includes two second gate signal segments G21 respectively located on both sides of the lead region HB along the first direction X, and the two second gate signal segments G21 in one second gate signal line G2 are electrically connected by one second winding R2. For example, the a number of gate signal lines include m second gate signal lines G2, the number of second gate signal lines G2 is the same as the number of rows of sub-pixels, one second gate signal line G2 is electrically connected to each sub-pixel in a row of sub-pixels, and is used to provide a second gate signal to each sub-pixel. Part of the m second gate signal lines G2 are interrupted by the light transmission region HA, and the remaining second gate signal lines G2 are continuously arranged along the first direction X.

[0125] Referring to FIG. 8, the third gate signal lines G3 are arranged along the second direction Y, and at least one third gate signal line G3 includes two third gate signal segments G31 respectively located on both sides of the lead region HB along the first direction X, and the two third gate signal segments G31 in one third gate signal line G3 are electrically connected by one third winding R3. For example, the a number of gate signal lines include m third gate signal lines G3, the number of third gate signal lines G3 is the same as the number of rows of sub-pixels, one third gate signal line G3 is electrically connected to each sub-pixel in a row of sub-pixels, and is used to provide a third gate signal to each sub-pixel. Part of the m third gate signal lines G3 are interrupted by the light transmission region HA, and the remaining third gate signal lines G3 are continuously arranged along the first direction X.

[0126] Referring to FIG. 9, the fourth gate signal lines G4 are arranged along the second direction Y, and at least one fourth gate signal line G4 includes two fourth gate signal segments G41 respectively located on both sides of the lead region HB along the first direction X, and the two fourth gate signal segments G41 in one fourth gate signal line G4 are electrically connected by one fourth wire R4. For example, the a gate signal lines include m fourth gate signal lines G4, the number of the fourth gate signal lines G4 is the same as the number of the sub-pixel rows, one fourth gate signal line G4 is electrically connected with each sub-pixel in one row of sub-pixel rows, and is used to provide a fourth gate signal to each sub-pixel. Part of the m fourth gate signal lines G4 is interrupted by the light-transmissive region HA, and the remaining fourth gate signal lines G4 are continuously arranged along the first direction X.

[0127] The first wire R1, the second wire R2, the third wire R3, and the fourth wire R4 are located in at least three conductive layers. Referring back to FIG. 4, for example, the first wire R1, the second wire R2, the third wire R3, and the fourth wire R4 are located in three conductive layers.

[0128] FIG. 10 schematically shows a structural schematic diagram of a structure taken along E1-E2 in FIG. 1. Referring to FIG. 10, for example, the first wire R1, the second wire R2, the third wire R3, and the fourth wire R4 are located in four conductive layers.

[0129] FIG. 11 schematically shows a structural schematic diagram of a fifth gate signal line in the region F3 in FIG. 1.

[0130] According to some exemplary embodiments, referring to FIG. 11, the a gate signal lines further include a plurality of fifth gate signal lines G5, each fifth gate signal line G5 is arranged along the second direction Y, and the fifth gate signal line G5 is used to transmit a gate signal of a data writing transistor. For example, the a gate signal lines include m fifth gate signal lines G5, the number of the fifth gate signal lines G5 is the same as the number of the sub-pixel rows, one fifth gate signal line G5 is electrically connected with each sub-pixel in one row of sub-pixel rows, and is used to provide a fifth gate signal to each sub-pixel. Part of the m fifth gate signal lines G5 is interrupted by the light-transmissive region HA, and the remaining fifth gate signal lines G5 are continuously arranged along the first direction X.

[0131] The gate driving circuit GOA includes m fifth gate signal output ends GOA5 located at the first peripheral region NA and m fifth gate signal output ends GOA5 located at the second peripheral region NA. Among them, the two adjacent fifth gate signal lines G5 are respectively electrically connected to the two fifth gate signal output ends GOA5 located at the first peripheral region NA at one end close to the first peripheral region NA, and the two adjacent fifth gate signal lines G5 are respectively electrically connected to the two fifth gate signal output ends GOA5 located at the second peripheral region NA at one end close to the second peripheral region NA. That is, the two ends of each fifth gate signal line G5 along the first direction X are respectively connected to the same fifth gate signal through different fifth gate signal output ends GOA5, and the two adjacent fifth gate signal lines G5 are connected to the fifth gate signal through different fifth gate signal output ends GOA5.

[0132] According to some exemplary embodiments, referring back to FIG. 1, the distance W1 from the center of the light transmission region HA to the first edge AA1 is less than the distance W2 from the center of the light transmission region HA to the second edge AA2. Referring to FIG. 11, at least one fifth gate signal line G5 includes two fifth gate signal segments G51 respectively located at both sides of the lead region HB along the first direction X, a plurality of windings R includes at least one fifth winding R5, and the two fifth gate signal segments in a fifth gate signal line G5 are electrically connected through the fifth winding R5. Since the light transmission region HA is closer to the first edge AA1, the lengths of the two fifth gate signal segments G51 in a fifth gate signal line G5 along the first direction X are not the same, and due to voltage drop and other reasons, there is a difference in voltage signal distribution between the two fifth gate signal segments G51, which may further cause display unevenness. Therefore, in this case, the two fifth gate signal segments G51 in a fifth gate signal line G5 are still electrically connected through a fifth winding R5.

[0133] According to some exemplary embodiments, one sub-pixel includes one pixel driving circuit and a light emitting element electrically connected to the pixel driving circuit. For example, FIG. 12 schematically shows a circuit structure schematic diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0134] Referring to FIG. 12, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is electrically connected to 10 signal lines (first gate signal line G1, second gate signal line G2, third gate signal line G3, fourth gate signal line G4, fifth gate signal line G5, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0135] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is electrically connected with the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is electrically connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is electrically connected with the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is electrically connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is also electrically connected with the anode of the light emitting device EL.

[0136] In the example embodiment, the first end of the storage capacitor C is electrically connected with the first node N1, and the second end of the storage capacitor C is electrically connected with the first power supply line VDD.

[0137] In the example embodiment, the first transistor T1 can be referred to as a first initialization transistor. The gate electrode of the first transistor T1 is electrically connected with the second gate signal line G2. The first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1. The second electrode of the first transistor T1 is electrically connected with the third node N3.

[0138] The second transistor T2 can be referred to as a compensation transistor. The gate electrode of the second transistor T2 is electrically connected with the first gate signal line G1. The first electrode of the second transistor T2 is electrically connected with the first node N1. The second electrode of the second transistor T2 is electrically connected with the third node N3.

[0139] The third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is electrically connected with the first node N1, i.e., the gate electrode of the third transistor T3 is electrically connected with the first end of the storage capacitor C. The first electrode of the third transistor T3 is electrically connected with the second node N2. The second electrode of the third transistor T3 is electrically connected with the third node N3.

[0140] The fourth transistor T4 can be referred to as a data writing transistor. The gate electrode of the fourth transistor T4 is electrically connected with the fifth gate signal line G5. The first electrode of the fourth transistor T4 is electrically connected with the data signal line DATA. The second electrode of the fourth transistor T4 is electrically connected with the second node N2.

[0141] The fifth transistor T5 can be referred to as a first light emitting control transistor. The gate electrode of the fifth transistor T5 is electrically connected with the third gate signal line G3. The first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD. The second electrode of the fifth transistor T5 is electrically connected with the second node N2.

[0142] The sixth transistor T6 can be referred to as a second light emitting control transistor, a gate electrode of the sixth transistor T6 is electrically connected with the third gate signal line G3, a first electrode of the sixth transistor T6 is electrically connected with the third node N3, and a second electrode of the sixth transistor T6 is electrically connected with the fourth node N4.

[0143] The seventh transistor T7 can be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is electrically connected with the fourth gate signal line G4, a first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected with the fourth node N4.

[0144] The eighth transistor T8 can be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is electrically connected with the fourth gate signal line G4, a first electrode of the eighth transistor T8 is electrically connected with the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is electrically connected with the second node N2.

[0145] In an exemplary embodiment, the light emitting device EL can be an OLED including a stacked anode (first electrode), an organic light emitting layer, and a cathode (second electrode), or can be a QLED including a stacked anode (first electrode), a quantum dot light emitting layer, and a cathode (second electrode).

[0146] In an exemplary embodiment, a first electrode of the light emitting device EL is electrically connected with the fourth node N4, a second electrode of the light emitting device EL is electrically connected with the second power supply line VSS, a signal of the second power supply line VSS is a continuously provided low level signal, and a signal of the first power supply line VDD is a continuously provided high level signal.

[0147] It should be noted that FIG. 12 exemplarily shows a circuit schematic diagram of a pixel driving circuit, but embodiments of the present disclosure are not limited thereto, and can be replaced by other conventional pixel driving circuits in the art according to actual needs.

[0148] According to some exemplary embodiments, the first gate signal segment G11 can be located in the same conductive layer as the first wire R1, the second gate signal segment G21 can be located in the same conductive layer as the second wire R2, the third gate signal segment G31 can be located in different conductive layers from the third wire R3, the fourth gate signal segment G41 can be located in different conductive layers from the fourth wire R4, and the fifth gate signal segment G51 can be located in different conductive layers from the fifth wire R5.

[0149] According to some exemplary embodiments, referring to FIG. 4, the first wire R1, the second wire R2, the third wire R3, the fourth wire R4, and the fifth wire R5 are located in four conductive layers.

[0150] According to some exemplary embodiments, referring to FIG. 4, the multi-layer conductive layer includes a third conductive layer M3 located on the side of the second conductive layer M2 close to the substrate 100, a fourth conductive layer M4 located on the side of the third conductive layer M3 close to the substrate 100, a fifth conductive layer M5 located on the side of the fourth conductive layer M4 close to the substrate 100, and a sixth conductive layer M6 located on the side of the fifth conductive layer M5 close to the substrate 100. The third wire R3 and the fourth wire R4 are located on the third conductive layer M3, the first wire R1 is located on the fourth conductive layer M4, the fifth wire R5 is located on the fifth conductive layer M5, and the second wire R2 is located on the sixth conductive layer M6.

[0151] For example, the first conductive layer M1 is a third source-drain metal layer, the second conductive layer M2 is a second source-drain metal layer, the third conductive layer M3 is a first source-drain metal layer, the fourth conductive layer M4 is a third gate metal layer, the fifth conductive layer M5 is a second gate metal layer, and the sixth conductive layer M6 is a first gate metal layer.

[0152] For example, the first conductive layer M1 and the second conductive layer M2 have a first insulating layer 200 therebetween, the second conductive layer M2 and the third conductive layer M3 have a second insulating layer 300 therebetween, the third conductive layer M3 and the fourth conductive layer M4 have a third insulating layer 400 therebetween, the fourth conductive layer M4 and the fifth conductive layer M5 have a fourth insulating layer 500 therebetween, and the fifth conductive layer M5 and the sixth conductive layer M6 have a fifth insulating layer 600 therebetween.

[0153] According to some exemplary embodiments, referring to FIG. 7, the gate drive circuit GOA includes a plurality of second gate signal output terminals GOA2, which are located on the first peripheral area NA or on the second peripheral area NA. FIG. 7 exemplarily shows the case where the second gate signal output terminals GOA2 are located on the first peripheral area NA. The plurality of second gate signal lines G2 include a plurality of second gate signal groups G2a, one second gate signal group G2a including two adjacent second gate signal lines G2, and the two second gate signal lines G2 being electrically connected to one second gate signal output terminal GOA2 respectively.

[0154] In some second gate signal groups G2a, the two second gate signal lines G2 each include two second gate signal segments G21, and the second gate signal group G2a further includes two second wires R2, the two second gate signal segments G21 in one second gate signal line G2 being electrically connected by one second wire R2, and the two second gate signal segments G21 in the other second gate signal line G2 being electrically connected by the other second wire R2.

[0155] Referring to FIG. 8, the gate driving circuit GOA includes a plurality of third gate signal output terminals GOA3, which are located in the first peripheral area NA or in the second peripheral area NA. FIG. 8 exemplarily shows a case where the third gate signal output terminals GOA3 are located in the first peripheral area NA. The plurality of third gate signal lines G3 includes a plurality of third gate signal groups G3a, one of which includes two adjacent third gate signal lines G3, which are electrically connected to one of the third gate signal output terminals GOA3, respectively.

[0156] In some of the third gate signal groups G3a, the two third gate signal lines G3 each include two third gate signal segments G31, and the third gate signal group G3a further includes one third routing line R3, through which the two third gate signal segments G31 in one of the third gate signal lines G3 are electrically connected, and through which the two third gate signal segments G31 in the other of the third gate signal lines G3 are electrically connected.

[0157] Referring to FIG. 9, the gate driving circuit GOA includes a plurality of fourth gate signal output terminals GOA4, which are located in the first peripheral area NA or in the second peripheral area NA. FIG. 9 exemplarily shows a case where the fourth gate signal output terminals GOA4 are located in the first peripheral area NA. The plurality of fourth gate signal lines G4 includes a plurality of fourth gate signal groups G4a, one of which includes two adjacent fourth gate signal lines G4, which are electrically connected to one of the fourth gate signal output terminals GOA4, respectively.

[0158] In some of the fourth gate signal groups G4a, the two fourth gate signal lines G4 each include two fourth gate signal segments G41, and the fourth gate signal group G4a further includes one fourth routing line R4, through which the two fourth gate signal segments G41 in one of the fourth gate signal lines G4 are electrically connected, and through which the two fourth gate signal segments G41 in the other of the fourth gate signal lines G4 are electrically connected.

[0159] In the routing distribution shown in FIG. 4, the third conductive layer M3 includes the third routing line R3 and the fourth routing line R4, i.e., two kinds of routing lines are provided in the third conductive layer M3, while one kind of routing line is provided in each of the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6. By electrically connecting the two third gate signal lines G3 in the third gate signal group G3a through the same third routing line R3 and electrically connecting the two fourth gate signal lines G4 in the fourth gate signal group G4a through the same fourth routing line R4, the number of routing lines provided in the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6 is substantially the same, thereby avoiding the problem of uneven display caused by the difference in the distribution density of the routing lines in different conductive layers.

[0160] According to some exemplary embodiments, referring to FIG. 4, the orthogonal projection of the second winding R2 on the substrate 100 is spaced apart from the orthogonal projection of the fifth winding R5 on the substrate 100, and the second winding R2 is arranged apart from the fifth winding R5 to avoid signal crosstalk between the second winding R2 and the fifth winding R5, because the thickness of the insulating layer between the fifth conductive layer M5 and the sixth conductive layer M6 is usually thin.

[0161] Further, the orthogonal projection of the first winding R1 on the substrate 100 partially overlaps the orthogonal projection of the second winding R2 on the substrate 100, and the orthogonal projection of the first winding R1 on the substrate 100 partially overlaps the orthogonal projection of the fifth winding R5 on the substrate 100, i.e., the orthogonal projection of the first winding R1 on the substrate 100 covers the interval region of the orthogonal projection of the fifth winding R5 on the substrate 100 and the orthogonal projection of the second winding R2 on the substrate 100.

[0162] Meanwhile, the orthogonal projection of the third winding R3 on the substrate 100 is spaced apart from the orthogonal projection of the first winding R1 on the substrate 100, the orthogonal projection of the third winding R3 on the substrate 100 partially overlaps the orthogonal projection of the second winding R2 on the substrate 100, and the orthogonal projection of the third winding R3 on the substrate 100 partially overlaps the orthogonal projection of the fifth winding R5 on the substrate 100, and the orthogonal projection of the fourth winding R4 on the substrate 100 is spaced apart from the orthogonal projection of the first winding R1 on the substrate 100, the orthogonal projection of the fourth winding R4 on the substrate 100 partially overlaps the orthogonal projection of the second winding R2 on the substrate 100, and the orthogonal projection of the fourth winding R4 on the substrate 100 partially overlaps the orthogonal projection of the fifth winding R5 on the substrate 100. Since the third winding R3 and the fourth winding R4 are located in the third conductive layer M3, for example, a titanium layer / aluminum layer / titanium layer laminated film layer, when etching to form the third conductive layer M3, the film layer located in the uneven terrain has the risk of etching residue, for example, the film layer located in the interval region of the second winding R2 and the fifth winding R5 is more prone to etching residue defects, therefore, the film layer located in the interval region of the second winding R2 and the fifth winding R5 is the third winding R3 and the fourth winding R4 that need to be reserved, thereby avoiding this problem.

[0163] According to some exemplary embodiments, referring to FIG. 4, the interval P between the orthogonal projection of the second winding R2 on the substrate 100 and the orthogonal projection of the fifth winding R5 on the substrate 100 is greater than or equal to 0.5 μm, to improve the problem of cracks in the part of the first winding R1 covering the interval region of the second winding R2 and the fifth winding R5.

[0164] According to some exemplary embodiments, referring to FIG. 2A, part of the j second data lines D2 are electrically connected by the bridge wires D23 located in the display area AA, and the rest part are still electrically connected by the winding wires located in the lead area HB, that is, the c sixth winding wires R6 are located in the lead area HB, and the first data segment D21 and the second data segment D22 of one second data line D2 are electrically connected by one sixth winding wire R6. Further, the d sixth winding wires R6 are located in the first conductive layer M1, and the (c-d) sixth winding wires R6 are located in the second conductive layer M2, 2≤c

[0165] For example, when the number of the sixth winding wires R6 is even, the number of the sixth winding wires R6 located in the first conductive layer M1 is equal to the number of the sixth winding wires R6 located in the second conductive layer M2. When the number of the sixth winding wires R6 is odd, the number of the sixth winding wires R6 located in the first conductive layer M1 is equal to the number of the sixth winding wires R6 located in the second conductive layer M2 with a difference of 1. By distributing the c sixth winding wires R6 substantially evenly in the first conductive layer M1 and the second conductive layer M2, the space occupied by the sixth winding wires R6 in the lead area HB is compressed, thereby facilitating the narrowing of the width of the lead area HB.

[0166] According to some exemplary embodiments, referring to FIG. 4, the orthogonal projection of the sixth winding wires R6 located in the first conductive layer M1 on the substrate 100 is spaced apart from the orthogonal projection of the sixth winding wires R6 located in the second conductive layer M2 on the substrate 100.

[0167] Further, the orthogonal projection of the sixth winding wires R6 located in the first conductive layer M1 on the substrate 100 at least partially overlaps with the orthogonal projection of the third winding wires R3 and the fourth winding wires R4 on the substrate 100. The orthogonal projection of the sixth winding wires R6 located in the second conductive layer M2 on the substrate 100 at least partially overlaps with the orthogonal projection of the first winding wires R1 on the substrate 100. That is, in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4, the winding wires in the adjacent two conductive layers are staggered.

[0168] FIG. 13 schematically shows another structural schematic view taken along E1-E2 in FIG. 1.

[0169] According to some exemplary embodiments, referring to FIG. 13, the orthogonal projection of the sixth winding wires R6 located in the first conductive layer M1 on the substrate 100 is spaced apart from the orthogonal projection of the sixth winding wires R6 located in the second conductive layer M2 on the substrate 100.

[0170] Further, the orthogonal projection of the sixth wire R6 in the first conductive layer M1 on the substrate 100 at least partially overlaps with the orthogonal projection of the fifth wire R5 on the substrate 100. The orthogonal projection of the sixth wire R6 in the second conductive layer M2 on the substrate 100 at least partially overlaps with the orthogonal projection of the second wire R2 on the substrate 100.

[0171] FIG. 14 schematically shows another structure diagram of FIG. 1 taken along E1-E2.

[0172] According to some exemplary embodiments, with reference to FIG. 14, the orthogonal projection of the second wire R2 on the substrate 100 is spaced apart from the orthogonal projection of the fifth wire R5 on the substrate 100. The orthogonal projection of the first wire R1 on the substrate 100 is spaced apart from the orthogonal projection of the fifth wire R5 on the substrate 100 and at least partially overlaps with the orthogonal projection of the second wire R2 on the substrate 100. The orthogonal projection of the third wire R3 and the fourth wire R4 on the substrate 100 is spaced apart from the orthogonal projection of the first wire R1 on the substrate 100 and at least partially overlaps with the orthogonal projection of the fifth wire R5 on the substrate 100. That is, in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6, the wires in the adjacent two conductive layers are staggered.

[0173] According to some exemplary embodiments, with reference to FIG. 14, the orthogonal projection of the sixth wire R6 in the first conductive layer M1 on the substrate 100 is spaced apart from the orthogonal projection of the sixth wire R6 in the second conductive layer M2 on the substrate 100. The orthogonal projection of the sixth wire R6 in the first conductive layer M1 on the substrate 100 at least partially overlaps with the orthogonal projection of the fifth wire R5 on the substrate 100. The orthogonal projection of the sixth wire R6 in the second conductive layer M2 on the substrate 100 at least partially overlaps with the orthogonal projection of the second wire R2 on the substrate 100. That is, in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6, the wires in the adjacent two conductive layers are staggered.

[0174] FIG. 15 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. FIG. 16 schematically shows a structure diagram of the fifth gate signal line in the region F3 in FIG. 15.

[0175] According to some exemplary embodiments, referring to FIG. 15, the distance W1 from the center of the light-transmissive region HA to the first edge AA1 is equal to the distance W2 from the center of the light-transmissive region HA to the second edge AA2. Referring to FIG. 16, the at least one fifth gate signal line G5 includes two fifth gate signal segments G51 respectively located on both sides of the lead region HB along the first direction X, and one end of the fifth gate signal segment G51 close to the light-transmissive region HA is cut off outside the lead region HB. Since the light-transmissive region HA is located in the middle of the first edge AA1 and the second edge AA2, the lengths of the two fifth gate signal segments G51 in one fifth gate signal line G5 are substantially the same, and the voltage signals in the two fifth gate signal segments G51 are substantially symmetrically distributed. In this case, the two fifth gate signal segments G51 can be discontinuously arranged, i.e., no electrical connection is required through the fifth winding R5.

[0176] FIG. 2C schematically shows another structural diagram of the data lines and the first signal lines in the region F1 in FIG. 1.

[0177] According to some exemplary embodiments, referring to FIG. 2C, each second data line D2 includes a bridge trace D23, i.e., j second data lines D2 include j bridge traces D23. In any second data line D2, the first data segment D21 and the second data segment D22 are electrically connected by a bridge trace D23, and thus the sixth winding R6 is not required. Further, a part of the first winding R1, the second winding R2, the third winding R3, the fourth winding R4, and the fifth winding R5 can be arranged in the first conductive layer M1 and the second conductive layer M2, which is beneficial to further narrowing the width of the lead region HB.

[0178] According to some exemplary embodiments, referring to FIG. 16 and FIG. 2C, each second data line D2 is electrically connected by a bridge trace D23, and the two fifth gate signal segments G51 in the fifth gate signal line G5 separated by the light-transmissive region HA are discontinuously arranged, i.e., the fifth winding and the sixth winding are not required. The first winding, the second winding, the third winding, and the fourth winding can be uniformly distributed in the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer, so as to further narrow the width of the lead region.

[0179] According to some exemplary embodiments, the second wire R2 is located on the sixth conductive layer M6, the first wire R1 is located on the fifth conductive layer M5, the third wire R3 is located on one of the third conductive layer M3 and the second conductive layer M2, the fourth wire R4 is located on one of the second conductive layer M2 and the first conductive layer M1, and the third wire R3 and the fourth wire R4 are not located on the second conductive layer M2 at the same time. For example, referring to FIG. 10, the second wire R2 is located on the sixth conductive layer M6, the first wire R1 is located on the fifth conductive layer M5, the third wire R3 is located on the third conductive layer M3, and the fourth wire R4 is located on the second conductive layer M2.

[0180] Further, referring to FIG. 7, in any one of the second gate signal lines G2 including two second gate signal segments G21, the two second gate signal segments G21 are electrically connected by one second wire R2, and two adjacent second gate signal lines G2 are electrically connected by two second wires R2. Similarly, in any one of the third gate signal lines including two third gate signal segments, the two third gate signal segments are electrically connected by one third wire, and two adjacent third gate signal lines are electrically connected by two third wires. The structure of such third gate signal lines is not shown in the drawings, and can be set according to the structure of the second gate signal lines shown in FIG. 7. Similarly, in any one of the fourth gate signal lines including two fourth gate signal segments, the two fourth gate signal segments are electrically connected by one fourth wire, and two adjacent fourth gate signal lines are electrically connected by two fourth wires. The structure of such fourth gate signal lines is not shown in the drawings, and can be set according to the structure of the second gate signal lines shown in FIG. 7. Thus, the number of wires in each of the sixth conductive layer M6, the fifth conductive layer M5, the third conductive layer M3, and the second conductive layer M2 is substantially equal, thereby ensuring that the wire distribution density of each layer is the same.

[0181] FIG. 3B schematically shows an enlarged view of region B2 in FIG. 3A.

[0182] Referring to FIG. 3B, the first gate signal line G1 includes a first sub-wire G1m and a second sub-wire G1n. The first sub-wire G1m can be located on the fifth conductive layer, and the second sub-wire G1n can be located on the fourth conductive layer. The orthogonal projection of the first sub-wire G1m on the substrate and the orthogonal projection of the second sub-wire G1n on the substrate at least partially overlap. The first sub-wire G1m and the second sub-wire G1n are electrically connected by a via in the second insulating layer between the fifth conductive layer and the fourth conductive layer, thereby reducing the resistance of the first gate signal line G1.

[0183] According to some exemplary embodiments, referring to FIG. 3B, the display substrate can further include a conductive connection part Pad located on the fourth conductive layer away from the substrate substrate, the conductive connection part Pad can be located in the winding area, the orthogonal projection of the conductive connection part Pad on the substrate substrate partially overlaps the orthogonal projection of the second sub-wire G1n on the substrate substrate, in the overlapping area, the conductive connection part Pad is electrically connected with the second sub-wire G1n through the via, similarly, the orthogonal projection of the conductive connection part Pad on the substrate substrate partially overlaps the orthogonal projection of the first sub-wire G1m on the substrate substrate, in the overlapping area, the conductive connection part Pad is electrically connected with the first sub-wire G1m through the via, that is, the second sub-wire G1n and the first sub-wire G1m can be electrically connected through the conductive connection part Pad. Exemplarily, the conductive connection part Pad can be located in the third conductive layer.

[0184] According to some exemplary embodiments, referring to FIG. 3B and FIG. 4, the first winding R1 can be located in the fourth conductive layer M4, that is, the first winding R1 can be located in the same layer as the second sub-wire G1n. According to some exemplary embodiments, referring to FIG. 10, the first winding R1 is located in the fifth conductive layer M5, that is, the first winding R1 can be located in the same layer as the first sub-wire.

[0185] FIG. 17 schematically shows another structure schematic view taken along E1-E2 in FIG. 1.

[0186] Referring to FIG. 17, the first winding R1 includes a first sub-winding R11 and a second sub-winding R12, the first sub-winding R11 is located in the fifth conductive layer M5, the second sub-winding R12 is located in the fourth conductive layer M4, the orthogonal projection of the first sub-winding R11 on the substrate substrate overlaps (for example, can be substantially coincident) with the orthogonal projection of the second sub-winding R12 on the substrate substrate, the first sub-winding R11 and the second sub-winding R12 are connected through the via in the second insulating layer 300, the via can be provided in the lead area, and can be multiple vias; or the first sub-winding R11 and the second sub-winding R12 can be lapped by digging a groove in the second insulating layer 300, so as to reduce the resistance of the first winding. Without providing the fifth winding and the sixth winding, the first winding R1 can be provided as a double-layer winding, that is, without increasing the width of the lead area, the resistance of the first winding R1 can be reduced, and further the load of the first gate signal line can be reduced.

[0187] According to some exemplary embodiments, in the case of space allowing, any one or more of the first winding to the fifth winding can be provided as a double-layer metal winding, and the insulating layer between the two layers of metal can be punched or grooved, so as to further reduce the resistance of the winding.

[0188] In another aspect, a display device is provided, which includes the display substrate described above. The display device can be a display device such as a liquid crystal display, electronic paper, an OLED (Organic Light-Emitting Diode) display, and the like, and any product or component having a touch and display function such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, and the like, including the display device.

[0189] It should be understood that the display device according to some example embodiments of the present disclosure has all the features and advantages of the display substrate described above, which can be referred to the description above for the display substrate and will not be repeated here.

[0190] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. In view of the process fluctuations, measurement problems and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), and the like, "about" or "approximately," as used herein, includes the stated value and means a range of values determined to be acceptable by one of ordinary skill in the art to the particular value. For example, "about" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0191] While some embodiments in accordance with the general inventive concept of the present disclosure have been illustrated and described, it is understood that various changes in form and details can be made therein without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined with the following claims and their equivalents.

Claims

1. A display substrate, characterized by, The display substrate comprises a light-transmitting region, a lead region surrounding the periphery of the light-transmitting region, a display region surrounding the periphery of the lead region, and a peripheral region located at the periphery of the display region, and the display substrate comprises: a substrate substrate; n data lines located on the substrate substrate, comprising i first data lines and j second data lines, the i first data lines and the j second data lines are arranged along a first direction and extend along a second direction, the first direction intersects the second direction, the first data lines continuously extend along the second direction from one side of the display region to the other side of the display region, the second data lines comprise first data segments and second data segments, the first data segments and the second data segments are respectively located on both sides of the lead region along the second direction, n, i and j are positive integers, and the sum of i and j is less than or equal to n; and a gate signal line located on the substrate substrate, the gate signal line extends along the first direction, b gate signal lines respectively comprise two gate signal segments located on both sides of the light-transmitting region along the first direction, the a gate signal lines further comprise c wires, the wires are located in the lead region, and the two gate signal segments in at least part of the gate signal lines are electrically connected through the wires, 2≤c≤b wherein at least part of the second data lines further comprise a bridge trace, one end of the bridge trace is electrically connected with the first data segment and the other end is electrically connected with the second data segment, and the bridge trace is located in the display region; and The display substrate further comprises a plurality of conductive layers located on the substrate substrate, and the c wires are located in at least two of the conductive layers.

2. The display substrate of claim 1, wherein, The bridge trace comprises at least two first bridge segments and at least one second bridge segment, the first bridge segments extend along the first direction, and the second bridge segments extend along the second direction; and one end of one first bridge segment is electrically connected with one end of the first data segment close to the light-transmitting region, and the other end is electrically connected with a first end of the second bridge segment, and one end of another first bridge segment is electrically connected with one end of the second data segment close to the light-transmitting region, and the other end is electrically connected with a second end of the second bridge segment. 3.The display substrate of claim 2, wherein, The display substrate comprises a first conductive layer located on the substrate substrate, and a second conductive layer located on the side of the first conductive layer close to the substrate substrate, the first data segment, the second data segment and the second bridge segment are located in the first conductive layer, and the second bridge segment is located in the second conductive layer.

4. The display substrate of claim 3, wherein, The first conductive layer further comprises a plurality of first signal lines, the plurality of first signal lines are arranged along the first direction and extend along the second direction, the first signal lines are used for transmitting first signals, and part of the first signal lines respectively form a plurality of first trace groups with a plurality of the second bridge segments; and One of the first routing groups comprises one of the second bridge sections and one of the first signal lines, the first signal line comprises two first signal sections which are spaced apart and extend along the second direction, the second bridge section is located between the two first signal sections, and the second bridge section is spaced apart from the two first signal sections.

5. The display substrate of claim 4, wherein, The second conductive layer further comprises a plurality of second signal lines, the plurality of second signal lines are arranged along the second direction and extend along the first direction, the second signal lines are used for transmitting the first signals, at least part of the second signal lines are electrically connected with at least part of the first signal lines, and part of the second signal lines respectively form a plurality of second routing groups with the plurality of first bridge sections. One of the second routing groups comprises one of the second signal lines and one of the first bridge sections, and the second signal line and the first bridge section are spaced apart. 6.The display substrate of claim 1, wherein, The plurality of gate signal lines comprises a plurality of first gate signal lines, the first gate signal lines are used for transmitting gate signals of threshold compensation transistors; the plurality of wires comprises a plurality of first wires; the display substrate further comprises a gate drive circuit located on the substrate, the gate drive circuit comprises a plurality of first gate signal output terminals, and at least two of the first gate signal lines are respectively electrically connected to one of the first gate signal output terminals; and At least one of the first gate signal lines comprises at least two first gate signal sections respectively located on two sides of the lead region along the first direction, and the at least two first gate signal sections are electrically connected by the first wire. 7.The display substrate of claim 6, wherein, The plurality of gate signal lines further comprises a plurality of second gate signal lines, a plurality of third gate signal lines and a plurality of fourth gate signal lines, and the plurality of wires further comprises a plurality of second wires, a plurality of third wires and a plurality of fourth wires. Each of the second gate signal lines is arranged along the second direction, at least one of the second gate signal lines comprises at least two second gate signal sections respectively located on two sides of the lead region along the first direction, and the at least two second gate signal sections are electrically connected by the second wire. Each of the third gate signal lines is arranged along the second direction, at least one of the third gate signal lines comprises at least two third gate signal sections respectively located on two sides of the lead region along the first direction, and the at least two third gate signal sections are electrically connected by the third wire. Each of the fourth gate signal lines is arranged along the second direction, at least one of the third gate signal lines comprises at least two fourth gate signal sections respectively located on two sides of the lead region along the first direction, and the at least two fourth gate signal sections are electrically connected by the fourth wire. The first wire, the second wire, the third wire and the fourth wire are located in at least two of the conductive layers. 8.The display substrate of claim 7, wherein, The plurality of gate signal lines further comprises a plurality of fifth gate signal lines, each of the fifth gate signal lines is arranged along the second direction, and the fifth gate signal lines are used for transmitting gate signals of data write transistors. The peripheral region includes a first peripheral region and a second peripheral region located on both sides of the display region along the first direction, and the gate drive circuit includes a plurality of fifth gate signal output ends located in the first peripheral region and a plurality of fifth gate signal output ends located in the second peripheral region. Among them, one end of two adjacent fifth gate signal lines close to the first peripheral region is respectively electrically connected to two fifth gate signal output ends located in the first peripheral region, and one end of two adjacent fifth gate signal lines close to the second peripheral region is respectively electrically connected to two fifth gate signal output ends located in the second peripheral region. 9.The display substrate of claim 8, wherein, The display region has a first edge and a second edge on both sides along the first direction, the center of the light-transmitting region is closer to the first edge than to the second edge, at least one fifth gate signal line includes at least two fifth gate signal segments respectively located on both sides of the lead region along the first direction, and the wire includes a fifth wire, and the at least two fifth gate signal segments are electrically connected through the fifth wire. 10.The display substrate of claim 9, wherein, The first gate signal segment and the first wire are located in the same conductive layer, the second gate signal segment and the second wire are located in the same conductive layer, the third gate signal segment and the third wire are located in different conductive layers, the fourth gate signal segment and the fourth wire are located in different conductive layers, and the fifth gate signal segment and the fifth wire are located in different conductive layers. 11.The display substrate of claim 10, wherein, The first wire, the second wire, the third wire, the fourth wire and the fifth wire are located in four conductive layers. 12.The display substrate of claim 11, wherein, The plurality of conductive layers include a third conductive layer located on a side of the second conductive layer close to the substrate substrate, a fourth conductive layer located on a side of the third conductive layer close to the substrate substrate, a fifth conductive layer located on a side of the fourth conductive layer close to the substrate substrate, and a sixth conductive layer located on a side of the fifth conductive layer close to the substrate substrate. Among them, the third wire and the fourth wire are located in the third conductive layer, the first wire is located in the fourth conductive layer, the fifth wire is located in the fifth conductive layer, and the second wire is located in the sixth conductive layer. 13.The display substrate of claim 12, wherein, The gate drive circuit includes a plurality of second gate signal output ends, two adjacent second gate signal lines are respectively electrically connected to one second gate signal output end, and a second gate signal line segment in two adjacent second gate signal lines is respectively electrically connected through two second wires; The gate drive circuit includes a plurality of third gate signal output ends, two adjacent third gate signal lines are respectively electrically connected to one third gate signal output end, and a third gate signal line segment in two adjacent third gate signal lines is electrically connected through one third wire; and The gate drive circuit includes a plurality of fourth gate signal output ends, two adjacent fourth gate signal lines are respectively electrically connected to one fourth gate signal output end, and a fourth gate signal line segment in two adjacent fourth gate signal lines is electrically connected through one fourth wire. 14.The display substrate of claim 10, wherein, A projection of the second wire on the substrate is spaced apart from a projection of the fifth wire on the substrate; A projection of the first wire on the substrate partially overlaps with a projection of the second wire on the substrate, and a projection of the first wire on the substrate partially overlaps with a projection of the fifth wire on the substrate; and A projection of the third wire and the fourth wire on the substrate is spaced apart from a projection of the first wire on the substrate, a projection of the third wire and the fourth wire on the substrate partially overlaps with a projection of the second wire on the substrate, and a projection of the third wire and the fourth wire on the substrate partially overlaps with a projection of the fifth wire on the substrate. 15.The display substrate of claim 13, wherein, A distance between a projection of the second wire on the substrate and a projection of the fifth wire on the substrate is greater than or equal to 0.5 μm.

16. The display substrate according to claim 14 or 15, characterized in that, The second data line further comprises c sixth wires located in the lead region, two second data segments in one second data line are electrically connected by one sixth wire, d sixth wires are located in the first conductive layer, (c-d) sixth wires are located in the second conductive layer, 2≤c<j, 1≤d<c, and c and d are integers. 17.The display substrate of claim 16, wherein, A projection of the sixth wire located in the first conductive layer on the substrate is spaced apart from a projection of the sixth wire located in the second conductive layer on the substrate; A projection of the sixth wire located in the first conductive layer on the substrate at least partially overlaps with a projection of the third wire and the fourth wire on the substrate; and A projection of the sixth wire located in the second conductive layer on the substrate at least partially overlaps with a projection of the first wire on the substrate. 18.The display substrate of claim 16, wherein, A projection of the sixth wire located in the first conductive layer on the substrate is spaced apart from a projection of the sixth wire located in the second conductive layer on the substrate; A projection of the sixth wire located in the first conductive layer on the substrate at least partially overlaps with a projection of the fifth wire on the substrate; and A projection of the sixth wire located in the second conductive layer on the substrate at least partially overlaps with a projection of the second wire on the substrate. 19.The display substrate of claim 13, wherein, A projection of the second wire on the substrate is spaced apart from a projection of the fifth wire on the substrate; A projection of the first wire on the substrate is spaced apart from a projection of the fifth wire on the substrate and at least partially overlaps with a projection of the second wire on the substrate; and The third winding and the fourth winding are spaced apart from the first winding on the substrate and the third winding and the fourth winding at least partially overlap the fifth winding on the substrate. 20.The display substrate of claim 19, wherein, The at least two second data lines further include a sixth winding in the lead region, and two second data segments in one of the second data lines are electrically connected by the sixth winding, part of the sixth winding is located in the first conductive layer, and the remaining part of the sixth winding is located in the second conductive layer. The sixth winding located in the first conductive layer is spaced apart from the sixth winding located in the second conductive layer on the substrate. The sixth winding located in the first conductive layer at least partially overlaps the fifth winding on the substrate. And The sixth winding located in the second conductive layer at least partially overlaps the second winding on the substrate. 21.The display substrate of claim 8, wherein, The display region has a first edge and a second edge on both sides along a first direction, a center of the light-transmitting region is equidistant from the first edge and the second edge, and at least one of the fifth gate signal lines includes two fifth gate signal segments located on both sides of the lead region along the first direction, respectively, and an end of the fifth gate signal segment close to the light-transmitting region is cut off outside the lead region. 22.The display substrate of claim 21, wherein, Each of the second data lines includes the bridge trace. 23.The display substrate of claim 22, wherein, The plurality of conductive layers include a third conductive layer located on a side of the second conductive layer close to the substrate, a fourth conductive layer located on a side of the third conductive layer close to the substrate, a fifth conductive layer located on a side of the fourth conductive layer close to the substrate, and a sixth conductive layer located on a side of the fifth conductive layer close to the substrate. The second winding is located in the sixth conductive layer, the first winding is located in the fifth conductive layer, the third winding is located in one of the third conductive layer and the second conductive layer, the fourth winding is located in one of the second conductive layer and the first conductive layer, and the third winding and the fourth winding are not located in the second conductive layer at the same time.

24. A display device comprising: The display device includes the display substrate according to any one of claims 1-23.

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